-# $OpenBSD: files,v 1.18 1996/05/05 12:23:24 mickey Exp $
+# $OpenBSD: files,v 1.19 1996/05/05 12:42:09 deraadt Exp $
# $NetBSD: files,v 1.83 1996/04/25 02:18:25 thorpej Exp $
# @(#)files.newconf 7.5 (Berkeley) 5/10/93
file dev/audio.c audio needs-flag
file dev/ccd.c ccd needs-flag
file dev/ic/aic7xxx.c aic7xxx
+file dev/ic/93cx6.c aic7xxx
file dev/ic/ncr5380sbc.c ncr5380sbc
file dev/ic/pdq.c pdq
file dev/ic/pdq_ifsubr.c pdq
--- /dev/null
+/*
+ * Product specific probe and attach routines for:
+ * 27/284X and aic7770 motherboard SCSI controllers
+ *
+ * Copyright (c) 1995, 1996 Justin T. Gibbs.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice immediately at the beginning of the file, without modification,
+ * this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: aic7770.c,v 1.1 1996/05/05 12:42:22 deraadt Exp $
+ */
+
+#if defined(__FreeBSD__)
+#include <eisa.h>
+#endif
+#if NEISA > 0 || defined(__NetBSD__)
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#if defined(__FreeBSD__)
+#include <sys/devconf.h>
+#endif
+#include <sys/kernel.h>
+
+#if defined(__NetBSD__)
+#include <sys/device.h>
+#if NetBSD1_1 < 3 /* NetBSD-1.1 */
+#include <machine/pio.h>
+#else
+#include <machine/bus.h>
+#ifdef __alpha__
+#include <machine/intr.h>
+#endif
+#endif
+#endif /* defined(__NetBSD__) */
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#if defined(__FreeBSD__)
+
+#include <machine/clock.h>
+
+#include <i386/eisa/eisaconf.h>
+#include <i386/scsi/aic7xxx.h>
+#include <dev/aic7xxx/aic7xxx_reg.h>
+
+#define EISA_DEVICE_ID_ADAPTEC_AIC7770 0x04907770
+#define EISA_DEVICE_ID_ADAPTEC_274x 0x04907771
+#define EISA_DEVICE_ID_ADAPTEC_284xB 0x04907756 /* BIOS enabled */
+#define EISA_DEVICE_ID_ADAPTEC_284x 0x04907757 /* BIOS disabled*/
+
+#elif defined(__NetBSD__)
+
+#if NetBSD1_1 < 3 /* NetBSD-1.1 */
+#include <dev/isa/isareg.h>
+#include <dev/isa/isavar.h>
+#include <dev/isa/isadmavar.h>
+
+/* Standard EISA Host ID regs (Offset from slot base) */
+#define HID0 0x80 /* 0,1: msb of ID2, 2-7: ID1 */
+#define HID1 0x81 /* 0-4: ID3, 5-7: LSB ID2 */
+#define HID2 0x82 /* product */
+#define HID3 0x83 /* firmware revision */
+
+#define CHAR1(B1,B2) (((B1>>2) & 0x1F) | '@')
+#define CHAR2(B1,B2) (((B1<<3) & 0x18) | ((B2>>5) & 0x7)|'@')
+#define CHAR3(B1,B2) ((B2 & 0x1F) | '@')
+
+#define EISA_MAX_SLOTS 16 /* XXX should be defined in a common header */
+static ahc_slot = 0; /* slot last board was found in */
+#else
+#include <dev/eisa/eisareg.h>
+#include <dev/eisa/eisavar.h>
+#include <dev/eisa/eisadevs.h>
+#endif
+
+#include <dev/ic/aic7xxxvar.h>
+#include <dev/microcode/aic7xxx/aic7xxx_reg.h>
+
+#endif /* defined(__NetBSD__) */
+
+#define AHC_EISA_SLOT_OFFSET 0xc00
+#define AHC_EISA_IOSIZE 0x100
+#define INTDEF 0x5cul /* Interrupt Definition Register */
+
+#if defined(__FreeBSD__)
+
+static int aic7770probe __P((void));
+static int aic7770_attach __P((struct eisa_device *e_dev));
+
+static struct eisa_driver ahc_eisa_driver = {
+ "ahc",
+ aic7770probe,
+ aic7770_attach,
+ /*shutdown*/NULL,
+ &ahc_unit
+ };
+
+DATA_SET (eisadriver_set, ahc_eisa_driver);
+
+static struct kern_devconf kdc_aic7770 = {
+ 0, 0, 0, /* filled in by dev_attach */
+ "ahc", 0, { MDDT_EISA, 0, "bio" },
+ eisa_generic_externalize, 0, 0, EISA_EXTERNALLEN,
+ &kdc_eisa0, /* parent */
+ 0, /* parentdata */
+ DC_UNCONFIGURED, /* always start out here */
+ NULL,
+ DC_CLS_MISC /* host adapters aren't special */
+};
+
+
+static char *aic7770_match __P((eisa_id_t type));
+
+static char*
+aic7770_match(type)
+ eisa_id_t type;
+{
+ switch(type) {
+ case EISA_DEVICE_ID_ADAPTEC_AIC7770:
+ return ("Adaptec aic7770 SCSI host adapter");
+ break;
+ case EISA_DEVICE_ID_ADAPTEC_274x:
+ return ("Adaptec 274X SCSI host adapter");
+ break;
+ case EISA_DEVICE_ID_ADAPTEC_284xB:
+ case EISA_DEVICE_ID_ADAPTEC_284x:
+ return ("Adaptec 284X SCSI host adapter");
+ break;
+ default:
+ break;
+ }
+ return (NULL);
+}
+
+static int
+aic7770probe(void)
+{
+ u_long iobase;
+ char intdef;
+ u_long irq;
+ struct eisa_device *e_dev = NULL;
+ int count;
+
+ count = 0;
+ while ((e_dev = eisa_match_dev(e_dev, aic7770_match))) {
+ iobase = (e_dev->ioconf.slot * EISA_SLOT_SIZE)
+ + AHC_EISA_SLOT_OFFSET;
+ ahc_reset(iobase);
+
+ eisa_add_iospace(e_dev, iobase, AHC_EISA_IOSIZE, RESVADDR_NONE);
+ intdef = inb(INTDEF + iobase);
+ switch (intdef & 0xf) {
+ case 9:
+ irq = 9;
+ break;
+ case 10:
+ irq = 10;
+ break;
+ case 11:
+ irq = 11;
+ break;
+ case 12:
+ irq = 12;
+ break;
+ case 14:
+ irq = 14;
+ break;
+ case 15:
+ irq = 15;
+ break;
+ default:
+ printf("aic7770 at slot %d: illegal "
+ "irq setting %d\n", e_dev->ioconf.slot,
+ intdef);
+ continue;
+ }
+ eisa_add_intr(e_dev, irq);
+ eisa_registerdev(e_dev, &ahc_eisa_driver, &kdc_aic7770);
+ if(e_dev->id == EISA_DEVICE_ID_ADAPTEC_284xB
+ || e_dev->id == EISA_DEVICE_ID_ADAPTEC_284x) {
+ /* Our real parent is the isa bus. Say so. */
+ e_dev->kdc->kdc_parent = &kdc_isa0;
+ }
+ count++;
+ }
+ return count;
+}
+
+#elif defined(__NetBSD__)
+
+#define bootverbose 1
+
+int ahe_irq __P((bus_chipset_tag_t, bus_io_handle_t));
+int ahematch __P((struct device *, void *, void *));
+void aheattach __P((struct device *, struct device *, void *));
+
+#if NetBSD1_1 < 3 /* NetBSD-1.1 */
+
+int aheprobe1 __P((struct ahc_data *, struct isa_attach_args *, int));
+int aheprobe __P((struct device *, void *, void *));
+
+struct cfdriver ahecd = {
+ NULL, "ahe", aheprobe, aheattach, DV_DULL,
+ sizeof(struct ahc_data)
+};
+
+int
+aheprobe1(ahc, ia, iobase)
+ struct ahc_data *ahc;
+ struct isa_attach_args *ia;
+ int iobase;
+{
+ int i, irq;
+ u_char intdef, sig_id[4];
+
+ static struct {
+ ahc_type type;
+ u_int8_t id;
+ } valid_ids[] = {
+ /* Entries of other tested adaptors should be added here */
+ { AHC_AIC7770, 0x70 }, /*aic7770 on Motherboard*/
+ { AHC_274, 0x71 }, /*274x*/
+ { AHC_284, 0x56 }, /*284x, BIOS enabled*/
+ { AHC_284, 0x57 } /*284x, BIOS disabled*/
+ };
+
+ for (i = 0; i < sizeof(sig_id); i++) {
+ /*
+ * An outb is required to prime these
+ * registers on VL cards
+ */
+ outb(iobase + HID0, HID0 + i);
+ sig_id[i] = inb(iobase + HID0 + i);
+ }
+ if (sig_id[0] == 0xff)
+ return (0);
+ /* Check manufacturer's ID. */
+ if (CHAR1(sig_id[0], sig_id[1]) != 'A' ||
+ CHAR2(sig_id[0], sig_id[1]) != 'D' ||
+ CHAR3(sig_id[0], sig_id[1]) != 'P' ||
+ sig_id[2] != 0x77)
+ return (0);
+ for (i = 0; i < sizeof(valid_ids)/sizeof(valid_ids[0]); i++) {
+ if (sig_id[3] != valid_ids[i].id)
+ continue;
+
+ ahc_reset("ahe", 0, iobase);
+ intdef = inb(INTDEF + iobase);
+ switch (irq = (intdef & 0xf)) {
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 14:
+ case 15:
+ break;
+ default:
+ printf("%s: illegal irq setting %d\n",
+ ahc->sc_dev.dv_xname, intdef);
+ return (0);
+ }
+
+ if (ia->ia_irq == IRQUNK) {
+ ia->ia_irq = irq;
+ } else if (ia->ia_irq != irq) {
+ printf("%s: irq mismatch; kernel configured %d"
+ "!= board configured %d\n",
+ ahc->sc_dev.dv_xname, ia->ia_irq, irq);
+ return (0);
+ }
+
+ ahc->type = valid_ids[i].type;
+
+ ia->ia_msize = 0;
+ ia->ia_iobase = iobase;
+ ia->ia_iosize = AHC_EISA_IOSIZE;
+ return (1);
+ }
+ return (0);
+}
+
+int
+aheprobe(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct isa_attach_args *ia = aux;
+ struct ahc_data *ahc = match;
+
+ if (ia->ia_iobase != IOBASEUNK)
+ return aheprobe1(ahc, ia, ia->ia_iobase);
+
+ ahc_slot++;
+ for (; ahc_slot < EISA_MAX_SLOTS; ahc_slot++) {
+ if (aheprobe1(ahc, ia,
+ 0x1000 * ahc_slot + AHC_EISA_SLOT_OFFSET))
+ return 1;
+ }
+ return (0);
+}
+
+#else
+
+struct cfattach ahe_ca = {
+ sizeof(struct ahc_data), ahematch, aheattach
+};
+
+struct cfdriver ahe_cd = {
+ NULL, "ahe", DV_DULL
+};
+
+/*
+ * Return irq setting of the board, otherwise -1.
+ */
+int
+ahe_irq(bc, ioh)
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+{
+ int irq;
+ u_char intdef;
+
+ ahc_reset("ahe", bc, ioh);
+ intdef = bus_io_read_1(bc, ioh, INTDEF);
+ switch (irq = (intdef & 0xf)) {
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 14:
+ case 15:
+ break;
+ default:
+ printf("ahe_irq: illegal irq setting %d\n", intdef);
+ return -1;
+ }
+
+ /* Note that we are going and return (to probe) */
+ return irq;
+}
+
+/*
+ * Check the slots looking for a board we recognise
+ * If we find one, note it's address (slot) and call
+ * the actual probe routine to check it out.
+ */
+int
+ahematch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct eisa_attach_args *ea = aux;
+ bus_io_handle_t ioh;
+ int irq;
+
+ /* must match one of our known ID strings */
+ if (strcmp(ea->ea_idstring, "ADP7770") &&
+ strcmp(ea->ea_idstring, "ADP7771") &&
+ strcmp(ea->ea_idstring, "ADP7756") && /* XXX - not EISA, but VL */
+ strcmp(ea->ea_idstring, "ADP7757")) /* XXX - not EISA, but VL */
+ return (0);
+
+#ifdef notyet
+ if (bus_io_map(ea->ea_bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE,
+ &ioh))
+ return (0);
+ /* This won't compile as-is, anyway. */
+ bus_io_write_1(ea->ea_bc, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
+ delay(10);
+ bus_io_write_1(ea->ea_bc, ioh, EISA_CONTROL, EISA_ENABLE);
+ /* Wait for reset? */
+ delay(1000);
+ bus_io_unmap(ea->ea_bc, ioh, EISA_SLOT_SIZE);
+#endif
+
+ if (bus_io_map(ea->ea_bc,
+ EISA_SLOT_ADDR(ea->ea_slot) + AHC_EISA_SLOT_OFFSET,
+ AHC_EISA_IOSIZE, &ioh))
+ return (0);
+ irq = ahe_irq(ea->ea_bc, ioh);
+ bus_io_unmap(ea->ea_bc, ioh, EISA_SLOT_SIZE);
+ return (irq >= 0);
+}
+
+#endif
+
+#endif /* defined(__NetBSD__) */
+
+#if defined(__FreeBSD__)
+static int
+aic7770_attach(e_dev)
+ struct eisa_device *e_dev;
+#elif defined(__NetBSD__)
+void
+aheattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+#endif
+{
+ ahc_type type;
+
+#if defined(__FreeBSD__)
+ struct ahc_data *ahc;
+ resvaddr_t *iospace;
+ int unit = e_dev->unit;
+ int irq = ffs(e_dev->ioconf.irq) - 1;
+
+ iospace = e_dev->ioconf.ioaddrs.lh_first;
+
+ if(!iospace)
+ return -1;
+
+ switch(e_dev->id) {
+ case EISA_DEVICE_ID_ADAPTEC_AIC7770:
+ type = AHC_AIC7770;
+ break;
+ case EISA_DEVICE_ID_ADAPTEC_274x:
+ type = AHC_274;
+ break;
+ case EISA_DEVICE_ID_ADAPTEC_284xB:
+ case EISA_DEVICE_ID_ADAPTEC_284x:
+ type = AHC_284;
+ break;
+ default:
+ printf("aic7770_attach: Unknown device type!\n");
+ return -1;
+ break;
+ }
+
+ if(!(ahc = ahc_alloc(unit, iospace->addr, type, AHC_FNONE)))
+ return -1;
+
+ eisa_reg_start(e_dev);
+ if(eisa_reg_iospace(e_dev, iospace)) {
+ ahc_free(ahc);
+ return -1;
+ }
+
+ /*
+ * The IRQMS bit enables level sensitive interrupts only allow
+ * IRQ sharing if its set.
+ */
+ if(eisa_reg_intr(e_dev, irq, ahc_intr, (void *)ahc, &bio_imask,
+ /*shared ==*/ahc->pause & IRQMS)) {
+ ahc_free(ahc);
+ return -1;
+ }
+ eisa_reg_end(e_dev);
+
+#elif defined(__NetBSD__)
+
+ struct ahc_data *ahc = (void *)self;
+ const char *model;
+#if NetBSD1_1 < 3 /* NetBSD-1.1 */
+ struct isa_attach_args *ia = aux;
+
+ switch (ahc->type) {
+ case AHC_AIC7770:
+ model = "AIC-7770 SCSI (on motherboard)";
+ break;
+ case AHC_274:
+ model = "AHA-274x SCSI";
+ break;
+ case AHC_284:
+ model = "AHA-284x SCSI";
+ break;
+ default:
+ panic("aheattach: Unknown device type 0x%x\n", ahc->type);
+ }
+ printf(": %s\n", model);
+
+ ahc_construct(ahc, ahc->sc_dev.dv_unit, 0,
+ ia->ia_iobase, ahc->type, AHC_FNONE);
+#else
+ struct eisa_attach_args *ea = aux;
+ bus_io_handle_t ioh; /* XXX - ioh */
+ eisa_intr_handle_t ih;
+ const char *intrstr;
+ int irq;
+
+ if (bus_io_map(ea->ea_bc,
+ EISA_SLOT_ADDR(ea->ea_slot) + AHC_EISA_SLOT_OFFSET,
+ AHC_EISA_IOSIZE, &ioh))
+ panic("aheattach: could not map I/O addresses");
+ if ((irq = ahe_irq(ea->ea_bc, ioh)) < 0)
+ panic("aheattach: ahe_irq failed!");
+
+ if (strcmp(ea->ea_idstring, "ADP7770") == 0) {
+ model = EISA_PRODUCT_ADP7770;
+ type = AHC_AIC7770;
+ } else if (strcmp(ea->ea_idstring, "ADP7771") == 0) {
+ model = EISA_PRODUCT_ADP7771;
+ type = AHC_274;
+ } else if (strcmp(ea->ea_idstring, "ADP7756") == 0) {
+ model = EISA_PRODUCT_ADP7756;
+ type = AHC_284;
+ } else if (strcmp(ea->ea_idstring, "ADP7757") == 0) {
+ model = EISA_PRODUCT_ADP7757;
+ type = AHC_284;
+ } else {
+ panic("aheattach: Unknown device type %s\n",
+ ea->ea_idstring);
+ }
+ printf(": %s\n", model);
+
+ ahc_construct(ahc,
+ ahc->sc_dev.dv_unit, ea->ea_bc, ioh, type, AHC_FNONE);
+ if (eisa_intr_map(ea->ea_ec, irq, &ih)) {
+ printf("%s: couldn't map interrupt (%d)\n",
+ ahc->sc_dev.dv_xname, irq);
+ return;
+ }
+#endif
+#endif /* defined(__NetBSD__) */
+
+ /*
+ * Tell the user what type of interrupts we're using.
+ * usefull for debugging irq problems
+ */
+ if(bootverbose) {
+ printf(
+#if defined(__FreeBSD__)
+ "ahc%d: Using %s Interrupts\n",
+ unit,
+#elif defined(__NetBSD__)
+ "%s: Using %s Interrupts\n",
+ ahc->sc_dev.dv_xname,
+#endif
+ ahc->pause & IRQMS ?
+ "Level Sensitive" : "Edge Triggered");
+ }
+
+ /*
+ * Now that we know we own the resources we need, do the
+ * card initialization.
+ *
+ * First, the aic7770 card specific setup.
+ */
+ switch( ahc->type ) {
+ case AHC_AIC7770:
+ {
+ /* XXX
+ * It would be really nice to know if the BIOS
+ * was installed for the motherboard controllers,
+ * but I don't know how to yet. Assume its enabled
+ * for now.
+ */
+ break;
+ }
+ case AHC_274:
+ {
+ if((AHC_INB(ahc, HA_274_BIOSCTRL) & BIOSMODE) == BIOSDISABLED)
+ ahc->flags |= AHC_USEDEFAULTS;
+ break;
+ }
+ case AHC_284:
+ {
+ /* XXX
+ * All values are automagically intialized at
+ * POST for these cards, so we can always rely
+ * on the Scratch Ram values. However, we should
+ * read the SEEPROM here (Dan has the code to do
+ * it) so we can say what kind of translation the
+ * BIOS is using. Printing out the geometry could
+ * save a lot of users the grief of failed installs.
+ */
+ break;
+ }
+ default:
+ break;
+ }
+
+ /*
+ * See if we have a Rev E or higher aic7770. Anything below a
+ * Rev E will have a R/O autoflush disable configuration bit.
+ * Its still not clear exactly what is differenent about the Rev E.
+ * We think it allows 8 bit entries in the QOUTFIFO to support
+ * "paging" SCBs so you can have more than 4 commands active at
+ * once.
+ */
+ {
+ char *id_string;
+ u_char sblkctl;
+ u_char sblkctl_orig;
+
+ sblkctl_orig = AHC_INB(ahc, SBLKCTL);
+ sblkctl = sblkctl_orig ^ AUTOFLUSHDIS;
+ AHC_OUTB(ahc, SBLKCTL, sblkctl);
+ sblkctl = AHC_INB(ahc, SBLKCTL);
+ if(sblkctl != sblkctl_orig)
+ {
+ id_string = "aic7770 >= Rev E, ";
+ /*
+ * Ensure autoflush is enabled
+ */
+ sblkctl &= ~AUTOFLUSHDIS;
+ AHC_OUTB(ahc, SBLKCTL, sblkctl);
+
+ /* Allow paging on this adapter */
+ ahc->flags |= AHC_PAGESCBS;
+ }
+ else
+ id_string = "aic7770 <= Rev C, ";
+
+#if defined(__FreeBSD__)
+ printf("ahc%d: %s", unit, id_string);
+#elif defined(__NetBSD__)
+ printf("%s: %s", ahc->sc_dev.dv_xname, id_string);
+#endif
+ }
+
+ /* Setup the FIFO threshold and the bus off time */
+ if(ahc->flags & AHC_USEDEFAULTS) {
+ AHC_OUTB(ahc, BUSSPD, DFTHRSH_100);
+ AHC_OUTB(ahc, BUSTIME, BOFF_60BCLKS);
+ }
+ else {
+ u_char hostconf = AHC_INB(ahc, HOSTCONF);
+ AHC_OUTB(ahc, BUSSPD, hostconf & DFTHRSH);
+ AHC_OUTB(ahc, BUSTIME, (hostconf << 2) & BOFF);
+ }
+
+ /*
+ * Generic aic7xxx initialization.
+ */
+ if(ahc_init(ahc)){
+#if defined(__FreeBSD__)
+ ahc_free(ahc);
+ /*
+ * The board's IRQ line is not yet enabled so its safe
+ * to release the irq.
+ */
+ eisa_release_intr(e_dev, irq, ahc_intr);
+ return -1;
+#elif defined(__NetBSD__)
+ ahc_free(ahc);
+ return;
+#endif
+ }
+
+ /*
+ * Enable the board's BUS drivers
+ */
+ AHC_OUTB(ahc, BCTL, ENABLE);
+
+#if defined(__FreeBSD__)
+ /*
+ * Enable our interrupt handler.
+ */
+ if(eisa_enable_intr(e_dev, irq)) {
+ ahc_free(ahc);
+ eisa_release_intr(e_dev, irq, ahc_intr);
+ return -1;
+ }
+
+ e_dev->kdc->kdc_state = DC_BUSY; /* host adapters always busy */
+#elif defined(__NetBSD__)
+#if NetBSD1_1 < 3 /* NetBSD-1.1 */
+ ahc->sc_ih = isa_intr_establish(ia->ia_irq,
+ ahc->pause & IRQMS ? IST_LEVEL : IST_EDGE, ISA_IPL_BIO,
+ ahc_intr, ahc);
+#else
+ intrstr = eisa_intr_string(ea->ea_ec, ih);
+ /*
+ * The IRQMS bit enables level sensitive interrupts only allow
+ * IRQ sharing if its set.
+ */
+#ifdef __OpenBSD__
+ ahc->sc_ih = eisa_intr_establish(ea->ea_ec, ih,
+ ahc->pause & IRQMS ? IST_LEVEL : IST_EDGE, IPL_BIO,
+ ahc_intr, ahc, ahc->sc_dev.dv_xname);
+#else
+ ahc->sc_ih = eisa_intr_establish(ea->ea_ec, ih,
+ ahc->pause & IRQMS ? IST_LEVEL : IST_EDGE, IPL_BIO,
+ ahc_intr, ahc);
+#endif
+ if (ahc->sc_ih == NULL) {
+ printf("%s: couldn't establish interrupt",
+ ahc->sc_dev.dv_xname);
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ ahc_free(ahc);
+ return;
+ }
+ if (intrstr != NULL)
+ printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname,
+ intrstr);
+#endif
+#endif /* defined(__NetBSD__) */
+
+ /* Attach sub-devices - always succeeds */
+ ahc_attach(ahc);
+
+#if defined(__FreeBSD__)
+ return 0;
+#endif
+}
+
+#endif /* NEISA > 0 */
-/* $OpenBSD: eisa.c,v 1.2 1996/04/21 22:20:23 deraadt Exp $ */
+/* $OpenBSD: eisa.c,v 1.3 1996/05/05 12:42:23 deraadt Exp $ */
/* $NetBSD: eisa.c,v 1.11 1996/04/09 22:46:11 cgd Exp $ */
/*
}
/* Get the vendor ID bytes */
- for (i = 0; i < EISA_NVIDREGS; i++)
+ for (i = 0; i < EISA_NVIDREGS; i++) {
+#ifdef EISA_SLOTOFF_PRIMING
+ bus_io_write_1(bc, slotioh,
+ EISA_SLOTOFF_PRIMING, EISA_PRIMING_VID(i));
+#endif
ea.ea_vid[i] = bus_io_read_1(bc, slotioh,
EISA_SLOTOFF_VID + i);
+ }
/* Check for device existence */
if (EISA_VENDID_NODEV(ea.ea_vid)) {
}
/* Get the product ID bytes */
- for (i = 0; i < EISA_NPIDREGS; i++)
+ for (i = 0; i < EISA_NPIDREGS; i++) {
+#ifdef EISA_SLOTOFF_PRIMING
+ bus_io_write_1(bc, slotioh,
+ EISA_SLOTOFF_PRIMING, EISA_PRIMING_PID(i));
+#endif
ea.ea_pid[i] = bus_io_read_1(bc, slotioh,
EISA_SLOTOFF_PID + i);
+ }
/* Create the ID string from the vendor and product IDs */
ea.ea_idstring[0] = EISA_VENDID_0(ea.ea_vid);
-/* $OpenBSD: eisareg.h,v 1.3 1996/04/21 22:20:42 deraadt Exp $ */
+/* $OpenBSD: eisareg.h,v 1.4 1996/05/05 12:42:24 deraadt Exp $ */
/* $NetBSD: eisareg.h,v 1.3 1996/04/09 22:46:13 cgd Exp $ */
/*
#define EISA_SLOTOFF_PID 0xc82 /* offset of product id regs */
#define EISA_NPIDREGS 2
+#ifdef AHA284X_HACK
+/*
+ * AHA-284x (VL bus) requires priming a register with the following values.
+ */
+#define EISA_SLOTOFF_PRIMING EISA_SLOTOFF_VID /* offset */
+#define EISA_PRIMING_VID(index) (0x80 + (index)) /* value for vendor */
+#define EISA_PRIMING_PID(index) (0x82 + (index)) /* value for product */
+#endif
/*
* EISA ID functions, used to manipulate and decode EISA ID registers.
-# $OpenBSD: files.eisa,v 1.4 1996/05/02 13:38:03 deraadt Exp $
+# $OpenBSD: files.eisa,v 1.5 1996/05/05 12:42:25 deraadt Exp $
# $NetBSD: files.eisa,v 1.8 1996/04/25 02:16:39 thorpej Exp $
#
# Config.new file and device description for machine-independent EISA code.
attach ahb at eisa
file dev/eisa/aha1742.c ahb
+# Adaptec AHA-27/284X and aic7770 motherboard SCSI controllers
+device ahe: scsi, aic7xxx
+attach ahe at eisa
+file dev/eisa/aic7770.c ahe
+
# 3Com 3c579 and 3c509 masquerading as EISA Ethernet Controllers
# device declaration in sys/conf/files
attach ep at eisa with ep_eisa
--- /dev/null
+/*
+ * Interface for the 93C46/26/06 serial eeprom parts.
+ *
+ * Copyright (c) 1995 Daniel M. Eischen
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice immediately at the beginning of the file, without modification,
+ * this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Absolutely no warranty of function or purpose is made by the author
+ * Daniel M. Eischen.
+ * 4. Modifications may be freely made to this file if the above conditions
+ * are met.
+ *
+ * $Id: 93cx6.c,v 1.1 1996/05/05 12:42:27 deraadt Exp $
+ */
+
+/*
+ * The instruction set of the 93C46/26/06 chips are as follows:
+ *
+ * Start OP
+ * Function Bit Code Address Data Description
+ * -------------------------------------------------------------------
+ * READ 1 10 A5 - A0 Reads data stored in memory,
+ * starting at specified address
+ * EWEN 1 00 11XXXX Write enable must preceed
+ * all programming modes
+ * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
+ * WRITE 1 01 A5 - A0 D15 - D0 Writes register
+ * ERAL 1 00 10XXXX Erase all registers
+ * WRAL 1 00 01XXXX D15 - D0 Writes to all registers
+ * EWDS 1 00 00XXXX Disables all programming
+ * instructions
+ * *Note: A value of X for address is a don't care condition.
+ *
+ * The 93C46 has a four wire interface: clock, chip select, data in, and
+ * data out. In order to perform one of the above functions, you need
+ * to enable the chip select for a clock period (typically a minimum of
+ * 1 usec, with the clock high and low a minimum of 750 and 250 nsec
+ * respectively. While the chip select remains high, you can clock in
+ * the instructions (above) starting with the start bit, followed by the
+ * OP code, Address, and Data (if needed). For the READ instruction, the
+ * requested 16-bit register contents is read from the data out line but
+ * is preceded by an initial zero (leading 0, followed by 16-bits, MSB
+ * first). The clock cycling from low to high initiates the next data
+ * bit to be sent from the chip.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#if defined(__FreeBSD__)
+#include <machine/clock.h>
+#include <i386/scsi/93cx6.h>
+#endif
+#if defined(__NetBSD__)
+#include <machine/pio.h>
+#include <dev/ic/93cx6.h>
+#endif
+
+/*
+ * Right now, we only have to read the SEEPROM. But we make it easier to
+ * add other 93Cx6 functions.
+ */
+static struct seeprom_cmd {
+ unsigned char len;
+ unsigned char bits[3];
+} seeprom_read = {3, {1, 1, 0}};
+
+
+/*
+ * Wait for the SEERDY to go high; about 800 ns.
+ */
+#define CLOCK_PULSE(p, rdy) \
+ while ((inb(p) & rdy) == 0) { \
+ ; /* Do nothing */ \
+ }
+
+/*
+ * Read the serial EEPROM and returns 1 if successful and 0 if
+ * not successful.
+ */
+int read_seeprom (u_long offset,
+ u_short *buf,
+ u_int start_addr,
+ int count,
+ u_short CS, /* chip select */
+ u_short CK, /* clock */
+ u_short DO, /* data out */
+ u_short DI, /* data in */
+ u_short RDY, /* ready */
+ u_short MS /* mode select */)
+{
+ int i = 0, k = 0;
+ unsigned char temp;
+
+ /*
+ * Read the requested registers of the seeprom. The loop
+ * will range from 0 to count-1.
+ */
+ for (k = start_addr; k < count + start_addr; k = k + 1) {
+ /* Send chip select for one clock cycle. */
+ outb(offset, MS | CK | CS);
+ CLOCK_PULSE(offset, RDY);
+
+ /*
+ * Now we're ready to send the read command followed by the
+ * address of the 16-bit register we want to read.
+ */
+ for (i = 0; i < seeprom_read.len; i = i + 1) {
+ if (seeprom_read.bits[i])
+ temp = MS | CS | DO;
+ else
+ temp = MS | CS;
+ outb(offset, temp);
+ CLOCK_PULSE(offset, RDY);
+ temp = temp ^ CK;
+ outb(offset, temp);
+ CLOCK_PULSE(offset, RDY);
+ }
+ /* Send the 6 bit address (MSB first, LSB last). */
+ for (i = 5; i >= 0; i = i - 1) {
+ /* k is the address, i is the bit */
+ if (k & (1 << i))
+ temp = MS | CS | DO;
+ else
+ temp = MS | CS;
+ outb(offset, temp);
+ CLOCK_PULSE(offset, RDY);
+ temp = temp ^ CK;
+ outb(offset, temp);
+ CLOCK_PULSE(offset, RDY);
+ }
+
+ /*
+ * Now read the 16 bit register. An initial 0 precedes the
+ * register contents which begins with bit 15 (MSB) and ends
+ * with bit 0 (LSB). The initial 0 will be shifted off the
+ * top of our word as we let the loop run from 0 to 16.
+ */
+ for (i = 0; i <= 16; i = i + 1) {
+ temp = MS | CS;
+ outb(offset, temp);
+ CLOCK_PULSE(offset, RDY);
+ temp = temp ^ CK;
+ if (inb(offset) & DI)
+ buf[k - start_addr] =
+ (buf[k - start_addr] << 1) | 0x1;
+ else
+ buf[k - start_addr] = (buf[k - start_addr]<< 1);
+ outb(offset, temp);
+ CLOCK_PULSE(offset, RDY);
+ }
+
+ /* Reset the chip select for the next command cycle. */
+ outb(offset, MS);
+ CLOCK_PULSE(offset, RDY);
+ outb(offset, MS | CK);
+ CLOCK_PULSE(offset, RDY);
+ outb(offset, MS);
+ CLOCK_PULSE(offset, RDY);
+ }
+#if 0
+ printf ("Serial EEPROM:");
+ for (k = 0; k < count; k = k + 1) {
+ if (((k % 8) == 0) && (k != 0))
+ {
+ printf ("\n ");
+ }
+ printf (" 0x%x", buf[k]);
+ }
+ printf ("\n");
+#endif
+ return (1);
+}
--- /dev/null
+/*
+ * Interface to the 93C46 serial EEPROM that is used to store BIOS
+ * settings for the aic7xxx based adaptec SCSI controllers. It can
+ * also be used for 93C26 and 93C06 serial EEPROMS.
+ *
+ * Copyright (c) 1994, 1995 Justin T. Gibbs.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice immediately at the beginning of the file, without modification,
+ * this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Absolutely no warranty of function or purpose is made by the author
+ * Justin T. Gibbs.
+ * 4. Modifications may be freely made to this file if the above conditions
+ * are met.
+ *
+ * $Id: 93cx6.h,v 1.1 1996/05/05 12:42:28 deraadt Exp $
+ */
+
+#include <sys/param.h>
+#if !defined(__NetBSD__)
+#include <sys/systm.h>
+#endif
+
+/*
+ * This function will read count 16-bit words from the serial EEPROM and
+ * return their value in buf. The port address of the aic7xxx serial EEPROM
+ * control register is passed in as offset. The following parameters are
+ * also passed in:
+ *
+ * CS - Chip select
+ * CK - Clock
+ * DO - Data out
+ * DI - Data in
+ * RDY - SEEPROM ready
+ * MS - Memory port mode select
+ *
+ * A failed read attempt returns 0, and a successful read returns 1.
+ */
+int read_seeprom (u_long offset,
+ u_short *buf,
+ u_int start_addr,
+ int count,
+ u_short CS,
+ u_short CK,
+ u_short DO,
+ u_short DI,
+ u_short RDY,
+ u_short MS);
-/* $OpenBSD: aic7xxx.c,v 1.4 1996/04/21 22:21:03 deraadt Exp $ */
-/* $NetBSD: aic7xxx.c,v 1.5 1996/03/29 00:24:58 mycroft Exp $ */
-
/*
* Generic driver for the aic7xxx based adaptec SCSI controllers
- * Copyright (c) 1994, 1995 Justin T. Gibbs.
- * All rights reserved.
- *
* Product specific probe and attach routines can be found in:
- * i386/isa/aic7770.c 27/284X and aic7770 motherboard controllers
- * /pci/aic7870.c 294x and aic7870 motherboard controllers
- *
- * Portions of this driver are based on the FreeBSD 1742 Driver:
+ * i386/eisa/aic7770.c 27/284X and aic7770 motherboard controllers
+ * pci/aic7870.c 3940, 2940, aic7870 and aic7850 controllers
*
- * Written by Julian Elischer (julian@tfs.com)
- * for TRW Financial Systems for use under the MACH(2.5) operating system.
+ * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs.
+ * All rights reserved.
*
- * TRW Financial Systems, in accordance with their agreement with Carnegie
- * Mellon University, makes this software available to CMU to distribute
- * or use in any manner that they see fit as long as this message is kept with
- * the software. For this reason TFS also grants any other persons or
- * organisations permission to use or modify this software.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice immediately at the beginning of the file, without modification,
+ * this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
*
- * TFS supplies this software to be publicly redistributed
- * on the understanding that TFS is not responsible for the correct
- * functioning of this software in any circumstances.
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
*
- * commenced: Sun Sep 27 18:14:01 PDT 1992
+ * $Id: aic7xxx.c,v 1.5 1996/05/05 12:42:29 deraadt Exp $
*/
/*
* TODO:
- * Add target reset capabilities
* Implement Target Mode
+ *
+ * A few notes on how SCB paging works...
+ *
+ * SCB paging takes advantage of the fact that devices stay disconnected
+ * from the bus a relatively long time and that while they're disconnected,
+ * having the SCBs for that device down on the host adapter is of little use.
+ * Instead we copy the SCB back up into kernel memory and reuse the SCB slot
+ * on the card to schedule another transaction. This can be a real payoff
+ * when doing random I/O to tagged queueing devices since there are more
+ * transactions active at once for the device to sort for optimal seek
+ * reduction. The algorithm goes like this...
+ *
+ * At the sequencer level:
+ * 1) Disconnected SCBs are threaded onto a doubly linked list, headed by
+ * DISCONNECTED_SCBH using the SCB_NEXT and SCB_PREV fields. The most
+ * recently disconnected device is always at the head.
+ *
+ * 2) The SCB has an added field SCB_TAG that corresponds to the kernel
+ * SCB number (ie 0-254).
+ *
+ * 3) When a command is queued, the hardware index of the SCB it was downloaded
+ * into is placed into the QINFIFO for easy indexing by the sequencer.
+ *
+ * 4) The tag field is used as the tag for tagged-queueing, for determining
+ * the related kernel SCB, and is the value put into the QOUTFIFO
+ * so the kernel doesn't have to upload the SCB to determine the kernel SCB
+ * that completed on command completes.
+ *
+ * 5) When a reconnect occurs, the sequencer must scan the SCB array (even
+ * in the tag case) looking for the appropriate SCB and if it can't find
+ * it, it interrupts the kernel so it can page the SCB in.
+ *
+ * 6) If the sequencer is successful in finding the SCB, it removes it from
+ * the doubly linked list of disconnected SCBS.
+ *
+ * At the kernel level:
+ * 1) There are four queues that a kernel SCB may reside on:
+ * free_scbs - SCBs that are not in use and have a hardware slot assigned
+ * to them.
+ * page_scbs - SCBs that are not in use and need to have a hardware slot
+ * assigned to them (i.e. they will most likely cause a page
+ * out event).
+ * waiting_scbs - SCBs that are active, don't have an assigned hardware
+ * slot assigned to them and are waiting for either a
+ * disconnection or a command complete to free up a slot.
+ * assigned_scbs - SCBs that were in the waiting_scbs queue, but were
+ * assigned a slot by ahc_free_scb.
+ *
+ * 2) When a new request comes in, an SCB is allocated from the free_scbs or
+ * page_scbs queue with preference to SCBs on the free_scbs queue.
+ *
+ * 3) If there are no free slots (we retrieved the SCB off of the page_scbs
+ * queue), the SCB is inserted onto the tail of the waiting_scbs list and
+ * we attempt to run this queue down.
+ *
+ * 4) ahc_run_waiing_queues() looks at both the assigned_scbs and waiting_scbs
+ * queues. In the case of the assigned_scbs, the commands are immediately
+ * downloaded and started. For waiting_scbs, we page in all that we can
+ * ensuring we don't create a resource deadlock (see comments in
+ * ahc_run_waing_queues()).
+ *
+ * 5) After we handle a bunch of command completes, we also try running the
+ * queues since many SCBs may have disconnected since the last command
+ * was started and we have at least one free slot on the card.
+ *
+ * 6) ahc_free_scb looks at the waiting_scbs queue for a transaction
+ * requiring a slot and moves it to the assigned_scbs queue if it
+ * finds one. Otherwise it puts the current SCB onto the free_scbs
+ * queue for later use.
+ *
+ * 7) The driver handles page-in requests from the sequencer in response to
+ * the NO_MATCH sequencer interrupt. For tagged commands, the approprite
+ * SCB is easily found since the tag is a direct index into our kernel SCB
+ * array. For non-tagged commands, we keep a separate array of 16 pointers
+ * that point to the single possible SCB that was paged out for that target.
*/
-#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
-#include <sys/kernel.h>
+#if defined(__NetBSD__)
#include <sys/device.h>
+#if NetBSD1_1 < 3
+#include <machine/pio.h>
+#else
+#include <machine/bus.h>
+#ifdef __alpha__
+#include <machine/intr.h>
+#endif
+#endif
+#endif /* defined(__NetBSD__) */
+
#include <sys/malloc.h>
#include <sys/buf.h>
#include <sys/proc.h>
-#include <sys/user.h>
-
-#include <machine/pio.h>
#include <scsi/scsi_all.h>
+#if defined(__NetBSD__)
#include <scsi/scsi_debug.h>
-#include <scsi/scsiconf.h>
-
-#include <dev/ic/aic7xxxvar.h>
-
-int ahc_init __P((struct ahc_softc *));
-void ahc_loadseq __P((int));
-int ahc_scsi_cmd __P((struct scsi_xfer *));
-void ahc_timeout __P((void *));
-void ahc_done __P((struct ahc_softc *, struct ahc_scb *));
-struct ahc_scb *ahc_get_scb __P((struct ahc_softc *, int));
-void ahc_free_scb __P((struct ahc_softc *, struct ahc_scb *, int));
-void ahc_abort_scb __P((struct ahc_softc *, struct ahc_scb *));
-void ahcminphys __P((struct buf *));
-int ahc_poll __P((struct ahc_softc *, struct scsi_xfer *, int));
-
-/* Different debugging levels */
-#ifdef AHC_DEBUG
-#define AHC_SHOWMISC 0x0001
-#define AHC_SHOWCMDS 0x0002
-#define AHC_SHOWSCBS 0x0004
-int ahc_debug = AHC_SHOWMISC;
#endif
+#include <scsi/scsiconf.h>
-#ifdef AHC_MORE_DEBUG
-#define DEBUGLEVEL -1
-#define DEBUGTARGET 0x0
+#if defined(__FreeBSD__)
+#include <machine/clock.h>
#endif
-/**** bit definitions for SCSIDEF ****/
-#define HSCSIID 0x07 /* our SCSI ID */
-#define HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
-
-struct scsi_adapter ahc_switch = {
- ahc_scsi_cmd,
- ahcminphys,
- 0,
- 0,
-};
-
-
-/* the below structure is so we have a default dev struct for our link struct */
-struct scsi_device ahc_dev = {
- NULL, /* Use default error handler */
- NULL, /* have a queue, served by this */
- NULL, /* have no async handler */
- NULL, /* Use default 'done' routine */
-};
-
-
-/*
- * All of these should be in a separate header file shared by the sequencer
- * code and the kernel level driver. The only catch is that we would need to
- * add an additional 0xc00 offset when using them in the kernel driver. The
- * aic7770 assembler must be modified to allow include files as well. All
- * page numbers refer to the Adaptec AIC-7770 Data Book available from
- * Adaptec's Technical Documents Department 1-800-934-2766
- */
-
-/* -------------------- AIC-7770 offset definitions ----------------------- */
-
-/*
- * SCSI Sequence Control (p. 3-11).
- * Each bit, when set starts a specific SCSI sequence on the bus
- */
-#define SCSISEQ 0xc00ul
-#define TEMODEO 0x80
-#define ENSELO 0x40
-#define ENSELI 0x20
-#define ENRSELI 0x10
-#define ENAUTOATNO 0x08
-#define ENAUTOATNI 0x04
-#define ENAUTOATNP 0x02
-#define SCSIRSTO 0x01
-
-/*
- * SCSI Transfer Control 1 Register (pp. 3-14,15).
- * Controls the SCSI module data path.
- */
-#define SXFRCTL1 0xc02ul
-#define BITBUCKET 0x80
-#define SWRAPEN 0x40
-#define ENSPCHK 0x20
-#define STIMESEL 0x18
-#define ENSTIMER 0x04
-#define ACTNEGEN 0x02
-#define STPWEN 0x01 /* Powered Termination */
-
-/*
- * SCSI Interrrupt Mode 1 (pp. 3-28,29).
- * Set bits in this register enable the corresponding
- * interrupt source.
- */
-#define SIMODE1 0xc11ul
-#define ENSELTIMO 0x80
-#define ENATNTARG 0x40
-#define ENSCSIRST 0x20
-#define ENPHASEMIS 0x10
-#define ENBUSFREE 0x08
-#define ENSCSIPERR 0x04
-#define ENPHASECHG 0x02
-#define ENREQINIT 0x01
-
-/*
- * SCSI Control Signal Read Register (p. 3-15).
- * Reads the actual state of the SCSI bus pins
- */
-#define SCSISIGI 0xc03ul
-#define CDI 0x80
-#define IOI 0x40
-#define MSGI 0x20
-#define ATNI 0x10
-#define SELI 0x08
-#define BSYI 0x04
-#define REQI 0x02
-#define ACKI 0x01
-
-/*
- * SCSI Contol Signal Write Register (p. 3-16).
- * Writing to this register modifies the control signals on the bus. Only
- * those signals that are allowed in the current mode (Initiator/Target) are
- * asserted.
- */
-#define SCSISIGO 0xc03ul
-#define CDO 0x80
-#define IOO 0x40
-#define MSGO 0x20
-#define ATNO 0x10
-#define SELO 0x08
-#define BSYO 0x04
-#define REQO 0x02
-#define ACKO 0x01
-
-/* XXX document this thing */
-#define SCSIRATE 0xc04ul
-
-/*
- * SCSI ID (p. 3-18).
- * Contains the ID of the board and the current target on the
- * selected channel
- */
-#define SCSIID 0xc05ul
-#define TID 0xf0 /* Target ID mask */
-#define OID 0x0f /* Our ID mask */
-
-/*
- * SCSI Status 0 (p. 3-21)
- * Contains one set of SCSI Interrupt codes
- * These are most likely of interest to the sequencer
- */
-#define SSTAT0 0xc0bul
-#define TARGET 0x80 /* Board is a target */
-#define SELDO 0x40 /* Selection Done */
-#define SELDI 0x20 /* Board has been selected */
-#define SELINGO 0x10 /* Selection In Progress */
-#define SWRAP 0x08 /* 24bit counter wrap */
-#define SDONE 0x04 /* STCNT = 0x000000 */
-#define SPIORDY 0x02 /* SCSI PIO Ready */
-#define DMADONE 0x01 /* DMA transfer completed */
-
-/*
- * Clear SCSI Interrupt 1 (p. 3-23)
- * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
- */
-#define CLRSINT1 0xc0cul
-#define CLRSELTIMEO 0x80
-#define CLRATNO 0x40
-#define CLRSCSIRSTI 0x20
-/* UNUSED 0x10 */
-#define CLRBUSFREE 0x08
-#define CLRSCSIPERR 0x04
-#define CLRPHASECHG 0x02
-#define CLRREQINIT 0x01
-
-/*
- * SCSI Status 1 (p. 3-24)
- * These interrupt bits are of interest to the kernel driver
- */
-#define SSTAT1 0xc0cul
-#define SELTO 0x80
-#define ATNTARG 0x40
-#define SCSIRSTI 0x20
-#define PHASEMIS 0x10
-#define BUSFREE 0x08
-#define SCSIPERR 0x04
-#define PHASECHG 0x02
-#define REQINIT 0x01
-
-/*
- * Selection/Reselection ID (p. 3-31)
- * Upper four bits are the device id. The ONEBIT is set when the re/selecting
- * device did not set its own ID.
- */
-#define SELID 0xc19ul
-#define SELID_MASK 0xf0
-#define ONEBIT 0x08
-/* UNUSED 0x07 */
-
-/*
- * SCSI Block Control (p. 3-32)
- * Controls Bus type and channel selection. In a twin channel configuration
- * addresses 0x00-0x1e are gated to the appropriate channel based on this
- * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
- * on a wide bus.
- */
-#define SBLKCTL 0xc1ful
-/* UNUSED 0xc0 */
-#define AUTOFLUSHDIS 0x20
-/* UNUSED 0x10 */
-#define SELBUSB 0x08
-/* UNUSED 0x04 */
-#define SELWIDE 0x02
-/* UNUSED 0x01 */
-
-/*
- * Sequencer Control (p. 3-33)
- * Error detection mode and speed configuration
- */
-#define SEQCTL 0xc60ul
-#define PERRORDIS 0x80
-#define PAUSEDIS 0x40
-#define FAILDIS 0x20
-#define FASTMODE 0x10
-#define BRKADRINTEN 0x08
-#define STEP 0x04
-#define SEQRESET 0x02
-#define LOADRAM 0x01
-
-/*
- * Sequencer RAM Data (p. 3-34)
- * Single byte window into the Scratch Ram area starting at the address
- * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
- * four bytes in sucessesion. The SEQADDRs will increment after the most
- * significant byte is written
- */
-#define SEQRAM 0xc61ul
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
-/*
- * Sequencer Address Registers (p. 3-35)
- * Only the first bit of SEQADDR1 holds addressing information
- */
-#define SEQADDR0 0xc62ul
-#define SEQADDR1 0xc63ul
-#define SEQADDR1_MASK 0x01
+#if defined(__FreeBSD__)
+#include <i386/scsi/aic7xxx.h>
-/*
- * Accumulator
- * We cheat by passing arguments in the Accumulator up to the kernel driver
- */
-#define ACCUM 0xc64ul
+#include <dev/aic7xxx/aic7xxx_reg.h>
-#define SINDEX 0xc65ul
+#define AHCNAME_FMT "ahc%d"
+#define AHCNAME_VAR(ahc) (ahc)->unit
+#endif /* defined(__FreeBSD__) */
-/*
- * Board Control (p. 3-43)
- */
-#define BCTL 0xc84ul
-/* RSVD 0xf0 */
-#define ACE 0x08 /* Support for external processors */
-/* RSVD 0x06 */
-#define ENABLE 0x01
+#if defined(__NetBSD__)
+#include <dev/ic/aic7xxxvar.h>
+#include <dev/microcode/aic7xxx/aic7xxx_reg.h>
-/*
- * Host Control (p. 3-47) R/W
- * Overal host control of the device.
- */
-#define HCNTRL 0xc87ul
-/* UNUSED 0x80 */
-#define POWRDN 0x40
-/* UNUSED 0x20 */
-#define SWINT 0x10
-#define IRQMS 0x08
-#define PAUSE 0x04
-#define INTEN 0x02
-#define CHIPRST 0x01
+#define bootverbose 1
-/*
- * SCB Pointer (p. 3-49)
- * Gate one of the four SCBs into the SCBARRAY window.
- */
-#define SCBPTR 0xc90ul
+#define DEBUGTARG DEBUGTARGET
+#if DEBUGTARG < 0 /* Negative numbrs for disabling cause warnings */
+#undef DEBUGTARG
+#define DEBUGTARG 9
+#endif
-/*
- * Interrupt Status (p. 3-50)
- * Status for system interrupts
- */
-#define INTSTAT 0xc91ul
-#define SEQINT_MASK 0xf0 /* SEQINT Status Codes */
-#define BAD_PHASE 0x00
-#define SEND_REJECT 0x10
-#define NO_IDENT 0x20
-#define NO_MATCH 0x30
-#define MSG_SDTR 0x40
-#define MSG_WDTR 0x50
-#define MSG_REJECT 0x60
-#define BAD_STATUS 0x70
-#define RESIDUAL 0x80
-#define ABORT_TAG 0x90
-#define BRKADRINT 0x08
-#define SCSIINT 0x04
-#define CMDCMPLT 0x02
-#define SEQINT 0x01
-#define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
+#define AHCNAME_FMT "%s"
+#define AHCNAME_VAR(ahc) (ahc)->sc_dev.dv_xname
+#endif /* defined(__NetBSD__) */
-/*
- * Hard Error (p. 3-53)
- * Reporting of catastrophic errors. You usually cannot recover from
- * these without a full board reset.
- */
-#define ERROR 0xc92ul
-/* UNUSED 0xf0 */
-#define PARERR 0x08
-#define ILLOPCODE 0x04
-#define ILLSADDR 0x02
-#define ILLHADDR 0x01
+#define PAGESIZ NBPG
-/*
- * Clear Interrupt Status (p. 3-52)
- */
-#define CLRINT 0xc92ul
-#define CLRBRKADRINT 0x08
-#define CLRSCSIINT 0x04
-#define CLRCMDINT 0x02
-#define CLRSEQINT 0x01
+#include <sys/kernel.h>
+#define KVTOPHYS(x) vtophys(x)
-/*
- * SCB Auto Increment (p. 3-59)
- * Byte offset into the SCB Array and an optional bit to allow auto
- * incrementing of the address during download and upload operations
- */
-#define SCBCNT 0xc9aul
-#define SCBAUTO 0x80
-#define SCBCNT_MASK 0x1f
+#define MIN(a,b) ((a < b) ? a : b)
+#define ALL_TARGETS -1
-/*
- * Queue In FIFO (p. 3-60)
- * Input queue for queued SCBs (commands that the seqencer has yet to start)
- */
-#define QINFIFO 0xc9bul
+u_long ahc_unit = 0;
-/*
- * Queue In Count (p. 3-60)
- * Number of queued SCBs
- */
-#define QINCNT 0xc9cul
+#ifdef AHC_DEBUG
+static int ahc_debug = AHC_SHOWSENSE;
+#endif
-/*
- * Queue Out FIFO (p. 3-61)
- * Queue of SCBs that have completed and await the host
- */
-#define QOUTFIFO 0xc9dul
+#ifdef AIC7XXX_BROKEN_CACHE
+int aic7xxx_broken_cache = 1;
/*
- * Queue Out Count (p. 3-61)
- * Number of queued SCBs in the Out FIFO
+ * "wbinvd" cause writing back whole cache (both CPU internal & external)
+ * to memory, so that the instruction takes a lot of time.
+ * This makes machine slow.
*/
-#define QOUTCNT 0xc9eul
-
-#define SCBARRAY 0xca0ul
-
-/* ---------------- END AIC-7770 Register Definitions ----------------- */
-
-/* --------------------- AIC-7870-only definitions -------------------- */
+#define INVALIDATE_CACHE() __asm __volatile("wbinvd")
+#endif
-#define DSPCISTATUS 0xc86ul
+/**** bit definitions for SCSIDEF ****/
+#define HSCSIID 0x07 /* our SCSI ID */
+#define HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
-/* ---------------------- Scratch RAM Offsets ------------------------- */
-/* These offsets are either to values that are initialized by the board's
- * BIOS or are specified by the Linux sequencer code. If I can figure out
- * how to read the EISA configuration info at probe time, the cards could
- * be run without BIOS support installed
- */
+static void ahcminphys __P((struct buf *bp));
+static int32_t ahc_scsi_cmd __P((struct scsi_xfer *xs));
-/*
- * 1 byte per target starting at this address for configuration values
- */
-#define HA_TARG_SCRATCH 0xc20ul
+static struct scsi_adapter ahc_switch =
+{
+ ahc_scsi_cmd,
+ ahcminphys,
+ 0,
+ 0,
+#if defined(__FreeBSD__)
+ 0,
+ "ahc",
+ { 0, 0 }
+#endif
+};
-/*
- * The sequencer will stick the frist byte of any rejected message here so
- * we can see what is getting thrown away.
- */
-#define HA_REJBYTE 0xc31ul
+/* the below structure is so we have a default dev struct for our link struct */
+static struct scsi_device ahc_dev =
+{
+ NULL, /* Use default error handler */
+ NULL, /* have a queue, served by this */
+ NULL, /* have no async handler */
+ NULL, /* Use default 'done' routine */
+#if defined(__FreeBSD__)
+ "ahc",
+ 0,
+ { 0, 0 }
+#endif
+};
/*
- * Length of pending message
+ * Since the sequencer can disable pausing in a critical section, we
+ * must loop until it actually stops.
+ * XXX Should add a timeout in here??
*/
-#define HA_MSG_LEN 0xc34ul
+#define PAUSE_SEQUENCER(ahc) \
+ outb(HCNTRL + ahc->baseport, ahc->pause); \
+ \
+ while ((inb(HCNTRL + ahc->baseport) & PAUSE) == 0) \
+ ;
-/*
- * message body
- */
-#define HA_MSG_START 0xc35ul /* outgoing message body */
+#define UNPAUSE_SEQUENCER(ahc) \
+ outb( HCNTRL + ahc->baseport, ahc->unpause )
/*
- * These are offsets into the card's scratch ram. Some of the values are
- * specified in the AHA2742 technical reference manual and are initialized
- * by the BIOS at boot time.
+ * Restart the sequencer program from address zero
*/
-#define HA_ARG_1 0xc4aul
-#define HA_RETURN_1 0xc4aul
-#define SEND_SENSE 0x80
-#define SEND_WDTR 0x80
-#define SEND_SDTR 0x80
-#define SEND_REJ 0x40
-
-#define HA_SIGSTATE 0xc4bul
-
-#define HA_SCBCOUNT 0xc52ul
-#define HA_FLAGS 0xc53ul
-#define SINGLE_BUS 0x00
-#define TWIN_BUS 0x01
-#define WIDE_BUS 0x02
-#define ACTIVE_MSG 0x20
-#define IDENTIFY_SEEN 0x40
-#define RESELECTING 0x80
-
-#define HA_ACTIVE0 0xc54ul
-#define HA_ACTIVE1 0xc55ul
-#define SAVED_TCL 0xc56ul
-#define WAITING_SCBH 0xc57ul
-#define WAITING_SCBT 0xc58ul
-
-#define HA_SCSICONF 0xc5aul
-#define INTDEF 0xc5cul
-#define HA_HOSTCONF 0xc5dul
-
-#define MSG_ABORT 0x06
-#define BUS_8_BIT 0x00
-#define BUS_16_BIT 0x01
-#define BUS_32_BIT 0x02
+#define RESTART_SEQUENCER(ahc) \
+ do { \
+ outb( SEQCTL + ahc->baseport, SEQRESET|FASTMODE ); \
+ } while (inb(SEQADDR0 + ahc->baseport) != 0 && \
+ inb(SEQADDR1 + ahc->baseport) != 0); \
+ \
+ UNPAUSE_SEQUENCER(ahc);
+#if defined(__NetBSD__)
/*
- * Since the sequencer can disable pausing in a critical section, we
- * must loop until it actually stops.
- * XXX Should add a timeout in here??
+ * Is device which is pointed by sc_link connected on second scsi bus ?
*/
-#define PAUSE_SEQUENCER(ahc) \
- do { \
- outb(HCNTRL + ahc->sc_iobase, ahc->pause); \
- while ((inb(HCNTRL + ahc->sc_iobase) & PAUSE) == 0) \
- ; \
- } while (0)
-
-#define UNPAUSE_SEQUENCER(ahc) \
- do { \
- outb(HCNTRL + ahc->sc_iobase, ahc->unpause); \
- } while (0)
+#define IS_SCSIBUS_B(ahc, sc_link) \
+ ((sc_link)->scsibus == (ahc)->sc_link_b.scsibus)
/*
- * Restart the sequencer program from address zero
- * XXX Should add a timeout in here??
+ * convert FreeBSD's SCSI symbols to NetBSD's
*/
-#define RESET_SEQUENCER(ahc) \
- do { \
- do { \
- outb(SEQCTL + ahc->sc_iobase, SEQRESET|FASTMODE); \
- } while (inb(SEQADDR0 + ahc->sc_iobase) != 0 && \
- inb(SEQADDR1 + ahc->sc_iobase) != 0); \
- } while (0)
+#define SCSI_NOMASK SCSI_POLL
+#define opennings openings
+#endif
-#define RESTART_SEQUENCER(ahc) \
- do { \
- RESET_SEQUENCER(ahc); \
- UNPAUSE_SEQUENCER(ahc); \
- } while (0)
+static u_char ahc_abort_wscb __P((struct ahc_data *ahc, struct scb *scbp,
+ u_char prev, u_long iobase,
+ u_char timedout_scb, u_int32_t xs_error));
+static void ahc_add_waiting_scb __P((u_long iobase, struct scb *scb));
+static void ahc_done __P((struct ahc_data *ahc, struct scb *scbp));
+static void ahc_free_scb __P((struct ahc_data *ahc, struct scb *scb,
+ int flags));
+static inline void ahc_send_scb __P((struct ahc_data *ahc, struct scb *scb));
+static inline void ahc_fetch_scb __P((struct ahc_data *ahc, struct scb *scb));
+static inline void ahc_page_scb __P((struct ahc_data *ahc, struct scb *out_scb,
+ struct scb *in_scb));
+static inline void ahc_run_waiting_queues __P((struct ahc_data *ahc));
+static struct scb *
+ ahc_get_scb __P((struct ahc_data *ahc, int flags));
+static void ahc_loadseq __P((u_long iobase));
+static int ahc_match_scb __P((struct scb *scb, int target, char channel));
+static int ahc_poll __P((struct ahc_data *ahc, int wait));
+#ifdef AHC_DEBUG
+static void ahc_print_scb __P((struct scb *scb));
+#endif
+static int ahc_reset_channel __P((struct ahc_data *ahc, char channel,
+ u_char timedout_scb, u_int32_t xs_error,
+ u_char initiate_reset));
+static int ahc_reset_device __P((struct ahc_data *ahc, int target,
+ char channel, u_char timedout_scb,
+ u_int32_t xs_error));
+static void ahc_reset_current_bus __P((u_long iobase));
+static void ahc_run_done_queue __P((struct ahc_data *ahc));
+static void ahc_scsirate __P((struct ahc_data* ahc, u_char *scsirate,
+ int period, int offset, int target));
+#if defined(__FreeBSD__)
+static timeout_t
+ ahc_timeout;
+#elif defined(__NetBSD__)
+static void ahc_timeout __P((void *));
+#endif
+static void ahc_busy_target __P((int target, char channel,
+ u_long iobase));
+static void ahc_unbusy_target __P((int target, char channel,
+ u_long iobase));
#ifdef AHC_DEBUG
-void
+static void
ahc_print_scb(scb)
- struct ahc_scb *scb;
+ struct scb *scb;
{
-
- printf("scb:0x%x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%x\n",
- scb,
- scb->control,
- scb->target_channel_lun,
- scb->cmdlen,
- scb->cmdpointer);
- printf("\tdatlen:%d data:0x%x res:0x%x segs:0x%x segp:0x%x\n",
- scb->datalen[2] << 16 | scb->datalen[1] << 8 | scb->datalen[0],
- scb->data,
- scb->RESERVED[1] << 8 | scb->RESERVED[0],
- scb->SG_segment_count,
- scb->SG_list_pointer);
- printf("\tsg_addr:%x sg_len:%d\n",
- scb->ahc_dma[0].seg_addr,
- scb->ahc_dma[0].seg_len);
- printf(" size:%d\n",
- (int)&scb->next_waiting - (int)scb);
+ printf("scb:%p control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n"
+ ,scb
+ ,scb->control
+ ,scb->tcl
+ ,scb->cmdlen
+ ,scb->cmdpointer );
+ printf(" datlen:%d data:0x%lx segs:0x%x segp:0x%lx\n"
+ ,scb->datalen
+ ,scb->data
+ ,scb->SG_segment_count
+ ,scb->SG_list_pointer);
+ printf(" sg_addr:%lx sg_len:%ld\n"
+ ,scb->ahc_dma[0].addr
+ ,scb->ahc_dma[0].len);
}
-void
-ahc_print_active_scb(ahc)
- struct ahc_softc *ahc;
-{
- int iobase = ahc->sc_iobase;
- int scb_index;
-
- PAUSE_SEQUENCER(ahc);
- scb_index = inb(SCBPTR + iobase);
- UNPAUSE_SEQUENCER(ahc);
-
- ahc_print_scb(ahc->scbarray[scb_index]);
-}
#endif
-#define PARERR 0x08
-#define ILLOPCODE 0x04
-#define ILLSADDR 0x02
-#define ILLHADDR 0x01
-
static struct {
- u_char errno;
+ u_char errno;
char *errmesg;
} hard_error[] = {
{ ILLHADDR, "Illegal Host Access" },
* stick in the scsiscfr reg to use that transfer rate.
*/
static struct {
- u_char sxfr;
- int period; /* in ns */
+ short sxfr;
+ /* Rates in Ultra mode have bit 8 of sxfr set */
+#define ULTRA_SXFR 0x100
+ short period; /* in ns */
char *rate;
} ahc_syncrates[] = {
- { 0x00, 100, "10.0" },
- { 0x10, 125, "8.0" },
- { 0x20, 150, "6.67" },
- { 0x30, 175, "5.7" },
- { 0x40, 200, "5.0" },
- { 0x50, 225, "4.4" },
- { 0x60, 250, "4.0" },
- { 0x70, 275, "3.6" }
+ { 0x100, 50, "20.0" },
+ { 0x110, 62, "16.0" },
+ { 0x120, 75, "13.4" },
+ { 0x130, 87, "11.4" },
+ { 0x140, 100, "10.0" },
+ { 0x150, 112, "8.8" },
+ { 0x160, 125, "8.0" },
+ { 0x170, 137, "7.2" },
+ { 0x000, 100, "10.0" },
+ { 0x010, 125, "8.0" },
+ { 0x020, 150, "6.67" },
+ { 0x030, 175, "5.7" },
+ { 0x040, 200, "5.0" },
+ { 0x050, 225, "4.4" },
+ { 0x060, 250, "4.0" },
+ { 0x070, 275, "3.6" }
};
static int ahc_num_syncrates =
sizeof(ahc_syncrates) / sizeof(ahc_syncrates[0]);
/*
- * Check if the device can be found at the port given
- * and if so, determine configuration and set it up for further work.
+ * Allocate a controller structures for a new device and initialize it.
+ * ahc_reset should be called before now since we assume that the card
+ * is paused.
+ *
*/
-
-int
-ahcprobe(ahc, iobase)
- struct ahc_softc *ahc;
- int iobase;
+#if defined(__FreeBSD__)
+struct ahc_data *
+ahc_alloc(unit, iobase, type, flags)
+ u_long iobase;
+#elif defined(__NetBSD__)
+void
+ahc_construct(ahc, unit, bc, iobase, type, flags)
+ struct ahc_data *ahc;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t iobase; /* XXX - ioh */
+#endif
+ int unit;
+ ahc_type type;
+ ahc_flag flags;
{
- ahc->sc_iobase = iobase;
+ /*
+ * find unit and check we have that many defined
+ */
+
+#if defined(__FreeBSD__)
+ struct ahc_data *ahc;
/*
- * Try to initialize a unit at this location
- * reset the AIC-7770, read its registers,
- * and fill in the dev structure accordingly
+ * Allocate a storage area for us
*/
- if (ahc_init(ahc) != 0)
- return (0);
+ ahc = malloc(sizeof(struct ahc_data), M_TEMP, M_NOWAIT);
+ if (!ahc) {
+ printf("ahc%d: cannot malloc!\n", unit);
+ return NULL;
+ }
+ bzero(ahc, sizeof(struct ahc_data));
+#endif
+ STAILQ_INIT(&ahc->free_scbs);
+ STAILQ_INIT(&ahc->page_scbs);
+ STAILQ_INIT(&ahc->waiting_scbs);
+ STAILQ_INIT(&ahc->assigned_scbs);
+ ahc->unit = unit;
+#if defined(__NetBSD__)
+ ahc->sc_bc = bc;
+#endif
+ ahc->baseport = iobase;
+ ahc->type = type;
+ ahc->flags = flags;
+ ahc->unpause = (inb(HCNTRL + iobase) & IRQMS) | INTEN;
+ ahc->pause = ahc->unpause | PAUSE;
+
+#if defined(__FreeBSD__)
+ return (ahc);
+#endif
+}
- return (1);
+void
+ahc_free(ahc)
+ struct ahc_data *ahc;
+{
+#if defined(__FreeBSD__)
+ free(ahc, M_DEVBUF);
+ return;
+#endif
}
+void
+#if defined(__FreeBSD__)
+ahc_reset(iobase)
+ u_long iobase;
+#elif defined(__NetBSD__)
+ahc_reset(devname, bc, iobase)
+ char *devname;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t iobase; /* XXX - ioh */
+#endif
+{
+ u_char hcntrl;
+ int wait;
+
+ /* Retain the IRQ type accross the chip reset */
+ hcntrl = (inb(HCNTRL + iobase) & IRQMS) | INTEN;
+ outb(HCNTRL + iobase, CHIPRST | PAUSE);
+ /*
+ * Ensure that the reset has finished
+ */
+ wait = 1000;
+ while (wait--) {
+ DELAY(1000);
+ if(!(inb(HCNTRL + iobase) & CHIPRST))
+ break;
+ }
+ if(wait == 0) {
+#if defined(__FreeBSD__)
+ printf("ahc at 0x%lx: WARNING - Failed chip reset! "
+ "Trying to initialize anyway.\n", iobase);
+#elif defined(__NetBSD__)
+ printf("%s: WARNING - Failed chip reset! "
+ "Trying to initialize anyway.\n", devname);
+#endif
+ }
+ outb(HCNTRL + iobase, hcntrl | PAUSE);
+}
/*
* Look up the valid period to SCSIRATE conversion in our table.
*/
-static u_char
-ahc_scsirate(offset, period, ahc, target)
- u_char offset;
- int period;
- struct ahc_softc *ahc;
- int target;
+static void
+ahc_scsirate(ahc, scsirate, period, offset, target )
+ struct ahc_data *ahc;
+ u_char *scsirate;
+ short period;
+ u_char offset;
+ int target;
{
int i;
for (i = 0; i < ahc_num_syncrates; i++) {
+
if ((ahc_syncrates[i].period - period) >= 0) {
- printf("%s: target %d synchronous at %sMB/s, "
- "offset = %d\n",
- ahc->sc_dev.dv_xname, target,
- ahc_syncrates[i].rate, offset);
-#ifdef AHC_DEBUG
-#endif /* AHC_DEBUG */
- return ((ahc_syncrates[i].sxfr) | (offset & 0x0f));
+ /*
+ * Watch out for Ultra speeds when ultra is not
+ * enabled and vice-versa.
+ */
+ if (ahc->type & AHC_ULTRA) {
+ if (!(ahc_syncrates[i].sxfr & ULTRA_SXFR)) {
+ printf(AHCNAME_FMT
+ ": target %d requests "
+ "%sMHz transfers, but adapter "
+ "in Ultra mode can only sync at "
+ "7.2MHz or above\n",
+ AHCNAME_VAR(ahc),
+ target, ahc_syncrates[i].rate);
+ break; /* Use Async */
+ }
+ }
+ else {
+ if (ahc_syncrates[i].sxfr & ULTRA_SXFR) {
+ /*
+ * This should only happen if the
+ * drive is the first to negotiate
+ * and chooses a high rate. We'll
+ * just move down the table util
+ * we hit a non ultra speed.
+ */
+ continue;
+ }
+ }
+ *scsirate = (ahc_syncrates[i].sxfr) | (offset & 0x0f);
+ if(bootverbose) {
+ printf(AHCNAME_FMT
+ ": target %d synchronous at %sMHz,"
+ " offset = 0x%x\n",
+ AHCNAME_VAR(ahc), target,
+ ahc_syncrates[i].rate, offset );
+ }
+ return;
}
}
-
/* Default to asyncronous transfers. Also reject this SDTR request. */
- printf("%s: target %d using asyncronous transfers\n",
- ahc->sc_dev.dv_xname, target);
- return (0);
-#ifdef AHC_DEBUG
-#endif /* AHC_DEBUG */
+ *scsirate = 0;
+ if(bootverbose) {
+ printf(AHCNAME_FMT ": target %d using asyncronous transfers\n",
+ AHCNAME_VAR(ahc), target );
+ }
}
+#if defined(__NetBSD__)
int
ahcprint(aux, name)
void *aux;
printf("%s: scsibus ", name);
return UNCONF;
}
+#endif
/*
* Attach all the sub-devices we can find
*/
int
-ahcattach(ahc)
- struct ahc_softc *ahc;
+ahc_attach(ahc)
+ struct ahc_data *ahc;
{
+ struct scsibus_data *scbus;
- TAILQ_INIT(&ahc->free_scb);
-
+#ifdef AIC7XXX_BROKEN_CACHE
+ if (cpu_class == CPUCLASS_386) /* doesn't have "wbinvd" instruction */
+ aic7xxx_broken_cache = 0;
+#endif
/*
* fill in the prototype scsi_link.
*/
+#if defined(__FreeBSD__)
+ ahc->sc_link.adapter_unit = ahc->unit;
+ ahc->sc_link.adapter_targ = ahc->our_id;
+ ahc->sc_link.fordriver = 0;
+#elif defined(__NetBSD__)
+ ahc->sc_link.adapter_target = ahc->our_id;
+#endif
ahc->sc_link.adapter_softc = ahc;
- ahc->sc_link.adapter_target = ahc->ahc_scsi_dev;
ahc->sc_link.adapter = &ahc_switch;
+ ahc->sc_link.opennings = 2;
ahc->sc_link.device = &ahc_dev;
- ahc->sc_link.openings = 1;
ahc->sc_link.flags = DEBUGLEVEL;
- ahc->sc_link.quirks = 0;
+
+ /*
+ * Prepare the scsibus_data area for the upperlevel
+ * scsi code.
+ */
+#if defined(__FreeBSD__)
+ scbus = scsi_alloc_bus();
+ if(!scbus)
+ return 0;
+ scbus->adapter_link = &ahc->sc_link;
+ if(ahc->type & AHC_WIDE)
+ scbus->maxtarg = 15;
+#elif defined(__NetBSD__)
+ /*
+ * XXX - Update MI SCSI code
+ *
+ * if(ahc->type & AHC_WIDE)
+ * XXX max target XXX = 15;
+ */
+#endif
/*
* ask the adapter what subunits are present
*/
+#if defined(__FreeBSD__)
+ if(bootverbose)
+ printf("ahc%d: Probing channel A\n", ahc->unit);
+ scsi_attachdevs(scbus);
+ scbus = NULL; /* Upper-level SCSI code owns this now */
+#elif defined(__NetBSD__)
+ ahc->sc_link_b.scsibus = 0xff; /* for IS_SCSIBUS_B(), never match */
+
printf("%s: Probing channel A\n", ahc->sc_dev.dv_xname);
config_found((void *)ahc, &ahc->sc_link, ahcprint);
- if (ahc->type & AHC_TWIN) {
+#endif
+ if(ahc->type & AHC_TWIN) {
/* Configure the second scsi bus */
ahc->sc_link_b = ahc->sc_link;
- /* XXXX Didn't do this before. */
- ahc->sc_link_b.adapter_target = ahc->ahc_scsi_dev_b;
- ahc->sc_link_b.quirks = 0x0008; /**/
+#if defined(__FreeBSD__)
+ ahc->sc_link_b.adapter_targ = ahc->our_id_b;
+ ahc->sc_link_b.adapter_bus = 1;
+ ahc->sc_link_b.fordriver = (void *)SELBUSB;
+ scbus = scsi_alloc_bus();
+ if(!scbus)
+ return 0;
+ scbus->adapter_link = &ahc->sc_link_b;
+ if(ahc->type & AHC_WIDE)
+ scbus->maxtarg = 15;
+ if(bootverbose)
+ printf("ahc%d: Probing Channel B\n", ahc->unit);
+ scsi_attachdevs(scbus);
+ scbus = NULL; /* Upper-level SCSI code owns this now */
+#elif defined(__NetBSD__)
+ /*
+ * XXX - Update MI SCSI code
+ *
+ * if(ahc->type & AHC_WIDE)
+ * XXX max target XXX = 15;
+ */
+ ahc->sc_link_b.adapter_target = ahc->our_id_b;
printf("%s: Probing channel B\n", ahc->sc_dev.dv_xname);
config_found((void *)ahc, &ahc->sc_link_b, ahcprint);
+#endif
}
-
return 1;
}
-void
+/*
+ * Send an SCB down to the card via PIO.
+ * We assume that the proper SCB is already selected in SCBPTR.
+ */
+static inline void
ahc_send_scb(ahc, scb)
- struct ahc_softc *ahc;
- struct ahc_scb *scb;
+ struct ahc_data *ahc;
+ struct scb *scb;
{
- int iobase = ahc->sc_iobase;
+ u_long iobase = ahc->baseport;
- PAUSE_SEQUENCER(ahc);
- outb(QINFIFO + iobase, scb->position);
- UNPAUSE_SEQUENCER(ahc);
+ outb(SCBCNT + iobase, SCBAUTO);
+ if( ahc->type == AHC_284 )
+ /* Can only do 8bit PIO */
+ outsb(SCBARRAY+iobase, scb, SCB_PIO_TRANSFER_SIZE);
+ else
+ outsl(SCBARRAY+iobase, scb,
+ (SCB_PIO_TRANSFER_SIZE + 3) / 4);
+ outb(SCBCNT + iobase, 0);
}
-static void
-ahc_getscb(iobase, scb)
- int iobase;
- struct ahc_scb *scb;
+/*
+ * Retrieve an SCB from the card via PIO.
+ * We assume that the proper SCB is already selected in SCBPTR.
+ */
+static inline void
+ahc_fetch_scb(ahc, scb)
+ struct ahc_data *ahc;
+ struct scb *scb;
{
+ u_long iobase = ahc->baseport;
+
+ outb(SCBCNT + iobase, 0x80); /* SCBAUTO */
+
+ /* Can only do 8bit PIO for reads */
+ insb(SCBARRAY+iobase, scb, SCB_PIO_TRANSFER_SIZE);
- outb(SCBCNT + iobase, SCBAUTO);
- insb(SCBARRAY + iobase, scb, SCB_UP_SIZE);
outb(SCBCNT + iobase, 0);
}
/*
- * Catch an interrupt from the adaptor
+ * Swap in_scbp for out_scbp down in the cards SCB array.
+ * We assume that the SCB for out_scbp is already selected in SCBPTR.
*/
-int
-ahcintr(ahc)
- struct ahc_softc *ahc;
+static inline void
+ahc_page_scb(ahc, out_scbp, in_scbp)
+ struct ahc_data *ahc;
+ struct scb *out_scbp;
+ struct scb *in_scbp;
{
- int iobase = ahc->sc_iobase;
- u_char intstat = inb(INTSTAT + iobase);
- u_char status;
- struct ahc_scb *scb = NULL;
+ /* Page-out */
+ ahc_fetch_scb(ahc, out_scbp);
+ out_scbp->flags |= SCB_PAGED_OUT;
+ if(!(out_scbp->control & TAG_ENB))
+ {
+ /* Stick in non-tagged array */
+ int index = (out_scbp->tcl >> 4)
+ | (out_scbp->tcl & SELBUSB);
+ ahc->pagedout_ntscbs[index] = out_scbp;
+ }
+
+ /* Page-in */
+ in_scbp->position = out_scbp->position;
+ out_scbp->position = SCB_LIST_NULL;
+ ahc_send_scb(ahc, in_scbp);
+ in_scbp->flags &= ~SCB_PAGED_OUT;
+}
+
+static inline void
+ahc_run_waiting_queues(ahc)
+ struct ahc_data *ahc;
+{
+ struct scb* scb;
+ u_char cur_scb;
+ u_long iobase = ahc->baseport;
+
+ if(!(ahc->assigned_scbs.stqh_first || ahc->waiting_scbs.stqh_first))
+ return;
+
+ PAUSE_SEQUENCER(ahc);
+ cur_scb = inb(SCBPTR + iobase);
+
+ /*
+ * First handle SCBs that are waiting but have been
+ * assigned a slot.
+ */
+ while((scb = ahc->assigned_scbs.stqh_first) != NULL) {
+ STAILQ_REMOVE_HEAD(&ahc->assigned_scbs, links);
+ outb(SCBPTR + iobase, scb->position);
+ ahc_send_scb(ahc, scb);
+
+ /* Mark this as an active command */
+ scb->flags = SCB_ACTIVE;
+
+ outb(QINFIFO + iobase, scb->position);
+ if (!(scb->xs->flags & SCSI_NOMASK)) {
+ timeout(ahc_timeout, (caddr_t)scb,
+ (scb->xs->timeout * hz) / 1000);
+ }
+ SC_DEBUG(scb->xs->sc_link, SDEV_DB3, ("cmd_sent\n"));
+ }
+ /* Now deal with SCBs that require paging */
+ if((scb = ahc->waiting_scbs.stqh_first) != NULL) {
+ u_char disc_scb = inb(DISCONNECTED_SCBH + iobase);
+ u_char active = inb(FLAGS+iobase) & (SELECTED|IDENTIFY_SEEN);
+ int count = 0;
+
+ do {
+ u_char next_scb;
+
+ /* Attempt to page this SCB in */
+ if(disc_scb == SCB_LIST_NULL)
+ break;
+
+ /*
+ * Advance disc_scb to the next on in the
+ * list.
+ */
+ outb(SCBPTR + iobase, disc_scb);
+ next_scb = inb(SCB_NEXT + iobase);
+
+ /*
+ * We have to be careful about when we allow
+ * an SCB to be paged out. There must always
+ * be at least one slot availible for a
+ * reconnecting target in case it references
+ * an SCB that has been paged out. Our
+ * heuristic is that either the disconnected
+ * list has at least two entries in it or
+ * there is one entry and the sequencer is
+ * activily working on an SCB which implies that
+ * it will either complete or disconnect before
+ * another reconnection can occur.
+ */
+ if((next_scb != SCB_LIST_NULL) || active)
+ {
+ u_char out_scbi;
+ struct scb* out_scbp;
+
+ STAILQ_REMOVE_HEAD(&ahc->waiting_scbs, links);
+
+ /*
+ * Find the in-core SCB for the one
+ * we're paging out.
+ */
+ out_scbi = inb(SCB_TAG + iobase);
+ out_scbp = ahc->scbarray[out_scbi];
+
+ /* Do the page out */
+ ahc_page_scb(ahc, out_scbp, scb);
+
+ /* Mark this as an active command */
+ scb->flags = SCB_ACTIVE;
+
+ /* Queue the command */
+ outb(QINFIFO + iobase, scb->position);
+ if (!(scb->xs->flags & SCSI_NOMASK)) {
+ timeout(ahc_timeout, (caddr_t)scb,
+ (scb->xs->timeout * hz) / 1000);
+ }
+ SC_DEBUG(scb->xs->sc_link, SDEV_DB3,
+ ("cmd_paged-in\n"));
+ count++;
+
+ /* Advance to the next disconnected SCB */
+ disc_scb = next_scb;
+ }
+ else
+ break;
+ } while((scb = ahc->waiting_scbs.stqh_first) != NULL);
+
+ if(count) {
+ /*
+ * Update the head of the disconnected list.
+ */
+ outb(DISCONNECTED_SCBH + iobase, disc_scb);
+ if(disc_scb != SCB_LIST_NULL) {
+ outb(SCBPTR + iobase, disc_scb);
+ outb(SCB_PREV + iobase, SCB_LIST_NULL);
+ }
+ }
+ }
+ /* Restore old position */
+ outb(SCBPTR + iobase, cur_scb);
+ UNPAUSE_SEQUENCER(ahc);
+}
+
+/*
+ * Add this SCB to the head of the "waiting for selection" list.
+ */
+static
+void ahc_add_waiting_scb (iobase, scb)
+ u_long iobase;
+ struct scb *scb;
+{
+ u_char next;
+ u_char curscb;
+
+ curscb = inb(SCBPTR + iobase);
+ next = inb(WAITING_SCBH + iobase);
+
+ outb(SCBPTR+iobase, scb->position);
+ outb(SCB_NEXT+iobase, next);
+ outb(WAITING_SCBH + iobase, scb->position);
+
+ outb(SCBPTR + iobase, curscb);
+}
+
+/*
+ * Catch an interrupt from the adapter
+ */
+#if defined(__FreeBSD__)
+void
+#elif defined (__NetBSD__)
+int
+#endif
+ahc_intr(arg)
+ void *arg;
+{
+ int intstat;
+ u_char status;
+ u_long iobase;
+ struct scb *scb = NULL;
struct scsi_xfer *xs = NULL;
-
+ struct ahc_data *ahc = (struct ahc_data *)arg;
+
+ iobase = ahc->baseport;
+ intstat = inb(INTSTAT + iobase);
/*
* Is this interrupt for me? or for
* someone who is sharing my interrupt
*/
- if ((intstat & INT_PEND) == 0)
+ if (!(intstat & INT_PEND))
+#if defined(__FreeBSD__)
+ return;
+#elif defined(__NetBSD__)
return 0;
-
- if (intstat & BRKADRINT) {
+#endif
+
+ if (intstat & BRKADRINT) {
/* We upset the sequencer :-( */
/* Lookup the error message */
int i, error = inb(ERROR + iobase);
int num_errors = sizeof(hard_error)/sizeof(hard_error[0]);
- for (i = 0; error != 1 && i < num_errors; i++)
+ for(i = 0; error != 1 && i < num_errors; i++)
error >>= 1;
- panic("%s: brkadrint, %s at seqaddr = 0x%x\n",
- ahc->sc_dev.dv_xname, hard_error[i].errmesg,
- (inb(SEQADDR1 + iobase) << 8) |
- (inb(SEQADDR0 + iobase) << 0));
- }
-
- if (intstat & SEQINT) {
- switch (intstat & SEQINT_MASK) {
- case BAD_PHASE:
- panic("%s: unknown scsi bus phase. "
+ panic(AHCNAME_FMT ": brkadrint, %s at seqaddr = 0x%x\n",
+ AHCNAME_VAR(ahc), hard_error[i].errmesg,
+ (inb(SEQADDR1 + iobase) << 8) |
+ inb(SEQADDR0 + iobase));
+ }
+ if (intstat & SEQINT) {
+ /*
+ * This code isn't used by the SCB page-in code. It
+ * should probably be moved to cut out the extra
+ * inb.
+ */
+ u_short targ_mask;
+ u_char target = (inb(SCSIID + iobase) >> 4) & 0x0f;
+ u_char scratch_offset = target;
+ char channel =
+ inb(SBLKCTL + iobase) & SELBUSB ? 'B': 'A';
+
+ if (channel == 'B')
+ scratch_offset += 8;
+ targ_mask = (0x01 << scratch_offset);
+
+ switch (intstat & SEQINT_MASK) {
+ case BAD_PHASE:
+ panic(AHCNAME_FMT ":%c:%d: unknown scsi bus phase. "
"Attempting to continue\n",
- ahc->sc_dev.dv_xname);
- break;
- case SEND_REJECT:
- printf("%s: Warning - "
- "message reject, message type: 0x%x\n",
- ahc->sc_dev.dv_xname,
- inb(HA_REJBYTE + iobase));
- break;
- case NO_IDENT:
- panic("%s: No IDENTIFY message from reconnecting "
- "target %d at seqaddr = 0x%x "
- "SAVED_TCL == 0x%x\n",
- ahc->sc_dev.dv_xname,
- (inb(SELID + iobase) >> 4) & 0xf,
- (inb(SEQADDR1 + iobase) << 8) |
- (inb(SEQADDR0 + iobase) << 0),
- inb(SAVED_TCL + iobase));
- break;
- case NO_MATCH: {
- u_char active;
- int active_port = HA_ACTIVE0 + iobase;
- int tcl = inb(SCBARRAY+1 + iobase);
- int target = (tcl >> 4) & 0x0f;
- printf("%s: no active SCB for reconnecting "
- "target %d, channel %c - issuing ABORT\n",
- ahc->sc_dev.dv_xname,
- target, tcl & 0x08 ? 'B' : 'A');
- printf("SAVED_TCL == 0x%x\n", inb(SAVED_TCL + iobase));
- if (tcl & 0x88) {
- /* Second channel stores its info
- * in byte two of HA_ACTIVE
- */
- active_port++;
+ AHCNAME_VAR(ahc), channel, target);
+ break;
+ case SEND_REJECT:
+ {
+ u_char rejbyte = inb(REJBYTE + iobase);
+ if(( rejbyte & 0xf0) == 0x20) {
+ /* Tagged Message */
+ printf("\n" AHCNAME_FMT
+ ":%c:%d: Tagged message "
+ "received without identify. "
+ "Disabling tagged commands "
+ "for this target.\n",
+ AHCNAME_VAR(ahc),
+ channel, target);
+ ahc->tagenable &= ~targ_mask;
+ }
+ else
+ printf(AHCNAME_FMT ":%c:%d: Warning - "
+ "unknown message recieved from "
+ "target (0x%x - 0x%x). Rejecting\n",
+ AHCNAME_VAR(ahc),
+ channel, target,
+ rejbyte, inb(REJBYTE_EXT + iobase));
+ break;
}
- active = inb(active_port);
- active &= ~(0x01 << (target & 0x07));
- outb(SCBARRAY + iobase, SCB_NEEDDMA);
- outb(active_port, active);
- outb(CLRSINT1 + iobase, CLRSELTIMEO);
- RESTART_SEQUENCER(ahc);
+ case NO_IDENT:
+ panic(AHCNAME_FMT
+ ":%c:%d: Target did not send an IDENTIFY "
+ "message. SAVED_TCL == 0x%x\n",
+ AHCNAME_VAR(ahc), channel, target,
+ inb(SAVED_TCL + iobase));
break;
- }
- case MSG_SDTR: {
- u_char scsi_id =
- (inb(SCSIID + iobase) >> 0x4) |
- (inb(SBLKCTL + iobase) & 0x08);
- u_char scratch, offset;
- int period;
-
- /*
- * Help the sequencer to translate the
- * negotiated transfer rate. Transfer is
- * 1/4 the period in ns as is returned by
- * the sync negotiation message. So, we must
- * multiply by four
- */
- period = inb(HA_ARG_1 + iobase) << 2;
- /* The bottom half of SCSIXFER */
- offset = inb(ACCUM + iobase);
-
- printf("%s: SDTR, target %d period %d offset %d\n",
- ahc->sc_dev.dv_xname, scsi_id, period, offset);
- scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id);
- scratch &= 0x80;
- scratch |= ahc_scsirate(offset, period, ahc, scsi_id);
+ case NO_MATCH:
+ if(ahc->flags & AHC_PAGESCBS) {
+ /* SCB Page-in request */
+ struct scb *outscb;
+ u_char arg_1 = inb(ARG_1 + iobase);
+ if(arg_1 == SCB_LIST_NULL) {
+ /* Non-tagged command */
+ int index = target |
+ (channel == 'B' ? SELBUSB : 0);
+ scb = ahc->pagedout_ntscbs[index];
+ }
+ else
+ scb = ahc->scbarray[arg_1];
- if ((scratch & 0x7f) == 0) {
- /*
- * The requested rate was so low
- * that asyncronous transfers are
- * faster (not to mention the
- * controller won't support them),
- * so we issue a message reject to
- * ensure we go to asyncronous
- * transfers.
- */
- outb(HA_RETURN_1 + iobase, SEND_REJ);
- } else if (ahc->sdtrpending & (0x01 << scsi_id)) {
/*
- * Don't send an SDTR back to the
- * target, since we asked first.
+ * Now to pick the SCB to page out.
+ * Either take a free SCB, an assigned SCB,
+ * an SCB that just completed or the first
+ * one on the disconnected SCB list.
*/
- outb(HA_RETURN_1 + iobase, 0);
- } else {
- /*
- * Send our own SDTR in reply
+ if(ahc->free_scbs.stqh_first) {
+ outscb = ahc->free_scbs.stqh_first;
+ STAILQ_REMOVE_HEAD(&ahc->free_scbs,
+ links);
+ scb->position = outscb->position;
+ outscb->position = SCB_LIST_NULL;
+ STAILQ_INSERT_HEAD(&ahc->page_scbs,
+ outscb, links);
+ outb(SCBPTR + iobase, scb->position);
+ ahc_send_scb(ahc, scb);
+ scb->flags &= ~SCB_PAGED_OUT;
+ }
+ else if(ahc->assigned_scbs.stqh_first) {
+ outscb = ahc->assigned_scbs.stqh_first;
+ STAILQ_REMOVE_HEAD(&ahc->assigned_scbs,
+ links);
+ scb->position = outscb->position;
+ outscb->position = SCB_LIST_NULL;
+ STAILQ_INSERT_HEAD(&ahc->waiting_scbs,
+ outscb, links);
+ outscb->flags = SCB_WAITINGQ;
+ outb(SCBPTR + iobase, scb->position);
+ ahc_send_scb(ahc, scb);
+ scb->flags &= ~SCB_PAGED_OUT;
+ }
+ else if(intstat & CMDCMPLT) {
+ int scb_index;
+
+ printf("PIC\n");
+ outb(CLRINT + iobase, CLRCMDINT);
+ scb_index = inb(QOUTFIFO + iobase);
+ if(!(inb(QOUTCNT + iobase) & ahc->qcntmask))
+ intstat &= ~CMDCMPLT;
+
+ outscb = ahc->scbarray[scb_index];
+ if (!outscb || !(outscb->flags & SCB_ACTIVE)) {
+ printf(AHCNAME_FMT
+ ": WARNING "
+ "no command for scb %d (cmdcmplt)\n",
+ AHCNAME_VAR(ahc),
+ scb_index );
+ goto use_disconnected_scb;
+ }
+ else {
+ scb->position = outscb->position;
+ outscb->position = SCB_LIST_NULL;
+ outb(SCBPTR + iobase, scb->position);
+ ahc_send_scb(ahc, scb);
+ scb->flags &= ~SCB_PAGED_OUT;
+ untimeout(ahc_timeout, (caddr_t)outscb);
+ ahc_done(ahc, outscb);
+ }
+ }
+ else {
+ u_char tag;
+ u_char next;
+ u_char disc_scb;
+use_disconnected_scb:
+ disc_scb =
+ inb(DISCONNECTED_SCBH + iobase);
+ if(disc_scb == SCB_LIST_NULL)
+ panic("Page-in request with no "
+ "candidates");
+ outb(SCBPTR + iobase, disc_scb);
+ tag = inb(SCB_TAG + iobase);
+ outscb = ahc->scbarray[tag];
+ next = inb(SCB_NEXT + iobase);
+ if(next != SCB_LIST_NULL) {
+ outb(SCBPTR + iobase, next);
+ outb(SCB_PREV + iobase,
+ SCB_LIST_NULL);
+ outb(SCBPTR + iobase, disc_scb);
+ }
+ outb(DISCONNECTED_SCBH + iobase, next);
+ ahc_page_scb(ahc, outscb, scb);
+ }
+ outb(RETURN_1 + iobase, SCB_PAGEDIN);
+ }
+ else {
+ printf(AHCNAME_FMT ":%c:%d: no active SCB for "
+ "reconnecting target - "
+ "issuing ABORT\n",
+ AHCNAME_VAR(ahc), channel, target);
+ printf("SAVED_TCL == 0x%x\n",
+ inb(SAVED_TCL + iobase));
+ ahc_unbusy_target(target, channel, iobase);
+ outb(SCB_CONTROL + iobase, 0);
+ outb(CLRSINT1 + iobase, CLRSELTIMEO);
+ outb(RETURN_1 + iobase, 0);
+ }
+ break;
+ case SDTR_MSG:
+ {
+ short period;
+ u_char offset, rate;
+ u_char targ_scratch;
+ u_char maxoffset;
+ /*
+ * Help the sequencer to translate the
+ * negotiated transfer rate. Transfer is
+ * 1/4 the period in ns as is returned by
+ * the sync negotiation message. So, we must
+ * multiply by four
*/
+ period = inb(ARG_1 + iobase) << 2;
+ offset = inb(ACCUM + iobase);
+ targ_scratch = inb(TARG_SCRATCH + iobase
+ + scratch_offset);
+ if(targ_scratch & WIDEXFER)
+ maxoffset = 0x08;
+ else
+ maxoffset = 0x0f;
+ ahc_scsirate(ahc, &rate, period,
+ MIN(offset,maxoffset),
+ target);
+ /* Preserve the WideXfer flag */
+ targ_scratch = rate | (targ_scratch & WIDEXFER);
+ outb(TARG_SCRATCH + iobase + scratch_offset,
+ targ_scratch);
+ outb(SCSIRATE + iobase, targ_scratch);
+ if( (targ_scratch & 0x0f) == 0 )
+ {
+ /*
+ * The requested rate was so low
+ * that asyncronous transfers are
+ * faster (not to mention the
+ * controller won't support them),
+ * so we issue a message reject to
+ * ensure we go to asyncronous
+ * transfers.
+ */
+ outb(RETURN_1 + iobase, SEND_REJ);
+ }
+ /* See if we initiated Sync Negotiation */
+ else if(ahc->sdtrpending & targ_mask)
+ {
+ /*
+ * Don't send an SDTR back to
+ * the target
+ */
+ outb(RETURN_1 + iobase, 0);
+ }
+ else{
+ /*
+ * Send our own SDTR in reply
+ */
#ifdef AHC_DEBUG
- if (ahc_debug & AHC_SHOWMISC)
- printf("Sending SDTR!!\n");
+ if(ahc_debug & AHC_SHOWMISC)
+ printf("Sending SDTR!!\n");
#endif
- outb(HA_RETURN_1 + iobase, SEND_SDTR);
+ outb(RETURN_1 + iobase, SEND_SDTR);
+ }
+ /*
+ * Negate the flags
+ */
+ ahc->needsdtr &= ~targ_mask;
+ ahc->sdtrpending &= ~targ_mask;
+ break;
}
- /*
- * Negate the flags
- */
- ahc->needsdtr &= ~(0x01 << scsi_id);
- ahc->sdtrpending &= ~(0x01 << scsi_id);
-
- outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch);
- outb(SCSIRATE + iobase, scratch);
- break;
- }
- case MSG_WDTR: {
- u_char scsi_id =
- (inb(SCSIID + iobase) >> 0x4) |
- (inb(SBLKCTL + iobase) & 0x08);
- u_char scratch, width;
+ case WDTR_MSG:
+ {
+ u_char scratch, bus_width;
- width = inb(ACCUM + iobase);
+ bus_width = inb(ARG_1 + iobase);
- scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id);
+ scratch = inb(TARG_SCRATCH + iobase
+ + scratch_offset);
- if (ahc->wdtrpending & (0x01 << scsi_id)) {
- /*
- * Don't send a WDTR back to the
- * target, since we asked first.
- */
- outb(HA_RETURN_1 + iobase, 0);
- switch (width) {
- case BUS_8_BIT:
- scratch &= 0x7f;
- break;
- case BUS_16_BIT:
- printf("%s: target %d using 16Bit "
- "transfers\n",
- ahc->sc_dev.dv_xname, scsi_id);
- scratch &= 0xf8;
- scratch |= 0x88;
- break;
- case BUS_32_BIT:
- /* XXXX */
+ if(ahc->wdtrpending & targ_mask)
+ {
+ /*
+ * Don't send a WDTR back to the
+ * target, since we asked first.
+ */
+ outb(RETURN_1 + iobase, 0);
+ switch(bus_width)
+ {
+ case BUS_8_BIT:
+ scratch &= 0x7f;
+ break;
+ case BUS_16_BIT:
+ if(bootverbose)
+ printf(AHCNAME_FMT
+ ": target "
+ "%d using 16Bit "
+ "transfers\n",
+ AHCNAME_VAR(ahc),
+ target);
+ scratch |= 0x80;
+ break;
+ case BUS_32_BIT:
+ /*
+ * How can we do 32bit
+ * transfers on a 16bit
+ * bus?
+ */
+ outb(RETURN_1 + iobase,
+ SEND_REJ);
+ printf(AHCNAME_FMT
+ ": target "
+ "%d requested 32Bit "
+ "transfers. "
+ "Rejecting...\n",
+ AHCNAME_VAR(ahc),
+ target);
+ break;
+ default:
+ break;
+ }
}
- } else {
- /*
- * Send our own WDTR in reply
- */
- switch (width) {
- case BUS_8_BIT:
- scratch &= 0x7f;
- break;
- case BUS_32_BIT:
- /* Negotiate 16_BITS */
- width = BUS_16_BIT;
- case BUS_16_BIT:
- printf("%s: target %d using 16Bit "
- "transfers\n",
- ahc->sc_dev.dv_xname, scsi_id);
- scratch &= 0xf8;
- scratch |= 0x88;
- break;
+ else {
+ /*
+ * Send our own WDTR in reply
+ */
+ switch(bus_width)
+ {
+ case BUS_8_BIT:
+ scratch &= 0x7f;
+ break;
+ case BUS_32_BIT:
+ case BUS_16_BIT:
+ if(ahc->type & AHC_WIDE) {
+ /* Negotiate 16_BITS */
+ bus_width = BUS_16_BIT;
+ if(bootverbose)
+ printf(AHCNAME_FMT
+ ": "
+ "target %d "
+ "using 16Bit "
+ "transfers\n",
+ AHCNAME_VAR(ahc),
+ target);
+ scratch |= 0x80;
+ }
+ else
+ bus_width = BUS_8_BIT;
+ break;
+ default:
+ break;
+ }
+ outb(RETURN_1 + iobase,
+ bus_width | SEND_WDTR);
}
- outb(HA_RETURN_1 + iobase,
- width | SEND_WDTR);
+ ahc->needwdtr &= ~targ_mask;
+ ahc->wdtrpending &= ~targ_mask;
+ outb(TARG_SCRATCH + iobase + scratch_offset,
+ scratch);
+ outb(SCSIRATE + iobase, scratch);
+ break;
}
- ahc->needwdtr &= ~(0x01 << scsi_id);
- ahc->wdtrpending &= ~(0x01 << scsi_id);
-
- outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch);
- outb(SCSIRATE + iobase, scratch);
- break;
- }
- case MSG_REJECT: {
- /*
- * What we care about here is if we had an
- * outstanding SDTR or WDTR message for this
- * target. If we did, this is a signal that
- * the target is refusing negotiation.
- */
-
- u_char scsi_id =
- (inb(SCSIID + iobase) >> 0x4) |
- (inb(SBLKCTL + iobase) & 0x08);
- u_char scratch;
- u_short mask;
-
- scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id);
-
- mask = (0x01 << scsi_id);
- if (ahc->wdtrpending & mask) {
- /* note 8bit xfers and clear flag */
- scratch &= 0x7f;
- ahc->needwdtr &= ~mask;
- ahc->wdtrpending &= ~mask;
- printf("%s: target %d refusing "
- "WIDE negotiation. Using "
- "8bit transfers\n",
- ahc->sc_dev.dv_xname, scsi_id);
- } else if (ahc->sdtrpending & mask) {
- /* note asynch xfers and clear flag */
- scratch &= 0xf0;
- ahc->needsdtr &= ~mask;
- ahc->sdtrpending &= ~mask;
- printf("%s: target %d refusing "
- "syncronous negotiation; using "
- "asyncronous transfers\n",
- ahc->sc_dev.dv_xname, scsi_id);
- } else {
+ case REJECT_MSG:
+ {
/*
- * Otherwise, we ignore it.
+ * What we care about here is if we had an
+ * outstanding SDTR or WDTR message for this
+ * target. If we did, this is a signal that
+ * the target is refusing negotiation.
*/
+
+ u_char targ_scratch;
+
+ targ_scratch = inb(TARG_SCRATCH + iobase
+ + scratch_offset);
+
+ if(ahc->wdtrpending & targ_mask){
+ /* note 8bit xfers and clear flag */
+ targ_scratch &= 0x7f;
+ ahc->needwdtr &= ~targ_mask;
+ ahc->wdtrpending &= ~targ_mask;
+ printf(AHCNAME_FMT ":%c:%d: refuses "
+ "WIDE negotiation. Using "
+ "8bit transfers\n",
+ AHCNAME_VAR(ahc),
+ channel, target);
+ }
+ else if(ahc->sdtrpending & targ_mask){
+ /* note asynch xfers and clear flag */
+ targ_scratch &= 0xf0;
+ ahc->needsdtr &= ~targ_mask;
+ ahc->sdtrpending &= ~targ_mask;
+ printf(AHCNAME_FMT ":%c:%d: refuses "
+ "syncronous negotiation. Using "
+ "asyncronous transfers\n",
+ AHCNAME_VAR(ahc),
+ channel, target);
+ }
+ else {
+ /*
+ * Otherwise, we ignore it.
+ */
#ifdef AHC_DEBUG
- if (ahc_debug & AHC_SHOWMISC)
- printf("Message reject -- ignored\n");
+ if(ahc_debug & AHC_SHOWMISC)
+ printf(AHCNAME_FMT
+ ":%c:%d: Message "
+ "reject -- ignored\n",
+ AHCNAME_VAR(ahc),
+ channel, target);
#endif
+ break;
+ }
+ outb(TARG_SCRATCH + iobase + scratch_offset,
+ targ_scratch);
+ outb(SCSIRATE + iobase, targ_scratch);
break;
}
+ case BAD_STATUS:
+ {
+ int scb_index;
+
+ /* The sequencer will notify us when a command
+ * has an error that would be of interest to
+ * the kernel. This allows us to leave the sequencer
+ * running in the common case of command completes
+ * without error.
+ */
+
+ scb_index = inb(SCB_TAG + iobase);
+ scb = ahc->scbarray[scb_index];
+
+ /*
+ * Set the default return value to 0 (don't
+ * send sense). The sense code will change
+ * this if needed and this reduces code
+ * duplication.
+ */
+ outb(RETURN_1 + iobase, 0);
+ if (!(scb && (scb->flags & SCB_ACTIVE))) {
+ printf(AHCNAME_FMT ":%c:%d: ahc_intr - referenced scb "
+ "not valid during seqint 0x%x scb(%d)\n",
+ AHCNAME_VAR(ahc),
+ channel, target, intstat,
+ scb_index);
+ goto clear;
+ }
+
+ xs = scb->xs;
+
+ scb->status = inb(SCB_TARGET_STATUS + iobase);
- outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch);
- outb(SCSIRATE + iobase, scratch);
- break;
- }
- case BAD_STATUS: {
- int scb_index = inb(SCBPTR + iobase);
- scb = ahc->scbarray[scb_index];
-
- /*
- * The sequencer will notify us when a command
- * has an error that would be of interest to
- * the kernel. This allows us to leave the sequencer
- * running in the common case of command completes
- * without error.
- */
-
- /*
- * Set the default return value to 0 (don't
- * send sense). The sense code with change
- * this if needed and this reduces code
- * duplication.
- */
- outb(HA_RETURN_1 + iobase, 0);
- if (!scb || scb->flags == SCB_FREE) {
- printf("%s: ahcintr: referenced scb not "
- "valid during seqint 0x%x scb(%d)\n",
- ahc->sc_dev.dv_xname, intstat, scb_index);
- goto clear;
- }
-
- xs = scb->xs;
-
- ahc_getscb(iobase, scb);
-
-#ifdef AHC_MORE_DEBUG
- if (xs->sc_link->target == DEBUGTARGET)
+#ifdef AHC_DEBUG
+ if((ahc_debug & AHC_SHOWSCBS)
+ && xs->sc_link->target == DEBUGTARG)
ahc_print_scb(scb);
#endif
- xs->status = scb->target_status;
- switch (scb->target_status) {
- case SCSI_OK:
- printf("%s: Interrupted for status of 0???\n",
- ahc->sc_dev.dv_xname);
+ xs->status = scb->status;
+ switch(scb->status){
+ case SCSI_OK:
+ printf(AHCNAME_FMT ": Interrupted for staus of"
+ " 0???\n", AHCNAME_VAR(ahc));
break;
- case SCSI_CHECK:
+ case SCSI_CHECK:
#ifdef AHC_DEBUG
- sc_print_addr(xs->sc_link);
- printf("requests Check Status\n");
+ if(ahc_debug & AHC_SHOWSENSE)
+ {
+ sc_print_addr(xs->sc_link);
+ printf("requests Check Status\n");
+ }
#endif
- if (xs->error == XS_NOERROR &&
- scb->flags != SCB_CHKSENSE) {
- u_char head;
- u_char tail;
+ if((xs->error == XS_NOERROR) &&
+ !(scb->flags & SCB_SENSE)) {
struct ahc_dma_seg *sg = scb->ahc_dma;
struct scsi_sense *sc = &(scb->sense_cmd);
- u_char control = scb->control;
- u_char tcl = scb->target_channel_lun;
#ifdef AHC_DEBUG
- sc_print_addr(xs->sc_link);
- printf("Sending Sense\n");
+ if(ahc_debug & AHC_SHOWSENSE)
+ {
+ sc_print_addr(xs->sc_link);
+ printf("Sending Sense\n");
+ }
#endif
- bzero(scb, SCB_DOWN_SIZE);
- scb->flags = SCB_CHKSENSE;
- scb->control = (control & SCB_TE);
+#if defined(__FreeBSD__)
+ sc->op_code = REQUEST_SENSE;
+#elif defined(__NetBSD__)
sc->opcode = REQUEST_SENSE;
+#endif
sc->byte2 = xs->sc_link->lun << 5;
sc->length = sizeof(struct scsi_sense_data);
sc->control = 0;
- sg->seg_addr = vtophys(&xs->sense);
- sg->seg_len = sizeof(struct scsi_sense_data);
+ sg->addr = KVTOPHYS(&xs->sense);
+ sg->len = sizeof(struct scsi_sense_data);
- scb->target_channel_lun = tcl;
+ scb->control &= DISCENB;
+ scb->status = 0;
scb->SG_segment_count = 1;
- scb->SG_list_pointer = vtophys(sg);
- scb->cmdpointer = vtophys(sc);
+ scb->SG_list_pointer = KVTOPHYS(sg);
+ scb->data = sg->addr;
+ scb->datalen = sg->len;
+#ifdef AIC7XXX_BROKEN_CACHE
+ if (aic7xxx_broken_cache)
+ INVALIDATE_CACHE();
+#endif
+ scb->cmdpointer = KVTOPHYS(sc);
scb->cmdlen = sizeof(*sc);
- outb(SCBCNT + iobase, SCBAUTO);
- outsb(SCBARRAY + iobase, scb,
- SCB_DOWN_SIZE);
- outb(SCBCNT + iobase, 0);
- outb(SCBARRAY + iobase + 30,
- SCB_LIST_NULL);
+ scb->flags |= SCB_SENSE;
+ ahc_send_scb(ahc, scb);
+ /*
+ * Ensure that the target is "BUSY"
+ * so we don't get overlapping
+ * commands if we happen to be doing
+ * tagged I/O.
+ */
+ ahc_busy_target(target,channel,iobase);
/*
- * Add this SCB to the "waiting for
- * selection" list.
+ * Make us the next command to run
*/
- head = inb(WAITING_SCBH + iobase);
- tail = inb(WAITING_SCBT + iobase);
- if (head & SCB_LIST_NULL) {
- /* List was empty */
- head = scb->position;
- tail = SCB_LIST_NULL;
- } else if (tail & SCB_LIST_NULL) {
- /* List had one element */
- tail = scb->position;
- outb(SCBPTR + iobase, head);
- outb(SCBARRAY + iobase + 30,
- tail);
- } else {
- outb(SCBPTR + iobase, tail);
- tail = scb->position;
- outb(SCBARRAY + iobase + 30,
- tail);
- }
- outb(WAITING_SCBH + iobase, head);
- outb(WAITING_SCBT + iobase, tail);
- outb(HA_RETURN_1 + iobase, SEND_SENSE);
+ ahc_add_waiting_scb(iobase, scb);
+ outb(RETURN_1 + iobase, SEND_SENSE);
break;
}
/*
- * Have the sequencer do a normal command
+ * Clear the SCB_SENSE Flag and have
+ * the sequencer do a normal command
* complete with either a "DRIVER_STUFFUP"
* error or whatever other error condition
* we already had.
*/
- if (xs->error == XS_NOERROR)
+ scb->flags &= ~SCB_SENSE;
+ if(xs->error == XS_NOERROR)
xs->error = XS_DRIVER_STUFFUP;
break;
- case SCSI_BUSY:
+ case SCSI_BUSY:
+ xs->error = XS_BUSY;
sc_print_addr(xs->sc_link);
printf("Target Busy\n");
- xs->error = XS_BUSY;
break;
-#if 0
- case SCSI_QUEUE_FULL:
+#if defined(__FreeBSD__)
+ case SCSI_QUEUE_FULL:
/*
* The upper level SCSI code will eventually
* handle this properly.
*/
sc_print_addr(xs->sc_link);
printf("Queue Full\n");
- xs->error = XS_BUSY;
+ scb->flags = SCB_ASSIGNEDQ;
+ STAILQ_INSERT_TAIL(&ahc->assigned_scbs,
+ scb, links);
break;
+#elif defined(__NetBSD__)
+ /*
+ * XXX -
+ * Do we need to handle this ?
+ * But FreeBSD MI SCSI code seems to
+ * do nothing about this.
+ */
#endif
- default:
+ default:
sc_print_addr(xs->sc_link);
printf("unexpected targ_status: %x\n",
- scb->target_status);
+ scb->status);
xs->error = XS_DRIVER_STUFFUP;
break;
}
break;
- }
- case RESIDUAL: {
- int scb_index = inb(SCBPTR + iobase);
+ }
+ case RESIDUAL:
+ {
+ int scb_index;
+ scb_index = inb(SCB_TAG + iobase);
scb = ahc->scbarray[scb_index];
-
+ xs = scb->xs;
/*
* Don't clobber valid resid info with
* a resid coming from a check sense
* operation.
*/
- if (scb->flags != SCB_CHKSENSE)
- scb->xs->resid =
- (inb(iobase + SCBARRAY + 17) << 16) |
- (inb(iobase + SCBARRAY + 16) << 8) |
- (inb(iobase + SCBARRAY + 15) << 0);
-#ifdef AHC_MORE_DEBUG
- printf("ahc: Handled Residual\n");
+ if(!(scb->flags & SCB_SENSE)) {
+ int resid_sgs;
+
+ /*
+ * Remainder of the SG where the transfer
+ * stopped.
+ */
+ xs->resid =
+ (inb(iobase+SCB_RESID_DCNT2)<<16) |
+ (inb(iobase+SCB_RESID_DCNT1)<<8) |
+ inb(iobase+SCB_RESID_DCNT0);
+
+ /*
+ * Add up the contents of all residual
+ * SG segments that are after the SG where
+ * the transfer stopped.
+ */
+ resid_sgs = inb(SCB_RESID_SGCNT + iobase) - 1;
+ while(resid_sgs > 0) {
+ int sg;
+
+ sg = scb->SG_segment_count - resid_sgs;
+ xs->resid += scb->ahc_dma[sg].len;
+ resid_sgs--;
+ }
+
+#if defined(__FreeBSD__)
+ xs->flags |= SCSI_RESID_VALID;
+#elif defined(__NetBSD__)
+ /* XXX - Update to do this right */
+#endif
+#ifdef AHC_DEBUG
+ if(ahc_debug & AHC_SHOWMISC) {
+ sc_print_addr(xs->sc_link);
+ printf("Handled Residual of %ld bytes\n"
+ ,xs->resid);
+ }
#endif
+ }
break;
- }
- case ABORT_TAG: {
- int scb_index = inb(SCBPTR + iobase);
+ }
+ case ABORT_TAG:
+ {
+ int scb_index;
+ scb_index = inb(SCB_TAG + iobase);
scb = ahc->scbarray[scb_index];
-
+ xs = scb->xs;
/*
* We didn't recieve a valid tag back from
* the target on a reconnect.
*/
sc_print_addr(xs->sc_link);
- printf("invalid tag recieved on channel %c "
- "-- sending ABORT_TAG\n",
- (xs->sc_link->quirks & 0x08) ? 'B' : 'A');
- scb->xs->error = XS_DRIVER_STUFFUP;
- untimeout(ahc_timeout, scb);
+ printf("invalid tag recieved -- sending ABORT_TAG\n");
+ xs->error = XS_DRIVER_STUFFUP;
+ untimeout(ahc_timeout, (caddr_t)scb);
ahc_done(ahc, scb);
break;
- }
- default:
- printf("%s: seqint, intstat == 0x%x, scsisigi = 0x%x\n",
- ahc->sc_dev.dv_xname,
- intstat, inb(SCSISIGI + iobase));
+ }
+ case AWAITING_MSG:
+ {
+ int scb_index;
+ scb_index = inb(SCB_TAG + iobase);
+ scb = ahc->scbarray[scb_index];
+ /*
+ * This SCB had a zero length command, informing
+ * the sequencer that we wanted to send a special
+ * message to this target. We only do this for
+ * BUS_DEVICE_RESET messages currently.
+ */
+ if(scb->flags & SCB_DEVICE_RESET)
+ {
+ outb(MSG0 + iobase,
+ MSG_BUS_DEVICE_RESET);
+ outb(MSG_LEN + iobase, 1);
+ printf("Bus Device Reset Message Sent\n");
+ }
+ else
+ panic("ahc_intr: AWAITING_MSG for an SCB that "
+ "does not have a waiting message");
+ break;
+ }
+ case IMMEDDONE:
+ {
+ /*
+ * Take care of device reset messages
+ */
+ u_char scbindex = inb(SCB_TAG + iobase);
+ scb = ahc->scbarray[scbindex];
+ if(scb->flags & SCB_DEVICE_RESET) {
+ u_char targ_scratch;
+ int found;
+ /*
+ * Go back to async/narrow transfers and
+ * renegotiate.
+ */
+ ahc_unbusy_target(target, channel, iobase);
+ ahc->needsdtr |= ahc->needsdtr_orig & targ_mask;
+ ahc->needwdtr |= ahc->needwdtr_orig & targ_mask;
+ ahc->sdtrpending &= ~targ_mask;
+ ahc->wdtrpending &= ~targ_mask;
+ targ_scratch = inb(TARG_SCRATCH + iobase
+ + scratch_offset);
+ targ_scratch &= SXFR;
+ outb(TARG_SCRATCH + iobase + scratch_offset,
+ targ_scratch);
+ found = ahc_reset_device(ahc, target,
+ channel, SCB_LIST_NULL,
+ XS_NOERROR);
+ sc_print_addr(scb->xs->sc_link);
+ printf("Bus Device Reset delivered. "
+ "%d SCBs aborted\n", found);
+ ahc->in_timeout = FALSE;
+ ahc_run_done_queue(ahc);
+ }
+ else
+ panic("ahc_intr: Immediate complete for "
+ "unknown operation.");
+ break;
+ }
+#if NOT_YET
+ /* XXX Fill these in later */
+ case MESG_BUFFER_BUSY:
+ break;
+ case MSGIN_PHASEMIS:
+ break;
+#endif
+ default:
+ printf("ahc_intr: seqint, "
+ "intstat == 0x%x, scsisigi = 0x%x\n",
+ intstat, inb(SCSISIGI + iobase));
break;
}
-
- clear:
+clear:
/*
* Clear the upper byte that holds SEQINT status
* codes and clear the SEQINT bit.
* we leave this section.
*/
UNPAUSE_SEQUENCER(ahc);
- }
-
- if (intstat & SCSIINT) {
- int scb_index = inb(SCBPTR + iobase);
- scb = ahc->scbarray[scb_index];
+ }
+
+
+ if (intstat & SCSIINT) {
+ int scb_index = inb(SCB_TAG + iobase);
status = inb(SSTAT1 + iobase);
- if (!scb || scb->flags == SCB_FREE) {
- printf("%s: ahcintr - referenced scb not "
+ scb = ahc->scbarray[scb_index];
+ if (scb != NULL) /* XXX - is this case exist ? */
+ xs = scb->xs;
+
+ if (status & SCSIRSTI) {
+ char channel;
+ channel = inb(SBLKCTL + iobase);
+ channel = channel & SELBUSB ? 'B' : 'A';
+ printf(AHCNAME_FMT ": Someone reset channel %c\n",
+ AHCNAME_VAR(ahc), channel);
+ ahc_reset_channel(ahc,
+ channel,
+ SCB_LIST_NULL,
+ XS_BUSY,
+ /* Initiate Reset */FALSE);
+ scb = NULL;
+ }
+ else if (!(scb && (scb->flags & SCB_ACTIVE))){
+ printf(AHCNAME_FMT ": ahc_intr - referenced scb not "
"valid during scsiint 0x%x scb(%d)\n",
- ahc->sc_dev.dv_xname, status, scb_index);
+ AHCNAME_VAR(ahc), status, scb_index);
outb(CLRSINT1 + iobase, status);
UNPAUSE_SEQUENCER(ahc);
outb(CLRINT + iobase, CLRSCSIINT);
scb = NULL;
- goto cmdcomplete;
}
- xs = scb->xs;
+ else if (status & SCSIPERR) {
+ /*
+ * Determine the bus phase and
+ * queue an appropriate message
+ */
+ char *phase;
+ u_char mesg_out = MSG_NOP;
+ u_char lastphase = inb(LASTPHASE + iobase);
-#ifdef AHC_MORE_DEBUG
- if ((xs->sc_link->target & 0xf) == DEBUGTARGET)
- printf("Intr status %x\n", status);
-#endif
+ sc_print_addr(xs->sc_link);
+
+ switch(lastphase) {
+ case P_DATAOUT:
+ phase = "Data-Out";
+ break;
+ case P_DATAIN:
+ phase = "Data-In";
+ mesg_out = MSG_INITIATOR_DET_ERROR;
+ break;
+ case P_COMMAND:
+ phase = "Command";
+ break;
+ case P_MESGOUT:
+ phase = "Message-Out";
+ break;
+ case P_STATUS:
+ phase = "Status";
+ mesg_out = MSG_INITIATOR_DET_ERROR;
+ break;
+ case P_MESGIN:
+ phase = "Message-In";
+ mesg_out = MSG_MSG_PARITY_ERROR;
+ break;
+ default:
+ phase = "unknown";
+ break;
+ }
+ printf("parity error during %s phase.\n", phase);
- if (status & SELTO) {
- u_char active;
+ /*
+ * We've set the hardware to assert ATN if we
+ * get a parity error on "in" phases, so all we
+ * need to do is stuff the message buffer with
+ * the appropriate message. In phases have set
+ * mesg_out to something other than MSG_NOP.
+ */
+ if(mesg_out != MSG_NOP) {
+ outb(MSG0 + iobase, mesg_out);
+ outb(MSG_LEN + iobase, 1);
+ }
+ else
+ /*
+ * Should we allow the target to make
+ * this decision for us?
+ */
+ xs->error = XS_DRIVER_STUFFUP;
+ }
+ else if (status & SELTO) {
u_char waiting;
u_char flags;
- int active_port = HA_ACTIVE0 + iobase;
-
- outb(SCSISEQ + iobase, ENRSELI);
- xs->error = XS_SELTIMEOUT;
+ xs->error = XS_SELTIMEOUT;
/*
* Clear any pending messages for the timed out
* target, and mark the target as free
*/
- flags = inb(HA_FLAGS + iobase);
- outb(HA_FLAGS + iobase, flags & ~ACTIVE_MSG);
-
- if (scb->target_channel_lun & 0x88)
- active_port++;
-
- active = inb(active_port) &
- ~(0x01 << (xs->sc_link->target & 0x07));
- outb(active_port, active);
+ flags = inb(FLAGS + iobase);
+ outb(MSG_LEN + iobase, 0);
+ ahc_unbusy_target(xs->sc_link->target,
+#if defined(__FreeBSD__)
+ ((long)xs->sc_link->fordriver & SELBUSB)
+#elif defined(__NetBSD__)
+ IS_SCSIBUS_B(ahc, xs->sc_link)
+#endif
+ ? 'B' : 'A',
+ iobase);
- outb(SCBARRAY + iobase, SCB_NEEDDMA);
+ outb(SCB_CONTROL + iobase, 0);
outb(CLRSINT1 + iobase, CLRSELTIMEO);
/* Shift the waiting for selection queue forward */
waiting = inb(WAITING_SCBH + iobase);
outb(SCBPTR + iobase, waiting);
- waiting = inb(SCBARRAY + iobase + 30);
+ waiting = inb(SCB_NEXT + iobase);
outb(WAITING_SCBH + iobase, waiting);
RESTART_SEQUENCER(ahc);
+ }
+ else if (!(status & BUSFREE)) {
+ sc_print_addr(xs->sc_link);
+ printf("Unknown SCSIINT. Status = 0x%x\n", status);
+ outb(CLRSINT1 + iobase, status);
+ UNPAUSE_SEQUENCER(ahc);
+ outb(CLRINT + iobase, CLRSCSIINT);
+ scb = NULL;
+ }
+ if(scb != NULL) {
+ /* We want to process the command */
+ untimeout(ahc_timeout, (caddr_t)scb);
+ ahc_done(ahc, scb);
}
+ }
+ if (intstat & CMDCMPLT) {
+ int scb_index;
- if (status & SCSIPERR) {
- sc_print_addr(xs->sc_link);
- printf("parity error on channel %c\n",
- (xs->sc_link->quirks & 0x08) ? 'B' : 'A');
- xs->error = XS_DRIVER_STUFFUP;
+ do {
+ scb_index = inb(QOUTFIFO + iobase);
+ scb = ahc->scbarray[scb_index];
+ if (!scb || !(scb->flags & SCB_ACTIVE)) {
+ printf(AHCNAME_FMT ": WARNING "
+ "no command for scb %d (cmdcmplt)\n"
+ "QOUTCNT == %d\n",
+ AHCNAME_VAR(ahc), scb_index,
+ inb(QOUTCNT + iobase));
+ outb(CLRINT + iobase, CLRCMDINT);
+ continue;
+ }
+ outb(CLRINT + iobase, CLRCMDINT);
+ untimeout(ahc_timeout, (caddr_t)scb);
+ ahc_done(ahc, scb);
- outb(CLRSINT1 + iobase, CLRSCSIPERR);
- UNPAUSE_SEQUENCER(ahc);
+ } while (inb(QOUTCNT + iobase) & ahc->qcntmask);
- outb(CLRINT + iobase, CLRSCSIINT);
- scb = NULL;
- }
- if (status & BUSFREE) {
-#if 0
- /*
- * Has seen busfree since selection, i.e.
- * a "spurious" selection. Shouldn't happen.
- */
- printf("ahc: unexpected busfree\n");
-#if 0
- xs->error = XS_DRIVER_STUFFUP;
- outb(CLRSINT1 + iobase, BUSFREE); /* CLRBUSFREE */
-#endif
-#endif
- } else {
- printf("%s: Unknown SCSIINT. Status = 0x%x\n",
- ahc->sc_dev.dv_xname, status);
- outb(CLRSINT1 + iobase, status);
- UNPAUSE_SEQUENCER(ahc);
- outb(CLRINT + iobase, CLRSCSIINT);
- scb = NULL;
- }
- if (scb != NULL) {
- /* We want to process the command */
- untimeout(ahc_timeout, scb);
- ahc_done(ahc, scb);
- }
+ ahc_run_waiting_queues(ahc);
}
-
-cmdcomplete:
- if (intstat & CMDCMPLT) {
- int scb_index;
-
- do {
- scb_index = inb(QOUTFIFO + iobase);
- scb = ahc->scbarray[scb_index];
-
- if (!scb || scb->flags == SCB_FREE) {
- printf("%s: WARNING "
- "no command for scb %d (cmdcmplt)\n"
- "QOUTCNT == %d\n",
- ahc->sc_dev.dv_xname,
- scb_index, inb(QOUTCNT + iobase));
- outb(CLRINT + iobase, CLRCMDINT);
- continue;
- }
-
- /* XXXX Should do this before reading FIFO? */
- outb(CLRINT + iobase, CLRCMDINT);
- untimeout(ahc_timeout, scb);
- ahc_done(ahc, scb);
- } while (inb(QOUTCNT + iobase));
- }
-
+#if defined(__NetBSD__)
return 1;
+#endif
}
/*
* adaptor, now we look to see how the operation
* went.
*/
-void
+static void
ahc_done(ahc, scb)
- struct ahc_softc *ahc;
- struct ahc_scb *scb;
+ struct ahc_data *ahc;
+ struct scb *scb;
{
struct scsi_xfer *xs = scb->xs;
-
-#ifdef AHC_MORE_DEBUG
- if ((xs->sc_link->target & 0xf) == DEBUGTARGET) {
- xs->sc_link->flags |= 0xf0;
- SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n"));
- printf("%x %x %x %x\n",
- scb->flags,
- scb->target_status,
- xs->flags,
- xs->error);
- }
-#endif
-
+
+ SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n"));
/*
* Put the results of the operation
* into the xfer and call whoever started it
*/
- if (xs->error == XS_NOERROR) {
- if (scb->flags == SCB_ABORTED)
- xs->error = XS_DRIVER_STUFFUP;
- else if (scb->flags == SCB_CHKSENSE)
- xs->error = XS_SENSE;
+#if defined(__NetBSD__)
+ if (xs->error != XS_NOERROR) {
+ /* Don't override the error value. */
+ } else if (scb->flags & SCB_ABORTED) {
+ xs->error = XS_DRIVER_STUFFUP;
+ } else
+#endif
+ if(scb->flags & SCB_SENSE)
+ xs->error = XS_SENSE;
+ if(scb->flags & SCB_SENTORDEREDTAG)
+ ahc->in_timeout = FALSE;
+#if defined(__FreeBSD__)
+ if ((xs->flags & SCSI_ERR_OK) && !(xs->error == XS_SENSE)) {
+ /* All went correctly OR errors expected */
+ xs->error = XS_NOERROR;
}
-
+#elif defined(__NetBSD__)
+ /*
+ * Since NetBSD doesn't have error ignoring operation mode
+ * (SCSI_ERR_OK in FreeBSD), we don't have to care this case.
+ */
+#endif
xs->flags |= ITSDONE;
-
#ifdef AHC_TAGENABLE
- if (xs->cmd->opcode == 0x12 && xs->error == XS_NOERROR) {
+ if(xs->cmd->opcode == INQUIRY && xs->error == XS_NOERROR)
+ {
struct scsi_inquiry_data *inq_data;
u_short mask = 0x01 << (xs->sc_link->target |
- (scb->target_channel_lun & 0x08));
+ (scb->tcl & 0x08));
/*
* Sneak a look at the results of the SCSI Inquiry
- * command and see if we can do Tagged queing. XXX This
+ * command and see if we can do Tagged queing. This
* should really be done by the higher level drivers.
*/
inq_data = (struct scsi_inquiry_data *)xs->data;
- if (((inq_data->device & SID_TYPE) == 0)
- && (inq_data->flags & SID_CmdQue)
- && !(ahc->tagenable & mask)) {
- /*
- * Disk type device and can tag
- */
- sc_print_addr(xs->sc_link);
- printf("Tagged Queuing Device\n");
+ if((inq_data->flags & SID_CmdQue) && !(ahc->tagenable & mask))
+ {
+ printf(AHCNAME_FMT
+ ": target %d Tagged Queuing Device\n",
+ AHCNAME_VAR(ahc), xs->sc_link->target);
ahc->tagenable |= mask;
-#ifdef QUEUE_FULL_SUPPORTED
- xs->sc_link->openings += 2; */
-#endif
+ if(ahc->maxhscbs >= 16 || (ahc->flags & AHC_PAGESCBS)) {
+ /* Default to 8 tags */
+ xs->sc_link->opennings += 6;
+ }
+ else
+ {
+ /*
+ * Default to 4 tags on whimpy
+ * cards that don't have much SCB
+ * space and can't page. This prevents
+ * a single device from hogging all
+ * slots. We should really have a better
+ * way of providing fairness.
+ */
+ xs->sc_link->opennings += 2;
+ }
}
}
#endif
-
ahc_free_scb(ahc, scb, xs->flags);
scsi_done(xs);
}
/*
* Start the board, ready for normal operation
*/
-/* XXXX clean */
int
ahc_init(ahc)
- struct ahc_softc *ahc;
+ struct ahc_data *ahc;
{
- int iobase = ahc->sc_iobase;
- u_char scsi_conf, sblkctl, i;
- int intdef, max_targ = 16, wait;
-
+ u_long iobase = ahc->baseport;
+ u_char scsi_conf, sblkctl, i;
+ int max_targ = 15;
/*
- * Assume we have a board at this stage
- * Find out the configured interupt and the card type.
+ * Assume we have a board at this stage and it has been reset.
*/
-#ifdef AHC_DEBUG
- printf("%s: scb %d bytes; SCB_SIZE %d bytes, ahc_dma %d bytes\n",
- ahc->sc_dev.dv_xname, sizeof(struct ahc_scb), SCB_DOWN_SIZE,
- sizeof(struct ahc_dma_seg));
-#endif /* AHC_DEBUG */
-
- /* Save the IRQ type before we do a chip reset */
-
- ahc->unpause = (inb(HCNTRL + iobase) & IRQMS) | INTEN;
- ahc->pause = ahc->unpause | PAUSE;
- outb(HCNTRL + iobase, CHIPRST | ahc->pause);
-
- /*
- * Ensure that the reset has finished
- */
- wait = 1000;
- while (wait--) {
- delay(1000);
- if (!(inb(HCNTRL + iobase) & CHIPRST))
- break;
- }
- if (wait == 0) {
- printf("\n%s: WARNING - Failed chip reset! "
- "Trying to initialize anyway.\n", ahc->sc_dev.dv_xname);
- /* Forcibly clear CHIPRST */
- outb(HCNTRL + iobase, ahc->pause);
- }
+ /* Handle the SCBPAGING option */
+#ifndef AHC_SCBPAGING_ENABLE
+ ahc->flags &= ~AHC_PAGESCBS;
+#endif
- switch (ahc->type) {
- case AHC_274:
- printf("%s: 274x ", ahc->sc_dev.dv_xname);
- ahc->maxscbs = 0x4;
- break;
- case AHC_284:
- printf("%s: 284x ", ahc->sc_dev.dv_xname);
- ahc->maxscbs = 0x4;
- break;
- case AHC_AIC7870:
- case AHC_294:
- if (ahc->type == AHC_AIC7870)
- printf("%s: aic7870 ", ahc->sc_dev.dv_xname);
- else
- printf("%s: 294x ", ahc->sc_dev.dv_xname);
- ahc->maxscbs = 0x10;
- #define DFTHRESH 3
- outb(DSPCISTATUS + iobase, DFTHRESH << 6);
- /*
- * XXX Hard coded SCSI ID until we can read it from the
- * SEEPROM or NVRAM.
- */
- outb(HA_SCSICONF + iobase, 0x07 | (DFTHRESH << 6));
- /* In case we are a wide card */
- outb(HA_SCSICONF + 1 + iobase, 0x07);
- break;
- default:
- printf("%s: unknown(0x%x) ", ahc->sc_dev.dv_xname, ahc->type);
- break;
- }
-
/* Determine channel configuration and who we are on the scsi bus. */
- switch ((sblkctl = inb(SBLKCTL + iobase) & 0x0f)) {
- case 0:
- ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID);
- printf("Single Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev);
- outb(HA_FLAGS + iobase, SINGLE_BUS);
+ switch ( (sblkctl = inb(SBLKCTL + iobase) & 0x0a) ) {
+ case 0:
+ ahc->our_id = (inb(SCSICONF + iobase) & HSCSIID);
+ if(ahc->type == AHC_394)
+ printf("Channel %c, SCSI Id=%d, ",
+ ahc->flags & AHC_CHNLB ? 'B' : 'A',
+ ahc->our_id);
+ else
+ printf("Single Channel, SCSI Id=%d, ", ahc->our_id);
+ outb(FLAGS + iobase, SINGLE_BUS | (ahc->flags & AHC_PAGESCBS));
break;
- case 2:
- ahc->ahc_scsi_dev = (inb(HA_SCSICONF + 1 + iobase) & HWSCSIID);
- printf("Wide Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev);
+ case 2:
+ ahc->our_id = (inb(SCSICONF + 1 + iobase) & HWSCSIID);
+ if(ahc->type == AHC_394)
+ printf("Wide Channel %c, SCSI Id=%d, ",
+ ahc->flags & AHC_CHNLB ? 'B' : 'A',
+ ahc->our_id);
+ else
+ printf("Wide Channel, SCSI Id=%d, ", ahc->our_id);
ahc->type |= AHC_WIDE;
- outb(HA_FLAGS + iobase, WIDE_BUS);
+ outb(FLAGS + iobase, WIDE_BUS | (ahc->flags & AHC_PAGESCBS));
break;
- case 8:
- ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID);
- ahc->ahc_scsi_dev_b = (inb(HA_SCSICONF + 1 + iobase) & HSCSIID);
+ case 8:
+ ahc->our_id = (inb(SCSICONF + iobase) & HSCSIID);
+ ahc->our_id_b = (inb(SCSICONF + 1 + iobase) & HSCSIID);
printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, ",
- ahc->ahc_scsi_dev, ahc->ahc_scsi_dev_b);
+ ahc->our_id, ahc->our_id_b);
ahc->type |= AHC_TWIN;
- outb(HA_FLAGS + iobase, TWIN_BUS);
+ outb(FLAGS + iobase, TWIN_BUS | (ahc->flags & AHC_PAGESCBS));
break;
- default:
- printf(" Unsupported adapter type. %x Ignoring\n", sblkctl);
+ default:
+ printf(" Unsupported adapter type. Ignoring\n");
return(-1);
}
- /*
- * Take the bus led out of diagnostic mode
- */
- outb(SBLKCTL + iobase, sblkctl);
+ /* Determine the number of SCBs */
- /*
- * Number of SCBs that will be used. Rev E aic7770s and
- * aic7870s have 16. The rest have 4.
- */
- if (!(ahc->type & AHC_AIC7870)) {
- /*
- * See if we have a Rev E or higher
- * aic7770. Anything below a Rev E will
- * have a R/O autoflush disable configuration
- * bit.
- */
- u_char sblkctl_orig;
- sblkctl_orig = inb(SBLKCTL + iobase);
- sblkctl = sblkctl_orig ^ AUTOFLUSHDIS;
- outb(SBLKCTL + iobase, sblkctl);
- sblkctl = inb(SBLKCTL + iobase);
- if (sblkctl != sblkctl_orig) {
- printf("aic7770 >= Rev E, ");
- /*
- * Ensure autoflush is enabled
- */
- sblkctl &= ~AUTOFLUSHDIS;
- outb(SBLKCTL + iobase, sblkctl);
- } else
- printf("aic7770 <= Rev C, ");
- } else
- printf("aic7870, ");
- printf("%d SCBs\n", ahc->maxscbs);
-
- if (ahc->pause & IRQMS)
- printf("%s: Using Level Sensitive Interrupts\n",
- ahc->sc_dev.dv_xname);
- else
- printf("%s: Using Edge Triggered Interrupts\n",
- ahc->sc_dev.dv_xname);
-
- if (!(ahc->type & AHC_AIC7870)) {
- /*
- * The 294x cards are PCI, so we get their interrupt from the
- * PCI BIOS.
- */
+ {
+ outb(SCBPTR + iobase, 0);
+ outb(SCB_CONTROL + iobase, 0);
+ for(i = 1; i < AHC_SCB_MAX; i++) {
+ outb(SCBPTR + iobase, i);
+ outb(SCB_CONTROL + iobase, i);
+ if(inb(SCB_CONTROL + iobase) != i)
+ break;
+ outb(SCBPTR + iobase, 0);
+ if(inb(SCB_CONTROL + iobase) != 0)
+ break;
+ /* Clear the control byte. */
+ outb(SCBPTR + iobase, i);
+ outb(SCB_CONTROL + iobase, 0);
- intdef = inb(INTDEF + iobase);
- switch (intdef & 0xf) {
- case 9:
- ahc->sc_irq = 9;
- break;
- case 10:
- ahc->sc_irq = 10;
- break;
- case 11:
- ahc->sc_irq = 11;
- break;
- case 12:
- ahc->sc_irq = 12;
- break;
- case 14:
- ahc->sc_irq = 14;
- break;
- case 15:
- ahc->sc_irq = 15;
- break;
- default:
- printf("illegal irq setting\n");
- return (EIO);
+ ahc->qcntmask |= i; /* Update the count mask. */
}
+
+ /* Ensure we clear the 0 SCB's control byte. */
+ outb(SCBPTR + iobase, 0);
+ outb(SCB_CONTROL + iobase, 0);
+
+ ahc->qcntmask |= i;
+ ahc->maxhscbs = i;
}
-
- /* Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels */
- if (ahc->type & AHC_TWIN) {
+
+ if((ahc->maxhscbs < AHC_SCB_MAX) && (ahc->flags & AHC_PAGESCBS))
+ ahc->maxscbs = AHC_SCB_MAX;
+ else {
+ ahc->maxscbs = ahc->maxhscbs;
+ ahc->flags &= ~AHC_PAGESCBS;
+ }
+
+ printf("%d SCBs\n", ahc->maxhscbs);
+
+#ifdef AHC_DEBUG
+ if(ahc_debug & AHC_SHOWMISC) {
+ struct scb test;
+ printf(AHCNAME_FMT ": hardware scb %ld bytes; kernel scb; "
+ "ahc_dma %d bytes\n",
+ AHCNAME_VAR(ahc),
+ (u_long)&(test.next) - (u_long)(&test),
+ sizeof(test),
+ sizeof(struct ahc_dma_seg));
+ }
+#endif /* AHC_DEBUG */
+
+ /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
+ if(ahc->type & AHC_TWIN)
+ {
/*
* The device is gated to channel B after a chip reset,
* so set those values first
*/
- outb(SCSIID + iobase, ahc->ahc_scsi_dev_b);
- scsi_conf = inb(HA_SCSICONF + 1 + iobase) & (ENSPCHK|STIMESEL);
+ outb(SCSIID + iobase, ahc->our_id_b);
+ scsi_conf = inb(SCSICONF + 1 + iobase) & (ENSPCHK|STIMESEL);
outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN);
- outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR);
+ outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
+ if(ahc->type & AHC_ULTRA)
+ outb(SXFRCTL0 + iobase, DFON|SPIOEN|ULTRAEN);
+ else
+ outb(SXFRCTL0 + iobase, DFON|SPIOEN);
+
+ /* Reset the bus */
+ outb(SCSISEQ + iobase, SCSIRSTO);
+ DELAY(1000);
+ outb(SCSISEQ + iobase, 0);
+
+ /* Ensure we don't get a RSTI interrupt from this */
+ outb(CLRSINT1 + iobase, CLRSCSIRSTI);
+ outb(CLRINT + iobase, CLRSCSIINT);
+
/* Select Channel A */
outb(SBLKCTL + iobase, 0);
}
- outb(SCSIID + iobase, ahc->ahc_scsi_dev);
- scsi_conf = inb(HA_SCSICONF + iobase) & (ENSPCHK|STIMESEL);
+ outb(SCSIID + iobase, ahc->our_id);
+ scsi_conf = inb(SCSICONF + iobase) & (ENSPCHK|STIMESEL);
outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN);
- outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR);
-
+ outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
+ if(ahc->type & AHC_ULTRA)
+ outb(SXFRCTL0 + iobase, DFON|SPIOEN|ULTRAEN);
+ else
+ outb(SXFRCTL0 + iobase, DFON|SPIOEN);
+
+ /* Reset the bus */
+ outb(SCSISEQ + iobase, SCSIRSTO);
+ DELAY(1000);
+ outb(SCSISEQ + iobase, 0);
+
+ /* Ensure we don't get a RSTI interrupt from this */
+ outb(CLRSINT1 + iobase, CLRSCSIRSTI);
+ outb(CLRINT + iobase, CLRSCSIINT);
+
/*
* Look at the information that board initialization or
* the board bios has left us. In the lower four bits of each
* target's scratch space any value other than 0 indicates
* that we should initiate syncronous transfers. If it's zero,
* the user or the BIOS has decided to disable syncronous
- * negotiation to that target so we don't activate the needsdr
+ * negotiation to that target so we don't activate the needsdtr
* flag.
*/
ahc->needsdtr_orig = 0;
ahc->needwdtr_orig = 0;
- if (!(ahc->type & AHC_WIDE))
- max_targ = 8;
- for (i = 0; i < max_targ; i++) {
- u_char target_settings = inb(HA_TARG_SCRATCH + i + iobase);
-#if 0 /* XXXX */
- target_settings |= 0x8f;
-#endif
- if (target_settings & 0x0f) {
+ /* Grab the disconnection disable table and invert it for our needs */
+ if(ahc->flags & AHC_USEDEFAULTS) {
+ printf(AHCNAME_FMT
+ ": Host Adapter Bios disabled. Using default SCSI "
+ "device parameters\n", AHCNAME_VAR(ahc));
+ ahc->discenable = 0xff;
+ }
+ else
+ ahc->discenable = ~((inb(DISC_DSB + iobase + 1) << 8)
+ | inb(DISC_DSB + iobase));
+
+ if(!(ahc->type & (AHC_WIDE|AHC_TWIN)))
+ max_targ = 7;
+
+ for(i = 0; i <= max_targ; i++){
+ u_char target_settings;
+ if (ahc->flags & AHC_USEDEFAULTS) {
+ target_settings = 0; /* 10MHz */
ahc->needsdtr_orig |= (0x01 << i);
- /* Default to a asyncronous transfers (0 offset) */
- target_settings &= 0xf0;
- }
- if (target_settings & 0x80) {
ahc->needwdtr_orig |= (0x01 << i);
- /*
- * We'll set the Wide flag when we
- * are successful with Wide negotiation,
- * so turn it off for now so we aren't
- * confused.
- */
- target_settings &= 0x7f;
}
- outb(HA_TARG_SCRATCH + i + iobase, target_settings);
+ else {
+ /* Take the settings leftover in scratch RAM. */
+ target_settings = inb(TARG_SCRATCH + i + iobase);
+
+ if(target_settings & 0x0f){
+ ahc->needsdtr_orig |= (0x01 << i);
+ /*Default to a asyncronous transfers(0 offset)*/
+ target_settings &= 0xf0;
+ }
+ if(target_settings & 0x80){
+ ahc->needwdtr_orig |= (0x01 << i);
+ /*
+ * We'll set the Wide flag when we
+ * are successful with Wide negotiation.
+ * Turn it off for now so we aren't
+ * confused.
+ */
+ target_settings &= 0x7f;
+ }
+ }
+ outb(TARG_SCRATCH+i+iobase,target_settings);
}
/*
* If we are not a WIDE device, forget WDTR. This
* leave these fields cleared when the BIOS is not
* installed.
*/
- if (!(ahc->type & AHC_WIDE))
+ if(!(ahc->type & AHC_WIDE))
ahc->needwdtr_orig = 0;
ahc->needsdtr = ahc->needsdtr_orig;
ahc->needwdtr = ahc->needwdtr_orig;
ahc->sdtrpending = 0;
ahc->wdtrpending = 0;
ahc->tagenable = 0;
-
- /*
- * Clear the control byte for every SCB so that the sequencer
- * doesn't get confused and think that one of them is valid
- */
- for (i = 0; i < ahc->maxscbs; i++) {
- outb(SCBPTR + iobase, i);
- outb(SCBARRAY + iobase, 0);
- }
+ ahc->orderedtag = 0;
#ifdef AHC_DEBUG
- printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n", ahc->needsdtr,
- ahc->needwdtr);
+ /* How did we do? */
+ if(ahc_debug & AHC_SHOWMISC)
+ printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n"
+ "DISCENABLE == 0x%x\n", ahc->needsdtr,
+ ahc->needwdtr, ahc->discenable);
#endif
-
/*
* Set the number of availible SCBs
*/
- outb(HA_SCBCOUNT + iobase, ahc->maxscbs);
+ outb(SCBCOUNT + iobase, ahc->maxhscbs);
+
+ /*
+ * 2's compliment of maximum tag value
+ */
+ i = ahc->maxscbs;
+ outb(COMP_SCBCOUNT + iobase, -i & 0xff);
+
+ /*
+ * QCount mask to deal with broken aic7850s that
+ * sporatically get garbage in the upper bits of
+ * their QCount registers.
+ */
+ outb(QCNTMASK + iobase, ahc->qcntmask);
/* We don't have any busy targets right now */
- outb(HA_ACTIVE0 + iobase, 0);
- outb(HA_ACTIVE1 + iobase, 0);
-
+ outb(ACTIVE_A + iobase, 0);
+ outb(ACTIVE_B + iobase, 0);
+
/* We don't have any waiting selections */
outb(WAITING_SCBH + iobase, SCB_LIST_NULL);
- outb(WAITING_SCBT + iobase, SCB_LIST_NULL);
+
+ /* Our disconnection list is empty too */
+ outb(DISCONNECTED_SCBH + iobase, SCB_LIST_NULL);
+
+ /* Message out buffer starts empty */
+ outb(MSG_LEN + iobase, 0x00);
+
/*
- * Load the Sequencer program and Enable the adapter.
- * Place the aic7770 in fastmode which makes a big
- * difference when doing many small block transfers.
- */
-
- printf("%s: Downloading Sequencer Program...", ahc->sc_dev.dv_xname);
+ * Load the Sequencer program and Enable the adapter
+ * in "fast" mode.
+ */
+ if(bootverbose)
+ printf(AHCNAME_FMT ": Downloading Sequencer Program...",
+ AHCNAME_VAR(ahc));
+
ahc_loadseq(iobase);
- printf("Done\n");
-
- if (!(ahc->type & AHC_AIC7870))
- outb(BCTL + iobase, ENABLE);
-
- /* Reset the bus */
- outb(SCSISEQ + iobase, SCSIRSTO);
- delay(1000);
- outb(SCSISEQ + iobase, 0);
-
- RESTART_SEQUENCER(ahc);
-
+
+ if(bootverbose)
+ printf("Done\n");
+
+ outb(SEQCTL + iobase, FASTMODE);
+
+ UNPAUSE_SEQUENCER(ahc);
+
+ /*
+ * Note that we are going and return (to probe)
+ */
+ ahc->flags |= AHC_INIT;
return (0);
}
-void
+static void
ahcminphys(bp)
- struct buf *bp;
+ struct buf *bp;
{
-
- if (bp->b_bcount > ((AHC_NSEG - 1) << PGSHIFT))
- bp->b_bcount = ((AHC_NSEG - 1) << PGSHIFT);
+/*
+ * Even though the card can transfer up to 16megs per command
+ * we are limited by the number of segments in the dma segment
+ * list that we can hold. The worst case is that all pages are
+ * discontinuous physically, hense the "page per segment" limit
+ * enforced here.
+ */
+ if (bp->b_bcount > ((AHC_NSEG - 1) * PAGESIZ)) {
+ bp->b_bcount = ((AHC_NSEG - 1) * PAGESIZ);
+ }
+#if defined(__NetBSD__)
minphys(bp);
+#endif
}
/*
* the data address, target, and lun all of which
* are stored in the scsi_xfer struct
*/
-int
+static int32_t
ahc_scsi_cmd(xs)
- struct scsi_xfer *xs;
+ struct scsi_xfer *xs;
{
- struct scsi_link *sc_link = xs->sc_link;
- struct ahc_softc *ahc = sc_link->adapter_softc;
- struct ahc_scb *scb;
- struct ahc_dma_seg *sg;
- int seg; /* scatter gather seg being worked on */
- u_long thiskv, thisphys, nextphys;
- int bytes_this_seg, bytes_this_page, datalen, flags;
- int s;
- u_short mask = (0x01 << (sc_link->target | (sc_link->quirks & 0x08)));
-
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- printf("ahc ahc_scsi_cmd for %x\n", sc_link->target);
- sc_link->flags = 0xf0;
- SC_DEBUG(sc_link, SDEV_DB2, ("ahc_scsi_cmd\n"));
- }
-#endif
-
- /*
- * get a scb to use. If the transfer
- * is from a buf (possibly from interrupt time)
- * then we can't allow it to sleep
- */
- flags = xs->flags;
- if ((flags & (ITSDONE|INUSE)) != INUSE) {
- printf("%s: done or not in use?\n", ahc->sc_dev.dv_xname);
- xs->flags &= ~ITSDONE;
- xs->flags |= INUSE;
- }
- if ((scb = ahc_get_scb(ahc, flags)) == NULL) {
- xs->error = XS_DRIVER_STUFFUP;
- return (TRY_AGAIN_LATER);
- }
- scb->xs = xs;
-
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUG(sc_link, SDEV_DB3, ("start scb(%x)\n", scb));
- }
+ struct scb *scb;
+ struct ahc_dma_seg *sg;
+ int seg; /* scatter gather seg being worked on */
+ int thiskv;
+ physaddr thisphys, nextphys;
+ int bytes_this_seg, bytes_this_page, datalen, flags;
+ struct ahc_data *ahc;
+ u_short mask;
+ int s;
+
+ ahc = (struct ahc_data *)xs->sc_link->adapter_softc;
+ mask = (0x01 << (xs->sc_link->target
+#if defined(__FreeBSD__)
+ | ((u_long)xs->sc_link->fordriver & 0x08)));
+#elif defined(__NetBSD__)
+ | (IS_SCSIBUS_B(ahc, xs->sc_link) ? SELBUSB : 0) ));
#endif
-
- if (flags & SCSI_RESET) {
- /* XXX: Needs Implementation */
- printf("ahc: SCSI_RESET called.\n");
+ SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_scsi_cmd\n"));
+ /*
+ * get an scb to use. If the transfer
+ * is from a buf (possibly from interrupt time)
+ * then we can't allow it to sleep
+ */
+ flags = xs->flags;
+ if (flags & ITSDONE) {
+ printf(AHCNAME_FMT ": Already done?", AHCNAME_VAR(ahc));
+ xs->flags &= ~ITSDONE;
+ }
+ if (!(flags & INUSE)) {
+ printf(AHCNAME_FMT ": Not in use?", AHCNAME_VAR(ahc));
+ xs->flags |= INUSE;
+ }
+ if (!(scb = ahc_get_scb(ahc, flags))) {
+ xs->error = XS_DRIVER_STUFFUP;
+ return (TRY_AGAIN_LATER);
+ }
+ SC_DEBUG(xs->sc_link, SDEV_DB3, ("start scb(%p)\n", scb));
+ scb->xs = xs;
+ if (flags & SCSI_RESET)
+ scb->flags |= SCB_DEVICE_RESET|SCB_IMMED;
+ /*
+ * Put all the arguments for the xfer in the scb
+ */
+
+ if(ahc->tagenable & mask) {
+ scb->control |= TAG_ENB;
+ if(ahc->orderedtag & mask) {
+ printf("Ordered Tag sent\n");
+ scb->control |= 0x02;
+ ahc->orderedtag &= ~mask;
+ }
}
-
- /*
- * Put all the arguments for the xfer in the scb
- */
- scb->control = 0;
- if (ahc->tagenable & mask)
- scb->control |= SCB_TE;
- if ((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask)) {
- scb->control |= SCB_NEEDWDTR;
+ if(ahc->discenable & mask)
+ scb->control |= DISCENB;
+ if((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask))
+ {
+ scb->control |= NEEDWDTR;
ahc->wdtrpending |= mask;
}
- if ((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask)) {
- scb->control |= SCB_NEEDSDTR;
+ else if((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask))
+ {
+ scb->control |= NEEDSDTR;
ahc->sdtrpending |= mask;
}
- scb->target_channel_lun = ((sc_link->target << 4) & 0xF0) |
- (sc_link->quirks & 0x08) | (sc_link->lun & 0x07);
+ scb->tcl = ((xs->sc_link->target << 4) & 0xF0) |
+#if defined(__FreeBSD__)
+ ((u_long)xs->sc_link->fordriver & 0x08) |
+#elif defined(__NetBSD__)
+ (IS_SCSIBUS_B(ahc,xs->sc_link)? SELBUSB : 0)|
+#endif
+ (xs->sc_link->lun & 0x07);
scb->cmdlen = xs->cmdlen;
- scb->cmdpointer = vtophys(xs->cmd);
-
+ scb->cmdpointer = KVTOPHYS(xs->cmd);
xs->resid = 0;
- if (xs->datalen) {
- scb->SG_list_pointer = vtophys(scb->ahc_dma);
+ xs->status = 0;
+ if (xs->datalen) { /* should use S/G only if not zero length */
+ scb->SG_list_pointer = KVTOPHYS(scb->ahc_dma);
sg = scb->ahc_dma;
seg = 0;
- {
- /*
- * Set up the scatter gather block
- */
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUG(sc_link, SDEV_DB4,
- ("%ld @%x:- ", xs->datalen, xs->data));
- }
-#endif
- datalen = xs->datalen;
- thiskv = (long) xs->data;
- thisphys = vtophys(thiskv);
-
- while (datalen && seg < AHC_NSEG) {
- bytes_this_seg = 0;
-
- /* put in the base address */
- sg->seg_addr = thisphys;
-
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUGN(sc_link, SDEV_DB4, ("0x%lx",
- thisphys));
- }
-#endif
+ /*
+ * Set up the scatter gather block
+ */
+ SC_DEBUG(xs->sc_link, SDEV_DB4,
+ ("%ld @%p:- ", xs->datalen, xs->data));
+ datalen = xs->datalen;
+ thiskv = (int) xs->data;
+ thisphys = KVTOPHYS(thiskv);
- /* do it at least once */
- nextphys = thisphys;
- while (datalen && thisphys == nextphys) {
- /*
- * This page is contiguous (physically)
- * with the the last, just extend the
- * length
- */
- /* how far to the end of the page */
- nextphys = (thisphys & ~PGOFSET) + NBPG;
- bytes_this_page = nextphys - thisphys;
- /**** or the data ****/
- bytes_this_page = min(bytes_this_page,
- datalen);
- bytes_this_seg += bytes_this_page;
- datalen -= bytes_this_page;
-
- /* get more ready for the next page */
- thiskv = (thiskv & ~PGOFSET) + NBPG;
- if (datalen)
- thisphys = vtophys(thiskv);
- }
+ while ((datalen) && (seg < AHC_NSEG)) {
+ bytes_this_seg = 0;
+
+ /* put in the base address */
+ sg->addr = thisphys;
+
+ SC_DEBUGN(xs->sc_link, SDEV_DB4, ("0x%lx", thisphys));
+
+ /* do it at least once */
+ nextphys = thisphys;
+ while ((datalen) && (thisphys == nextphys)) {
/*
- * next page isn't contiguous, finish the seg
+ * This page is contiguous (physically)
+ * with the the last, just extend the
+ * length
*/
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUGN(sc_link, SDEV_DB4, ("(0x%x)",
- bytes_this_seg));
- }
-#endif
- sg->seg_len = bytes_this_seg;
- sg++;
- seg++;
+ /* how far to the end of the page */
+ nextphys = (thisphys & (~(PAGESIZ - 1)))
+ + PAGESIZ;
+ bytes_this_page = nextphys - thisphys;
+ /**** or the data ****/
+ bytes_this_page = min(bytes_this_page ,datalen);
+ bytes_this_seg += bytes_this_page;
+ datalen -= bytes_this_page;
+
+ /* get more ready for the next page */
+ thiskv = (thiskv & (~(PAGESIZ - 1)))
+ + PAGESIZ;
+ if (datalen)
+ thisphys = KVTOPHYS(thiskv);
}
- }
- /*end of iov/kv decision */
- scb->SG_segment_count = seg;
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUGN(sc_link, SDEV_DB4, ("\n"));
- }
-#endif
- if (datalen) {
/*
- * there's still data, must have run out of segs!
+ * next page isn't contiguous, finish the seg
*/
- printf("%s: ahc_scsi_cmd: more than %d dma segs\n",
- ahc->sc_dev.dv_xname, AHC_NSEG);
+ SC_DEBUGN(xs->sc_link, SDEV_DB4,
+ ("(0x%x)", bytes_this_seg));
+ sg->len = bytes_this_seg;
+ sg++;
+ seg++;
+ }
+ scb->SG_segment_count = seg;
+
+ /* Copy the first SG into the data pointer area */
+ scb->data = scb->ahc_dma->addr;
+ scb->datalen = scb->ahc_dma->len;
+ SC_DEBUGN(xs->sc_link, SDEV_DB4, ("\n"));
+ if (datalen) {
+ /* there's still data, must have run out of segs! */
+ printf(AHCNAME_FMT
+ ": ahc_scsi_cmd: more than %d DMA segs\n",
+ AHCNAME_VAR(ahc), AHC_NSEG);
xs->error = XS_DRIVER_STUFFUP;
ahc_free_scb(ahc, scb, flags);
return (COMPLETE);
}
- } else {
- scb->SG_list_pointer = (physaddr)0;
+#ifdef AIC7XXX_BROKEN_CACHE
+ if (aic7xxx_broken_cache)
+ INVALIDATE_CACHE();
+#endif
+ }
+ else {
+ /*
+ * No data xfer, use non S/G values
+ */
scb->SG_segment_count = 0;
+ scb->SG_list_pointer = 0;
+ scb->data = 0;
+ scb->datalen = 0;
}
-#ifdef AHC_MORE_DEBUG
- if (sc_link->target == DEBUGTARGET)
+#ifdef AHC_DEBUG
+ if((ahc_debug & AHC_SHOWSCBS) && (xs->sc_link->target == DEBUGTARG))
ahc_print_scb(scb);
#endif
-
s = splbio();
- ahc_send_scb(ahc, scb);
+ if( scb->position != SCB_LIST_NULL )
+ {
+ /* We already have a valid slot */
+ u_long iobase = ahc->baseport;
+ u_char curscb;
- /*
- * Usually return SUCCESSFULLY QUEUED
- */
- if ((flags & SCSI_POLL) == 0) {
- timeout(ahc_timeout, scb, (xs->timeout * hz) / 1000);
- splx(s);
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUG(sc_link, SDEV_DB3, ("cmd_sent\n"));
+ PAUSE_SEQUENCER(ahc);
+ curscb = inb(SCBPTR + iobase);
+ outb(SCBPTR + iobase, scb->position);
+ ahc_send_scb(ahc, scb);
+ outb(SCBPTR + iobase, curscb);
+ outb(QINFIFO + iobase, scb->position);
+ UNPAUSE_SEQUENCER(ahc);
+ scb->flags = SCB_ACTIVE;
+ if (!(flags & SCSI_NOMASK)) {
+ timeout(ahc_timeout, (caddr_t)scb,
+ (xs->timeout * hz) / 1000);
}
-#endif
+ SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_sent\n"));
+ }
+ else {
+ scb->flags = SCB_WAITINGQ;
+ STAILQ_INSERT_TAIL(&ahc->waiting_scbs, scb, links);
+ ahc_run_waiting_queues(ahc);
+ }
+ if (!(flags & SCSI_NOMASK)) {
+ splx(s);
return (SUCCESSFULLY_QUEUED);
}
-
- splx(s);
-
/*
- * If we can't use interrupts, poll on completion
+ * If we can't use interrupts, poll for completion
*/
-#ifdef AHC_MORE_DEBUG
- if ((sc_link->target & 0xf) == DEBUGTARGET) {
- sc_link->flags = 0xf0;
- SC_DEBUG(sc_link, SDEV_DB3, ("cmd_wait\n"));
- }
-#endif
- if (ahc_poll(ahc, xs, xs->timeout)) {
- ahc_timeout(scb);
- if (ahc_poll(ahc, xs, 2000))
+ SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n"));
+ do {
+ if (ahc_poll(ahc, xs->timeout)) {
+ if (!(xs->flags & SCSI_SILENT))
+ printf("cmd fail\n");
ahc_timeout(scb);
- }
+ break;
+ }
+ } while (!(xs->flags & ITSDONE)); /* a non command complete intr */
+ splx(s);
return (COMPLETE);
}
* A scb (and hence an scb entry on the board is put onto the
* free list.
*/
-void
+static void
ahc_free_scb(ahc, scb, flags)
- struct ahc_softc *ahc;
- struct ahc_scb *scb;
- int flags;
+ struct ahc_data *ahc;
+ int flags;
+ struct scb *scb;
{
- int s;
+ struct scb *wscb;
+ unsigned int opri;
- s = splbio();
+ opri = splbio();
scb->flags = SCB_FREE;
- TAILQ_INSERT_TAIL(&ahc->free_scb, scb, chain);
-#ifdef AHC_DEBUG
- ahc->activescbs--;
-#endif
-
- /*
- * If there were none, wake anybody waiting for one to come free,
- * starting with queued entries.
- */
- if (scb->chain.tqe_next == 0)
- wakeup(&ahc->free_scb);
-
- splx(s);
-}
-
-/* XXXX check */
-static inline void
-ahc_init_scb(ahc, scb)
- struct ahc_softc *ahc;
- struct ahc_scb *scb;
-{
- int iobase = ahc->sc_iobase;
- u_char scb_index;
-
- bzero(scb, sizeof(struct ahc_scb));
- scb->position = ahc->numscbs;
- /*
- * Place in the scbarray
- * Never is removed. Position
- * in ahc->scbarray is the scbarray
- * position on the board we will
- * load it into.
- */
- ahc->scbarray[scb->position] = scb;
-
+ if(scb->position == SCB_LIST_NULL) {
+ STAILQ_INSERT_HEAD(&ahc->page_scbs, scb, links);
+ if(!scb->links.stqe_next && !ahc->free_scbs.stqh_first)
+ /*
+ * If there were no SCBs availible, wake anybody waiting
+ * for one to come free.
+ */
+ wakeup((caddr_t)&ahc->free_scbs);
+ }
/*
- * Initialize the host memory location
- * of this SCB down on the board and
- * flag that it should be DMA's before
- * reference. Also set its psuedo
- * next pointer (for use in the psuedo
- * list of SCBs waiting for selection)
- * to SCB_LIST_NULL.
+ * If there are any SCBS on the waiting queue,
+ * assign the slot of this "freed" SCB to the first
+ * one. We'll run the waiting queues after all command
+ * completes for a particular interrupt are completed
+ * or when we start another command.
*/
- scb->control = SCB_NEEDDMA;
- scb->host_scb = vtophys(scb);
- scb->next_waiting = SCB_LIST_NULL;
- PAUSE_SEQUENCER(ahc);
- scb_index = inb(SCBPTR + iobase);
- outb(SCBPTR + iobase, scb->position);
- outb(SCBCNT + iobase, SCBAUTO);
- outsb(SCBARRAY + iobase, scb, 31);
- outb(SCBCNT + iobase, 0);
- outb(SCBPTR + iobase, scb_index);
- UNPAUSE_SEQUENCER(ahc);
- scb->control = 0;
-}
-
-static inline void
-ahc_reset_scb(ahc, scb)
- struct ahc_softc *ahc;
- struct ahc_scb *scb;
-{
-
- bzero(scb, SCB_BZERO_SIZE);
+ else if((wscb = ahc->waiting_scbs.stqh_first) != NULL) {
+ wscb->position = scb->position;
+ STAILQ_REMOVE_HEAD(&ahc->waiting_scbs, links);
+ STAILQ_INSERT_HEAD(&ahc->assigned_scbs, wscb, links);
+ wscb->flags = SCB_ASSIGNEDQ;
+
+ /*
+ * The "freed" SCB will need to be assigned a slot
+ * before being used, so put it in the page_scbs
+ * queue.
+ */
+ scb->position = SCB_LIST_NULL;
+ STAILQ_INSERT_HEAD(&ahc->page_scbs, scb, links);
+ if(!scb->links.stqe_next && !ahc->free_scbs.stqh_first)
+ /*
+ * If there were no SCBs availible, wake anybody waiting
+ * for one to come free.
+ */
+ wakeup((caddr_t)&ahc->free_scbs);
+ }
+ else {
+ STAILQ_INSERT_HEAD(&ahc->free_scbs, scb, links);
+#ifdef AHC_DEBUG
+ ahc->activescbs--;
+#endif
+ if(!scb->links.stqe_next && !ahc->page_scbs.stqh_first)
+ /*
+ * If there were no SCBs availible, wake anybody waiting
+ * for one to come free.
+ */
+ wakeup((caddr_t)&ahc->free_scbs);
+ }
+ splx(opri);
}
/*
- * Get a free scb
- *
- * If there are none, see if we can allocate a new one.
+ * Get a free scb, either one already assigned to a hardware slot
+ * on the adapter or one that will require an SCB to be paged out before
+ * use. If there are none, see if we can allocate a new SCB. Otherwise
+ * either return an error or sleep.
*/
-struct ahc_scb *
+static struct scb *
ahc_get_scb(ahc, flags)
- struct ahc_softc *ahc;
- int flags;
+ struct ahc_data *ahc;
+ int flags;
{
- struct ahc_scb *scb;
- int s;
-
- s = splbio();
+ unsigned opri;
+ struct scb *scbp;
+ opri = splbio();
/*
* If we can and have to, sleep waiting for one to come free
* but only if we can't allocate a new one.
*/
- for (;;) {
- scb = ahc->free_scb.tqh_first;
- if (scb) {
- TAILQ_REMOVE(&ahc->free_scb, scb, chain);
- break;
+ while (1) {
+ if((scbp = ahc->free_scbs.stqh_first)) {
+ STAILQ_REMOVE_HEAD(&ahc->free_scbs, links);
}
- if (ahc->numscbs < ahc->maxscbs) {
- if (scb = (struct ahc_scb *) malloc(sizeof(struct ahc_scb),
- M_TEMP, M_NOWAIT)) {
- ahc_init_scb(ahc, scb);
+ else if((scbp = ahc->page_scbs.stqh_first)) {
+ STAILQ_REMOVE_HEAD(&ahc->page_scbs, links);
+ }
+ else if (ahc->numscbs < ahc->maxscbs) {
+ scbp = (struct scb *) malloc(sizeof(struct scb),
+ M_TEMP, M_NOWAIT);
+ if (scbp) {
+ bzero(scbp, sizeof(struct scb));
+ scbp->tag = ahc->numscbs;
+ if( ahc->numscbs < ahc->maxhscbs )
+ scbp->position = ahc->numscbs;
+ else
+ scbp->position = SCB_LIST_NULL;
ahc->numscbs++;
- } else {
- printf("%s: can't malloc scb\n",
- ahc->sc_dev.dv_xname);
- goto out;
+ /*
+ * Place in the scbarray
+ * Never is removed.
+ */
+ ahc->scbarray[scbp->tag] = scbp;
+ }
+ else {
+ printf(AHCNAME_FMT ": Can't malloc SCB\n",
+ AHCNAME_VAR(ahc));
+ }
+ }
+ else {
+ if (!(flags & SCSI_NOSLEEP)) {
+ tsleep((caddr_t)&ahc->free_scbs, PRIBIO,
+ "ahcscb", 0);
+ continue;
}
- break;
}
- if ((flags & SCSI_NOSLEEP) != 0)
- goto out;
- tsleep(&ahc->free_scb, PRIBIO, "ahcscb", 0);
+ break;
}
- ahc_reset_scb(ahc, scb);
- scb->flags = SCB_ACTIVE;
+ if (scbp) {
+ scbp->control = 0;
+ scbp->status = 0;
+ scbp->flags = 0;
#ifdef AHC_DEBUG
- ahc->activescbs++;
- if (ahc->activescbs == ahc->maxscbs)
- printf("%s: Max SCBs active\n", ahc->sc_dev.dv_xname);
+ ahc->activescbs++;
+ if((ahc_debug & AHC_SHOWSCBCNT)
+ && (ahc->activescbs == ahc->maxhscbs))
+ printf(AHCNAME_FMT ": Max SCBs active\n",
+ AHCNAME_VAR(ahc));
#endif
+ }
-out:
- splx(s);
- return (scb);
+ splx(opri);
+
+ return (scbp);
}
-/* XXXX check */
-void
-ahc_loadseq(iobase)
- int iobase;
+static void ahc_loadseq(iobase)
+ u_long iobase;
{
- static u_char seqprog[] = {
+ static unsigned char seqprog[] = {
# include "aic7xxx_seq.h"
};
outb(SEQCTL + iobase, PERRORDIS|SEQRESET|LOADRAM);
+
outsb(SEQRAM + iobase, seqprog, sizeof(seqprog));
+
outb(SEQCTL + iobase, FASTMODE|SEQRESET);
+ do {
+ outb(SEQCTL + iobase, SEQRESET|FASTMODE);
+
+ } while (inb(SEQADDR0 + iobase) != 0 &&
+ inb(SEQADDR1 + iobase) != 0);
}
/*
- * Function to poll for command completion when in poll mode
+ * Function to poll for command completion when
+ * interrupts are disabled (crash dumps)
*/
-int
-ahc_poll(ahc, xs, count)
- struct ahc_softc *ahc;
- struct scsi_xfer *xs;
- int count;
-{ /* in msec */
- int iobase = ahc->sc_iobase;
- int stport = INTSTAT + iobase;
-
- while (count) {
+static int
+ahc_poll(ahc, wait)
+ struct ahc_data *ahc;
+ int wait; /* in msec */
+{
+ u_long iobase = ahc->baseport;
+ u_long stport = INTSTAT + iobase;
+
+ while (--wait) {
+ DELAY(1000);
+ if (inb(stport) & INT_PEND)
+ break;
+ } if (wait == 0) {
+ printf(AHCNAME_FMT ": board not responding\n",
+ AHCNAME_VAR(ahc));
+ return (EIO);
+ }
+ ahc_intr((void *)ahc);
+ return (0);
+}
+
+static void
+ahc_timeout(arg)
+ void *arg;
+{
+ struct scb *scb = (struct scb *)arg;
+ struct ahc_data *ahc;
+ int s, h, found;
+ u_char bus_state;
+ u_long iobase;
+ char channel;
+
+ s = splbio();
+
+ h = splhigh();
+
+ if (!(scb->flags & SCB_ACTIVE)) {
+ /* Previous timeout took care of me already */
+ splx(h);
+ splx(s);
+ return;
+ }
+
+ ahc = (struct ahc_data *)scb->xs->sc_link->adapter_softc;
+
+ if (ahc->in_timeout) {
/*
- * If we had interrupts enabled, would we
- * have got an interrupt?
+ * Some other SCB has started a recovery operation
+ * and is still working on cleaning things up.
*/
- if (inb(stport) & INT_PEND)
- ahcintr(ahc);
- if (xs->flags & ITSDONE)
- return 0;
- delay(1000);
- count--;
+ if (scb->flags & SCB_TIMEDOUT) {
+ /*
+ * This SCB has been here before and is not the
+ * recovery SCB. Cut our losses and panic. Its
+ * better to do this than trash a filesystem.
+ */
+ panic(AHCNAME_FMT ": Timed-out command times out "
+ "again\n", AHCNAME_VAR(ahc));
+ }
+ else if (!(scb->flags & SCB_ABORTED))
+ {
+ /*
+ * This is not the SCB that started this timeout
+ * processing. Give this scb another lifetime so
+ * that it can continue once we deal with the
+ * timeout.
+ */
+ scb->flags |= SCB_TIMEDOUT;
+ timeout(ahc_timeout, (caddr_t)scb,
+ (scb->xs->timeout * hz) / 1000);
+ splx(h);
+ splx(s);
+ return;
+ }
}
- return 1;
+ ahc->in_timeout = TRUE;
+ splx(h);
+
+ /*
+ * Ensure that the card doesn't do anything
+ * behind our back.
+ */
+ PAUSE_SEQUENCER(ahc);
+
+ sc_print_addr(scb->xs->sc_link);
+ printf("timed out ");
+ /*
+ * Take a snapshot of the bus state and print out
+ * some information so we can track down driver bugs.
+ */
+ iobase = ahc->baseport;
+ bus_state = inb(iobase + LASTPHASE);
+
+ switch(bus_state & PHASE_MASK)
+ {
+ case P_DATAOUT:
+ printf("in dataout phase");
+ break;
+ case P_DATAIN:
+ printf("in datain phase");
+ break;
+ case P_COMMAND:
+ printf("in command phase");
+ break;
+ case P_MESGOUT:
+ printf("in message out phase");
+ break;
+ case P_STATUS:
+ printf("in status phase");
+ break;
+ case P_MESGIN:
+ printf("in message in phase");
+ break;
+ default:
+ printf("while idle, LASTPHASE == 0x%x",
+ bus_state);
+ /*
+ * We aren't in a valid phase, so assume we're
+ * idle.
+ */
+ bus_state = 0;
+ break;
+ }
+
+ printf(", SCSISIGI == 0x%x\n", inb(iobase + SCSISIGI));
+
+ /* Decide our course of action */
+
+ if(scb->flags & SCB_ABORTED)
+ {
+ /*
+ * Been down this road before.
+ * Do a full bus reset.
+ */
+ char channel = (scb->tcl & SELBUSB)
+ ? 'B': 'A';
+ found = ahc_reset_channel(ahc, channel, scb->tag,
+ XS_TIMEOUT, /*Initiate Reset*/TRUE);
+ printf(AHCNAME_FMT ": Issued Channel %c Bus Reset #1. "
+ "%d SCBs aborted\n", AHCNAME_VAR(ahc), channel, found);
+ ahc->in_timeout = FALSE;
+ }
+ else if(scb->control & TAG_ENB) {
+ /*
+ * We could be starving this command
+ * try sending an ordered tag command
+ * to the target we come from.
+ */
+ scb->flags |= SCB_ABORTED|SCB_SENTORDEREDTAG;
+ ahc->orderedtag |= 0xFF;
+ timeout(ahc_timeout, (caddr_t)scb, (5 * hz));
+ UNPAUSE_SEQUENCER(ahc);
+ printf("Ordered Tag queued\n");
+ goto done;
+ }
+ else {
+ /*
+ * Send a Bus Device Reset Message:
+ * The target that is holding up the bus may not
+ * be the same as the one that triggered this timeout
+ * (different commands have different timeout lengths).
+ * It is also impossible to get a message to a target
+ * if we are in a "frozen" data transfer phase. Our
+ * strategy here is to queue a bus device reset message
+ * to the timed out target if it is disconnected.
+ * Otherwise, if we have an active target we stuff the
+ * message buffer with a bus device reset message and
+ * assert ATN in the hopes that the target will let go
+ * of the bus and finally disconnect. If this fails,
+ * we'll get another timeout 2 seconds later which will
+ * cause a bus reset.
+ *
+ * XXX If the SCB is paged out, we simply reset the
+ * bus. We should probably queue a new command
+ * instead.
+ */
+
+ /* Test to see if scb is disconnected */
+ if( !(scb->flags & SCB_PAGED_OUT ) ){
+ u_char active_scb;
+ struct scb *active_scbp;
+
+ active_scb = inb(SCBPTR + iobase);
+ active_scbp = ahc->scbarray[inb(SCB_TAG + iobase)];
+ outb(SCBPTR + iobase, scb->position);
+
+ if(inb(SCB_CONTROL + iobase) & DISCONNECTED) {
+ if(ahc->flags & AHC_PAGESCBS) {
+ /*
+ * Pull this SCB out of the
+ * disconnected list.
+ */
+ u_char prev = inb(SCB_PREV + iobase);
+ u_char next = inb(SCB_NEXT + iobase);
+ if(prev == SCB_LIST_NULL) {
+ /* At the head */
+ outb(DISCONNECTED_SCBH + iobase,
+ next );
+ }
+ else {
+ outb(SCBPTR + iobase, prev);
+ outb(SCB_NEXT + iobase, next);
+ if(next != SCB_LIST_NULL) {
+ outb(SCBPTR + iobase,
+ next);
+ outb(SCB_PREV + iobase,
+ prev);
+ }
+ outb(SCBPTR + iobase,
+ scb->position);
+ }
+ }
+ scb->flags |= SCB_DEVICE_RESET|SCB_ABORTED;
+ scb->control &= DISCENB;
+ scb->cmdlen = 0;
+ scb->SG_segment_count = 0;
+ scb->SG_list_pointer = 0;
+ scb->data = 0;
+ scb->datalen = 0;
+ ahc_send_scb(ahc, scb);
+ ahc_add_waiting_scb(iobase, scb);
+ timeout(ahc_timeout, (caddr_t)scb, (2 * hz));
+ sc_print_addr(scb->xs->sc_link);
+ printf("BUS DEVICE RESET message queued.\n");
+ outb(SCBPTR + iobase, active_scb);
+ UNPAUSE_SEQUENCER(ahc);
+ goto done;
+ }
+ /* Is the active SCB really active? */
+ else if((active_scbp->flags & SCB_ACTIVE) && bus_state){
+ outb(MSG_LEN + iobase, 1);
+ outb(MSG0 + iobase, MSG_BUS_DEVICE_RESET);
+ outb(SCSISIGO + iobase, bus_state|ATNO);
+ sc_print_addr(active_scbp->xs->sc_link);
+ printf("asserted ATN - device reset in "
+ "message buffer\n");
+ active_scbp->flags |= SCB_DEVICE_RESET
+ | SCB_ABORTED;
+ if(active_scbp != scb) {
+ untimeout(ahc_timeout,
+ (caddr_t)active_scbp);
+ /* Give scb a new lease on life */
+ timeout(ahc_timeout, (caddr_t)scb,
+ (scb->xs->timeout * hz) / 1000);
+ }
+ timeout(ahc_timeout, (caddr_t)active_scbp,
+ (2 * hz));
+ outb(SCBPTR + iobase, active_scb);
+ UNPAUSE_SEQUENCER(ahc);
+ goto done;
+ }
+ }
+ /*
+ * No active target or a paged out SCB.
+ * Try reseting the bus.
+ */
+ channel = (scb->tcl & SELBUSB) ? 'B': 'A';
+ found = ahc_reset_channel(ahc, channel, scb->tag,
+ XS_TIMEOUT,
+ /*Initiate Reset*/TRUE);
+ printf(AHCNAME_FMT ": Issued Channel %c Bus Reset #2. "
+ "%d SCBs aborted\n", AHCNAME_VAR(ahc), channel,
+ found);
+ ahc->in_timeout = FALSE;
+ }
+done:
+ splx(s);
}
-/* XXXX check */
-void
-ahc_abort_scb(ahc, scb)
- struct ahc_softc *ahc;
- struct ahc_scb *scb;
+
+/*
+ * The device at the given target/channel has been reset. Abort
+ * all active and queued scbs for that target/channel.
+ */
+static int
+ahc_reset_device(ahc, target, channel, timedout_scb, xs_error)
+ struct ahc_data *ahc;
+ int target;
+ char channel;
+ u_char timedout_scb;
+ u_int32_t xs_error;
{
- int iobase = ahc->sc_iobase;
+ u_long iobase = ahc->baseport;
+ struct scb *scbp;
+ u_char active_scb;
+ int i = 0;
int found = 0;
- int scb_index;
- u_char flags;
- u_char scb_control;
- PAUSE_SEQUENCER(ahc);
+ /* restore this when we're done */
+ active_scb = inb(SCBPTR + iobase);
+
/*
- * Case 1: In the QINFIFO
+ * Search the QINFIFO.
*/
{
int saved_queue[AHC_SCB_MAX];
- int i;
- int queued = inb(QINCNT + iobase);
+ int queued = inb(QINCNT + iobase) & ahc->qcntmask;
for (i = 0; i < (queued - found); i++) {
saved_queue[i] = inb(QINFIFO + iobase);
- if (saved_queue[i] == scb->position) {
+ outb(SCBPTR + iobase, saved_queue[i]);
+ scbp = ahc->scbarray[inb(SCB_TAG + iobase)];
+ if (ahc_match_scb (scbp, target, channel)){
+ /*
+ * We found an scb that needs to be aborted.
+ */
+ scbp->flags = SCB_ABORTED|SCB_QUEUED_FOR_DONE;
+ scbp->xs->error |= xs_error;
+ if(scbp->position != timedout_scb)
+ untimeout(ahc_timeout, (caddr_t)scbp);
+ outb(SCB_CONTROL + iobase, 0);
i--;
- found = 1;
+ found++;
}
}
- /* Re-insert entries back into the queue */
- for (queued = 0; queued < i; queued++)
- outb(QINFIFO + iobase, saved_queue[queued]);
-
- if (found)
- goto done;
+ /* Now put the saved scbs back. */
+ for (queued = 0; queued < i; queued++) {
+ outb (QINFIFO + iobase, saved_queue[queued]);
+ }
}
-
- scb_index = inb(SCBPTR + iobase);
+
/*
- * Case 2: Not the active command
+ * Search waiting for selection list.
*/
- if (scb_index != scb->position) {
- /*
- * Select the SCB we want to abort
- * and turn off the disconnected bit.
- * the driver will then abort the command
- * and notify us of the abort.
- */
- outb(SCBPTR + iobase, scb->position);
- scb_control = inb(SCBARRAY + iobase);
- scb_control &= ~SCB_DIS;
- outb(SCBARRAY + iobase, scb_control);
- outb(SCBPTR + iobase, scb_index);
- goto done;
- }
- scb_control = inb(SCBARRAY + iobase);
- if (scb_control & SCB_DIS) {
- scb_control &= ~SCB_DIS;
- outb(SCBARRAY + iobase, scb_control);
- goto done;
+ {
+ u_char next, prev;
+
+ next = inb(WAITING_SCBH + iobase); /* Start at head of list. */
+ prev = SCB_LIST_NULL;
+
+ while (next != SCB_LIST_NULL) {
+ outb(SCBPTR + iobase, next);
+ scbp = ahc->scbarray[inb(SCB_TAG + iobase)];
+ /*
+ * Select the SCB.
+ */
+ if (ahc_match_scb(scbp, target, channel)) {
+ next = ahc_abort_wscb(ahc, scbp, prev,
+ iobase, timedout_scb, xs_error);
+ found++;
+ }
+ else {
+ prev = next;
+ next = inb(SCB_NEXT + iobase);
+ }
+ }
}
/*
- * Case 3: Currently active command
+ * Go through the entire SCB array now and look for
+ * commands for this target that are active. These
+ * are other (most likely tagged) commands that
+ * were disconnected when the reset occured.
*/
- if ((flags = inb(HA_FLAGS + iobase)) & ACTIVE_MSG) {
- /*
- * If there's a message in progress,
- * reset the bus and have all devices renegotiate.
- */
- if (scb->target_channel_lun & 0x08) {
- ahc->needsdtr |= (ahc->needsdtr_orig & 0xff00);
- ahc->sdtrpending &= 0x00ff;
- outb(HA_ACTIVE1, 0);
- } else if (ahc->type & AHC_WIDE) {
- ahc->needsdtr = ahc->needsdtr_orig;
- ahc->needwdtr = ahc->needwdtr_orig;
- ahc->sdtrpending = 0;
- ahc->wdtrpending = 0;
- outb(HA_ACTIVE0, 0);
- outb(HA_ACTIVE1, 0);
- } else {
- ahc->needsdtr |= (ahc->needsdtr_orig & 0x00ff);
- ahc->sdtrpending &= 0xff00;
- outb(HA_ACTIVE0, 0);
+ for(i = 0; i < ahc->numscbs; i++) {
+ scbp = ahc->scbarray[i];
+ if((scbp->flags & SCB_ACTIVE)
+ && ahc_match_scb(scbp, target, channel)) {
+ /* Ensure the target is "free" */
+ ahc_unbusy_target(target, channel, iobase);
+ if( !(scbp->flags & SCB_PAGED_OUT) )
+ {
+ outb(SCBPTR + iobase, scbp->position);
+ outb(SCB_CONTROL + iobase, 0);
+ }
+ scbp->flags = SCB_ABORTED|SCB_QUEUED_FOR_DONE;
+ scbp->xs->error |= xs_error;
+ if(scbp->tag != timedout_scb)
+ untimeout(ahc_timeout, (caddr_t)scbp);
+ found++;
}
+ }
+ outb(SCBPTR + iobase, active_scb);
+ return found;
+}
- /* Reset the bus */
- outb(SCSISEQ + iobase, SCSIRSTO);
- delay(1000);
- outb(SCSISEQ + iobase, 0);
- goto done;
+/*
+ * Manipulate the waiting for selection list and return the
+ * scb that follows the one that we remove.
+ */
+static u_char
+ahc_abort_wscb (ahc, scbp, prev, iobase, timedout_scb, xs_error)
+ struct ahc_data *ahc;
+ struct scb *scbp;
+ u_char prev;
+ u_long iobase;
+ u_char timedout_scb;
+ u_int32_t xs_error;
+{
+ u_char curscbp, next;
+ int target = ((scbp->tcl >> 4) & 0x0f);
+ char channel = (scbp->tcl & SELBUSB) ? 'B' : 'A';
+ /*
+ * Select the SCB we want to abort and
+ * pull the next pointer out of it.
+ */
+ curscbp = inb(SCBPTR + iobase);
+ outb(SCBPTR + iobase, scbp->position);
+ next = inb(SCB_NEXT + iobase);
+
+ /* Clear the necessary fields */
+ outb(SCB_CONTROL + iobase, 0);
+ outb(SCB_NEXT + iobase, SCB_LIST_NULL);
+ ahc_unbusy_target(target, channel, iobase);
+
+ /* update the waiting list */
+ if( prev == SCB_LIST_NULL )
+ /* First in the list */
+ outb(WAITING_SCBH + iobase, next);
+ else {
+ /*
+ * Select the scb that pointed to us
+ * and update its next pointer.
+ */
+ outb(SCBPTR + iobase, prev);
+ outb(SCB_NEXT + iobase, next);
}
-
/*
- * Otherwise, set up an abort message and have the sequencer
- * clean up
+ * Point us back at the original scb position
+ * and inform the SCSI system that the command
+ * has been aborted.
*/
- outb(HA_FLAGS + iobase, flags | ACTIVE_MSG);
- outb(HA_MSG_LEN + iobase, 1);
- outb(HA_MSG_START + iobase, MSG_ABORT);
-
- outb(SCSISIGO + iobase, inb(HA_SIGSTATE + iobase) | 0x10);
-
-done:
- scb->flags = SCB_ABORTED;
- UNPAUSE_SEQUENCER(ahc);
- ahc_done(ahc, scb);
- return;
+ outb(SCBPTR + iobase, curscbp);
+ scbp->flags = SCB_ABORTED|SCB_QUEUED_FOR_DONE;
+ scbp->xs->error |= xs_error;
+ if(scbp->tag != timedout_scb)
+ untimeout(ahc_timeout, (caddr_t)scbp);
+ return next;
}
-void
-ahc_timeout(arg)
- void *arg;
+static void
+ahc_busy_target(target, channel, iobase)
+ u_char target;
+ char channel;
+ u_long iobase;
{
- struct ahc_scb *scb = arg;
- struct scsi_xfer *xs = scb->xs;
- struct scsi_link *sc_link = xs->sc_link;
- struct ahc_softc *ahc = sc_link->adapter_softc;
- int s;
+ u_char active;
+ u_long active_port = ACTIVE_A + iobase;
+ if(target > 0x07 || channel == 'B') {
+ /*
+ * targets on the Second channel or
+ * above id 7 store info in byte two
+ * of HA_ACTIVE
+ */
+ active_port++;
+ }
+ active = inb(active_port);
+ active |= (0x01 << (target & 0x07));
+ outb(active_port, active);
+}
- sc_print_addr(sc_link);
- printf("timed out");
+static void
+ahc_unbusy_target(target, channel, iobase)
+ u_char target;
+ char channel;
+ u_long iobase;
+{
+ u_char active;
+ u_long active_port = ACTIVE_A + iobase;
+ if(target > 0x07 || channel == 'B') {
+ /*
+ * targets on the Second channel or
+ * above id 7 store info in byte two
+ * of HA_ACTIVE
+ */
+ active_port++;
+ }
+ active = inb(active_port);
+ active &= ~(0x01 << (target & 0x07));
+ outb(active_port, active);
+}
- s = splbio();
+static void
+ahc_reset_current_bus(iobase)
+ u_long iobase;
+{
+ outb(SCSISEQ + iobase, SCSIRSTO);
+ DELAY(1000);
+ outb(SCSISEQ + iobase, 0);
+}
-#ifdef SCSIDEBUG
- show_scsi_cmd(scb->xs);
-#endif
-#ifdef AHC_DEBUG
- if (ahc_debug & AHC_SHOWSCBS)
- ahc_print_active_scb(ahc);
-#endif /*AHC_DEBUG */
-
- if (scb->flags & SCB_IMMED) {
- printf("\n");
- scb->xs->retries = 0; /* I MEAN IT ! */
- scb->flags |= SCB_IMMED_FAIL;
- ahc_done(ahc, scb);
- splx(s);
- return;
+static int
+ahc_reset_channel(ahc, channel, timedout_scb, xs_error, initiate_reset)
+ struct ahc_data *ahc;
+ char channel;
+ u_char timedout_scb;
+ u_int32_t xs_error;
+ u_char initiate_reset;
+{
+ u_long iobase = ahc->baseport;
+ u_char sblkctl;
+ char cur_channel;
+ u_long offset, offset_max;
+ int found;
+
+ /*
+ * Clean up all the state information for the
+ * pending transactions on this bus.
+ */
+ found = ahc_reset_device(ahc, ALL_TARGETS, channel,
+ timedout_scb, xs_error);
+ if(channel == 'B'){
+ ahc->needsdtr |= (ahc->needsdtr_orig & 0xff00);
+ ahc->sdtrpending &= 0x00ff;
+ outb(ACTIVE_B + iobase, 0);
+ offset = TARG_SCRATCH + iobase + 8;
+ offset_max = TARG_SCRATCH + iobase + 16;
+ }
+ else if (ahc->type & AHC_WIDE){
+ ahc->needsdtr = ahc->needsdtr_orig;
+ ahc->needwdtr = ahc->needwdtr_orig;
+ ahc->sdtrpending = 0;
+ ahc->wdtrpending = 0;
+ outb(ACTIVE_A + iobase, 0);
+ outb(ACTIVE_B + iobase, 0);
+ offset = TARG_SCRATCH + iobase;
+ offset_max = TARG_SCRATCH + iobase + 16;
+ }
+ else{
+ ahc->needsdtr |= (ahc->needsdtr_orig & 0x00ff);
+ ahc->sdtrpending &= 0xff00;
+ outb(ACTIVE_A + iobase, 0);
+ offset = TARG_SCRATCH + iobase;
+ offset_max = TARG_SCRATCH + iobase + 8;
+ }
+ for(;offset < offset_max;offset++) {
+ /*
+ * Revert to async/narrow transfers
+ * until we renegotiate.
+ */
+ u_char targ_scratch;
+ targ_scratch = inb(offset);
+ targ_scratch &= SXFR;
+ outb(offset, targ_scratch);
}
/*
- * If it has been through before, then
- * a previous abort has failed, don't
- * try abort again
+ * Reset the bus if we are initiating this reset and
+ * restart/unpause the sequencer
*/
- if (scb->flags == SCB_ABORTED) {
- /* abort timed out */
- printf(" AGAIN\n");
- scb->xs->retries = 0; /* I MEAN IT ! */
- ahc_done(ahc, scb);
- } else {
- /* abort the operation that has timed out */
- printf("\n");
- scb->xs->error = XS_TIMEOUT;
- scb->flags = SCB_ABORTED;
- ahc_abort_scb(ahc, scb);
- /* 2 secs for the abort */
- if ((xs->flags & SCSI_POLL) == 0)
- timeout(ahc_timeout, scb, 2 * hz);
+ /* Case 1: Command for another bus is active */
+ sblkctl = inb(SBLKCTL + iobase);
+ cur_channel = (sblkctl & SELBUSB) ? 'B' : 'A';
+ if(cur_channel != channel)
+ {
+ /*
+ * Stealthily reset the other bus
+ * without upsetting the current bus
+ */
+ outb(SBLKCTL + iobase, sblkctl ^ SELBUSB);
+ if( initiate_reset )
+ {
+ ahc_reset_current_bus(iobase);
+ }
+ outb(CLRSINT1 + iobase, CLRSCSIRSTI|CLRSELTIMEO);
+ outb(CLRINT + iobase, CLRSCSIINT);
+ outb(SBLKCTL + iobase, sblkctl);
+ UNPAUSE_SEQUENCER(ahc);
}
+ /* Case 2: A command from this bus is active or we're idle */
+ else {
+ if( initiate_reset )
+ {
+ ahc_reset_current_bus(iobase);
+ }
+ outb(CLRSINT1 + iobase, CLRSCSIRSTI|CLRSELTIMEO);
+ outb(CLRINT + iobase, CLRSCSIINT);
+ RESTART_SEQUENCER(ahc);
+ }
+ ahc_run_done_queue(ahc);
+ return found;
+}
- splx(s);
+void
+ahc_run_done_queue(ahc)
+ struct ahc_data *ahc;
+{
+ int i;
+ struct scb *scbp;
+
+ for(i = 0; i < ahc->numscbs; i++) {
+ scbp = ahc->scbarray[i];
+ if(scbp->flags & SCB_QUEUED_FOR_DONE)
+ ahc_done(ahc, scbp);
+ }
+}
+
+static int
+ahc_match_scb (scb, target, channel)
+ struct scb *scb;
+ int target;
+ char channel;
+{
+ int targ = (scb->tcl >> 4) & 0x0f;
+ char chan = (scb->tcl & SELBUSB) ? 'B' : 'A';
+
+ if (target == ALL_TARGETS)
+ return (chan == channel);
+ else
+ return ((chan == channel) && (targ == target));
}
-/* $OpenBSD: aic7xxxvar.h,v 1.3 1996/04/21 22:21:12 deraadt Exp $ */
-/* $NetBSD: aic7xxxvar.h,v 1.3 1996/03/29 00:25:02 mycroft Exp $ */
-
/*
- * Interface to the generic driver for the aic7xxx based adaptec
- * SCSI controllers. This is used to implement product specific
+ * Interface to the generic driver for the aic7xxx based adaptec
+ * SCSI controllers. This is used to implement product specific
* probe and attach routines.
*
- * Copyright (c) 1994, 1995 Justin T. Gibbs.
+ * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. Absolutely no warranty of function or purpose is made by the author
- * Justin T. Gibbs.
- * 4. Modifications may be freely made to this file if the above conditions
- * are met.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: aic7xxxvar.h,v 1.4 1996/05/05 12:42:31 deraadt Exp $
*/
#ifndef _AIC7XXX_H_
#define _AIC7XXX_H_
+#if defined(__FreeBSD__)
+#include "ahc.h" /* for NAHC from config */
+#endif
+
+#ifndef STAILQ_ENTRY /* for NetBSD, from FreeBSD <sys/queue.h> */
+/*
+ * Singly-linked Tail queue definitions.
+ */
+#define STAILQ_HEAD(name, type) \
+struct name { \
+ struct type *stqh_first;/* first element */ \
+ struct type **stqh_last;/* addr of last next element */ \
+}
+
+#define STAILQ_ENTRY(type) \
+struct { \
+ struct type *stqe_next; /* next element */ \
+}
+
+/*
+ * Singly-linked Tail queue functions.
+ */
+#define STAILQ_INIT(head) { \
+ (head)->stqh_first = NULL; \
+ (head)->stqh_last = &(head)->stqh_first; \
+}
+
+#define STAILQ_INSERT_HEAD(head, elm, field) { \
+ if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \
+ (head)->stqh_last = &(elm)->field.stqe_next; \
+ (head)->stqh_first = (elm); \
+}
+
+#define STAILQ_INSERT_TAIL(head, elm, field) { \
+ (elm)->field.stqe_next = NULL; \
+ *(head)->stqh_last = (elm); \
+ (head)->stqh_last = &(elm)->field.stqe_next; \
+}
+
+#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) { \
+ if (((elm)->field.stqe_next = (tqelm)->field.stqe_next) == NULL)\
+ (head)->stqh_last = &(elm)->field.stqe_next; \
+ (tqelm)->field.stqe_next = (elm); \
+}
+
+#define STAILQ_REMOVE_HEAD(head, field) { \
+ if (((head)->stqh_first = \
+ (head)->stqh_first->field.stqe_next) == NULL) \
+ (head)->stqh_last = &(head)->stqh_first; \
+}
+
+#define STAILQ_REMOVE(head, elm, type, field) { \
+ if ((head)->stqh_first == (elm)) { \
+ STAILQ_REMOVE_HEAD(head, field); \
+ } \
+ else { \
+ struct type *curelm = (head)->stqh_first; \
+ while( curelm->field.stqe_next != (elm) ) \
+ curelm = curelm->field.stqe_next; \
+ if((curelm->field.stqe_next = \
+ curelm->field.stqe_next->field.stqe_next) == NULL) \
+ (head)->stqh_last = &(curelm)->field.stqe_next; \
+ } \
+}
+
+#endif /* STAILQ_ENTRY */
+
+#ifndef NetBSD1_1
+#define NetBSD1_1 0
+#endif
+
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+#define AHC_INB(ahc, port) \
+ inb((ahc)->baseport+(port))
+#define AHC_INSB(ahc, port, valp, size) \
+ insb((ahc)->baseport+(port), valp, size)
+#define AHC_OUTB(ahc, port, val) \
+ outb((ahc)->baseport+(port), val)
+#define AHC_OUTSB(ahc, port, valp, size) \
+ outsb((ahc)->baseport+(port), valp, size)
+#define AHC_OUTSL(ahc, port, valp, size) \
+ outsl((ahc)->baseport+(port), valp, size)
+#elif defined(__NetBSD__)
+#define AHC_INB(ahc, port) \
+ bus_io_read_1((ahc)->sc_bc, ahc->baseport, port)
+#define AHC_INSB(ahc, port, valp, size) \
+ bus_io_read_multi_1((ahc)->sc_bc, ahc->baseport, port, valp, size)
+#define AHC_OUTB(ahc, port, val) \
+ bus_io_write_1((ahc)->sc_bc, ahc->baseport, port, val)
+#define AHC_OUTSB(ahc, port, valp, size) \
+ bus_io_write_multi_1((ahc)->sc_bc, ahc->baseport, port, valp, size)
+#define AHC_OUTSL(ahc, port, valp, size) \
+ bus_io_write_multi_4((ahc)->sc_bc, ahc->baseport, port, valp, size)
+#endif
+
#define AHC_NSEG 256 /* number of dma segments supported */
-#define AHC_SCB_MAX 16 /*
- * Up to 16 SCBs on some types of aic7xxx based
- * boards. The aic7770 family only have 4
+#define AHC_SCB_MAX 255 /*
+ * Up to 255 SCBs on some types of aic7xxx
+ * based boards. The aic7870 have 16 internal
+ * SCBs, but external SRAM bumps this to 255.
+ * The aic7770 family have only 4, and the
+ * aic7850 has only 3.
*/
-/* #define AHCDEBUG */
-typedef u_long physaddr;
-typedef u_long physlen;
+typedef unsigned long int physaddr;
+extern u_long ahc_unit;
struct ahc_dma_seg {
- physaddr seg_addr;
- physlen seg_len;
+ physaddr addr;
+ long len;
};
-
-typedef u_char ahc_type;
-#define AHC_NONE 0x00
-#define AHC_WIDE 0x02 /* Wide Channel */
-#define AHC_TWIN 0x08 /* Twin Channel */
-#define AHC_274 0x10 /* EISA Based Controller */
-#define AHC_284 0x20 /* VL/ISA Based Controller */
-#define AHC_AIC7870 0x40 /* PCI Based Controller */
-#define AHC_294 0xc0 /* PCI Based Controller */
+
+typedef enum {
+ AHC_NONE = 0x000,
+ AHC_ULTRA = 0x001, /* Supports 20MHz Transfers */
+ AHC_WIDE = 0x002, /* Wide Channel */
+ AHC_TWIN = 0x008, /* Twin Channel */
+ AHC_AIC7770 = 0x010,
+ AHC_AIC7850 = 0x020,
+ AHC_AIC7860 = 0x021, /* ULTRA version of the aic7850 */
+ AHC_AIC7870 = 0x040,
+ AHC_AIC7880 = 0x041,
+ AHC_AIC78X0 = 0x060, /* PCI Based Controller */
+ AHC_274 = 0x110, /* EISA Based Controller */
+ AHC_284 = 0x210, /* VL/ISA Based Controller */
+ AHC_294 = 0x440, /* PCI Based Controller */
+ AHC_294U = 0x441, /* ULTRA PCI Based Controller */
+ AHC_394 = 0x840, /* Twin Channel PCI Controller */
+ AHC_394U = 0x841, /* Twin, ULTRA Channel PCI Controller */
+}ahc_type;
+
+typedef enum {
+ AHC_FNONE = 0x00,
+ AHC_INIT = 0x01,
+ AHC_RUNNING = 0x02,
+ AHC_PAGESCBS = 0x04, /* Enable SCB paging */
+ AHC_USEDEFAULTS = 0x10, /*
+ * For cards without an seeprom
+ * or a BIOS to initialize the chip's
+ * SRAM, we use the default chip and
+ * target settings.
+ */
+ AHC_CHNLB = 0x20, /*
+ * Second controller on 3940
+ * Also encodes the offset in the
+ * SEEPROM for CHNLB info (32)
+ */
+}ahc_flag;
/*
* The driver keeps up to MAX_SCB scb structures per card in memory. Only the
- * first 26 bytes of the structure are valid for the hardware, the rest used
- * for driver level bookeeping. The "__attribute ((packed))" tags ensure that
- * gcc does not attempt to pad the long ints in the structure to word
- * boundaries since the first 26 bytes of this structure must have the correct
- * offsets for the hardware to find them. The driver is further optimized
- * so that we only have to download the first 19 bytes since as long
- * as we always use S/G, the last fields should be zero anyway.
+ * first 26 bytes of the structure need to be transfered to the card during
+ * normal operation. The fields starting at byte 32 are used for kernel level
+ * bookkeeping.
*/
-#if __GNUC__ >= 2
-#if __GNUC_MINOR__ <5
-#pragma pack(1)
-#endif
-#endif
-
-struct ahc_scb {
+struct scb {
/* ------------ Begin hardware supported fields ---------------- */
-/*1*/ u_char control;
-#define SCB_NEEDWDTR 0x80 /* Initiate Wide Negotiation */
-#define SCB_NEEDSDTR 0x40 /* Initiate Sync Negotiation */
-#define SCB_TE 0x20 /* Tag enable */
-#define SCB_NEEDDMA 0x08 /* Refresh SCB from host ram */
-#define SCB_DIS 0x04
-#define SCB_TAG_TYPE 0x3
-#define SIMPLE_QUEUE 0x0
-#define HEAD_QUEUE 0x1
-#define OR_QUEUE 0x2
-/*2*/ u_char target_channel_lun; /* 4/1/3 bits */
+/*0*/ u_char control;
+/*1*/ u_char tcl; /* 4/1/3 bits */
+/*2*/ u_char status;
/*3*/ u_char SG_segment_count;
-/*7*/ physaddr SG_list_pointer __attribute__ ((packed));
-/*11*/ physaddr cmdpointer __attribute__ ((packed));
-/*12*/ u_char cmdlen;
-/*14*/ u_char RESERVED[2]; /* must be zero */
-/*15*/ u_char target_status;
-/*18*/ u_char residual_data_count[3];
-/*19*/ u_char residual_SG_segment_count;
-#define SCB_DOWN_SIZE 19 /* amount to actually download */
-#define SCB_BZERO_SIZE 19 /*
- * amount we need to clear between
- * commands
+/*4*/ physaddr SG_list_pointer;
+/*8*/ u_char residual_SG_segment_count;
+/*9*/ u_char residual_data_count[3];
+/*12*/ physaddr data;
+/*16*/ u_long datalen; /* Really only three bits, but its
+ * faster to treat it as a long on
+ * a quad boundary.
*/
-/*23*/ physaddr data __attribute__ ((packed));
-/*26*/ u_char datalen[3];
-#define SCB_UP_SIZE 26 /*
- * amount we need to upload to perform
- * a request sense.
+/*20*/ physaddr cmdpointer;
+/*24*/ u_char cmdlen;
+/*25*/ u_char tag; /* Index into our kernel SCB array.
+ * Also used as the tag for tagged I/O
*/
-/*30*/ physaddr host_scb __attribute__ ((packed));
-/*31*/ u_char next_waiting; /* Used to thread SCBs awaiting
- * selection
+#define SCB_PIO_TRANSFER_SIZE 26 /* amount we need to upload/download
+ * via PIO to initialize a transaction.
*/
-#define SCB_LIST_NULL 0x10 /* SCB list equivelent to NULL */
-#if 0
- /*
- * No real point in transferring this to the
- * SCB registers.
- */
- unsigned char RESERVED[1];
-#endif
- /*-----------------end of hardware supported fields----------------*/
- TAILQ_ENTRY(ahc_scb) chain;
+/*26*/ u_char next; /* Used for threading SCBs in the
+ * "Waiting for Selection" and
+ * "Disconnected SCB" lists down
+ * in the sequencer.
+ */
+/*27*/ u_char prev;
+/*-----------------end of hardware supported fields----------------*/
+ STAILQ_ENTRY(scb) links; /* for chaining */
struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
- int flags;
-#define SCB_FREE 0
-#define SCB_ACTIVE 1
-#define SCB_ABORTED 2
-#define SCB_CHKSENSE 3
-#define SCB_IMMED 4
-#define SCB_IMMED_FAIL 8
- int position; /* Position in scbarray */
+ int flags;
+#define SCB_FREE 0x000
+#define SCB_ACTIVE 0x001
+#define SCB_ABORTED 0x002
+#define SCB_DEVICE_RESET 0x004
+#define SCB_IMMED 0x008
+#define SCB_SENSE 0x010
+#define SCB_TIMEDOUT 0x020
+#define SCB_QUEUED_FOR_DONE 0x040
+#define SCB_PAGED_OUT 0x080
+#define SCB_WAITINGQ 0x100
+#define SCB_ASSIGNEDQ 0x200
+#define SCB_SENTORDEREDTAG 0x400
+ u_char position; /* Position in card's scbarray */
struct ahc_dma_seg ahc_dma[AHC_NSEG] __attribute__ ((packed));
struct scsi_sense sense_cmd; /* SCSI command block */
};
-#if __GNUC__ >= 2
-#if __GNUC_MINOR__ <5
-#pragma pack(4)
+#if defined(__NetBSD__)
+#if NetBSD1_1 < 3 /* NetBSD-1.1 */
+typedef int bus_chipset_tag_t;
+typedef int bus_io_handle_t;
#endif
#endif
-
-struct ahc_softc {
- struct device sc_dev;
- void *sc_ih;
-
- int sc_iobase;
- int sc_irq;
+struct ahc_data {
+#if defined(__NetBSD__)
+ struct device sc_dev;
+ void *sc_ih;
+ bus_chipset_tag_t sc_bc;
+#endif
+ int unit;
ahc_type type;
-
- struct ahc_scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */
- TAILQ_HEAD(, ahc_scb) free_scb;
- int ahc_scsi_dev; /* our scsi id */
- int ahc_scsi_dev_b; /* B channel scsi id */
- struct ahc_scb *immed_ecb; /* an outstanding immediete command */
+ ahc_flag flags;
+ u_long baseport;
+ struct scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */
+ struct scb *pagedout_ntscbs[16];/*
+ * Paged out, non-tagged scbs
+ * indexed by target.
+ */
+ STAILQ_HEAD(, scb) free_scbs; /*
+ * SCBs assigned to free slots
+ * on the card. (no paging required)
+ */
+ STAILQ_HEAD(, scb) page_scbs; /*
+ * SCBs that will require paging
+ * before use (no assigned slot)
+ */
+ STAILQ_HEAD(, scb) waiting_scbs;/*
+ * SCBs waiting to be paged in
+ * and started.
+ */
+ STAILQ_HEAD(, scb)assigned_scbs;/*
+ * SCBs that were waiting but have
+ * now been assigned a slot by
+ * ahc_free_scb.
+ */
struct scsi_link sc_link;
struct scsi_link sc_link_b; /* Second bus for Twin channel cards */
u_short needsdtr_orig; /* Targets we initiate sync neg with */
u_short sdtrpending; /* Pending SDTR to these targets */
u_short wdtrpending; /* Pending WDTR to these targets */
u_short tagenable; /* Targets that can handle tagqueing */
- int numscbs;
- int activescbs;
- u_char maxscbs;
+ u_short orderedtag; /* Targets to use ordered tag on */
+ u_short discenable; /* Targets allowed to disconnect */
+ u_char our_id; /* our scsi id */
+ u_char our_id_b; /* B channel scsi id */
+ u_char numscbs;
+ u_char activescbs;
+ u_char maxhscbs; /* Number of SCBs on the card */
+ u_char maxscbs; /*
+ * Max SCBs we allocate total including
+ * any that will force us to page SCBs
+ */
+ u_char qcntmask;
u_char unpause;
u_char pause;
+ u_char in_timeout;
};
+/* #define AHC_DEBUG */
+#ifdef AHC_DEBUG
+/* Different debugging levels used when AHC_DEBUG is defined */
+#define AHC_SHOWMISC 0x0001
+#define AHC_SHOWCMDS 0x0002
+#define AHC_SHOWSCBS 0x0004
+#define AHC_SHOWABORTS 0x0008
+#define AHC_SHOWSENSE 0x0010
+#define AHC_SHOWSCBCNT 0x0020
+
+extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */
+#endif
+
+#if defined(__FreeBSD__)
+void ahc_reset __P((u_long iobase));
+struct ahc_data *ahc_alloc __P((int unit, u_long io_base, ahc_type type, ahc_flag flags));
+#elif defined(__NetBSD__)
+void ahc_reset __P((char *devname, bus_chipset_tag_t bc, bus_io_handle_t ioh));
+void ahc_construct __P((struct ahc_data *ahc, int unit, bus_chipset_tag_t bc, bus_io_handle_t ioh, ahc_type type, ahc_flag flags));
+#endif
+void ahc_free __P((struct ahc_data *));
+int ahc_init __P((struct ahc_data *));
+int ahc_attach __P((struct ahc_data *));
+#if defined(__FreeBSD__)
+void ahc_intr __P((void *arg));
+#elif defined(__NetBSD__)
+int ahc_intr __P((void *arg));
+#endif
+
#endif /* _AIC7XXX_H_ */
-# $OpenBSD: files.isa,v 1.14 1996/05/04 13:29:31 deraadt Exp $
+# $OpenBSD: files.isa,v 1.15 1996/05/05 12:42:34 deraadt Exp $
# $NetBSD: files.isa,v 1.18 1996/04/25 02:15:42 thorpej Exp $
#
# Config.new file and device description for machine-independent ISA code.
attach aha at isa
file dev/isa/aha.c aha
-# Adapctec AIC-6[32]60 ICs
+# Adaptec AIC-6[32]60 ICs
device aic: scsi, isadma
attach aic at isa
file dev/isa/aic6360.c aic
-# Adaptec 7770-based EISA, VLB, etc. controllers
-device ahe: scsi, aic7xxx
-attach ahe at isa
-file dev/isa/aha284x.c ahe
-
# BusLogic BT-74x EISA family (XXX; should be EISA. it's special)
device bt: scsi, isadma
attach bt at isa
aic7xxx.o: aic7xxx_seq.h
aic7xxx_seq.h: aic7xxx_asm $S/dev/microcode/aic7xxx/aic7xxx.seq
- ./aic7xxx_asm -v -o ${.TARGET} $S/dev/microcode/aic7xxx/aic7xxx.seq
+ ./aic7xxx_asm -o ${.TARGET} $S/dev/microcode/aic7xxx/aic7xxx.seq
aic7xxx_asm: $S/dev/microcode/aic7xxx/aic7xxx_asm.c
+ cc -o ${.TARGET} $<
.endif
-##+M#########################################################################
-# Adaptec 274x/284x/294x device driver for Linux and FreeBSD.
-#
-# Copyright (c) 1994 John Aycock
-# The University of Calgary Department of Computer Science.
-# All rights reserved.
-#
-# Modifications/enhancements:
-# Copyright (c) 1994, 1995 Justin Gibbs. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-# 1. Redistributions of source code must retain the above copyright
-# notice, this list of conditions, and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-# 3. All advertising materials mentioning features or use of this software
-# must display the following acknowledgement:
-# This product includes software developed by the University of Calgary
-# Department of Computer Science and its contributors.
-# 4. Neither the name of the University nor the names of its contributors
-# may be used to endorse or promote products derived from this software
-# without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-# SUCH DAMAGE.
-#
-# FreeBSD, Twin, Wide, 2 command per target support, tagged queuing and other
-# optimizations provided by Justin T. Gibbs (gibbs@FreeBSD.org)
-#
-##-M#########################################################################
-
-VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.1.1.1 1995/10/18 08:52:39 deraadt Exp $"
-
-SCBMASK = 0x1f
-
-SCSISEQ = 0x00
-ENRSELI = 0x10
-SXFRCTL0 = 0x01
-SXFRCTL1 = 0x02
-SCSISIGI = 0x03
-SCSISIGO = 0x03
-SCSIRATE = 0x04
-SCSIID = 0x05
-SCSIDATL = 0x06
-STCNT = 0x08
-STCNT+0 = 0x08
-STCNT+1 = 0x09
-STCNT+2 = 0x0a
-CLRSINT0 = 0x0b
-SSTAT0 = 0x0b
-SELDO = 0x40
-SELDI = 0x20
-CLRSINT1 = 0x0c
-SSTAT1 = 0x0c
-SIMODE1 = 0x11
-SCSIBUSL = 0x12
-SHADDR = 0x14
-SELID = 0x19
-SBLKCTL = 0x1f
-SEQCTL = 0x60
-A = 0x64 # == ACCUM
-SINDEX = 0x65
-DINDEX = 0x66
-ALLZEROS = 0x6a
-NONE = 0x6a
-SINDIR = 0x6c
-DINDIR = 0x6d
-FUNCTION1 = 0x6e
-HADDR = 0x88
-HADDR+1 = 0x89
-HADDR+2 = 0x8a
-HADDR+3 = 0x8b
-HCNT = 0x8c
-HCNT+0 = 0x8c
-HCNT+1 = 0x8d
-HCNT+2 = 0x8e
-SCBPTR = 0x90
-INTSTAT = 0x91
-DFCNTRL = 0x93
-DFSTATUS = 0x94
-DFDAT = 0x99
-QINFIFO = 0x9b
-QINCNT = 0x9c
-QOUTFIFO = 0x9d
-
-SCSICONF_A = 0x5a
-SCSICONF_B = 0x5b
-
-# The two reserved bytes at SCBARRAY+1[23] are expected to be set to
-# zero, and the reserved bit in SCBARRAY+0 is used as an internal flag
-# to indicate whether or not to reload scatter-gather parameters after
-# a disconnect. We also use bits 6 & 7 to indicate whether or not to
-# initiate SDTR or WDTR repectively when starting this command.
-#
-SCBARRAY+0 = 0xa0
-
-DISCONNECTED = 0x04
-NEEDDMA = 0x08
-SG_LOAD = 0x10
-TAG_ENB = 0x20
-NEEDSDTR = 0x40
-NEEDWDTR = 0x80
-
-SCBARRAY+1 = 0xa1
-SCBARRAY+2 = 0xa2
-SCBARRAY+3 = 0xa3
-SCBARRAY+4 = 0xa4
-SCBARRAY+5 = 0xa5
-SCBARRAY+6 = 0xa6
-SCBARRAY+7 = 0xa7
-SCBARRAY+8 = 0xa8
-SCBARRAY+9 = 0xa9
-SCBARRAY+10 = 0xaa
-SCBARRAY+11 = 0xab
-SCBARRAY+12 = 0xac
-SCBARRAY+13 = 0xad
-SCBARRAY+14 = 0xae
-SCBARRAY+15 = 0xaf
-SCBARRAY+16 = 0xb0
-SCBARRAY+17 = 0xb1
-SCBARRAY+18 = 0xb2
-SCBARRAY+19 = 0xb3
-SCBARRAY+20 = 0xb4
-SCBARRAY+21 = 0xb5
-SCBARRAY+22 = 0xb6
-SCBARRAY+23 = 0xb7
-SCBARRAY+24 = 0xb8
-SCBARRAY+25 = 0xb9
-SCBARRAY+26 = 0xba
-SCBARRAY+27 = 0xbb
-SCBARRAY+28 = 0xbc
-SCBARRAY+29 = 0xbd
-SCBARRAY+30 = 0xbe
-
-BAD_PHASE = 0x01 # unknown scsi bus phase
-CMDCMPLT = 0x02 # Command Complete
-SEND_REJECT = 0x11 # sending a message reject
-NO_IDENT = 0x21 # no IDENTIFY after reconnect
-NO_MATCH = 0x31 # no cmd match for reconnect
-MSG_SDTR = 0x41 # SDTR message recieved
-MSG_WDTR = 0x51 # WDTR message recieved
-MSG_REJECT = 0x61 # Reject message recieved
-BAD_STATUS = 0x71 # Bad status from target
-RESIDUAL = 0x81 # Residual byte count != 0
-ABORT_TAG = 0x91 # Sent an ABORT_TAG message
-
-# The host adapter card (at least the BIOS) uses 20-2f for SCSI
-# device information, 32-33 and 5a-5f as well. As it turns out, the
-# BIOS trashes 20-2f, writing the synchronous negotiation results
-# on top of the BIOS values, so we re-use those for our per-target
-# scratchspace (actually a value that can be copied directly into
-# SCSIRATE). The kernel driver will enable synchronous negotiation
-# for all targets that have a value other than 0 in the lower four
-# bits of the target scratch space. This should work irregardless of
-# whether the bios has been installed. NEEDWDTR and NEEDSDTR are the top
-# two bits of the SCB control byte. The kernel driver will set these
-# when a WDTR or SDTR message should be sent to the target the SCB's
-# command references.
-#
-# REJBYTE contains the first byte of a MESSAGE IN message, so the driver
-# can report an intelligible error if a message is rejected.
-#
-# FLAGS's high bit is true if we are currently handling a reselect;
-# its next-highest bit is true ONLY IF we've seen an IDENTIFY message
-# from the reselecting target. If we haven't had IDENTIFY, then we have
-# no idea what the lun is, and we can't select the right SCB register
-# bank, so force a kernel panic if the target attempts a data in/out or
-# command phase instead of corrupting something. FLAGS also contains
-# configuration bits so that we can optimize for TWIN and WIDE controllers
-# as well as the MAX_SYNC bit which we set when we want to negotiate for
-# 10MHz irregardless of what the per target scratch space says.
-#
-# Note that SG_NEXT occupies four bytes.
-#
-SYNCNEG = 0x20
-
-REJBYTE = 0x31
-DISC_DSB_A = 0x32
-DISC_DSB_B = 0x33
-
-MSG_LEN = 0x34
-MSG_START+0 = 0x35
-MSG_START+1 = 0x36
-MSG_START+2 = 0x37
-MSG_START+3 = 0x38
-MSG_START+4 = 0x39
-MSG_START+5 = 0x3a
--MSG_START+0 = 0xcb # 2's complement of MSG_START+0
-
-ARG_1 = 0x4a # sdtr conversion args & return
-BUS_16_BIT = 0x01
-RETURN_1 = 0x4a
-
-SIGSTATE = 0x4b # value written to SCSISIGO
-
-# Linux users should use 0xc (12) for SG_SIZEOF
-SG_SIZEOF = 0x8 # sizeof(struct ahc_dma)
-#SG_SIZEOF = 0xc # sizeof(struct scatterlist)
-SCB_SIZEOF = 0x13 # sizeof SCB to DMA (19 bytes)
-
-SG_NOLOAD = 0x4c # load SG pointer/length?
-SG_COUNT = 0x4d # working value of SG count
-SG_NEXT = 0x4e # working value of SG pointer
-SG_NEXT+0 = 0x4e
-SG_NEXT+1 = 0x4f
-SG_NEXT+2 = 0x50
-SG_NEXT+3 = 0x51
-
-SCBCOUNT = 0x52 # the actual number of SCBs
-FLAGS = 0x53 # Device configuration flags
-TWIN_BUS = 0x01
-WIDE_BUS = 0x02
-MAX_SYNC = 0x08
-ACTIVE_MSG = 0x20
-IDENTIFY_SEEN = 0x40
-RESELECTED = 0x80
-
-ACTIVE_A = 0x54
-ACTIVE_B = 0x55
-SAVED_TCL = 0x56 # Temporary storage for the
- # target/channel/lun of a
- # reconnecting target
-
-# After starting the selection hardware, we return to the "poll_for_work"
-# loop so that we can check for reconnecting targets as well as for our
-# selection to complete just in case the reselection wins bus arbitration.
-# The problem with this is that we must keep track of the SCB that we've
-# already pulled from the QINFIFO and started the selection on just in case
-# the reselection wins so that we can retry the selection at a later time.
-# This problem cannot be resolved by holding a single entry in scratch
-# ram since a reconnecting target can request sense and this will create
-# yet another SCB waiting for selection. The solution used here is to
-# use byte 31 of the SCB as a psuedo-next pointer and to thread a list
-# of SCBs that are awaiting selection. Since 0 is a valid SCB offset,
-# SCB_LIST_NULL is 0x10 which is out of range. The kernel driver must
-# add an entry to this list everytime a request sense occurs. The sequencer
-# will automatically consume the entries.
-
-WAITING_SCBH = 0x57 # head of list of SCBs awaiting
- # selection
-WAITING_SCBT = 0x58 # tail of list of SCBs awaiting
- # selection
-SCB_LIST_NULL = 0x10
-
-
-# Poll QINCNT for work - the lower bits contain
-# the number of entries in the Queue In FIFO.
-#
+/*+M***********************************************************************
+ *Adaptec 274x/284x/294x device driver for Linux and FreeBSD.
+ *
+ *Copyright (c) 1994 John Aycock
+ * The University of Calgary Department of Computer Science.
+ * All rights reserved.
+ *
+ *FreeBSD, Twin, Wide, 2 command per target support, tagged queuing,
+ *SCB paging and other optimizations:
+ *Copyright (c) 1994, 1995, 1996 Justin Gibbs. All rights reserved.
+ *
+ *Redistribution and use in source and binary forms, with or without
+ *modification, are permitted provided that the following conditions
+ *are met:
+ *1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer.
+ *2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of Calgary
+ * Department of Computer Science and its contributors.
+ *4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *SUCH DAMAGE.
+ *
+ *-M************************************************************************/
+
+VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.2 1996/05/05 12:42:37 deraadt Exp $"
+
+#if defined(__NetBSD__)
+#include "../../../../dev/microcode/aic7xxx/aic7xxx_reg.h"
+#elif defined(__FreeBSD__)
+#include "../../dev/aic7xxx/aic7xxx_reg.h"
+#endif
+
+/*
+ * We can't just use ACCUM in the sequencer code because it
+ * must be treated specially by the assembler, and it currently
+ * looks for the symbol 'A'. This is the only register defined in
+ * the assembler's symbol space.
+ */
+A = ACCUM
+
+/* After starting the selection hardware, we check for reconnecting targets
+ * as well as for our selection to complete just in case the reselection wins
+ * bus arbitration. The problem with this is that we must keep track of the
+ * SCB that we've already pulled from the QINFIFO and started the selection
+ * on just in case the reselection wins so that we can retry the selection at
+ * a later time. This problem cannot be resolved by holding a single entry
+ * in scratch ram since a reconnecting target can request sense and this will
+ * create yet another SCB waiting for selection. The solution used here is to
+ * use byte 27 of the SCB as a psuedo-next pointer and to thread a list
+ * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB offsets,
+ * SCB_LIST_NULL is 0xff which is out of range. The kernel driver must
+ * add an entry to this list everytime a request sense occurs. The sequencer
+ * will automatically consume the entries.
+ */
+
+/*
+ * We assume that the kernel driver may reset us at any time, even in the
+ * middle of a DMA, so clear DFCNTRL too.
+ */
+reset:
+ clr DFCNTRL
+ clr SCSISIGO /* De-assert BSY */
+/*
+ * We jump to start after every bus free.
+ */
start:
- test WAITING_SCBH,SCB_LIST_NULL jz start_waiting
+ and FLAGS,0x0f /* clear target specific flags */
+ mvi SCSISEQ,ENRSELI /* Always allow reselection */
poll_for_work:
- test FLAGS,TWIN_BUS jz start2 # Are we a twin channel device?
-# For fairness, we check the other bus first, since we just finished a
-# transaction on the current channel.
- xor SBLKCTL,0x08 # Toggle to the other bus
+ /*
+ * Are we a twin channel device?
+ * For fairness, we check the other bus first,
+ * since we just finished a transaction on the
+ * current channel.
+ */
+ test FLAGS,TWIN_BUS jz start2
+ xor SBLKCTL,SELBUSB /* Toggle to the other bus */
test SSTAT0,SELDI jnz reselect
- test SSTAT0,SELDO jnz select
- xor SBLKCTL,0x08 # Toggle to the original bus
+ xor SBLKCTL,SELBUSB /* Toggle to the original bus */
start2:
test SSTAT0,SELDI jnz reselect
- test SSTAT0,SELDO jnz select
- test WAITING_SCBH,SCB_LIST_NULL jz start_waiting
- test QINCNT,SCBMASK jz poll_for_work
-
-# We have at least one queued SCB now and we don't have any
-# SCBs in the list of SCBs awaiting selection. Set the SCB
-# pointer from the FIFO so we see the right bank of SCB
-# registers, then set SCSI options and set the initiator and
-# target SCSI IDs.
-#
+ cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting
+ mov A, QCNTMASK
+ test QINCNT,A jz poll_for_work
+
+/*
+ * We have at least one queued SCB now and we don't have any
+ * SCBs in the list of SCBs awaiting selection. Set the SCB
+ * pointer from the FIFO so we see the right bank of SCB
+ * registers.
+ */
mov SCBPTR,QINFIFO
-# If the control byte of this SCB has the NEEDDMA flag set, we have
-# yet to DMA it from host memory
-
-test SCBARRAY+0,NEEDDMA jz test_busy
- clr HCNT+2
- clr HCNT+1
- mvi HCNT+0,SCB_SIZEOF
-
- mvi DINDEX,HADDR
- mvi SCBARRAY+26 call bcopy_4
-
- mvi DFCNTRL,0xd # HDMAEN|DIRECTION|FIFORESET
-
-# Wait for DMA from host memory to data FIFO to complete, then disable
-# DMA and wait for it to acknowledge that it's off.
-#
- call dma_finish
-
-# Copy the SCB from the FIFO to the SCBARRAY
-
- mvi DINDEX, SCBARRAY+0
- call bcopy_3_dfdat
- call bcopy_4_dfdat
- call bcopy_4_dfdat
- call bcopy_4_dfdat
- call bcopy_4_dfdat
-
-# See if there is not already an active SCB for this target. This code
-# locks out on a per target basis instead of target/lun. Although this
-# is not ideal for devices that have multiple luns active at the same
-# time, it is faster than looping through all SCB's looking for active
-# commands. It may be benificial to make findscb a more general procedure
-# to see if the added cost of the search is negligible. This code also
-# assumes that the kernel driver will clear the active flags on board
-# initialization, board reset, and a target's SELTO.
+/*
+ * See if there is not already an active SCB for this target. This code
+ * locks out on a per target basis instead of target/lun. Although this
+ * is not ideal for devices that have multiple luns active at the same
+ * time, it is faster than looping through all SCB's looking for active
+ * commands. It may be benificial to make findscb a more general procedure
+ * to see if the added cost of the search is negligible. This code also
+ * assumes that the kernel driver will clear the active flags on board
+ * initialization, board reset, and a target SELTO. Tagged commands
+ * don't set the active bits since you can queue more than one command
+ * at a time. We do, however, look to see if there are any non-tagged
+ * I/Os in progress, and requeue the command if there are. Tagged and
+ * non-tagged commands cannot be mixed to a single target.
+ */
test_busy:
- test SCBARRAY+0,0x20 jnz start_scb
- and FUNCTION1,0x70,SCBARRAY+1
+ mov FUNCTION1,SCB_TCL
mov A,FUNCTION1
- test SCBARRAY+1,0x88 jz test_a # Id < 8 && A channel
+ test SCB_TCL,0x88 jz test_a /* Id < 8 && A channel */
test ACTIVE_B,A jnz requeue
- or ACTIVE_B,A # Mark the current target as busy
+ test SCB_CONTROL,TAG_ENB jnz start_scb
+ /* Mark the current target as busy */
+ or ACTIVE_B,A
jmp start_scb
-# Place the currently active back on the queue for later processing
+/* Place the currently active SCB back on the queue for later processing */
requeue:
mov QINFIFO, SCBPTR
jmp poll_for_work
-# Pull the first entry off of the waiting for selection list
+/*
+ * Pull the first entry off of the waiting for selection list
+ * We don't have to "test_busy" because only transactions that
+ * have passed that test can be in the waiting_scb list.
+ */
start_waiting:
mov SCBPTR,WAITING_SCBH
- jmp start_scb
+ jmp start_scb2
test_a:
- test ACTIVE_A,A jnz requeue
- or ACTIVE_A,A # Mark the current target as busy
+ test ACTIVE_A,A jnz requeue
+ test SCB_CONTROL,TAG_ENB jnz start_scb
+ /* Mark the current target as busy */
+ or ACTIVE_A,A
start_scb:
- and SINDEX,0xf7,SBLKCTL #Clear the channel select bit
- and A,0x08,SCBARRAY+1 #Get new channel bit
- or SINDEX,A
- mov SBLKCTL,SINDEX # select channel
- mov SCBARRAY+1 call initialize_scsiid
-
-# Enable selection phase as an initiator, and do automatic ATN
-# after the selection. We do this now so that we can overlap the
-# rest of our work to set up this target with the arbitration and
-# selection bus phases.
-#
-start_selection:
- or SCSISEQ,0x48 # ENSELO|ENAUTOATNO
+ mov SCB_NEXT,WAITING_SCBH
mov WAITING_SCBH, SCBPTR
- clr SG_NOLOAD
- and FLAGS,0x3f # !RESELECTING
-
-# As soon as we get a successful selection, the target should go
-# into the message out phase since we have ATN asserted. Prepare
-# the message to send, locking out the device driver. If the device
-# driver hasn't beaten us with an ABORT or RESET message, then tack
-# on an SDTR negotiation if required.
-#
-# Messages are stored in scratch RAM starting with a flag byte (high bit
-# set means active message), one length byte, and then the message itself.
-#
- mov SCBARRAY+1 call disconnect # disconnect ok?
-
- and SINDEX,0x7,SCBARRAY+1 # lun
- or SINDEX,A # return value from disconnect
- or SINDEX,0x80 call mk_mesg # IDENTIFY message
-
- mov A,SINDEX
- test SCBARRAY+0,0xe0 jz !message # WDTR, SDTR or TAG??
- cmp MSG_START+0,A jne !message # did driver beat us?
-
-# Tag Message if Tag enabled in SCB control block. Use SCBPTR as the tag
-# value
+start_scb2:
+ and SINDEX,0xf7,SBLKCTL /* Clear the channel select bit */
+ and A,0x08,SCB_TCL /* Get new channel bit */
+ or SINDEX,A
+ mov SBLKCTL,SINDEX /* select channel */
+ mov SCB_TCL call initialize_scsiid
+
+/*
+ * Enable selection phase as an initiator, and do automatic ATN
+ * after the selection. We do this now so that we can overlap the
+ * rest of our work to set up this target with the arbitration and
+ * selection bus phases.
+ */
+start_selection:
+ mvi SCSISEQ,0x58 /* ENSELO|ENAUTOATNO|ENRSELI */
+
+/*
+ * As soon as we get a successful selection, the target should go
+ * into the message out phase since we have ATN asserted. Prepare
+ * the message to send.
+ *
+ * Messages are stored in scratch RAM starting with a length byte
+ * followed by the message itself.
+ */
+ test SCB_CMDLEN,0xff jnz mk_identify /* 0 Length Command? */
+
+/*
+ * The kernel has sent us an SCB with no command attached. This implies
+ * that the kernel wants to send a message of some sort to this target,
+ * so we interrupt the driver, allow it to fill the message buffer, and
+ * then go back into the arbitration loop
+ */
+ mvi INTSTAT,AWAITING_MSG
+ jmp wait_for_selection
+
+mk_identify:
+ and A,DISCENB,SCB_CONTROL /* mask off disconnect privledge */
+
+ and MSG0,0x7,SCB_TCL /* lun */
+ or MSG0,A /* or in disconnect privledge */
+ or MSG0,MSG_IDENTIFY
+ mvi MSG_LEN, 1
+
+ test SCB_CONTROL,0xb0 jz !message /* WDTR, SDTR or TAG?? */
+/*
+ * Send a tag message if TAG_ENB is set in the SCB control block.
+ * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
+ */
mk_tag:
- mvi DINDEX, MSG_START+1
- test SCBARRAY+0,TAG_ENB jz mk_tag_done
- and A,0x23,SCBARRAY+0
- mov DINDIR,A
- mov DINDIR,SCBPTR
+ mvi DINDEX, MSG1
+ test SCB_CONTROL,TAG_ENB jz mk_tag_done
+ and DINDIR,0x23,SCB_CONTROL
+ mov DINDIR,SCB_TAG
- add MSG_LEN,-MSG_START+0,DINDEX # update message length
+ add MSG_LEN,COMP_MSG0,DINDEX /* update message length */
mk_tag_done:
- mov DINDEX call mk_dtr # build DTR message if needed
+ test SCB_CONTROL,0x90 jz !message /* NEEDWDTR|NEEDSDTR */
+ mov DINDEX call mk_dtr /* build DTR message if needed */
!message:
- jmp poll_for_work
-
-# Reselection has been initiated by a target. Make a note that we've been
-# reselected, but haven't seen an IDENTIFY message from the target
-# yet.
-#
+wait_for_selection:
+ test SSTAT0,SELDO jnz select
+ test SSTAT0,SELDI jz wait_for_selection
+
+/*
+ * Reselection has been initiated by a target. Make a note that we've been
+ * reselected, but haven't seen an IDENTIFY message from the target
+ * yet.
+ */
reselect:
+ clr MSG_LEN /* Don't have anything in the mesg buffer */
mov SELID call initialize_scsiid
- and FLAGS,0x3f # reselected, no IDENTIFY
- or FLAGS,RESELECTED jmp select2
-
-# After the selection, remove this SCB from the "waiting for selection"
-# list. This is achieved by simply moving our "next" pointer into
-# WAITING_SCBH and setting our next pointer to null so that the next
-# time this SCB is used, we don't get confused.
-#
+ or FLAGS,RESELECTED
+ jmp select2
+
+/*
+ * After the selection, remove this SCB from the "waiting for selection"
+ * list. This is achieved by simply moving our "next" pointer into
+ * WAITING_SCBH. Our next pointer will be set to null the next time this
+ * SCB is used, so don't bother with it now.
+ */
select:
- or SCBARRAY+0,NEEDDMA
- mov WAITING_SCBH,SCBARRAY+30
- mvi SCBARRAY+30,SCB_LIST_NULL
+ mov WAITING_SCBH,SCB_NEXT
+ or FLAGS,SELECTED
select2:
- call initialize_for_target
- mvi SCSISEQ,ENRSELI
- mvi CLRSINT0,0x60 # CLRSELDI|CLRSELDO
- mvi CLRSINT1,0x8 # CLRBUSFREE
-
-# Main loop for information transfer phases. If BSY is false, then
-# we have a bus free condition, expected or not. Otherwise, wait
-# for the target to assert REQ before checking MSG, C/D and I/O
-# for the bus phase.
-#
-# We can't simply look at the values of SCSISIGI here (if we want
-# to do synchronous data transfer), because the target won't assert
-# REQ if it's already sent us some data that we haven't acknowledged
-# yet.
-#
+/*
+ * Set CLRCHN here before the target has entered a data transfer mode -
+ * with synchronous SCSI, if you do it later, you blow away some
+ * data in the SCSI FIFO that the target has already sent to you.
+ */
+ or SXFRCTL0,CLRCHN
+/*
+ * Initialize SCSIRATE with the appropriate value for this target.
+ */
+ call ndx_dtr
+ mov SCSIRATE,SINDIR
+
+ mvi SCSISEQ,ENAUTOATNP /*
+ * ATN on parity errors
+ * for "in" phases
+ */
+ mvi CLRSINT1,CLRBUSFREE
+ mvi CLRSINT0,0x60 /* CLRSELDI|CLRSELDO */
+
+/*
+ * Main loop for information transfer phases. If BSY is false, then
+ * we have a bus free condition, expected or not. Otherwise, wait
+ * for the target to assert REQ before checking MSG, C/D and I/O
+ * for the bus phase.
+ *
+ */
ITloop:
- test SSTAT1,0x8 jnz p_busfree # BUSFREE
- test SSTAT1,0x1 jz ITloop # REQINIT
+ test SSTAT1,BUSFREE jnz p_busfree
+ test SSTAT1,REQINIT jz ITloop
- and A,0xe0,SCSISIGI # CDI|IOI|MSGI
+ and A,PHASE_MASK,SCSISIGI
+ mov LASTPHASE,A
+ mov SCSISIGO,A
cmp ALLZEROS,A je p_dataout
- cmp A,0x40 je p_datain
- cmp A,0x80 je p_command
- cmp A,0xc0 je p_status
- cmp A,0xa0 je p_mesgout
- cmp A,0xe0 je p_mesgin
+ cmp A,P_DATAIN je p_datain
+ cmp A,P_COMMAND je p_command
+ cmp A,P_MESGOUT je p_mesgout
+ cmp A,P_STATUS je p_status
+ cmp A,P_MESGIN je p_mesgin
- mvi INTSTAT,BAD_PHASE # unknown - signal driver
+ mvi INTSTAT,BAD_PHASE /* unknown phase - signal driver */
p_dataout:
- mvi 0 call scsisig # !CDO|!IOO|!MSGO
- call assert
- call sg_load
-
- mvi DINDEX,HADDR
- mvi SCBARRAY+19 call bcopy_4
-
-# mvi DINDEX,HCNT # implicit since HCNT is next to HADDR
- mvi SCBARRAY+23 call bcopy_3
-
- mvi DINDEX,STCNT
- mvi SCBARRAY+23 call bcopy_3
-
-# If we are the last SG block, don't set wideodd.
- test SCBARRAY+18,0xff jnz p_dataout_wideodd
- mvi 0x3d call dma # SCSIEN|SDMAEN|HDMAEN|
- # DIRECTION|FIFORESET
- jmp p_dataout_rest
-
-p_dataout_wideodd:
- mvi 0xbd call dma # WIDEODD|SCSIEN|SDMAEN|HDMAEN|
- # DIRECTION|FIFORESET
-
-p_dataout_rest:
-# After a DMA finishes, save the final transfer pointer and count
-# back into the SCB, in case a device disconnects in the middle of
-# a transfer. Use SHADDR and STCNT instead of HADDR and HCNT, since
-# it's a reflection of how many bytes were transferred on the SCSI
-# (as opposed to the host) bus.
-#
- mvi DINDEX,SCBARRAY+23
- mvi STCNT call bcopy_3
+ mvi DMAPARAMS,0x7d /*
+ * WIDEODD|SCSIEN|SDMAEN|HDMAEN|
+ * DIRECTION|FIFORESET
+ */
+ jmp data_phase_init
+
+/*
+ * If we re-enter the data phase after going through another phase, the
+ * STCNT may have been cleared, so restore it from the residual field.
+ */
+data_phase_reinit:
+ mov STCNT0,SCB_RESID_DCNT0
+ mov STCNT1,SCB_RESID_DCNT1
+ mov STCNT2,SCB_RESID_DCNT2
+ jmp data_phase_loop
- mvi DINDEX,SCBARRAY+19
- mvi SHADDR call bcopy_4
+p_datain:
+ mvi DMAPARAMS,0x79 /*
+ * WIDEODD|SCSIEN|SDMAEN|HDMAEN|
+ * !DIRECTION|FIFORESET
+ */
+data_phase_init:
+ call assert
- call sg_advance
- mov SCBARRAY+18,SG_COUNT # residual S/G count
+ test FLAGS, DPHASE jnz data_phase_reinit
+ call sg_scb2ram
+ or FLAGS, DPHASE /* We have seen a data phase */
- jmp ITloop
+data_phase_loop:
+/* If we are the last SG block, don't set wideodd. */
+ cmp SG_COUNT,0x01 jne data_phase_wideodd
+ and DMAPARAMS, 0xbf /* Turn off WIDEODD */
+data_phase_wideodd:
+ mov DMAPARAMS call dma
-p_datain:
- mvi 0x40 call scsisig # !CDO|IOO|!MSGO
- call assert
- call sg_load
+/* Exit if we had an underrun */
+ test SSTAT0,SDONE jz data_phase_finish /* underrun STCNT != 0 */
- mvi DINDEX,HADDR
- mvi SCBARRAY+19 call bcopy_4
+/*
+ * Advance the scatter-gather pointers if needed
+ */
+sg_advance:
+ dec SG_COUNT /* one less segment to go */
-# mvi DINDEX,HCNT # implicit since HCNT is next to HADDR
- mvi SCBARRAY+23 call bcopy_3
+ test SG_COUNT, 0xff jz data_phase_finish /* Are we done? */
- mvi DINDEX,STCNT
- mvi SCBARRAY+23 call bcopy_3
+ clr A /* add sizeof(struct scatter) */
+ add SG_NEXT0,SG_SIZEOF,SG_NEXT0
+ adc SG_NEXT1,A,SG_NEXT1
-# If we are the last SG block, don't set wideodd.
- test SCBARRAY+18,0xff jnz p_datain_wideodd
- mvi 0x39 call dma # SCSIEN|SDMAEN|HDMAEN|
- # !DIRECTION|FIFORESET
- jmp p_datain_rest
-p_datain_wideodd:
- mvi 0xb9 call dma # WIDEODD|SCSIEN|SDMAEN|HDMAEN|
- # !DIRECTION|FIFORESET
-p_datain_rest:
- mvi DINDEX,SCBARRAY+23
- mvi STCNT call bcopy_3
+/*
+ * Load a struct scatter and set up the data address and length.
+ * If the working value of the SG count is nonzero, then
+ * we need to load a new set of values.
+ *
+ * This, like all DMA's, assumes little-endian host data storage.
+ */
+sg_load:
+ clr HCNT2
+ clr HCNT1
+ mvi HCNT0,SG_SIZEOF
- mvi DINDEX,SCBARRAY+19
- mvi SHADDR call bcopy_4
+ mov HADDR0,SG_NEXT0
+ mov HADDR1,SG_NEXT1
+ mov HADDR2,SG_NEXT2
+ mov HADDR3,SG_NEXT3
- call sg_advance
- mov SCBARRAY+18,SG_COUNT # residual S/G count
+ or DFCNTRL,0xd /* HDMAEN|DIRECTION|FIFORESET */
+/*
+ * Wait for DMA from host memory to data FIFO to complete, then disable
+ * DMA and wait for it to acknowledge that it's off.
+ */
+dma_finish:
+ test DFSTATUS,HDONE jz dma_finish
+ /* Turn off DMA preserving WIDEODD */
+ and DFCNTRL,WIDEODD
+dma_finish2:
+ test DFCNTRL,HDMAENACK jnz dma_finish2
+
+/*
+ * Copy data from FIFO into SCB data pointer and data count. This assumes
+ * that the struct scatterlist has this structure (this and sizeof(struct
+ * scatterlist) == 12 are asserted in aic7xxx.c for the Linux driver):
+ *
+ * struct scatterlist {
+ * char *address; four bytes, little-endian order
+ * ... four bytes, ignored
+ * unsigned short length; two bytes, little-endian order
+ * }
+ *
+ *
+ * In FreeBSD, the scatter list entry is only 8 bytes.
+ *
+ * struct ahc_dma_seg {
+ * physaddr addr; four bytes, little-endian order
+ * long len; four bytes, little endian order
+ * };
+ */
+
+ mov HADDR0,DFDAT
+ mov HADDR1,DFDAT
+ mov HADDR2,DFDAT
+ mov HADDR3,DFDAT
+/*
+ * For Linux, we must throw away four bytes since there is a 32bit gap
+ * in the middle of a struct scatterlist.
+ */
+#ifdef linux
+ mov NONE,DFDAT
+ mov NONE,DFDAT
+ mov NONE,DFDAT
+ mov NONE,DFDAT
+#endif
+ mov HCNT0,DFDAT
+ mov HCNT1,DFDAT
+ mov HCNT2,DFDAT
+
+/* Load STCNT as well. It is a mirror of HCNT */
+ mov STCNT0,HCNT0
+ mov STCNT1,HCNT1
+ mov STCNT2,HCNT2
+ test SSTAT1,PHASEMIS jz data_phase_loop
+
+data_phase_finish:
+/*
+ * After a DMA finishes, save the SG and STCNT residuals back into the SCB
+ * We use STCNT instead of HCNT, since it's a reflection of how many bytes
+ * were transferred on the SCSI (as opposed to the host) bus.
+ */
+ mov SCB_RESID_DCNT0,STCNT0
+ mov SCB_RESID_DCNT1,STCNT1
+ mov SCB_RESID_DCNT2,STCNT2
+ mov SCB_RESID_SGCNT, SG_COUNT
jmp ITloop
-# Command phase. Set up the DMA registers and let 'er rip - the
-# two bytes after the SCB SCSI_cmd_length are zeroed by the driver,
-# so we can copy those three bytes directly into HCNT.
-#
+/*
+ * Command phase. Set up the DMA registers and let 'er rip.
+ */
p_command:
- mvi 0x80 call scsisig # CDO|!IOO|!MSGO
call assert
- mvi DINDEX,HADDR
- mvi SCBARRAY+7 call bcopy_4
-
-# mvi DINDEX,HCNT # implicit since HCNT is next to HADDR
- mvi SCBARRAY+11 call bcopy_3
-
- mvi DINDEX,STCNT
- mvi SCBARRAY+11 call bcopy_3
+/*
+ * Load HADDR and HCNT.
+ */
+ mov HADDR0, SCB_CMDPTR0
+ mov HADDR1, SCB_CMDPTR1
+ mov HADDR2, SCB_CMDPTR2
+ mov HADDR3, SCB_CMDPTR3
+ mov HCNT0, SCB_CMDLEN
+ clr HCNT1
+ clr HCNT2
+
+ mov STCNT0, HCNT0
+ mov STCNT1, HCNT1
+ mov STCNT2, HCNT2
mvi 0x3d call dma # SCSIEN|SDMAEN|HDMAEN|
# DIRECTION|FIFORESET
jmp ITloop
-# Status phase. Wait for the data byte to appear, then read it
-# and store it into the SCB.
-#
+/*
+ * Status phase. Wait for the data byte to appear, then read it
+ * and store it into the SCB.
+ */
p_status:
- mvi 0xc0 call scsisig # CDO|IOO|!MSGO
-
- mvi SCBARRAY+14 call inb_first
- jmp p_mesgin_done
+ mvi SCB_TARGET_STATUS call inb_first
+ jmp mesgin_done
-# Message out phase. If there is no active message, but the target
-# took us into this phase anyway, build a no-op message and send it.
-#
+/*
+ * Message out phase. If there is not an active message, but the target
+ * took us into this phase anyway, build a no-op message and send it.
+ */
p_mesgout:
- mvi 0xa0 call scsisig # CDO|!IOO|MSGO
- mvi 0x8 call mk_mesg # build NOP message
-
- clr STCNT+2
- clr STCNT+1
-
-# Set up automatic PIO transfer from MSG_START. Bit 3 in
-# SXFRCTL0 (SPIOEN) is already on.
-#
- mvi SINDEX,MSG_START+0
+ test MSG_LEN, 0xff jnz p_mesgout_start
+ mvi MSG_NOP call mk_mesg /* build NOP message */
+
+p_mesgout_start:
+/*
+ * Set up automatic PIO transfer from MSG0. Bit 3 in
+ * SXFRCTL0 (SPIOEN) is already on.
+ */
+ mvi SINDEX,MSG0
mov DINDEX,MSG_LEN
-# When target asks for a byte, drop ATN if it's the last one in
-# the message. Otherwise, keep going until the message is exhausted.
-# (We can't use outb for this since it wants the input in SINDEX.)
-#
-# Keep an eye out for a phase change, in case the target issues
-# a MESSAGE REJECT.
-#
-p_mesgout2:
- test SSTAT0,0x2 jz p_mesgout2 # SPIORDY
- test SSTAT1,0x10 jnz p_mesgout6 # PHASEMIS
-
- cmp DINDEX,1 jne p_mesgout3 # last byte?
- mvi CLRSINT1,0x40 # CLRATNO - drop ATN
-
-# Write a byte to the SCSI bus. The AIC-7770 refuses to automatically
-# send ACKs in automatic PIO or DMA mode unless you make sure that the
-# "expected" bus phase in SCSISIGO matches the actual bus phase. This
-# behaviour is completely undocumented and caused me several days of
-# grief.
-#
-# After plugging in different drives to test with and using a longer
-# SCSI cable, I found that I/O in Automatic PIO mode ceased to function,
-# especially when transferring >1 byte. It seems to be much more stable
-# if STCNT is set to one before the transfer, and SDONE (in SSTAT0) is
-# polled for transfer completion - for both output _and_ input. The
-# only theory I have is that SPIORDY doesn't drop right away when SCSIDATL
-# is accessed (like the documentation says it does), and that on a longer
-# cable run, the sequencer code was fast enough to loop back and see
-# an SPIORDY that hadn't dropped yet.
-#
-p_mesgout3:
- mvi STCNT+0, 0x01
+/*
+ * When target asks for a byte, drop ATN if it's the last one in
+ * the message. Otherwise, keep going until the message is exhausted.
+ *
+ * Keep an eye out for a phase change, in case the target issues
+ * a MESSAGE REJECT.
+ */
+p_mesgout_loop:
+ test SSTAT1,PHASEMIS jnz p_mesgout_phasemis
+ test SSTAT0,SPIORDY jz p_mesgout_loop
+ cmp DINDEX,1 jne p_mesgout_outb /* last byte? */
+ mvi CLRSINT1,CLRATNO /* drop ATN */
+p_mesgout_outb:
+ dec DINDEX
+ or CLRSINT0, CLRSPIORDY
mov SCSIDATL,SINDIR
-
+
p_mesgout4:
- test SSTAT0,0x4 jz p_mesgout4 # SDONE
- dec DINDEX
- test DINDEX,0xff jnz p_mesgout2
+ test DINDEX,0xff jnz p_mesgout_loop
-# If the next bus phase after ATN drops is a message out, it means
-# that the target is requesting that the last message(s) be resent.
-#
-p_mesgout5:
- test SSTAT1,0x8 jnz p_mesgout6 # BUSFREE
- test SSTAT1,0x1 jz p_mesgout5 # REQINIT
+/*
+ * If the next bus phase after ATN drops is a message out, it means
+ * that the target is requesting that the last message(s) be resent.
+ */
+p_mesgout_snoop:
+ test SSTAT1,BUSFREE jnz p_mesgout_done
+ test SSTAT1,REQINIT jz p_mesgout_snoop
- and A,0xe0,SCSISIGI # CDI|IOI|MSGI
- cmp A,0xa0 jne p_mesgout6
- mvi 0x10 call scsisig # ATNO - re-assert ATN
+ test SSTAT1,PHASEMIS jnz p_mesgout_done
+
+ or SCSISIGO,ATNO /* turn on ATNO */
jmp ITloop
-p_mesgout6:
- mvi CLRSINT1,0x40 # CLRATNO - in case of PHASEMIS
- and FLAGS,0xdf # no active msg
+p_mesgout_phasemis:
+ mvi CLRSINT1,CLRATNO /* Be sure to turn ATNO off */
+p_mesgout_done:
+ clr MSG_LEN /* no active msg */
jmp ITloop
-# Message in phase. Bytes are read using Automatic PIO mode, but not
-# using inb. This alleviates a race condition, namely that if ATN had
-# to be asserted under Automatic PIO mode, it had to beat the SCSI
-# circuitry sending an ACK to the target. This showed up under heavy
-# loads and really confused things, since ABORT commands wouldn't be
-# seen by the drive after an IDENTIFY message in until it had changed
-# to a data I/O phase.
-#
+/*
+ * Message in phase. Bytes are read using Automatic PIO mode.
+ */
p_mesgin:
- mvi 0xe0 call scsisig # CDO|IOO|MSGO
- mvi A call inb_first # read the 1st message byte
- mvi REJBYTE,A # save it for the driver
-
- cmp ALLZEROS,A jne p_mesgin1
-
-# We got a "command complete" message, so put the SCB pointer
-# into the Queue Out, and trigger a completion interrupt.
-# Check status for non zero return and interrupt driver if needed
-# This allows the driver to interpret errors only when they occur
-# instead of always uploading the scb. If the status is SCSI_CHECK,
-# the driver will download a new scb requesting sense to replace
-# the old one, modify the "waiting for selection" SCB list and set
-# RETURN_1 to 0x80. If RETURN_1 is set to 0x80 the sequencer imediately
-# jumps to main loop where it will run down the waiting SCB list.
-# If the kernel driver does not wish to request sense, it need
-# only clear RETURN_1, and the command is allowed to complete. We don't
-# bother to post to the QOUTFIFO in the error case since it would require
-# extra work in the kernel driver to ensure that the entry was removed
-# before the command complete code tried processing it.
-
-# First check for residuals
- test SCBARRAY+15,0xff jnz resid
- test SCBARRAY+16,0xff jnz resid
- test SCBARRAY+17,0xff jnz resid
+ mvi A call inb_first /* read the 1st message byte */
+ mov REJBYTE,A /* save it for the driver */
+
+ test A,MSG_IDENTIFY jnz mesgin_identify
+ cmp A,MSG_DISCONNECT je mesgin_disconnect
+ cmp A,MSG_SDPTRS je mesgin_sdptrs
+ cmp ALLZEROS,A je mesgin_complete
+ cmp A,MSG_RDPTRS je mesgin_rdptrs
+ cmp A,MSG_EXTENDED je mesgin_extended
+ cmp A,MSG_REJECT je mesgin_reject
+
+rej_mesgin:
+/*
+ * We have no idea what this message in is, and there's no way
+ * to pass it up to the kernel, so we issue a message reject and
+ * hope for the best. Since we're now using manual PIO mode to
+ * read in the message, there should no longer be a race condition
+ * present when we assert ATN. In any case, rejection should be a
+ * rare occurrence - signal the driver when it happens.
+ */
+ or SCSISIGO,ATNO /* turn on ATNO */
+ mvi INTSTAT,SEND_REJECT /* let driver know */
+
+ mvi MSG_REJECT call mk_mesg
+
+mesgin_done:
+ call inb_last /*ack & turn auto PIO back on*/
+ jmp ITloop
+
+
+mesgin_complete:
+/*
+ * We got a "command complete" message, so put the SCB_TAG into QUEUEOUT,
+ * and trigger a completion interrupt. Check status for non zero return
+ * and interrupt driver if needed. This allows the driver to interpret
+ * errors only when they occur instead of always uploading the scb. If
+ * the status is SCSI_CHECK, the driver will download a new scb requesting
+ * sense to replace the old one, modify the "waiting for selection" SCB list
+ * and set RETURN_1 to SEND_SENSE. If RETURN_1 is set to SEND_SENSE the
+ * sequencer imediately jumps to main loop where it will run down the waiting
+ * SCB list and process the sense request. If the kernel driver does not
+ * wish to request sense, it need only clear RETURN_1, and the command is
+ * allowed to complete. We don't bother to post to the QOUTFIFO in the
+ * error case since it would require extra work in the kernel driver to
+ * ensure that the entry was removed before the command complete code tried
+ * processing it.
+ *
+ * First check for residuals
+ */
+ test SCB_RESID_SGCNT,0xff jz check_status
+/*
+ * If we have a residual count, interrupt and tell the host. Other
+ * alternatives are to pause the sequencer on all command completes (yuck),
+ * dma the resid directly to the host (slick, we may have space to do it now)
+ * or have the sequencer pause itself when it encounters a non-zero resid
+ * (unecessary pause just to flag the command -yuck-, but takes one instruction
+ * and since it shouldn't happen that often is good enough for our purposes).
+ */
+resid:
+ mvi INTSTAT,RESIDUAL
check_status:
- test SCBARRAY+14,0xff jz status_ok # 0 Status?
- mvi INTSTAT,BAD_STATUS # let driver know
- test RETURN_1, 0x80 jz status_ok
- jmp p_mesgin_done
+ test SCB_TARGET_STATUS,0xff jz status_ok /* Good Status? */
+ mvi INTSTAT,BAD_STATUS /* let driver know */
+ cmp RETURN_1, SEND_SENSE jne status_ok
+ jmp mesgin_done
status_ok:
-# First, mark this target as free.
- test SCBARRAY+0,0x20 jnz complete # Tagged command
- and FUNCTION1,0x70,SCBARRAY+1
+/* First, mark this target as free. */
+ test SCB_CONTROL,TAG_ENB jnz test_immediate /*
+ * Tagged commands
+ * don't busy the
+ * target.
+ */
+ mov FUNCTION1,SCB_TCL
mov A,FUNCTION1
- test SCBARRAY+1,0x88 jz clear_a
+ test SCB_TCL,0x88 jz clear_a
xor ACTIVE_B,A
- jmp complete
+ jmp test_immediate
clear_a:
xor ACTIVE_A,A
+test_immediate:
+ test SCB_CMDLEN,0xff jnz complete /* Immediate message complete */
+/*
+ * Pause the sequencer until the driver gets around to handling the command
+ * complete. This is so that any action that might require carefull timing
+ * with the completion of this command can occur.
+ */
+ mvi INTSTAT,IMMEDDONE
+ jmp start
complete:
- mov QOUTFIFO,SCBPTR
+ mov QOUTFIFO,SCB_TAG
mvi INTSTAT,CMDCMPLT
- jmp p_mesgin_done
+ jmp mesgin_done
-# If we have a residual count, interrupt and tell the host. Other
-# alternatives are to pause the sequencer on all command completes (yuck),
-# dma the resid directly to the host (slick, but a ton of instructions), or
-# have the sequencer pause itself when it encounters a non-zero resid
-# (unecessary pause just to flag the command -- yuck, but takes few instructions
-# and since it shouldn't happen that often is good enough for our purposes).
-resid:
- mvi INTSTAT,RESIDUAL
- jmp check_status
-
-# Is it an extended message? We only support the synchronous and wide data
-# transfer request messages, which will probably be in response to
-# WDTR or SDTR message outs from us. If it's not SDTR or WDTR, reject it -
-# apparently this can be done after any message in byte, according
-# to the SCSI-2 spec.
-#
-p_mesgin1:
- cmp A,1 jne p_mesgin2 # extended message code?
-
- mvi ARG_1 call inb_next # extended message length
- mvi A call inb_next # extended message code
+/*
+ * Is it an extended message? We only support the synchronous and wide data
+ * transfer request messages, which will probably be in response to
+ * WDTR or SDTR message outs from us. If it's not SDTR or WDTR, reject it -
+ * apparently this can be done after any message in byte, according
+ * to the SCSI-2 spec.
+ */
+mesgin_extended:
+ mvi ARG_1 call inb_next /* extended message length */
+ mvi REJBYTE_EXT call inb_next /* extended message code */
- cmp A,1 je p_mesginSDTR # Syncronous negotiation message
- cmp A,3 je p_mesginWDTR # Wide negotiation message
- jmp p_mesginN
+ cmp REJBYTE_EXT,MSG_SDTR je p_mesginSDTR
+ cmp REJBYTE_EXT,MSG_WDTR je p_mesginWDTR
+ jmp rej_mesgin
p_mesginWDTR:
- cmp ARG_1,2 jne p_mesginN # extended mesg length = 2
- mvi A call inb_next # Width of bus
- mvi INTSTAT,MSG_WDTR # let driver know
- test RETURN_1,0x80 jz p_mesgin_done# Do we need to send WDTR?
-
-# We didn't initiate the wide negotiation, so we must respond to the request
- and RETURN_1,0x7f # Clear the SEND_WDTR Flag
- or FLAGS,ACTIVE_MSG
- mvi DINDEX,MSG_START+0
- mvi MSG_START+0 call mk_wdtr # build WDTR message
- or SINDEX,0x10,SIGSTATE # turn on ATNO
- call scsisig
- jmp p_mesgin_done
+ cmp ARG_1,2 jne rej_mesgin /* extended mesg length=2 */
+ mvi ARG_1 call inb_next /* Width of bus */
+ mvi INTSTAT,WDTR_MSG /* let driver know */
+ test RETURN_1,0xff jz mesgin_done /* Do we need to send WDTR? */
+ cmp RETURN_1,SEND_REJ je rej_mesgin /*
+ * Bus width was too large
+ * Reject it.
+ */
+
+/* We didn't initiate the wide negotiation, so we must respond to the request */
+ and RETURN_1,0x7f /* Clear the SEND_WDTR Flag */
+ mvi DINDEX,MSG0
+ mvi MSG0 call mk_wdtr /* build WDTR message */
+ or SCSISIGO,ATNO /* turn on ATNO */
+ jmp mesgin_done
p_mesginSDTR:
- cmp ARG_1,3 jne p_mesginN # extended mesg length = 3
- mvi ARG_1 call inb_next # xfer period
- mvi A call inb_next # REQ/ACK offset
- mvi INTSTAT,MSG_SDTR # call driver to convert
-
- test RETURN_1,0xc0 jz p_mesgin_done# Do we need to mk_sdtr or rej?
- test RETURN_1,0x40 jnz p_mesginN # Requested SDTR too small - rej
- or FLAGS,ACTIVE_MSG
- mvi DINDEX, MSG_START+0
- mvi MSG_START+0 call mk_sdtr
- or SINDEX,0x10,SIGSTATE # turn on ATNO
- call scsisig
- jmp p_mesgin_done
-
-# Is it a disconnect message? Set a flag in the SCB to remind us
-# and await the bus going free.
-#
-p_mesgin2:
- cmp A,4 jne p_mesgin3 # disconnect code?
-
- or SCBARRAY+0,0x4 # set "disconnected" bit
- jmp p_mesgin_done
-
-# Save data pointers message? Copy working values into the SCB,
-# usually in preparation for a disconnect.
-#
-p_mesgin3:
- cmp A,2 jne p_mesgin4 # save data pointers code?
-
+ cmp ARG_1,3 jne rej_mesgin /* extended mesg length=3 */
+ mvi ARG_1 call inb_next /* xfer period */
+ mvi A call inb_next /* REQ/ACK offset */
+ mvi INTSTAT,SDTR_MSG /* call driver to convert */
+
+ test RETURN_1,0xff jz mesgin_done /* Do we need to mk_sdtr/rej */
+ cmp RETURN_1,SEND_REJ je rej_mesgin /*
+ * Requested SDTR too small
+ * Reject it.
+ */
+ clr ARG_1 /* Use the scratch ram rate */
+ mvi DINDEX, MSG0
+ mvi MSG0 call mk_sdtr
+ or SCSISIGO,ATNO /* turn on ATNO */
+ jmp mesgin_done
+
+/*
+ * Is it a disconnect message? Set a flag in the SCB to remind us
+ * and await the bus going free.
+ */
+mesgin_disconnect:
+ or SCB_CONTROL,DISCONNECTED
+ test FLAGS, PAGESCBS jz mesgin_done
+/*
+ * Link this SCB into the DISCONNECTED list. This list holds the
+ * candidates for paging out an SCB if one is needed for a new command.
+ * Modifying the disconnected list is a critical(pause dissabled) section.
+ */
+ mvi SCB_PREV, SCB_LIST_NULL
+ mvi SEQCTL,0x50 /* PAUSEDIS|FASTMODE */
+ mov SCB_NEXT, DISCONNECTED_SCBH
+ mov DISCONNECTED_SCBH, SCBPTR
+ cmp SCB_NEXT,SCB_LIST_NULL je linkdone
+ mov SCBPTR,SCB_NEXT
+ mov SCB_PREV,DISCONNECTED_SCBH
+ mov SCBPTR,DISCONNECTED_SCBH
+linkdone:
+ mvi SEQCTL,0x10 /* !PAUSEDIS|FASTMODE */
+ jmp mesgin_done
+
+/*
+ * Save data pointers message? Copy working values into the SCB,
+ * usually in preparation for a disconnect.
+ */
+mesgin_sdptrs:
call sg_ram2scb
- jmp p_mesgin_done
-
-# Restore pointers message? Data pointers are recopied from the
-# SCB anyway at the start of any DMA operation, so the only thing
-# to copy is the scatter-gather values.
-#
-p_mesgin4:
- cmp A,3 jne p_mesgin5 # restore pointers code?
-
- call sg_scb2ram
- jmp p_mesgin_done
-
-# Identify message? For a reconnecting target, this tells us the lun
-# that the reconnection is for - find the correct SCB and switch to it,
-# clearing the "disconnected" bit so we don't "find" it by accident later.
-#
-p_mesgin5:
- test A,0x80 jz p_mesgin6 # identify message?
-
- test A,0x78 jnz p_mesginN # !DiscPriv|!LUNTAR|!Reserved
-
- and A,0x07 # lun in lower three bits
+ jmp mesgin_done
+
+/*
+ * Restore pointers message? Data pointers are recopied from the
+ * SCB anytime we enter a data phase for the first time, so all
+ * we need to do is clear the DPHASE flag and let the data phase
+ * code do the rest.
+ */
+mesgin_rdptrs:
+ and FLAGS,0xef /*
+ * !DPHASE we'll reload them
+ * the next time through
+ */
+ jmp mesgin_done
+
+/*
+ * Identify message? For a reconnecting target, this tells us the lun
+ * that the reconnection is for - find the correct SCB and switch to it,
+ * clearing the "disconnected" bit so we don't "find" it by accident later.
+ */
+mesgin_identify:
+ test A,0x78 jnz rej_mesgin /*!DiscPriv|!LUNTAR|!Reserved*/
+
+ and A,0x07 /* lun in lower three bits */
or SAVED_TCL,A,SELID
and SAVED_TCL,0xf7
- and A,0x08,SBLKCTL # B Channel??
+ and A,SELBUSB,SBLKCTL /* B Channel?? */
or SAVED_TCL,A
- call inb_last # ACK
- mov ALLZEROS call findSCB
+ call inb_last /* ACK */
+
+/*
+ * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
+ * If we get one, we use the tag returned to switch to find the proper
+ * SCB. With SCB paging, this requires using findSCB for both tagged
+ * and non-tagged transactions since the SCB may exist in any slot.
+ * If we're not using SCB paging, we can use the tag as the direct
+ * index to the SCB.
+ */
+ mvi ARG_1,SCB_LIST_NULL /* Default to no-tag */
+snoop_tag_loop:
+ test SSTAT1,BUSFREE jnz use_findSCB
+ test SSTAT1,REQINIT jz snoop_tag_loop
+ test SSTAT1,PHASEMIS jnz use_findSCB
+ mvi A call inb_first
+ cmp A,MSG_SIMPLE_TAG jne use_findSCB
+get_tag:
+ mvi ARG_1 call inb_next /* tag value */
+/*
+ * See if the tag is in range. The tag is < SCBCOUNT if we add
+ * the complement of SCBCOUNT to the incomming tag and there is
+ * no carry.
+ */
+ mov A,COMP_SCBCOUNT
+ add SINDEX,A,ARG_1
+ jc abort_tag
+
+/*
+ * Ensure that the SCB the tag points to is for an SCB transaction
+ * to the reconnecting target.
+ */
+ test FLAGS, PAGESCBS jz index_by_tag
+ call inb_last /* Ack Tag */
+use_findSCB:
+ mov ALLZEROS call findSCB /* Have to search */
setup_SCB:
- and SCBARRAY+0,0xfb # clear disconnect bit in SCB
- or FLAGS,IDENTIFY_SEEN # make note of IDENTIFY
-
- call sg_scb2ram # implied restore pointers
- # required on reselect
+ and SCB_CONTROL,0xfb /* clear disconnect bit in SCB */
+ or FLAGS,IDENTIFY_SEEN /* make note of IDENTIFY */
jmp ITloop
-get_tag:
- mvi A call inb_first
- cmp A,0x20 jne return # Simple Tag message?
- mvi A call inb_next
- call inb_last
- test A,0xf0 jnz abort_tag # Tag in range?
- mov SCBPTR,A
+index_by_tag:
+ mov SCBPTR,ARG_1
mov A,SAVED_TCL
- cmp SCBARRAY+1,A jne abort_tag
- test SCBARRAY+0,TAG_ENB jz abort_tag
- ret
-abort_tag:
- or SINDEX,0x10,SIGSTATE # turn on ATNO
- call scsisig
- mvi INTSTAT,ABORT_TAG # let driver know
- mvi 0xd call mk_mesg # ABORT TAG message
- ret
-
-# Message reject? Let the kernel driver handle this. If we have an
-# outstanding WDTR or SDTR negotiation, assume that it's a response from
-# the target selecting 8bit or asynchronous transfer, otherwise just ignore
-# it since we have no clue what it pertains to.
-#
-p_mesgin6:
- cmp A,7 jne p_mesgin7 # message reject code?
-
- mvi INTSTAT, MSG_REJECT
- jmp p_mesgin_done
-
-# [ ADD MORE MESSAGE HANDLING HERE ]
-#
-p_mesgin7:
-
-# We have no idea what this message in is, and there's no way
-# to pass it up to the kernel, so we issue a message reject and
-# hope for the best. Since we're now using manual PIO mode to
-# read in the message, there should no longer be a race condition
-# present when we assert ATN. In any case, rejection should be a
-# rare occurrence - signal the driver when it happens.
-#
-p_mesginN:
- or SINDEX,0x10,SIGSTATE # turn on ATNO
- call scsisig
- mvi INTSTAT,SEND_REJECT # let driver know
-
- mvi 0x7 call mk_mesg # MESSAGE REJECT message
-
-p_mesgin_done:
- call inb_last # ack & turn auto PIO back on
- jmp ITloop
-
+ cmp SCB_TCL,A jne abort_tag
+ test SCB_CONTROL,TAG_ENB jz abort_tag
+ call inb_last /* Ack Successful tag */
+ jmp setup_SCB
-# Bus free phase. It might be useful to interrupt the device
-# driver if we aren't expecting this. For now, make sure that
-# ATN isn't being asserted and look for a new command.
-#
+abort_tag:
+ or SCSISIGO,ATNO /* turn on ATNO */
+ mvi INTSTAT,ABORT_TAG /* let driver know */
+ mvi MSG_ABORT_TAG call mk_mesg /* ABORT TAG message */
+ jmp mesgin_done
+
+/*
+ * Message reject? Let the kernel driver handle this. If we have an
+ * outstanding WDTR or SDTR negotiation, assume that it's a response from
+ * the target selecting 8bit or asynchronous transfer, otherwise just ignore
+ * it since we have no clue what it pertains to.
+ */
+mesgin_reject:
+ mvi INTSTAT, REJECT_MSG
+ jmp mesgin_done
+
+/*
+ * [ ADD MORE MESSAGE HANDLING HERE ]
+ */
+
+/*
+ * Bus free phase. It might be useful to interrupt the device
+ * driver if we aren't expecting this. For now, make sure that
+ * ATN isn't being asserted and look for a new command.
+ */
p_busfree:
- mvi CLRSINT1,0x40 # CLRATNO
- clr SIGSTATE
+ mvi CLRSINT1,CLRATNO
+ clr LASTPHASE
+
+/*
+ * if this is an immediate command, perform a psuedo command complete to
+ * notify the driver.
+ */
+ test SCB_CMDLEN,0xff jz status_ok
jmp start
-# Instead of a generic bcopy routine that requires an argument, we unroll
-# the two cases that are actually used, and call them explicitly. This
-# not only reduces the overhead of doing a bcopy by 2/3rds, but ends up
-# saving space in the program since you don't have to put the argument
-# into the accumulator before the call. Both functions expect DINDEX to
-# contain the destination address and SINDEX to contain the source
-# address.
-bcopy_3:
- mov DINDIR,SINDIR
- mov DINDIR,SINDIR
- mov DINDIR,SINDIR ret
-
-bcopy_4:
- mov DINDIR,SINDIR
- mov DINDIR,SINDIR
- mov DINDIR,SINDIR
- mov DINDIR,SINDIR ret
-
-bcopy_3_dfdat:
- mov DINDIR,DFDAT
- mov DINDIR,DFDAT
- mov DINDIR,DFDAT ret
-
-bcopy_4_dfdat:
- mov DINDIR,DFDAT
- mov DINDIR,DFDAT
- mov DINDIR,DFDAT
- mov DINDIR,DFDAT ret
-
-# Locking the driver out, build a one-byte message passed in SINDEX
-# if there is no active message already. SINDEX is returned intact.
-#
+/*
+ * Locking the driver out, build a one-byte message passed in SINDEX
+ * if there is no active message already. SINDEX is returned intact.
+ */
mk_mesg:
- mvi SEQCTL,0x50 # PAUSEDIS|FASTMODE
- test FLAGS,ACTIVE_MSG jnz mk_mesg1 # active message?
-
- or FLAGS,ACTIVE_MSG # if not, there is now
- mvi MSG_LEN,1 # length = 1
- mov MSG_START+0,SINDEX # 1-byte message
+ mvi SEQCTL,0x50 /* PAUSEDIS|FASTMODE */
+ test MSG_LEN,0xff jz mk_mesg1 /* Should always succeed */
+
+ /*
+ * Hmmm. For some reason the mesg buffer is in use.
+ * Tell the driver. It should look at SINDEX to find
+ * out what we wanted to use the buffer for and resolve
+ * the conflict.
+ */
+ mvi SEQCTL,0x10 /* !PAUSEDIS|FASTMODE */
+ mvi INTSTAT,MSG_BUFFER_BUSY
mk_mesg1:
- mvi SEQCTL,0x10 ret # !PAUSEDIS|FASTMODE
-
-# Carefully read data in Automatic PIO mode. I first tried this using
-# Manual PIO mode, but it gave me continual underrun errors, probably
-# indicating that I did something wrong, but I feel more secure leaving
-# Automatic PIO on all the time.
-#
-# According to Adaptec's documentation, an ACK is not sent on input from
-# the target until SCSIDATL is read from. So we wait until SCSIDATL is
-# latched (the usual way), then read the data byte directly off the bus
-# using SCSIBUSL. When we have pulled the ATN line, or we just want to
-# acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
-# spec guarantees that the target will hold the data byte on the bus until
-# we send our ACK.
-#
-# The assumption here is that these are called in a particular sequence,
-# and that REQ is already set when inb_first is called. inb_{first,next}
-# use the same calling convention as inb.
-#
-inb_first:
- clr STCNT+2
- clr STCNT+1
- mov DINDEX,SINDEX
- mov DINDIR,SCSIBUSL ret # read byte directly from bus
+ mvi MSG_LEN,1 /* length = 1 */
+ mov MSG0,SINDEX /* 1-byte message */
+ mvi SEQCTL,0x10 ret /* !PAUSEDIS|FASTMODE */
+
+/*
+ * Functions to read data in Automatic PIO mode.
+ *
+ * According to Adaptec's documentation, an ACK is not sent on input from
+ * the target until SCSIDATL is read from. So we wait until SCSIDATL is
+ * latched (the usual way), then read the data byte directly off the bus
+ * using SCSIBUSL. When we have pulled the ATN line, or we just want to
+ * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
+ * spec guarantees that the target will hold the data byte on the bus until
+ * we send our ACK.
+ *
+ * The assumption here is that these are called in a particular sequence,
+ * and that REQ is already set when inb_first is called. inb_{first,next}
+ * use the same calling convention as inb.
+ */
inb_next:
- mov DINDEX,SINDEX # save SINDEX
-
- mvi STCNT+0,1 # xfer one byte
- mov NONE,SCSIDATL # dummy read from latch to ACK
-inb_next1:
- test SSTAT0,0x4 jz inb_next1 # SDONE
-inb_next2:
- test SSTAT0,0x2 jz inb_next2 # SPIORDY - wait for next byte
- mov DINDIR,SCSIBUSL ret # read byte directly from bus
-
+ or CLRSINT0, CLRSPIORDY
+ mov NONE,SCSIDATL /*dummy read from latch to ACK*/
+inb_next_wait:
+ test SSTAT1,PHASEMIS jnz mesgin_phasemis
+ test SSTAT0,SPIORDY jz inb_next_wait /* wait for next byte */
+inb_first:
+ mov DINDEX,SINDEX
+ mov DINDIR,SCSIBUSL ret /*read byte directly from bus*/
inb_last:
- mvi STCNT+0,1 # ACK with dummy read
- mov NONE,SCSIDATL
-inb_last1:
- test SSTAT0,0x4 jz inb_last1 # wait for completion
- ret
+ mov NONE,SCSIDATL ret /*dummy read from latch to ACK*/
-# DMA data transfer. HADDR and HCNT must be loaded first, and
-# SINDEX should contain the value to load DFCNTRL with - 0x3d for
-# host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared
-# during initialization.
-#
+mesgin_phasemis:
+/*
+ * We expected to receive another byte, but the target changed phase
+ */
+ mvi INTSTAT, MSGIN_PHASEMIS
+ jmp ITloop
+
+/*
+ * DMA data transfer. HADDR and HCNT must be loaded first, and
+ * SINDEX should contain the value to load DFCNTRL with - 0x3d for
+ * host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared
+ * during initialization.
+ */
dma:
mov DFCNTRL,SINDEX
dma1:
-dma2:
- test SSTAT0,0x1 jnz dma3 # DMADONE
- test SSTAT1,0x10 jz dma1 # PHASEMIS, ie. underrun
-
-# We will be "done" DMAing when the transfer count goes to zero, or
-# the target changes the phase (in light of this, it makes sense that
-# the DMA circuitry doesn't ACK when PHASEMIS is active). If we are
-# doing a SCSI->Host transfer, the data FIFO should be flushed auto-
-# magically on STCNT=0 or a phase change, so just wait for FIFO empty
-# status.
-#
+ test SSTAT0,DMADONE jnz dma3
+ test SSTAT1,PHASEMIS jz dma1 /* ie. underrun */
+
+/*
+ * We will be "done" DMAing when the transfer count goes to zero, or
+ * the target changes the phase (in light of this, it makes sense that
+ * the DMA circuitry doesn't ACK when PHASEMIS is active). If we are
+ * doing a SCSI->Host transfer, the data FIFO should be flushed auto-
+ * magically on STCNT=0 or a phase change, so just wait for FIFO empty
+ * status.
+ */
dma3:
- test SINDEX,0x4 jnz dma5 # DIRECTION
+ test SINDEX,DIRECTION jnz dma5
dma4:
- test DFSTATUS,0x1 jz dma4 # !FIFOEMP
+ test DFSTATUS,FIFOEMP jz dma4
-# Now shut the DMA enables off, and copy STCNT (ie. the underrun
-# amount, if any) to the SCB registers; SG_COUNT will get copied to
-# the SCB's residual S/G count field after sg_advance is called. Make
-# sure that the DMA enables are actually off first lest we get an ILLSADDR.
-#
+/*
+ * Now shut the DMA enables off and make sure that the DMA enables are
+ * actually off first lest we get an ILLSADDR.
+ */
dma5:
- clr DFCNTRL # disable DMA
+ /* disable DMA, but maintain WIDEODD */
+ and DFCNTRL,WIDEODD
dma6:
- test DFCNTRL,0x38 jnz dma6 # SCSIENACK|SDMAENACK|HDMAENACK
-
- mvi DINDEX,SCBARRAY+15
- mvi STCNT call bcopy_3
-
- ret
-
-dma_finish:
- test DFSTATUS,0x8 jz dma_finish # HDONE
+ test DFCNTRL,0x38 jnz dma6 /* SCSIENACK|SDMAENACK|HDMAENACK */
- clr DFCNTRL # disable DMA
-dma_finish2:
- test DFCNTRL,0x8 jnz dma_finish2 # HDMAENACK
ret
-# Common SCSI initialization for selection and reselection. Expects
-# the target SCSI ID to be in the upper four bits of SINDEX, and A's
-# contents are stomped on return.
-#
+/*
+ * Common SCSI initialization for selection and reselection. Expects
+ * the target SCSI ID to be in the upper four bits of SINDEX, and A's
+ * contents are stomped on return.
+ */
initialize_scsiid:
- and SINDEX,0xf0 # Get target ID
+ and SINDEX,0xf0 /* Get target ID */
and A,0x0f,SCSIID
or SINDEX,A
mov SCSIID,SINDEX ret
-initialize_for_target:
-# Turn on Automatic PIO mode now, before we expect to see a REQ
-# from the target. It shouldn't hurt anything to leave it on. Set
-# CLRCHN here before the target has entered a data transfer mode -
-# with synchronous SCSI, if you do it later, you blow away some
-# data in the SCSI FIFO that the target has already sent to you.
-#
- clr SIGSTATE
-
- mvi SXFRCTL0,0x8a # DFON|SPIOEN|CLRCHN
-
-# Initialize scatter-gather pointers by setting up the working copy
-# in scratch RAM.
-#
- call sg_scb2ram
-
-# Initialize SCSIRATE with the appropriate value for this target.
-#
- call ndx_dtr
- mov SCSIRATE,SINDIR ret
-
-# Assert that if we've been reselected, then we've seen an IDENTIFY
-# message.
-#
+/*
+ * Assert that if we've been reselected, then we've seen an IDENTIFY
+ * message.
+ */
assert:
- test FLAGS,RESELECTED jz return # reselected?
- test FLAGS,IDENTIFY_SEEN jnz return # seen IDENTIFY?
-
- mvi INTSTAT,NO_IDENT ret # no - cause a kernel panic
-
-# Find out if disconnection is ok from the information the BIOS has left
-# us. The tcl from SCBARRAY+1 should be in SINDEX; A will
-# contain either 0x40 (disconnection ok) or 0x00 (disconnection not ok)
-# on exit.
-#
-# To allow for wide or twin busses, we check the upper bit of the target ID
-# and the channel ID and look at the appropriate disconnect register.
-#
-disconnect:
- and FUNCTION1,0x70,SINDEX # strip off extra just in case
- mov A,FUNCTION1
- test SINDEX, 0x88 jz disconnect_a
-
- test DISC_DSB_B,A jz disconnect1 # bit nonzero if DISabled
- clr A ret
-
-disconnect_a:
- test DISC_DSB_A,A jz disconnect1 # bit nonzero if DISabled
- clr A ret
-
-disconnect1:
- mvi A,0x40 ret
-
-# Locate the SCB matching the target ID/channel/lun in SAVED_TCL and switch
-# the SCB to it. Have the kernel print a warning message if it can't be
-# found, and generate an ABORT message to the target. SINDEX should be
-# cleared on call.
-#
+ test FLAGS,RESELECTED jz return /* reselected? */
+ test FLAGS,IDENTIFY_SEEN jnz return /* seen IDENTIFY? */
+
+ mvi INTSTAT,NO_IDENT ret /* no - cause a kernel panic */
+
+/*
+ * Locate the SCB matching the target ID/channel/lun in SAVED_TCL, and the tag
+ * value in ARG_1. If ARG_1 == SCB_LIST_NULL, we're looking for a non-tagged
+ * SCB. Have the kernel print a warning message if it can't be found, and
+ * generate an ABORT/ABORT_TAG message to the target. SINDEX should be
+ * cleared on call.
+ */
findSCB:
mov A,SAVED_TCL
- mov SCBPTR,SINDEX # switch to new SCB
- cmp SCBARRAY+1,A jne findSCB1 # target ID/channel/lun match?
- test SCBARRAY+0,0x4 jz findSCB1 # should be disconnected
- test SCBARRAY+0,TAG_ENB jnz get_tag
- ret
+ mov SCBPTR,SINDEX /* switch to next SCB */
+ mvi SEQCTL,0x50 /* PAUSEDIS|FASTMODE */
+ cmp SCB_TCL,A jne findSCB1 /* target ID/channel/lun match? */
+ test SCB_CONTROL,DISCONNECTED jz findSCB1 /*should be disconnected*/
+ test SCB_CONTROL,TAG_ENB jnz findTaggedSCB
+ cmp ARG_1,SCB_LIST_NULL je foundSCB
+ jmp findSCB1
+findTaggedSCB:
+ mov A, ARG_1 /* Tag passed in ARG_1 */
+ cmp SCB_TAG,A jne findSCB1 /* Found it? */
+foundSCB:
+ test FLAGS,PAGESCBS jz foundSCB_ret
+/* Remove this SCB from the disconnection list */
+ cmp SCB_NEXT,SCB_LIST_NULL je unlink_prev
+ mov SAVED_LINKPTR, SCB_PREV
+ mov SCBPTR, SCB_NEXT
+ mov SCB_PREV, SAVED_LINKPTR
+ mov SCBPTR, SINDEX
+unlink_prev:
+ cmp SCB_PREV,SCB_LIST_NULL je rHead/* At the head of the list */
+ mov SAVED_LINKPTR, SCB_NEXT
+ mov SCBPTR, SCB_PREV
+ mov SCB_NEXT, SAVED_LINKPTR
+ mov SCBPTR, SINDEX
+ mvi SEQCTL,0x10 ret /* !PAUSEDIS|FASTMODE */
+rHead:
+ mov DISCONNECTED_SCBH,SCB_NEXT
+foundSCB_ret:
+ mvi SEQCTL,0x10 ret /* !PAUSEDIS|FASTMODE */
findSCB1:
+ mvi SEQCTL,0x10 /* !PAUSEDIS|FASTMODE */
inc SINDEX
mov A,SCBCOUNT
cmp SINDEX,A jne findSCB
- mvi INTSTAT,NO_MATCH # not found - signal kernel
- mvi 0x6 call mk_mesg # ABORT message
-
- or SINDEX,0x10,SIGSTATE # assert ATNO
- call scsisig
- ret
+ mvi INTSTAT,NO_MATCH /* not found - signal kernel */
+ cmp RETURN_1,SCB_PAGEDIN je return
+ or SCSISIGO,ATNO /* assert ATNO */
+ cmp ARG_1,SCB_LIST_NULL jne find_abort_tag
+ mvi MSG_ABORT call mk_mesg
+ jmp ITloop
+find_abort_tag:
+ mvi MSG_ABORT_TAG call mk_mesg
+ jmp ITloop
-# Make a working copy of the scatter-gather parameters in the SCB.
-#
+/*
+ * Make a working copy of the scatter-gather parameters from the SCB.
+ */
sg_scb2ram:
- mov SG_COUNT,SCBARRAY+2
-
- mvi DINDEX,SG_NEXT
- mvi SCBARRAY+3 call bcopy_4
-
- mvi SG_NOLOAD,0x80
- test SCBARRAY+0,0x10 jnz return # don't reload s/g?
- clr SG_NOLOAD ret
-
-# Copying RAM values back to SCB, for Save Data Pointers message.
-#
+ mov HADDR0, SCB_DATAPTR0
+ mov HADDR1, SCB_DATAPTR1
+ mov HADDR2, SCB_DATAPTR2
+ mov HADDR3, SCB_DATAPTR3
+ mov HCNT0, SCB_DATACNT0
+ mov HCNT1, SCB_DATACNT1
+ mov HCNT2, SCB_DATACNT2
+
+ mov STCNT0, HCNT0
+ mov STCNT1, HCNT1
+ mov STCNT2, HCNT2
+
+ mov SG_COUNT,SCB_SGCOUNT
+
+ mov SG_NEXT0, SCB_SGPTR0
+ mov SG_NEXT1, SCB_SGPTR1
+ mov SG_NEXT2, SCB_SGPTR2
+ mov SG_NEXT3, SCB_SGPTR3 ret
+
+/*
+ * Copying RAM values back to SCB, for Save Data Pointers message, but
+ * only if we've actually been into a data phase to change them. This
+ * protects against bogus data in scratch ram and the residual counts
+ * since they are only initialized when we go into data_in or data_out.
+ */
sg_ram2scb:
- mov SCBARRAY+2,SG_COUNT
+ test FLAGS, DPHASE jz return
+ mov SCB_SGCOUNT,SG_COUNT
- mvi DINDEX,SCBARRAY+3
- mvi SG_NEXT call bcopy_4
-
- and SCBARRAY+0,0xef,SCBARRAY+0
- test SG_NOLOAD,0x80 jz return # reload s/g?
- or SCBARRAY+0,SG_LOAD ret
-
-# Load a struct scatter if needed and set up the data address and
-# length. If the working value of the SG count is nonzero, then
-# we need to load a new set of values.
-#
-# This, like the above DMA, assumes a little-endian host data storage.
-#
-sg_load:
- test SG_COUNT,0xff jz return # SG being used?
- test SG_NOLOAD,0x80 jnz return # don't reload s/g?
-
- clr HCNT+2
- clr HCNT+1
- mvi HCNT+0,SG_SIZEOF
-
- mvi DINDEX,HADDR
- mvi SG_NEXT call bcopy_4
-
- mvi DFCNTRL,0xd # HDMAEN|DIRECTION|FIFORESET
-
-# Wait for DMA from host memory to data FIFO to complete, then disable
-# DMA and wait for it to acknowledge that it's off.
-#
-
- call dma_finish
-
-# Copy data from FIFO into SCB data pointer and data count. This assumes
-# that the struct scatterlist has this structure (this and sizeof(struct
-# scatterlist) == 12 are asserted in aic7xxx.c):
-#
-# struct scatterlist {
-# char *address; /* four bytes, little-endian order */
-# ... /* four bytes, ignored */
-# unsigned short length; /* two bytes, little-endian order */
-# }
-#
-
-# Not in FreeBSD. the scatter list entry is only 8 bytes.
-#
-# struct ahc_dma_seg {
-# physaddr addr; /* four bytes, little-endian order */
-# long len; /* four bytes, little endian order */
-# };
-#
-
- mvi DINDEX, SCBARRAY+19
- call bcopy_4_dfdat
-
-# For Linux, we must throw away four bytes since there is a 32bit gap
-# in the middle of a struct scatterlist
-# mov NONE,DFDAT
-# mov NONE,DFDAT
-# mov NONE,DFDAT
-# mov NONE,DFDAT
-
- call bcopy_3_dfdat #Only support 24 bit length.
- ret
-
-# Advance the scatter-gather pointers only IF NEEDED. If SG is enabled,
-# and the SCSI transfer count is zero (note that this should be called
-# right after a DMA finishes), then move the working copies of the SG
-# pointer/length along. If the SCSI transfer count is not zero, then
-# presumably the target is disconnecting - do not reload the SG values
-# next time.
-#
-sg_advance:
- test SG_COUNT,0xff jz return # s/g enabled?
-
- test STCNT+0,0xff jnz sg_advance1 # SCSI transfer count nonzero?
- test STCNT+1,0xff jnz sg_advance1
- test STCNT+2,0xff jnz sg_advance1
-
- clr SG_NOLOAD # reload s/g next time
- dec SG_COUNT # one less segment to go
-
- clr A # add sizeof(struct scatter)
- add SG_NEXT+0,SG_SIZEOF,SG_NEXT+0
- adc SG_NEXT+1,A,SG_NEXT+1
- adc SG_NEXT+2,A,SG_NEXT+2
- adc SG_NEXT+3,A,SG_NEXT+3 ret
-
-sg_advance1:
- mvi SG_NOLOAD,0x80 ret # don't reload s/g next time
-
-# Add the array base SYNCNEG to the target offset (the target address
-# is in SCSIID), and return the result in SINDEX. The accumulator
-# contains the 3->8 decoding of the target ID on return.
-#
+ mov SCB_SGPTR0,SG_NEXT0
+ mov SCB_SGPTR1,SG_NEXT1
+ mov SCB_SGPTR2,SG_NEXT2
+ mov SCB_SGPTR3,SG_NEXT3
+
+ mov SCB_DATAPTR0,SHADDR0
+ mov SCB_DATAPTR1,SHADDR1
+ mov SCB_DATAPTR2,SHADDR2
+ mov SCB_DATAPTR3,SHADDR3
+
+/*
+ * Use the residual number since STCNT is corrupted by any message transfer
+ */
+ mov SCB_DATACNT0,SCB_RESID_DCNT0
+ mov SCB_DATACNT1,SCB_RESID_DCNT1
+ mov SCB_DATACNT2,SCB_RESID_DCNT2 ret
+
+/*
+ * Add the array base TARG_SCRATCH to the target offset (the target address
+ * is in SCSIID), and return the result in SINDEX. The accumulator
+ * contains the 3->8 decoding of the target ID on return.
+ */
ndx_dtr:
shr A,SCSIID,4
- test SBLKCTL,0x08 jz ndx_dtr_2
- or A,0x08 # Channel B entries add 8
+ test SBLKCTL,SELBUSB jz ndx_dtr_2
+ or A,0x08 /* Channel B entries add 8 */
ndx_dtr_2:
- add SINDEX,SYNCNEG,A
-
- and FUNCTION1,0x70,SCSIID # 3-bit target address decode
- mov A,FUNCTION1 ret
-
-# If we need to negotiate transfer parameters, build the WDTR or SDTR message
-# starting at the address passed in SINDEX. DINDEX is modified on return.
-# The SCSI-II spec requires that Wide negotiation occur first and you can
-# only negotiat one or the other at a time otherwise in the event of a message
-# reject, you wouldn't be able to tell which message was the culpret.
-#
+ add SINDEX,TARG_SCRATCH,A ret
+
+/*
+ * If we need to negotiate transfer parameters, build the WDTR or SDTR message
+ * starting at the address passed in SINDEX. DINDEX is modified on return.
+ * The SCSI-II spec requires that Wide negotiation occur first and you can
+ * only negotiat one or the other at a time otherwise in the event of a message
+ * reject, you wouldn't be able to tell which message was the culpret.
+ */
mk_dtr:
- test SCBARRAY+0,0xc0 jz return # NEEDWDTR|NEEDSDTR
- test SCBARRAY+0,NEEDWDTR jnz mk_wdtr_16bit
- or FLAGS, MAX_SYNC # Force an offset of 15
+ test SCB_CONTROL,NEEDWDTR jnz mk_wdtr_16bit
+ mvi ARG_1, MAXOFFSET /* Force an offset of 15 or 8 if WIDE */
mk_sdtr:
- mvi DINDIR,1 # extended message
- mvi DINDIR,3 # extended message length = 3
- mvi DINDIR,1 # SDTR code
+ mvi DINDIR,1 /* extended message */
+ mvi DINDIR,3 /* extended message length = 3 */
+ mvi DINDIR,1 /* SDTR code */
call sdtr_to_rate
- mov DINDIR,RETURN_1 # REQ/ACK transfer period
- test FLAGS, MAX_SYNC jnz mk_sdtr_max_sync
- and DINDIR,0xf,SINDIR # Sync Offset
+ mov DINDIR,RETURN_1 /* REQ/ACK transfer period */
+ cmp ARG_1, MAXOFFSET je mk_sdtr_max_offset
+ and DINDIR,0x0f,SINDIR /* Sync Offset */
mk_sdtr_done:
- add MSG_LEN,-MSG_START+0,DINDEX ret # update message length
+ add MSG_LEN,COMP_MSG0,DINDEX ret /* update message length */
+
+mk_sdtr_max_offset:
+/*
+ * We're initiating sync negotiation, so request the max offset we can (15 or 8)
+ */
+ /* Talking to a WIDE device? */
+ test SCSIRATE, WIDEXFER jnz wmax_offset
+ mvi DINDIR, MAX_OFFSET_8BIT
+ jmp mk_sdtr_done
-mk_sdtr_max_sync:
-# We're initiating sync negotiation, so request the max offset we can (15)
- mvi DINDIR, 0x0f
- xor FLAGS, MAX_SYNC
+wmax_offset:
+ mvi DINDIR, MAX_OFFSET_16BIT
jmp mk_sdtr_done
mk_wdtr_16bit:
mvi ARG_1,BUS_16_BIT
mk_wdtr:
- mvi DINDIR,1 # extended message
- mvi DINDIR,2 # extended message length = 2
- mvi DINDIR,3 # WDTR code
- mov DINDIR,ARG_1 # bus width
+ mvi DINDIR,1 /* extended message */
+ mvi DINDIR,2 /* extended message length = 2 */
+ mvi DINDIR,3 /* WDTR code */
+ mov DINDIR,ARG_1 /* bus width */
- add MSG_LEN,-MSG_START+0,DINDEX ret # update message length
+ add MSG_LEN,COMP_MSG0,DINDEX ret /* update message length */
-# Set SCSI bus control signal state. This also saves the last-written
-# value into a location where the higher-level driver can read it - if
-# it has to send an ABORT or RESET message, then it needs to know this
-# so it can assert ATN without upsetting SCSISIGO. The new value is
-# expected in SINDEX. Change the actual state last to avoid contention
-# from the driver.
-#
-scsisig:
- mov SIGSTATE,SINDEX
- mov SCSISIGO,SINDEX ret
-
sdtr_to_rate:
- call ndx_dtr # index scratch space for target
+ call ndx_dtr /* index scratch space for target */
shr A,SINDIR,0x4
- dec SINDEX #Preserve SINDEX
+ dec SINDEX /* Preserve SINDEX */
and A,0x7
clr RETURN_1
sdtr_to_rate_loop:
test A,0x0f jz sdtr_to_rate_done
- add RETURN_1,0x18
+ add RETURN_1,0x19
dec A
jmp sdtr_to_rate_loop
sdtr_to_rate_done:
shr RETURN_1,0x2
- add RETURN_1,0x18 ret
-
+ add RETURN_1,0x19
+ test SXFRCTL0,ULTRAEN jz return
+ shr RETURN_1,0x1
return:
ret
* are token separators.
*
*-M*************************************************************************/
-static char id[] = "$Id: aic7xxx_asm.c,v 1.1.1.1 1995/10/18 08:52:39 deraadt Exp $";
+static char id[] = "$Id: aic7xxx_asm.c,v 1.2 1996/05/05 12:42:38 deraadt Exp $";
#include <ctype.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
+#include <fcntl.h>
#define MEMORY 448
#define MAXLINE 1024
int debug;
int lineno, LC;
char *filename;
-FILE *ifp, *ofp;
unsigned char M[MEMORY][4];
-void
+void
error(char *s)
{
fprintf(stderr, "%s: %s at line %d\n", filename, s, lineno);
struct sym_t *next; /* MUST BE FIRST */
char *name;
int value;
- int npatch;
+ int npatch;
int *patch;
} sym_t;
return(NULL);
}
-void
+void
patch(sym_t *p, int location)
{
p->npatch += 1;
i = 0;
- while (fgets(buf, sizeof(buf), ifp)) {
+ while (fgets(buf, sizeof(buf), stdin)) {
lineno += 1;
else
error("too many tokens");
if (quote) {
- quote++;
+ quote++;
p = strchr(quote, '\"');
if (!p)
error("unterminated string constant");
else
error("too many tokens");
goto rescan;
- }
+ }
if (i) {
*n = i;
return(a);
{ 0, 0, 0, 0, 0, 0, 0, 0 }
};
-int
+int
eval_operand(char **a, int spec)
{
int i;
#undef A
void
-assemble(void)
+assemble(FILE *ofile)
{
int n;
char **a;
continue;
if (n == 3 && !strcmp("VERSION", *a))
- fprintf(ofp, "#define %s \"%s\"\n", a[1], a[2]);
+ fprintf(ofile, "#define %s \"%s\"\n", a[1], a[2]);
else {
if (n == 3 && !strcmp("=", a[1]))
define(*a, strtol(a[2], NULL, 0));
}
backpatch();
- output(ofp);
+ output(ofile);
if (debug)
output(stderr);
int
main(int argc, char **argv)
-{ int my_version_print_flag;
+{
int c;
+ int pid;
+ int ifile;
+ FILE *ofile;
+ int fd[2];
- my_version_print_flag=0;
-
- while ((c = getopt(argc, argv, "dho:vD")) != EOF) {
+ ofile = NULL;
+ while ((c = getopt(argc, argv, "dho:vD:")) != EOF) {
switch (c) {
case 'd':
debug = !0;
break;
}
case 'o':
- ofp = fopen(optarg, "w");
- if (!ofp) {
+
+ if ((ofile = fopen(optarg, "w")) == NULL) {
perror(optarg);
exit(EXIT_FAILURE);
}
break;
case 'h':
- printf("usage: %s [-d] [-Dname] [-ooutput] input\n",
+ printf("usage: %s [-d] [-Dname] [-ooutput] input\n",
*argv);
exit(EXIT_SUCCESS);
break;
case 'v':
- if (!my_version_print_flag)
- { printf("%s\n",id);
-
- my_version_print_flag=1;
- }
+ printf("%s\n", id);
+ exit(EXIT_SUCCESS);
break;
default:
exit(EXIT_FAILURE);
}
if (argc - optind != 1) {
- if (my_version_print_flag)
- { exit(EXIT_SUCCESS);
- }
fprintf(stderr, "%s: must have one input file\n", *argv);
exit(EXIT_FAILURE);
}
filename = argv[optind];
- ifp = fopen(filename, "r");
- if (!ifp) {
+
+ if ((ifile = open(filename, O_RDONLY)) < 0) {
perror(filename);
exit(EXIT_FAILURE);
}
- if (!ofp) {
- ofp = fopen(ADOTOUT, "w");
- if (!ofp) {
+ if (!ofile) {
+ if ((ofile = fopen(ADOTOUT, "w")) == NULL) {
perror(ADOTOUT);
exit(EXIT_FAILURE);
}
}
- assemble();
- exit(EXIT_SUCCESS);
+ if (pipe(fd) < 0) {
+ perror("pipe failed");
+ exit(1);
+ }
+
+ if ((pid = fork()) < 0 ) {
+ perror("fork failed");
+ exit(1);
+ }
+ else if (pid > 0) { /* Parent */
+ close(fd[1]); /* Close write end */
+ if (fd[0] != STDIN_FILENO) {
+ if (dup2(fd[0], STDIN_FILENO) != STDIN_FILENO) {
+ perror("dup2 error on stdin");
+ exit(EXIT_FAILURE);
+ }
+ close(fd[0]);
+ }
+ assemble(ofile);
+ exit(EXIT_SUCCESS);
+ }
+ else { /* Child */
+ close(fd[0]); /* Close Read end */
+ if (fd[1] != STDOUT_FILENO) {
+ if (dup2(fd[1], STDOUT_FILENO) != STDOUT_FILENO) {
+ perror("dup2 error on stdout");
+ exit(EXIT_FAILURE);
+ }
+ close(fd[1]);
+ }
+ if (ifile != STDIN_FILENO) {
+ if (dup2(ifile, STDIN_FILENO) != STDIN_FILENO) {
+ perror("dup2 error on stdin");
+ exit(EXIT_FAILURE);
+ }
+ close(ifile);
+ }
+ execl("/usr/bin/cpp", "/usr/bin/cpp", "-P", "-", "-", NULL);
+ }
+ return(EXIT_SUCCESS);
}
--- /dev/null
+/*
+ * Aic7xxx register and scratch ram definitions.
+ *
+ * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice immediately at the beginning of the file, without modification,
+ * this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: aic7xxx_reg.h,v 1.1 1996/05/05 12:42:39 deraadt Exp $
+ */
+
+/*
+ * This header is shared by the sequencer code and the kernel level driver.
+ *
+ * All page numbers refer to the Adaptec AIC-7770 Data Book availible from
+ * Adaptec's Technical Documents Department 1-800-934-2766
+ */
+
+/*
+ * SCSI Sequence Control (p. 3-11).
+ * Each bit, when set starts a specific SCSI sequence on the bus
+ */
+#define SCSISEQ 0x000
+#define TEMODEO 0x80
+#define ENSELO 0x40
+#define ENSELI 0x20
+#define ENRSELI 0x10
+#define ENAUTOATNO 0x08
+#define ENAUTOATNI 0x04
+#define ENAUTOATNP 0x02
+#define SCSIRSTO 0x01
+
+/*
+ * SCSI Transfer Control 0 Register (pp. 3-13).
+ * Controls the SCSI module data path.
+ */
+#define SXFRCTL0 0x001
+#define DFON 0x80
+#define DFPEXP 0x40
+#define ULTRAEN 0x20
+#define CLRSTCNT 0x10
+#define SPIOEN 0x08
+#define SCAMEN 0x04
+#define CLRCHN 0x02
+/* UNUSED 0x01 */
+
+/*
+ * SCSI Transfer Control 1 Register (pp. 3-14,15).
+ * Controls the SCSI module data path.
+ */
+#define SXFRCTL1 0x002
+#define BITBUCKET 0x80
+#define SWRAPEN 0x40
+#define ENSPCHK 0x20
+#define STIMESEL 0x18
+#define ENSTIMER 0x04
+#define ACTNEGEN 0x02
+#define STPWEN 0x01 /* Powered Termination */
+
+/*
+ * SCSI Control Signal Read Register (p. 3-15).
+ * Reads the actual state of the SCSI bus pins
+ */
+#define SCSISIGI 0x003
+#define CDI 0x80
+#define IOI 0x40
+#define MSGI 0x20
+#define ATNI 0x10
+#define SELI 0x08
+#define BSYI 0x04
+#define REQI 0x02
+#define ACKI 0x01
+
+/*
+ * Possible phases in SCSISIGI
+ */
+#define PHASE_MASK 0xe0
+#define P_DATAOUT 0x00
+#define P_DATAIN 0x40
+#define P_COMMAND 0x80
+#define P_MESGOUT 0xa0
+#define P_STATUS 0xc0
+#define P_MESGIN 0xe0
+/*
+ * SCSI Contol Signal Write Register (p. 3-16).
+ * Writing to this register modifies the control signals on the bus. Only
+ * those signals that are allowed in the current mode (Initiator/Target) are
+ * asserted.
+ */
+#define SCSISIGO 0x003
+#define CDO 0x80
+#define IOO 0x40
+#define MSGO 0x20
+#define ATNO 0x10
+#define SELO 0x08
+#define BSYO 0x04
+#define REQO 0x02
+#define ACKO 0x01
+
+/*
+ * SCSI Rate Control (p. 3-17).
+ * Contents of this register determine the Synchronous SCSI data transfer
+ * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
+ * SOFS (3:0) bits disables synchronous data transfers. Any offset value
+ * greater than 0 enables synchronous transfers.
+ */
+#define SCSIRATE 0x004
+#define WIDEXFER 0x80 /* Wide transfer control */
+#define SXFR 0x70 /* Sync transfer rate */
+#define SOFS 0x0f /* Sync offset */
+
+/*
+ * SCSI ID (p. 3-18).
+ * Contains the ID of the board and the current target on the
+ * selected channel.
+ */
+#define SCSIID 0x005
+#define TID 0xf0 /* Target ID mask */
+#define OID 0x0f /* Our ID mask */
+
+/*
+ * SCSI Latched Data (p. 3-19).
+ * Read/Write latchs used to transfer data on the SCSI bus during
+ * Automatic or Manual PIO mode. SCSIDATH can be used for the
+ * upper byte of a 16bit wide asyncronouse data phase transfer.
+ */
+#define SCSIDATL 0x006
+#define SCSIDATH 0x007
+
+/*
+ * SCSI Transfer Count (pp. 3-19,20)
+ * These registers count down the number of bytes transfered
+ * across the SCSI bus. The counter is decremented only once
+ * the data has been safely transfered. SDONE in SSTAT0 is
+ * set when STCNT goes to 0
+ */
+#define STCNT 0x008
+#define STCNT0 0x008
+#define STCNT1 0x009
+#define STCNT2 0x00a
+
+/*
+ * Clear SCSI Interrupt 0 (p. 3-20)
+ * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
+ */
+#define CLRSINT0 0x00b
+#define CLRSELDO 0x40
+#define CLRSELDI 0x20
+#define CLRSELINGO 0x10
+#define CLRSWRAP 0x08
+/* UNUSED 0x04 */
+#define CLRSPIORDY 0x02
+/* UNUSED 0x01 */
+
+/*
+ * SCSI Status 0 (p. 3-21)
+ * Contains one set of SCSI Interrupt codes
+ * These are most likely of interest to the sequencer
+ */
+#define SSTAT0 0x00b
+#define TARGET 0x80 /* Board acting as target */
+#define SELDO 0x40 /* Selection Done */
+#define SELDI 0x20 /* Board has been selected */
+#define SELINGO 0x10 /* Selection In Progress */
+#define SWRAP 0x08 /* 24bit counter wrap */
+#define SDONE 0x04 /* STCNT = 0x000000 */
+#define SPIORDY 0x02 /* SCSI PIO Ready */
+#define DMADONE 0x01 /* DMA transfer completed */
+
+/*
+ * Clear SCSI Interrupt 1 (p. 3-23)
+ * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
+ */
+#define CLRSINT1 0x00c
+#define CLRSELTIMEO 0x80
+#define CLRATNO 0x40
+#define CLRSCSIRSTI 0x20
+/* UNUSED 0x10 */
+#define CLRBUSFREE 0x08
+#define CLRSCSIPERR 0x04
+#define CLRPHASECHG 0x02
+#define CLRREQINIT 0x01
+
+/*
+ * SCSI Status 1 (p. 3-24)
+ */
+#define SSTAT1 0x00c
+#define SELTO 0x80
+#define ATNTARG 0x40
+#define SCSIRSTI 0x20
+#define PHASEMIS 0x10
+#define BUSFREE 0x08
+#define SCSIPERR 0x04
+#define PHASECHG 0x02
+#define REQINIT 0x01
+
+/*
+ * SCSI Interrupt Mode 1 (pp. 3-28,29)
+ * Setting any bit will enable the corresponding function
+ * in SIMODE1 to interrupt via the IRQ pin.
+ */
+#define SIMODE1 0x011
+#define ENSELTIMO 0x80
+#define ENATNTARG 0x40
+#define ENSCSIRST 0x20
+#define ENPHASEMIS 0x10
+#define ENBUSFREE 0x08
+#define ENSCSIPERR 0x04
+#define ENPHASECHG 0x02
+#define ENREQINIT 0x01
+
+/*
+ * SCSI Data Bus (High) (p. 3-29)
+ * This register reads data on the SCSI Data bus directly.
+ */
+#define SCSIBUSL 0x012
+#define SCSIBUSH 0x013
+
+/*
+ * SCSI/Host Address (p. 3-30)
+ * These registers hold the host address for the byte about to be
+ * transfered on the SCSI bus. They are counted up in the same
+ * manner as STCNT is counted down. SHADDR should always be used
+ * to determine the address of the last byte transfered since HADDR
+ * can be squewed by write ahead.
+ */
+#define SHADDR 0x014
+#define SHADDR0 0x014
+#define SHADDR1 0x015
+#define SHADDR2 0x016
+#define SHADDR3 0x017
+
+/*
+ * Selection/Reselection ID (p. 3-31)
+ * Upper four bits are the device id. The ONEBIT is set when the re/selecting
+ * device did not set its own ID.
+ */
+#define SELID 0x019
+#define SELID_MASK 0xf0
+#define ONEBIT 0x08
+/* UNUSED 0x07 */
+
+/*
+ * SCSI Block Control (p. 3-32)
+ * Controls Bus type and channel selection. In a twin channel configuration
+ * addresses 0x00-0x1e are gated to the appropriate channel based on this
+ * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
+ * on a wide bus.
+ */
+#define SBLKCTL 0x01f
+#define DIAGLEDEN 0x80 /* Aic78X0 only */
+#define DIAGLEDON 0x40 /* Aic78X0 only */
+#define AUTOFLUSHDIS 0x20
+/* UNUSED 0x10 */
+#define SELBUS_MASK 0x0a
+#define SELBUSB 0x08
+/* UNUSED 0x04 */
+#define SELWIDE 0x02
+/* UNUSED 0x01 */
+#define SELNARROW 0x00
+
+/*
+ * Sequencer Control (p. 3-33)
+ * Error detection mode and speed configuration
+ */
+#define SEQCTL 0x060
+#define PERRORDIS 0x80
+#define PAUSEDIS 0x40
+#define FAILDIS 0x20
+#define FASTMODE 0x10
+#define BRKADRINTEN 0x08
+#define STEP 0x04
+#define SEQRESET 0x02
+#define LOADRAM 0x01
+
+/*
+ * Sequencer RAM Data (p. 3-34)
+ * Single byte window into the Scratch Ram area starting at the address
+ * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
+ * four bytes in sucessesion. The SEQADDRs will increment after the most
+ * significant byte is written
+ */
+#define SEQRAM 0x061
+
+/*
+ * Sequencer Address Registers (p. 3-35)
+ * Only the first bit of SEQADDR1 holds addressing information
+ */
+#define SEQADDR0 0x062
+#define SEQADDR1 0x063
+#define SEQADDR1_MASK 0x01
+
+/*
+ * Accumulator
+ * We cheat by passing arguments in the Accumulator up to the kernel driver
+ */
+#define ACCUM 0x064
+
+#define SINDEX 0x065
+#define DINDEX 0x066
+#define ALLZEROS 0x06a
+#define NONE 0x06a
+#define SINDIR 0x06c
+#define DINDIR 0x06d
+#define FUNCTION1 0x06e
+
+/*
+ * Host Address (p. 3-48)
+ * This register contains the address of the byte about
+ * to be transfered across the host bus.
+ */
+#define HADDR 0x088
+#define HADDR0 0x088
+#define HADDR1 0x089
+#define HADDR2 0x08a
+#define HADDR3 0x08b
+
+#define HCNT 0x08c
+#define HCNT0 0x08c
+#define HCNT1 0x08d
+#define HCNT2 0x08e
+/*
+ * SCB Pointer (p. 3-49)
+ * Gate one of the four SCBs into the SCBARRAY window.
+ */
+#define SCBPTR 0x090
+
+/*
+ * Board Control (p. 3-43)
+ */
+#define BCTL 0x084
+/* RSVD 0xf0 */
+#define ACE 0x08 /* Support for external processors */
+/* RSVD 0x06 */
+#define ENABLE 0x01
+
+/*
+ * On the aic78X0 chips, Board Control is replaced by the DSCommand
+ * register (p. 4-64)
+ */
+#define DSCOMMAND 0x084
+#define CACHETHEN 0x80 /* Cache Threshold enable */
+#define DPARCKEN 0x40 /* Data Parity Check Enable */
+#define MPARCKEN 0x20 /* Memory Parity Check Enable */
+#define EXTREQLCK 0x10 /* External Request Lock */
+
+/*
+ * Bus On/Off Time (p. 3-44)
+ */
+#define BUSTIME 0x085
+#define BOFF 0xf0
+#define BON 0x0f
+#define BOFF_60BCLKS 0xf0
+
+/*
+ * Bus Speed (p. 3-45)
+ */
+#define BUSSPD 0x086
+#define DFTHRSH 0xc0
+#define STBOFF 0x38
+#define STBON 0x07
+#define DFTHRSH_100 0xc0
+
+/*
+ * Host Control (p. 3-47) R/W
+ * Overal host control of the device.
+ */
+#define HCNTRL 0x087
+/* UNUSED 0x80 */
+#define POWRDN 0x40
+/* UNUSED 0x20 */
+#define SWINT 0x10
+#define IRQMS 0x08
+#define PAUSE 0x04
+#define INTEN 0x02
+#define CHIPRST 0x01
+
+/*
+ * Interrupt Status (p. 3-50)
+ * Status for system interrupts
+ */
+#define INTSTAT 0x091
+#define SEQINT_MASK 0xf1 /* SEQINT Status Codes */
+#define BAD_PHASE 0x01 /* unknown scsi bus phase */
+#define SEND_REJECT 0x11 /* sending a message reject */
+#define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/
+#define NO_MATCH 0x31 /* no cmd match for reconnect */
+#define SDTR_MSG 0x41 /* SDTR message received */
+#define WDTR_MSG 0x51 /* WDTR message received */
+#define REJECT_MSG 0x61 /* Reject message received */
+#define BAD_STATUS 0x71 /* Bad status from target */
+#define RESIDUAL 0x81 /* Residual byte count != 0 */
+#define ABORT_TAG 0x91 /* Sent an ABORT_TAG message */
+#define AWAITING_MSG 0xa1 /*
+ * Kernel requested to specify
+ * a message to this target
+ * (command was null), so tell
+ * it that it can fill the
+ * message buffer.
+ */
+#define IMMEDDONE 0xb1 /*
+ * An immediate command has
+ * completed
+ */
+#define MSG_BUFFER_BUSY 0xc1 /*
+ * Sequencer wants to use the
+ * message buffer, but it
+ * already contains a message
+ */
+#define MSGIN_PHASEMIS 0xd1 /*
+ * Target changed phase on us
+ * when we were expecting
+ * another msgin byte.
+ */
+#define BRKADRINT 0x08
+#define SCSIINT 0x04
+#define CMDCMPLT 0x02
+#define SEQINT 0x01
+#define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
+
+/*
+ * Hard Error (p. 3-53)
+ * Reporting of catastrophic errors. You usually cannot recover from
+ * these without a full board reset.
+ */
+#define ERROR 0x092
+/* UNUSED 0xf0 */
+#define PARERR 0x08
+#define ILLOPCODE 0x04
+#define ILLSADDR 0x02
+#define ILLHADDR 0x01
+
+/*
+ * Clear Interrupt Status (p. 3-52)
+ */
+#define CLRINT 0x092
+#define CLRBRKADRINT 0x08
+#define CLRSCSIINT 0x04
+#define CLRCMDINT 0x02
+#define CLRSEQINT 0x01
+
+#define DFCNTRL 0x093
+#define WIDEODD 0x40
+#define SCSIEN 0x20
+#define SDMAEN 0x10
+#define SDMAENACK 0x10
+#define HDMAEN 0x08
+#define HDMAENACK 0x08
+#define DIRECTION 0x04
+#define FIFOFLUSH 0x02
+#define FIFORESET 0x01
+
+#define DFSTATUS 0x094
+#define HDONE 0x08
+#define FIFOEMP 0x01
+
+#define DFDAT 0x099
+
+/*
+ * SCB Auto Increment (p. 3-59)
+ * Byte offset into the SCB Array and an optional bit to allow auto
+ * incrementing of the address during download and upload operations
+ */
+#define SCBCNT 0x09a
+#define SCBAUTO 0x80
+#define SCBCNT_MASK 0x1f
+
+/*
+ * Queue In FIFO (p. 3-60)
+ * Input queue for queued SCBs (commands that the seqencer has yet to start)
+ */
+#define QINFIFO 0x09b
+
+/*
+ * Queue In Count (p. 3-60)
+ * Number of queued SCBs
+ */
+#define QINCNT 0x09c
+
+/*
+ * Queue Out FIFO (p. 3-61)
+ * Queue of SCBs that have completed and await the host
+ */
+#define QOUTFIFO 0x09d
+
+/*
+ * Queue Out Count (p. 3-61)
+ * Number of queued SCBs in the Out FIFO
+ */
+#define QOUTCNT 0x09e
+
+/*
+ * SCB Definition (p. 5-4)
+ * The two reserved bytes at SCBARRAY+1[23] are expected to be set to
+ * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate
+ * whether or not to DMA an SCB from host ram. This flag prevents the
+ * "re-fetching" of transactions that are requed because the target is
+ * busy with another command. We also use bits 6 & 7 to indicate whether
+ * or not to initiate SDTR or WDTR repectively when starting this command.
+ */
+#define SCBARRAY 0x0a0
+#define SCB_CONTROL 0x0a0
+#define NEEDWDTR 0x80
+#define DISCENB 0x40
+#define TAG_ENB 0x20
+#define NEEDSDTR 0x10
+#define DISCONNECTED 0x04
+#define SCB_TAG_TYPE 0x03
+#define SCB_TCL 0x0a1
+#define SCB_TARGET_STATUS 0x0a2
+#define SCB_SGCOUNT 0x0a3
+#define SCB_SGPTR 0x0a4
+#define SCB_SGPTR0 0x0a4
+#define SCB_SGPTR1 0x0a5
+#define SCB_SGPTR2 0x0a6
+#define SCB_SGPTR3 0x0a7
+#define SCB_RESID_SGCNT 0x0a8
+#define SCB_RESID_DCNT 0x0a9
+#define SCB_RESID_DCNT0 0x0a9
+#define SCB_RESID_DCNT1 0x0aa
+#define SCB_RESID_DCNT2 0x0ab
+#define SCB_DATAPTR 0x0ac
+#define SCB_DATAPTR0 0x0ac
+#define SCB_DATAPTR1 0x0ad
+#define SCB_DATAPTR2 0x0ae
+#define SCB_DATAPTR3 0x0af
+#define SCB_DATACNT 0x0b0
+#define SCB_DATACNT0 0x0b0
+#define SCB_DATACNT1 0x0b1
+#define SCB_DATACNT2 0x0b2
+/* UNUSED - QUAD PADDING 0x0b3 */
+#define SCB_CMDPTR 0x0b4
+#define SCB_CMDPTR0 0x0b4
+#define SCB_CMDPTR1 0x0b5
+#define SCB_CMDPTR2 0x0b6
+#define SCB_CMDPTR3 0x0b7
+#define SCB_CMDLEN 0x0b8
+#define SCB_TAG 0x0b9
+#define SCB_NEXT 0x0ba
+#define SCB_PREV 0x0bb
+
+#ifdef linux
+#define SG_SIZEOF 0x0c /* sizeof(struct scatterlist) */
+#else
+#define SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
+#endif
+
+/* --------------------- AHA-2840-only definitions -------------------- */
+
+#define SEECTL_2840 0x0c0
+/* UNUSED 0xf8 */
+#define CS_2840 0x04
+#define CK_2840 0x02
+#define DO_2840 0x01
+
+#define STATUS_2840 0x0c1
+#define EEPROM_TF 0x80
+#define BIOS_SEL 0x60
+#define ADSEL 0x1e
+#define DI_2840 0x01
+
+/* --------------------- AIC-7870-only definitions -------------------- */
+
+#define DSPCISTATUS 0x086
+
+/*
+ * Serial EEPROM Control (p. 4-92 in 7870 Databook)
+ * Controls the reading and writing of an external serial 1-bit
+ * EEPROM Device. In order to access the serial EEPROM, you must
+ * first set the SEEMS bit that generates a request to the memory
+ * port for access to the serial EEPROM device. When the memory
+ * port is not busy servicing another request, it reconfigures
+ * to allow access to the serial EEPROM. When this happens, SEERDY
+ * gets set high to verify that the memory port access has been
+ * granted.
+ *
+ * After successful arbitration for the memory port, the SEECS bit of
+ * the SEECTL register is connected to the chip select. The SEECK,
+ * SEEDO, and SEEDI are connected to the clock, data out, and data in
+ * lines respectively. The SEERDY bit of SEECTL is useful in that it
+ * gives us an 800 nsec timer. After a write to the SEECTL register,
+ * the SEERDY goes high 800 nsec later. The one exception to this is
+ * when we first request access to the memory port. The SEERDY goes
+ * high to signify that access has been granted and, for this case, has
+ * no implied timing.
+ *
+ * See 93cx6.c for detailed information on the protocol necessary to
+ * read the serial EEPROM.
+ */
+#define SEECTL 0x01e
+#define EXTARBACK 0x80
+#define EXTARBREQ 0x40
+#define SEEMS 0x20
+#define SEERDY 0x10
+#define SEECS 0x08
+#define SEECK 0x04
+#define SEEDO 0x02
+#define SEEDI 0x01
+
+/* ---------------------- Scratch RAM Offsets ------------------------- */
+/* These offsets are either to values that are initialized by the board's
+ * BIOS or are specified by the sequencer code.
+ *
+ * The host adapter card (at least the BIOS) uses 20-2f for SCSI
+ * device information, 32-33 and 5a-5f as well. As it turns out, the
+ * BIOS trashes 20-2f, writing the synchronous negotiation results
+ * on top of the BIOS values, so we re-use those for our per-target
+ * scratchspace (actually a value that can be copied directly into
+ * SCSIRATE). The kernel driver will enable synchronous negotiation
+ * for all targets that have a value other than 0 in the lower four
+ * bits of the target scratch space. This should work regardless of
+ * whether the bios has been installed.
+ */
+
+/*
+ * 1 byte per target starting at this address for configuration values
+ */
+#define TARG_SCRATCH 0x020
+
+/*
+ * The sequencer will stick the frist byte of any rejected message here so
+ * we can see what is getting thrown away. Extended messages put the
+ * extended message type in REJBYTE_EXT.
+ */
+#define REJBYTE 0x030
+#define REJBYTE_EXT 0x031
+
+/*
+ * Bit vector of targets that have disconnection disabled.
+ */
+#define DISC_DSB 0x032
+#define DISC_DSB_A 0x032
+#define DISC_DSB_B 0x033
+
+/*
+ * Length of pending message
+ */
+#define MSG_LEN 0x034
+
+/* We reserve 8bytes to store outgoing messages */
+#define MSG0 0x035
+#define COMP_MSG0 0xcb /* 2's complement of MSG0 */
+#define MSG1 0x036
+#define MSG2 0x037
+#define MSG3 0x038
+#define MSG4 0x039
+#define MSG5 0x03a
+#define MSG6 0x03b
+#define MSG7 0x03c
+
+/*
+ * These are offsets into the card's scratch ram. Some of the values are
+ * specified in the AHA2742 technical reference manual and are initialized
+ * by the BIOS at boot time.
+ */
+#define LASTPHASE 0x03d
+#define ARG_1 0x03e
+#define MAXOFFSET 0x01
+#define RETURN_1 0x03f
+#define SEND_WDTR 0x80
+#define SEND_SDTR 0x60
+#define SEND_SENSE 0x40
+#define SEND_REJ 0x20
+#define SCB_PAGEDIN 0x10
+
+#define SIGSTATE 0x040
+
+#define DMAPARAMS 0x041 /* Parameters for DMA Logic */
+
+#define SG_COUNT 0x042
+#define SG_NEXT 0x043 /* working value of SG pointer */
+#define SG_NEXT0 0x043
+#define SG_NEXT1 0x044
+#define SG_NEXT2 0x045
+#define SG_NEXT3 0x046
+
+#define SCBCOUNT 0x047 /*
+ * Number of SCBs supported by
+ * this card.
+ */
+#define COMP_SCBCOUNT 0x048 /*
+ * Two's compliment of SCBCOUNT
+ */
+#define QCNTMASK 0x049 /*
+ * Mask of bits to test against
+ * when looking at the Queue Count
+ * registers. Works around a bug
+ * on aic7850 chips.
+ */
+#define FLAGS 0x04a
+#define SINGLE_BUS 0x00
+#define TWIN_BUS 0x01
+#define WIDE_BUS 0x02
+#define PAGESCBS 0x04
+#define DPHASE 0x10
+#define SELECTED 0x20
+#define IDENTIFY_SEEN 0x40
+#define RESELECTED 0x80
+
+#define SAVED_TCL 0x04b /*
+ * Temporary storage for the
+ * target/channel/lun of a
+ * reconnecting target
+ */
+#define ACTIVE_A 0x04c
+#define ACTIVE_B 0x04d
+#define WAITING_SCBH 0x04e /*
+ * head of list of SCBs awaiting
+ * selection
+ */
+#define DISCONNECTED_SCBH 0x04f /*
+ * head of list of SCBs that are
+ * disconnected. Used for SCB
+ * paging.
+ */
+#define SCB_LIST_NULL 0xff
+
+#define SAVED_LINKPTR 0x050
+#define SAVED_SCBPTR 0x051
+
+#define SCSICONF 0x05a
+#define HOSTCONF 0x05d
+
+#define HA_274_BIOSCTRL 0x05f
+#define BIOSMODE 0x30
+#define BIOSDISABLED 0x30
+
+/* Message codes */
+#define MSG_EXTENDED 0x01
+#define MSG_SDTR 0x01
+#define MSG_WDTR 0x03
+#define MSG_SDPTRS 0x02
+#define MSG_RDPTRS 0x03
+#define MSG_DISCONNECT 0x04
+#define MSG_INITIATOR_DET_ERROR 0x05
+#define MSG_ABORT 0x06
+#define MSG_REJECT 0x07
+#define MSG_NOP 0x08
+#define MSG_MSG_PARITY_ERROR 0x09
+#define MSG_BUS_DEVICE_RESET 0x0c
+#define MSG_ABORT_TAG 0x0d
+#define MSG_SIMPLE_TAG 0x20
+#define MSG_IDENTIFY 0x80
+
+/* WDTR Message values */
+#define BUS_8_BIT 0x00
+#define BUS_16_BIT 0x01
+#define BUS_32_BIT 0x02
+
+#define MAX_OFFSET_8BIT 0x0f
+#define MAX_OFFSET_16BIT 0x08
-/* $NetBSD: aic7870.c,v 1.8 1996/03/17 00:55:23 thorpej Exp $ */
-
/*
* Product specific probe and attach routines for:
- * 294X and aic7870 motherboard SCSI controllers
+ * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers
*
- * Copyright (c) 1995 Justin T. Gibbs
+ * Copyright (c) 1995, 1996 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. Absolutely no warranty of function or purpose is made by the author
- * Justin T. Gibbs.
- * 4. Modifications may be freely made to this file if the above conditions
- * are met.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: aic7870.c,v 1.8 1996/05/05 12:42:41 deraadt Exp $
*/
+#if defined(__FreeBSD__)
+#include <pci.h>
+#endif
+#if NPCI > 0 || defined(__NetBSD__)
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
+#include <sys/queue.h>
+#if defined(__NetBSD__)
#include <sys/device.h>
+#if NetBSD1_1 < 3
+#include <machine/pio.h>
+#else
+#include <machine/bus.h>
+#ifdef __alpha__
+#include <machine/intr.h>
+#endif
+#endif
+#endif /* defined(__NetBSD__) */
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
+#if defined(__FreeBSD__)
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#include <machine/clock.h>
+
+#include <i386/scsi/aic7xxx.h>
+#include <i386/scsi/93cx6.h>
+
+#include <dev/aic7xxx/aic7xxx_reg.h>
+
+#define PCI_BASEADR0 PCI_MAP_REG_START
+
+#elif defined(__NetBSD__)
+
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
-#include <dev/pci/pcidevs.h>
#include <dev/ic/aic7xxxvar.h>
+#include <dev/ic/93cx6.h>
+
+#include <dev/microcode/aic7xxx/aic7xxx_reg.h>
+
+#define bootverbose 1
+#if NetBSD1_1 < 3
+#define PCI_BASEADR0 PCI_MAP_REG_START
+#else
+#define PCI_BASEADR0 PCI_MAPREG_START
+#endif
+
+#endif /* defined(__NetBSD__) */
+
+#define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul
+#define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul
+#define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul
+#define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul
+#define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul
+#define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul
+#define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul
+#define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul
+#define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul
+#define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul
+#define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul
+#define DEVCONFIG 0x40
+#define MPORTMODE 0x00000400ul /* aic7870 only */
+#define RAMPSM 0x00000200ul /* aic7870 only */
+#define VOLSENSE 0x00000100ul
+#define SCBRAMSEL 0x00000080ul
+#define MRDCEN 0x00000040ul
+#define EXTSCBTIME 0x00000020ul /* aic7870 only */
+#define EXTSCBPEN 0x00000010ul /* aic7870 only */
+#define BERREN 0x00000008ul
+#define DACEN 0x00000004ul
+#define STPWLEVEL 0x00000002ul
+#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
-#define PCI_BASEADR0 PCI_MAPREG_START
-#define PCI_VENDORID(x) ((x) & 0xFFFF)
-#define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
+#define CSIZE_LATTIME 0x0c
+#define CACHESIZE 0x0000003ful /* only 5 bits */
+#define LATTIME 0x0000ff00ul
-static int aic7870_probe __P((struct device *, void *, void *));
-static void aic7870_attach __P((struct device *, struct device *, void *));
+/*
+ * Define the format of the aic78X0 SEEPROM registers (16 bits).
+ *
+ */
+
+struct seeprom_config {
+
+/*
+ * SCSI ID Configuration Flags
+ */
+#define CFXFER 0x0007 /* synchronous transfer rate */
+#define CFSYNCH 0x0008 /* enable synchronous transfer */
+#define CFDISC 0x0010 /* enable disconnection */
+#define CFWIDEB 0x0020 /* wide bus device */
+/* UNUSED 0x00C0 */
+#define CFSTART 0x0100 /* send start unit SCSI command */
+#define CFINCBIOS 0x0200 /* include in BIOS scan */
+#define CFRNFOUND 0x0400 /* report even if not found */
+/* UNUSED 0xf800 */
+ unsigned short device_flags[16]; /* words 0-15 */
+/*
+ * BIOS Control Bits
+ */
+#define CFSUPREM 0x0001 /* support all removeable drives */
+#define CFSUPREMB 0x0002 /* support removeable drives for boot only */
+#define CFBIOSEN 0x0004 /* BIOS enabled */
+/* UNUSED 0x0008 */
+#define CFSM2DRV 0x0010 /* support more than two drives */
+/* UNUSED 0x0060 */
+#define CFEXTEND 0x0080 /* extended translation enabled */
+/* UNUSED 0xff00 */
+ unsigned short bios_control; /* word 16 */
+
+/*
+ * Host Adapter Control Bits
+ */
+/* UNUSED 0x0001 */
+#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */
+#define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */
+#define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */
+#define CFSPARITY 0x0010 /* SCSI parity */
+/* UNUSED 0x0020 */
+#define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */
+/* UNUSED 0xff80 */
+ unsigned short adapter_control; /* word 17 */
+
+/*
+ * Bus Release, Host Adapter ID
+ */
+#define CFSCSIID 0x000f /* host adapter SCSI ID */
+/* UNUSED 0x00f0 */
+#define CFBRTIME 0xff00 /* bus release time */
+ unsigned short brtime_id; /* word 18 */
+
+/*
+ * Maximum targets
+ */
+#define CFMAXTARG 0x00ff /* maximum targets */
+/* UNUSED 0xff00 */
+ unsigned short max_targets; /* word 19 */
+
+ unsigned short res_1[11]; /* words 20-30 */
+ unsigned short checksum; /* word 31 */
+
+};
+
+static int load_seeprom __P((struct ahc_data *ahc));
+static int acquire_seeprom __P((u_long offset, u_short CS, u_short CK,
+ u_short DO, u_short DI, u_short RDY,
+ u_short MS));
+static void release_seeprom __P((u_long offset, u_short CS, u_short CK,
+ u_short DO, u_short DI, u_short RDY,
+ u_short MS));
+
+static u_char aic3940_count;
+
+#if defined(__FreeBSD__)
+
+static char* aic7870_probe __P((pcici_t tag, pcidi_t type));
+static void aic7870_attach __P((pcici_t config_id, int unit));
+
+static struct pci_device ahc_pci_driver = {
+ "ahc",
+ aic7870_probe,
+ aic7870_attach,
+ &ahc_unit,
+ NULL
+};
+
+DATA_SET (pcidevice_set, ahc_pci_driver);
+
+static char*
+aic7870_probe (pcici_t tag, pcidi_t type)
+{
+ switch(type) {
+ case PCI_DEVICE_ID_ADAPTEC_3940U:
+ return ("Adaptec 3940 Ultra SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_3940:
+ return ("Adaptec 3940 SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_2944U:
+ return ("Adaptec 2944 Ultra SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_2940U:
+ return ("Adaptec 2940 Ultra SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_2944:
+ return ("Adaptec 2944 SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_2940:
+ return ("Adaptec 2940 SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7880:
+ return ("Adaptec aic7880 Ultra SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7870:
+ return ("Adaptec aic7870 SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7860:
+ return ("Adaptec aic7860 SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7855:
+ return ("Adaptec aic7855 SCSI host adapter");
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7850:
+ return ("Adaptec aic7850 SCSI host adapter");
+ break;
+ default:
+ break;
+ }
+ return (0);
+
+}
+
+#elif defined(__NetBSD__)
+
+int aic7870_probe __P((struct device *, void *, void *));
+void aic7870_attach __P((struct device *, struct device *, void *));
+
+#if NetBSD1_1 < 3
+struct cfdriver ahccd = {
+ NULL, "ahc", aic7870_probe, aic7870_attach, DV_DULL,
+ sizeof(struct ahc_data)
+};
+#else
struct cfattach ahc_ca = {
- sizeof(struct ahc_softc), aic7870_probe, aic7870_attach
+ sizeof(struct ahc_data), aic7870_probe, aic7870_attach
};
struct cfdriver ahc_cd = {
NULL, "ahc", DV_DULL
};
-
-int ahcintr __P((void *));
-
+#endif
int
aic7870_probe(parent, match, aux)
{
struct pci_attach_args *pa = aux;
- if (PCI_VENDORID(pa->pa_id) != PCI_VENDOR_ADP)
- return 0;
-
- switch (PCI_CHIPID(pa->pa_id)) {
- case PCI_PRODUCT_ADP_AIC7870:
- case PCI_PRODUCT_ADP_2940:
- case PCI_PRODUCT_ADP_2940U:
+ switch (pa->pa_id) {
+ case PCI_DEVICE_ID_ADAPTEC_3940U:
+ case PCI_DEVICE_ID_ADAPTEC_2944U:
+ case PCI_DEVICE_ID_ADAPTEC_2940U:
+ case PCI_DEVICE_ID_ADAPTEC_3940:
+ case PCI_DEVICE_ID_ADAPTEC_2944:
+ case PCI_DEVICE_ID_ADAPTEC_2940:
+ case PCI_DEVICE_ID_ADAPTEC_AIC7880:
+ case PCI_DEVICE_ID_ADAPTEC_AIC7870:
+ case PCI_DEVICE_ID_ADAPTEC_AIC7860:
+ case PCI_DEVICE_ID_ADAPTEC_AIC7855:
+ case PCI_DEVICE_ID_ADAPTEC_AIC7850:
return 1;
- default:
- return 0;
}
+ return 0;
}
+#endif /* defined(__NetBSD__) */
+#if defined(__FreeBSD__)
+static void
+aic7870_attach(config_id, unit)
+ pcici_t config_id;
+ int unit;
+#elif defined(__NetBSD__)
void
aic7870_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
-{
- struct pci_attach_args *pa = aux;
- struct ahc_softc *ahc = (void *)self;
- int iobase;
-
- switch (PCI_CHIPID(pa->pa_id)) {
- case PCI_PRODUCT_ADP_AIC7870:
- ahc->type = AHC_AIC7870;
- break;
-
- case PCI_PRODUCT_ADP_2940:
- case PCI_PRODUCT_ADP_2940U:
- ahc->type = AHC_294;
- break;
- }
+#endif
+{
+#if defined(__FreeBSD__)
+ u_long io_port;
+#elif defined(__NetBSD__)
+ struct pci_attach_args *pa = aux;
+ struct ahc_data *ahc = (void *)self;
+ int unit = ahc->sc_dev.dv_unit;
+#if NetBSD1_1 < 3
+ pcitag_t config_id = pa->pa_tag;
+ u_long io_port;
+#else
+ bus_io_addr_t iobase;
+ bus_io_size_t iosize;
+ bus_io_handle_t ioh;
+ pci_intr_handle_t ih;
+ const char *intrstr;
+#endif
+#endif
+ u_long id;
+ unsigned opri = 0;
+ ahc_type ahc_t = AHC_NONE;
+ ahc_flag ahc_f = AHC_FNONE;
+#if defined(__FreeBSD__)
+ struct ahc_data *ahc;
+#endif
- if (pci_map_io(pa->pa_tag, PCI_BASEADR0, &iobase))
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+ if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0)))
return;
+ /*
+ * The first bit of PCI_BASEADR0 is always
+ * set hence we mask it off.
+ */
+ io_port &= 0xfffffffe;
+#elif defined(__NetBSD__)
+ if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize))
+ return;
+ if (bus_io_map(pa->pa_bc, iobase, iosize, &ioh))
+ return;
+#endif
+
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+ switch ((id = pci_conf_read(config_id, PCI_ID_REG))) {
+#elif defined(__NetBSD__)
+ switch (id = pa->pa_id) {
+#endif
+ case PCI_DEVICE_ID_ADAPTEC_3940U:
+ case PCI_DEVICE_ID_ADAPTEC_3940:
+ if (id == PCI_DEVICE_ID_ADAPTEC_3940U)
+ ahc_t = AHC_394U;
+ else
+ ahc_t = AHC_394;
+ aic3940_count++;
+ if(!(aic3940_count & 0x01))
+ /* Even count implies second channel */
+ ahc_f |= AHC_CHNLB;
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_2944U:
+ case PCI_DEVICE_ID_ADAPTEC_2940U:
+ ahc_t = AHC_294U;
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_2944:
+ case PCI_DEVICE_ID_ADAPTEC_2940:
+ ahc_t = AHC_294;
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7880:
+ ahc_t = AHC_AIC7880;
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7870:
+ ahc_t = AHC_AIC7870;
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7860:
+ ahc_t = AHC_AIC7860;
+ break;
+ case PCI_DEVICE_ID_ADAPTEC_AIC7855:
+ case PCI_DEVICE_ID_ADAPTEC_AIC7850:
+ ahc_t = AHC_AIC7850;
+ break;
+ default:
+ break;
+ }
+
+ /* On all PCI adapters, we allow SCB paging */
+ ahc_f |= AHC_PAGESCBS;
+
+#if defined(__FreeBSD__)
+ ahc_reset(io_port);
+#elif defined(__NetBSD__)
+ printf("\n");
+#if NetBSD1_1 < 3
+ ahc_reset(ahc->sc_dev.dv_xname, 0, io_port);
+#else
+ ahc_reset(ahc->sc_dev.dv_xname, pa->pa_bc, ioh);
+#endif
+#endif
+
+ if(ahc_t & AHC_AIC7870){
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+ u_long devconfig = pci_conf_read(config_id, DEVCONFIG);
+#elif defined(__NetBSD__)
+ u_long devconfig =
+ pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
+#endif
+
+ if(devconfig & (RAMPSM)) {
+ /*
+ * External SRAM present. Have the probe walk
+ * the SCBs to see how much SRAM we have and set
+ * the number of SCBs accordingly. We have to
+ * turn off SCBRAMSEL to access the external
+ * SCB SRAM.
+ *
+ * It seems that early versions of the aic7870
+ * didn't use these bits, hence the hack for the
+ * 3940 above. I would guess that recent 3940s
+ * using later aic7870 or aic7880 chips do
+ * actually set RAMPSM.
+ *
+ * The documentation isn't clear, but it sounds
+ * like the value written to devconfig must not
+ * have RAMPSM set. The second sixteen bits of
+ * the register are R/O anyway, so it shouldn't
+ * affect RAMPSM either way.
+ */
+ devconfig &= ~(RAMPSM|SCBRAMSEL);
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+ pci_conf_write(config_id, DEVCONFIG, devconfig);
+#elif defined(__NetBSD__)
+ pci_conf_write(pa->pa_bc, pa->pa_tag,
+ DEVCONFIG, devconfig);
+#endif
+ }
+ }
/*
- * Make the offsets the same as for EISA
+ * Ensure that we are using good values for the PCI burst size
+ * and latency timer.
*/
- iobase -= 0xc00ul;
+ {
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+ u_long csize_lattime = pci_conf_read(config_id, CSIZE_LATTIME);
+#elif defined(__NetBSD__)
+ u_long csize_lattime =
+ pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME);
+#endif
+
+ if((csize_lattime & CACHESIZE) == 0) {
+ /* default to 8DWDs. What's the PCI define for this? */
+ csize_lattime |= 8;
+ }
+ if((csize_lattime & LATTIME) == 0) {
+ /* Default to 64 PCLKS (is this a good value?) */
+ /* This may also be availble in the SEEPROM?? */
+ csize_lattime |= (64 << 8);
+ }
+ if(bootverbose)
+ printf("ahc%d: BurstLen = %ldDWDs, "
+ "Latency Timer = %ldPCLKS\n",
+ unit,
+ csize_lattime & CACHESIZE,
+ (csize_lattime >> 8) & 0xff);
+#if defined(__FreeBSD__) || NetBSD1_1 < 3
+ pci_conf_write(config_id, CSIZE_LATTIME, csize_lattime);
+#elif defined(__NetBSD__)
+ pci_conf_write(pa->pa_bc, pa->pa_tag, CSIZE_LATTIME,
+ csize_lattime);
+#endif
+ }
+
+#if defined(__FreeBSD__)
+ if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f)))
+ return; /* XXX PCI code should take return status */
- if (ahcprobe(ahc, iobase) == 0)
+ if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) {
+ ahc_free(ahc);
return;
+ }
+#elif defined(__NetBSD__)
+#if NetBSD1_1 < 3
+ ahc_construct(ahc, unit, 0, io_port, ahc_t, ahc_f);
+ ahc->sc_ih = pci_map_int(pa->pa_tag, PCI_IPL_BIO, ahc_intr, ahc);
+#else
+ ahc_construct(ahc, unit, pa->pa_bc, ioh, ahc_t, ahc_f);
+
+ if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
+ pa->pa_intrline, &ih)) {
+ printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname);
+ ahc_free(ahc);
+ return;
+ }
+ intrstr = pci_intr_string(pa->pa_pc, ih);
+#ifdef __OpenBSD__
+ ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc,
+ ahc->sc_dev.dv_xname);
+#else
+ ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc);
+#endif
+ if (ahc->sc_ih == NULL) {
+ printf("%s: couldn't establish interrupt",
+ ahc->sc_dev.dv_xname);
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ ahc_free(ahc);
+ return;
+ }
+ if (intrstr != NULL)
+ printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname,
+ intrstr);
+#endif
+#endif
+ /*
+ * Protect ourself from spurrious interrupts during
+ * intialization.
+ */
+ opri = splbio();
+
+ /*
+ * Do aic7870/aic7880/aic7850 specific initialization
+ */
+ {
+ u_char sblkctl;
+ char *id_string;
+
+ switch(ahc->type) {
+ case AHC_394U:
+ case AHC_294U:
+ case AHC_AIC7880:
+ {
+ id_string = "aic7880 ";
+ load_seeprom(ahc);
+ break;
+ }
+ case AHC_394:
+ case AHC_294:
+ case AHC_AIC7870:
+ {
+ id_string = "aic7870 ";
+ load_seeprom(ahc);
+ break;
+ }
+ case AHC_AIC7860:
+ {
+ id_string = "aic7860 ";
+ /* Assume there is no BIOS for these cards? */
+ ahc->flags |= AHC_USEDEFAULTS;
+ break;
+ }
+ case AHC_AIC7850:
+ {
+ id_string = "aic7850 ";
+ /* Assume there is no BIOS for these cards? */
+ ahc->flags |= AHC_USEDEFAULTS;
+ break;
+ }
+ default:
+ {
+ printf("ahc: Unknown controller type. Ignoring.\n");
+ ahc_free(ahc);
+ splx(opri);
+ return;
+ }
+ }
+
+ printf("ahc%d: %s", unit, id_string);
- ahcattach(ahc);
+ /*
+ * Take the LED out of diagnostic mode
+ */
+ sblkctl = AHC_INB(ahc, SBLKCTL);
+ AHC_OUTB(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
- ahc->sc_ih = pci_map_int(pa->pa_tag, IPL_BIO, ahcintr, ahc);
+ /*
+ * I don't know where this is set in the SEEPROM or by the
+ * BIOS, so we default to 100%.
+ */
+ AHC_OUTB(ahc, DSPCISTATUS, DFTHRSH_100);
+
+ if(ahc->flags & AHC_USEDEFAULTS) {
+ /*
+ * PCI Adapter default setup
+ * Should only be used if the adapter does not have
+ * an SEEPROM and we don't think a BIOS was installed.
+ */
+ /* Set the host ID */
+ AHC_OUTB(ahc, SCSICONF, 7);
+ /* In case we are a wide card */
+ AHC_OUTB(ahc, SCSICONF + 1, 7);
+ }
+ }
+
+ if(ahc_init(ahc)){
+ ahc_free(ahc);
+ splx(opri);
+ return; /* XXX PCI code should take return status */
+ }
+ splx(opri);
+
+ ahc_attach(ahc);
+ return;
}
+
+/*
+ * Read the SEEPROM. Return 0 on failure
+ */
+int
+load_seeprom(ahc)
+ struct ahc_data *ahc;
+{
+ struct seeprom_config sc;
+ u_short *scarray = (u_short *)≻
+ u_short checksum = 0;
+ u_long iobase = ahc->baseport;
+ u_char scsi_conf;
+ u_char host_id;
+ int have_seeprom, retval;
+
+ if(bootverbose)
+ printf("ahc%d: Reading SEEPROM...", ahc->unit);
+ have_seeprom = acquire_seeprom(iobase + SEECTL, SEECS,
+ SEECK, SEEDO, SEEDI, SEERDY, SEEMS);
+ if (have_seeprom) {
+ have_seeprom = read_seeprom(iobase + SEECTL,
+ (u_short *)&sc,
+ ahc->flags & AHC_CHNLB,
+ sizeof(sc)/2, SEECS, SEECK, SEEDO,
+ SEEDI, SEERDY, SEEMS);
+ release_seeprom(iobase + SEECTL, SEECS, SEECK, SEEDO,
+ SEEDI, SEERDY, SEEMS);
+ if (have_seeprom) {
+ /* Check checksum */
+ int i;
+
+ for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1)
+ checksum = checksum + scarray[i];
+ if (checksum != sc.checksum) {
+ printf ("checksum error");
+ have_seeprom = 0;
+ }
+ else if(bootverbose)
+ printf("done.\n");
+ }
+ }
+ if (!have_seeprom) {
+ printf("\nahc%d: SEEPROM read failed, "
+ "using leftover BIOS values\n", ahc->unit);
+ retval = 0;
+
+ host_id = 0x7;
+ scsi_conf = host_id | ENSPCHK; /* Assume a default */
+ /*
+ * If we happen to be an ULTRA card,
+ * default to non-ultra mode.
+ */
+ ahc->type &= ~AHC_ULTRA;
+ }
+ else {
+ /*
+ * Put the data we've collected down into SRAM
+ * where ahc_init will find it.
+ */
+ int i;
+ int max_targ = sc.max_targets & CFMAXTARG;
+
+ for(i = 0; i <= max_targ; i++){
+ u_char target_settings;
+ target_settings = (sc.device_flags[i] & CFXFER) << 4;
+ if (sc.device_flags[i] & CFSYNCH)
+ target_settings |= SOFS;
+ if (sc.device_flags[i] & CFWIDEB)
+ target_settings |= WIDEXFER;
+ if (sc.device_flags[i] & CFDISC)
+ ahc->discenable |= (0x01 << i);
+ outb(TARG_SCRATCH+i+iobase, target_settings);
+ }
+ outb(DISC_DSB + iobase, ~(ahc->discenable & 0xff));
+ outb(DISC_DSB + iobase + 1, ~((ahc->discenable >> 8) & 0xff));
+
+ host_id = sc.brtime_id & CFSCSIID;
+
+ scsi_conf = (host_id & 0x7);
+ if(sc.adapter_control & CFSPARITY)
+ scsi_conf |= ENSPCHK;
+
+ if(ahc->type & AHC_ULTRA) {
+ /* Should we enable Ultra mode? */
+ if(!(sc.adapter_control & CFULTRAEN))
+ /* Treat us as a non-ultra card */
+ ahc->type &= ~AHC_ULTRA;
+ }
+ retval = 1;
+ }
+ /* Set the host ID */
+ outb(SCSICONF + iobase, scsi_conf);
+ /* In case we are a wide card */
+ outb(SCSICONF + 1 + iobase, host_id);
+
+ return(retval);
+}
+
+static int
+acquire_seeprom(offset, CS, CK, DO, DI, RDY, MS)
+ u_long offset;
+ u_short CS; /* chip select */
+ u_short CK; /* clock */
+ u_short DO; /* data out */
+ u_short DI; /* data in */
+ u_short RDY; /* ready */
+ u_short MS; /* mode select */
+{
+ int wait;
+ /*
+ * Request access of the memory port. When access is
+ * granted, SEERDY will go high. We use a 1 second
+ * timeout which should be near 1 second more than
+ * is needed. Reason: after the chip reset, there
+ * should be no contention.
+ */
+ outb(offset, MS);
+ wait = 1000; /* 1 second timeout in msec */
+ while (--wait && ((inb(offset) & RDY) == 0)) {
+ DELAY (1000); /* delay 1 msec */
+ }
+ if ((inb(offset) & RDY) == 0) {
+ outb (offset, 0);
+ return (0);
+ }
+ return(1);
+}
+
+static void
+release_seeprom(offset, CS, CK, DO, DI, RDY, MS)
+ u_long offset;
+ u_short CS; /* chip select */
+ u_short CK; /* clock */
+ u_short DO; /* data out */
+ u_short DI; /* data in */
+ u_short RDY; /* ready */
+ u_short MS; /* mode select */
+{
+ /* Release access to the memory port and the serial EEPROM. */
+ outb(offset, 0);
+}
+
+#endif /* NPCI > 0 */
projects / openbsd / commitdiff