Replace a bunch of (1 << 31) with (1U << 31)

diff --git a/sys/arch/amd64/amd64/vmm_machdep.c b/sys/arch/amd64/amd64/vmm_machdep.c
index 24a376a..352126d 100644 (file)
--- a/sys/arch/amd64/amd64/vmm_machdep.c
+++ b/sys/arch/amd64/amd64/vmm_machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: vmm_machdep.c,v 1.4 2023/07/10 03:32:10 guenther Exp $ */
+/* $OpenBSD: vmm_machdep.c,v 1.5 2023/08/15 08:27:29 miod Exp $ */
 /*
  * Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
  *
@@ -6447,7 +6447,7 @@ vcpu_run_svm(struct vcpu *vcpu, struct vm_run_params *vrp)
                /* Handle vmd(8) injected interrupts */
                /* Is there an interrupt pending injection? */
                if (irq != 0xFFFF && vcpu->vc_irqready) {
-                       vmcb->v_eventinj = (irq & 0xFF) | (1 << 31);
+                       vmcb->v_eventinj = (irq & 0xFF) | (1U << 31);
                        irq = 0xFFFF;
                }
 
@@ -6467,7 +6467,7 @@ vcpu_run_svm(struct vcpu *vcpu, struct vm_run_params *vrp)
                                case VMM_EX_AC:
                                        vmcb->v_eventinj |= (1ULL << 11);
                        }
-                       vmcb->v_eventinj |= (vcpu->vc_event) | (1 << 31);
+                       vmcb->v_eventinj |= (vcpu->vc_event) | (1U << 31);
                        vmcb->v_eventinj |= (3ULL << 8); /* Exception */
                        vcpu->vc_event = 0;
                }

diff --git a/sys/dev/acpi/tpm.c b/sys/dev/acpi/tpm.c
index 518b087..a00368c 100644 (file)
--- a/sys/dev/acpi/tpm.c
+++ b/sys/dev/acpi/tpm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: tpm.c,v 1.17 2022/04/06 18:59:27 naddy Exp $ */
+/* $OpenBSD: tpm.c,v 1.18 2023/08/15 08:27:29 miod Exp $ */
 
 /*
  * Minimal interface to Trusted Platform Module chips implementing the
@@ -150,7 +150,7 @@
 #define TPM_CRB_CTRL_CANCEL_CLEAR      0x0
 
 #define TPM_CRB_CTRL_START_CMD         (1 << 0)
-#define TPM_CRB_INT_ENABLED_BIT                (1 << 31)
+#define TPM_CRB_INT_ENABLED_BIT                (1U << 31)
 
 #define TPM2_RC_SUCCESS                        0x0000
 #define TPM2_RC_INITIALIZE             0x0100

diff --git a/sys/dev/fdt/amlclock.c b/sys/dev/fdt/amlclock.c
index e07792d..46980c6 100644 (file)
--- a/sys/dev/fdt/amlclock.c
+++ b/sys/dev/fdt/amlclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: amlclock.c,v 1.14 2022/06/28 23:43:12 naddy Exp $     */
+/*     $OpenBSD: amlclock.c,v 1.15 2023/08/15 08:27:29 miod Exp $      */
 /*
  * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -89,7 +89,7 @@
 #define HHI_NAND_CLK_CNTL      0x97
 #define HHI_SD_EMMC_CLK_CNTL   0x99
 #define HHI_SYS_PLL_CNTL0      0xbd
-#define  HHI_SYS_DPLL_LOCK     (1 << 31)
+#define  HHI_SYS_DPLL_LOCK     (1U << 31)
 #define  HHI_SYS_DPLL_RESET    (1 << 29)
 #define  HHI_SYS_DPLL_EN       (1 << 28)
 #define  HHI_SYS_DPLL_OD(x)    (((x) >> 16) & 0x7)

diff --git a/sys/dev/fdt/if_cad.c b/sys/dev/fdt/if_cad.c
index dfc2735..7e20c9f 100644 (file)
--- a/sys/dev/fdt/if_cad.c
+++ b/sys/dev/fdt/if_cad.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: if_cad.c,v 1.12 2022/08/14 21:10:08 jca Exp $ */
+/*     $OpenBSD: if_cad.c,v 1.13 2023/08/15 08:27:30 miod Exp $        */
 
 /*
  * Copyright (c) 2021-2022 Visa Hankala
@@ -220,7 +220,7 @@ struct cad_desc64 {
 #define GEM_RXD_ADDR_WRAP      (1 << 1)
 #define GEM_RXD_ADDR_USED      (1 << 0)
 
-#define GEM_RXD_BCAST          (1 << 31)
+#define GEM_RXD_BCAST          (1U << 31)
 #define GEM_RXD_MCAST          (1 << 30)
 #define GEM_RXD_UCAST          (1 << 29)
 #define GEM_RXD_SPEC           (1 << 27)
@@ -237,7 +237,7 @@ struct cad_desc64 {
 #define GEM_RXD_BADFCS         (1 << 13)
 #define GEM_RXD_LEN_MASK       0x1fff
 
-#define GEM_TXD_USED           (1 << 31)
+#define GEM_TXD_USED           (1U << 31)
 #define GEM_TXD_WRAP           (1 << 30)
 #define GEM_TXD_RLIMIT         (1 << 29)
 #define GEM_TXD_CORRUPT                (1 << 27)

diff --git a/sys/dev/fdt/if_dwge.c b/sys/dev/fdt/if_dwge.c
index ccd298e..4ec1331 100644 (file)
--- a/sys/dev/fdt/if_dwge.c
+++ b/sys/dev/fdt/if_dwge.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: if_dwge.c,v 1.18 2023/07/06 08:32:37 jmatthew Exp $   */
+/*     $OpenBSD: if_dwge.c,v 1.19 2023/08/15 08:27:30 miod Exp $       */
 /*
  * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
  * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se>
@@ -194,7 +194,7 @@ struct dwge_desc {
 #define TDES0_PCE              (1 << 12)
 #define TDES0_JT               (1 << 14)
 #define TDES0_IHE              (1 << 16)
-#define TDES0_OWN              (1 << 31)
+#define TDES0_OWN              (1U << 31)
 
 #define ETDES0_TCH             (1 << 20)
 #define ETDES0_FS              (1 << 28)
@@ -217,7 +217,7 @@ struct dwge_desc {
 #define RDES0_FL_MASK          0x3fff
 #define RDES0_FL_SHIFT         16
 #define RDES0_AFM              (1 << 30)
-#define RDES0_OWN              (1 << 31)
+#define RDES0_OWN              (1U << 31)
 
 /* Tx size bits */
 #define TDES1_TBS1             (0xfff << 0)
@@ -229,12 +229,12 @@ struct dwge_desc {
 #define TDES1_CIC_FULL         (3 << 27)
 #define TDES1_FS               (1 << 29)
 #define TDES1_LS               (1 << 30)
-#define TDES1_IC               (1 << 31)
+#define TDES1_IC               (1U << 31)
 
 /* Rx size bits */
 #define RDES1_RBS1             (0xfff << 0)
 #define RDES1_RCH              (1 << 24)
-#define RDES1_DIC              (1 << 31)
+#define RDES1_DIC              (1U << 31)
 
 #define ERDES1_RCH             (1 << 14)
 

diff --git a/sys/dev/fdt/if_dwxe.c b/sys/dev/fdt/if_dwxe.c
index 430459d..6f3e1af 100644 (file)
--- a/sys/dev/fdt/if_dwxe.c
+++ b/sys/dev/fdt/if_dwxe.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: if_dwxe.c,v 1.21 2022/07/09 20:51:39 kettenis Exp $   */
+/*     $OpenBSD: if_dwxe.c,v 1.22 2023/08/15 08:27:30 miod Exp $       */
 /*
  * Copyright (c) 2008 Mark Kettenis
  * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se>
@@ -184,7 +184,7 @@ struct dwxe_desc {
 #define DWXE_TX_PAYLOAD_ERR            (1 << 12)
 #define DWXE_TX_LENGTH_ERR             (1 << 14)
 #define DWXE_TX_HEADER_ERR             (1 << 16)
-#define DWXE_TX_DESC_CTL               (1 << 31)
+#define DWXE_TX_DESC_CTL               (1U << 31)
 
 /* Rx status bits */
 #define DWXE_RX_PAYLOAD_ERR            (1 << 0)
@@ -202,7 +202,7 @@ struct dwxe_desc {
 #define DWXE_RX_FRM_LEN_MASK           0x3fff
 #define DWXE_RX_FRM_LEN_SHIFT          16
 #define DWXE_RX_DAF_FAIL               (1 << 30)
-#define DWXE_RX_DESC_CTL               (1 << 31)
+#define DWXE_RX_DESC_CTL               (1U << 31)
 
 /* Tx size bits */
 #define DWXE_TX_BUF_SIZE               (0xfff << 0)
@@ -213,11 +213,11 @@ struct dwxe_desc {
 #define DWXE_TX_CHECKSUM_CTL_FULL      (3 << 27)
 #define DWXE_TX_FIR_DESC               (1 << 29)
 #define DWXE_TX_LAST_DESC              (1 << 30)
-#define DWXE_TX_INT_CTL                (1 << 31)
+#define DWXE_TX_INT_CTL                (1U << 31)
 
 /* Rx size bits */
 #define DWXE_RX_BUF_SIZE               (0xfff << 0)
-#define DWXE_RX_INT_CTL                (1 << 31)
+#define DWXE_RX_INT_CTL                (1U << 31)
 
 /* EMAC syscon bits */
 #define SYSCON_EMAC                    0x30

diff --git a/sys/dev/fdt/imxiomuxc.c b/sys/dev/fdt/imxiomuxc.c
index e4c19fe..dee363e 100644 (file)
--- a/sys/dev/fdt/imxiomuxc.c
+++ b/sys/dev/fdt/imxiomuxc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxiomuxc.c,v 1.7 2021/10/24 17:52:26 mpi Exp $ */
+/* $OpenBSD: imxiomuxc.c,v 1.8 2023/08/15 08:27:30 miod Exp $ */
 /*
  * Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
  * Copyright (c) 2016 Mark Kettenis <kettenis@openbsd.org>
@@ -35,7 +35,7 @@
 
 #define IOMUX_CONFIG_SION              (1 << 4)
 
-#define IMX_PINCTRL_NO_PAD_CTL         (1 << 31)
+#define IMX_PINCTRL_NO_PAD_CTL         (1U << 31)
 #define IMX_PINCTRL_SION               (1 << 30)
 
 struct imxiomuxc_softc {

diff --git a/sys/dev/fdt/mvpinctrl.c b/sys/dev/fdt/mvpinctrl.c
index f5805ce..c5d239f 100644 (file)
--- a/sys/dev/fdt/mvpinctrl.c
+++ b/sys/dev/fdt/mvpinctrl.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mvpinctrl.c,v 1.11 2022/06/28 23:43:12 naddy Exp $ */
+/* $OpenBSD: mvpinctrl.c,v 1.12 2023/08/15 08:27:30 miod Exp $ */
 /*
  * Copyright (c) 2013,2016 Patrick Wildt <patrick@blueri.se>
  * Copyright (c) 2016 Mark Kettenis <kettenis@openbsd.org>
@@ -332,7 +332,7 @@ mvpinctrl_set_pin(void *cookie, uint32_t *cells, int val)
 /* Armada 3700 XTAL block */
 
 #define XTAL                   0xc
-#define  XTAL_MODE                     (1 << 31)
+#define  XTAL_MODE                     (1U << 31)
 
 uint32_t
 a3700_xtal_get_frequency(void *cookie, uint32_t *cells)

diff --git a/sys/dev/fdt/sxiccmu.c b/sys/dev/fdt/sxiccmu.c
index 641e797..d4c2e76 100644 (file)
--- a/sys/dev/fdt/sxiccmu.c
+++ b/sys/dev/fdt/sxiccmu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: sxiccmu.c,v 1.31 2022/06/28 23:43:12 naddy Exp $      */
+/*     $OpenBSD: sxiccmu.c,v 1.32 2023/08/15 08:27:30 miod Exp $       */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -1158,7 +1158,7 @@ sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 
 /* Allwinner H3/H5 */
 #define H3_PLL_CPUX_CTRL_REG           0x0000
-#define H3_PLL_CPUX_ENABLE             (1 << 31)
+#define H3_PLL_CPUX_ENABLE             (1U << 31)
 #define H3_PLL_CPUX_LOCK               (1 << 28)
 #define H3_PLL_CPUX_OUT_EXT_DIVP(x)    (((x) >> 16) & 0x3)
 #define H3_PLL_CPUX_OUT_EXT_DIVP_MASK  (0x3 << 16)

diff --git a/sys/dev/ic/ufshcireg.h b/sys/dev/ic/ufshcireg.h
index 17e272d..18091ec 100644 (file)
--- a/sys/dev/ic/ufshcireg.h
+++ b/sys/dev/ic/ufshcireg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: ufshcireg.h,v 1.2 2023/02/17 08:01:03 jsg Exp $ */
+/*     $OpenBSD: ufshcireg.h,v 1.3 2023/08/15 08:27:30 miod Exp $ */
 
 /*
  * Copyright (c) 2022 Marcus Glocker <mglocker@openbsd.org>
@@ -119,7 +119,7 @@
 #define UFSHCI_REG_UECDME              0x48
 /* UTP Transfer Request Interrupt Aggregation Control Register */
 #define UFSHCI_REG_UTRIACR             0x4C
-#define  UFSHCI_REG_UTRIACR_IAEN       (1 << 31) /* RW */
+#define  UFSHCI_REG_UTRIACR_IAEN       (1U << 31) /* RW */
 #define  UFSHCI_REG_UTRIACR_IAPWEN     (1 << 24) /* WO */
 #define  UFSHCI_REG_UTRIACR_IASB       (1 << 20) /* RO */
 #define  UFSHCI_REG_UTRIACR_CTR                (1 << 16) /* WO */

diff --git a/sys/dev/pci/if_aq_pci.c b/sys/dev/pci/if_aq_pci.c
index 1439196..6ad899e 100644 (file)
--- a/sys/dev/pci/if_aq_pci.c
+++ b/sys/dev/pci/if_aq_pci.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_aq_pci.c,v 1.22 2023/05/02 12:32:22 kettenis Exp $ */
+/* $OpenBSD: if_aq_pci.c,v 1.23 2023/08/15 08:27:30 miod Exp $ */
 /*     $NetBSD: if_aq.c,v 1.27 2021/06/16 00:21:18 riastradh Exp $     */
 
 /*
@@ -175,7 +175,7 @@
 #define AQ_INTR_CTRL_IRQMODE_MSIX              2
 #define  AQ_INTR_CTRL_MULTIVEC                 (1 << 2)
 #define  AQ_INTR_CTRL_RESET_DIS                        (1 << 29)
-#define  AQ_INTR_CTRL_RESET_IRQ                        (1 << 31)
+#define  AQ_INTR_CTRL_RESET_IRQ                        (1U << 31)
 #define AQ_MBOXIF_POWER_GATING_CONTROL_REG     0x32a8
 
 #define FW_MPI_MBOX_ADDR_REG                   0x0360
@@ -220,12 +220,12 @@
 #define  RPF_L2UC_MSW_MACADDR_HI               0xFFFF
 #define  RPF_L2UC_MSW_ACTION                   0x70000
 #define  RPF_L2UC_MSW_TAG                      0x03c00000
-#define  RPF_L2UC_MSW_EN                       (1 << 31)
+#define  RPF_L2UC_MSW_EN                       (1U << 31)
 #define AQ_HW_MAC_NUM                          34
 
 /* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */
 #define RPF_MCAST_FILTER_REG(i)                        (0x5250 + (i) * 4)
-#define  RPF_MCAST_FILTER_EN                   (1 << 31)
+#define  RPF_MCAST_FILTER_EN                   (1U << 31)
 #define RPF_MCAST_FILTER_MASK_REG              0x5270
 #define  RPF_MCAST_FILTER_MASK_ALLMULTI                (1 << 14)
 
@@ -240,14 +240,14 @@
 
 /* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */
 #define RPF_ETHERTYPE_FILTER_REG(i)            (0x5300 + (i) * 4)
-#define  RPF_ETHERTYPE_FILTER_EN               (1 << 31)
+#define  RPF_ETHERTYPE_FILTER_EN               (1U << 31)
 
 /* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */
 #define RPF_L3_FILTER_REG(i)                   (0x5380 + (i) * 4)
-#define  RPF_L3_FILTER_L4_EN                   (1 << 31)
+#define  RPF_L3_FILTER_L4_EN                   (1U << 31)
 
 #define RX_FLR_RSS_CONTROL1_REG                        0x54c0
-#define  RX_FLR_RSS_CONTROL1_EN                        (1 << 31)
+#define  RX_FLR_RSS_CONTROL1_EN                        (1U << 31)
 
 #define RPF_RPB_RX_TC_UPT_REG                   0x54c4
 #define  RPF_RPB_RX_TC_UPT_MASK(i)              (0x00000007 << ((i) * 4))
@@ -278,7 +278,7 @@
 #define RPB_RXB_BUFSIZE_REG(i)                 (0x5710 + (i) * 0x10)
 #define  RPB_RXB_BUFSIZE                       0x1FF
 #define RPB_RXB_XOFF_REG(i)                    (0x5714 + (i) * 0x10)
-#define  RPB_RXB_XOFF_EN                       (1 << 31)
+#define  RPB_RXB_XOFF_EN                       (1U << 31)
 #define  RPB_RXB_XOFF_THRESH_HI                 0x3FFF0000
 #define  RPB_RXB_XOFF_THRESH_LO                 0x3FFF
 
@@ -301,7 +301,7 @@
 #define  RX_DMA_DESC_RESET                     (1 << 25)
 #define  RX_DMA_DESC_HEADER_SPLIT              (1 << 28)
 #define  RX_DMA_DESC_VLAN_STRIP                        (1 << 29)
-#define  RX_DMA_DESC_EN                                (1 << 31)
+#define  RX_DMA_DESC_EN                                (1U << 31)
 #define RX_DMA_DESC_HEAD_PTR_REG(i)            (0x5b0c + (i) * 0x20)
 #define  RX_DMA_DESC_HEAD_PTR                  0xFFF
 #define RX_DMA_DESC_TAIL_PTR_REG(i)            (0x5b10 + (i) * 0x20)
@@ -313,10 +313,10 @@
 #define  RX_DMA_DCAD_CPUID                     0xFF
 #define  RX_DMA_DCAD_PAYLOAD_EN                        (1 << 29)
 #define  RX_DMA_DCAD_HEADER_EN                 (1 << 30)
-#define  RX_DMA_DCAD_DESC_EN                   (1 << 31)
+#define  RX_DMA_DCAD_DESC_EN                   (1U << 31)
 
 #define RX_DMA_DCA_REG                         0x6180
-#define  RX_DMA_DCA_EN                         (1 << 31)
+#define  RX_DMA_DCA_EN                         (1U << 31)
 #define  RX_DMA_DCA_MODE                       0xF
 
 #define TX_SYSCONTROL_REG                      0x7000
@@ -328,7 +328,7 @@
 #define TPS_DESC_VM_ARB_MODE_REG               0x7300
 #define  TPS_DESC_VM_ARB_MODE                  (1 << 0)
 #define TPS_DESC_RATE_REG                      0x7310
-#define  TPS_DESC_RATE_TA_RST                  (1 << 31)
+#define  TPS_DESC_RATE_TA_RST                  (1U << 31)
 #define  TPS_DESC_RATE_LIM                     0x7FF
 #define TPS_DESC_TC_ARB_MODE_REG               0x7200
 #define  TPS_DESC_TC_ARB_MODE                  0x3
@@ -393,7 +393,7 @@
 #define  TDM_DCAD_CPUID_EN                     0x80000000
 
 #define TDM_DCA_REG                            0x8480
-#define  TDM_DCA_EN                            (1 << 31)
+#define  TDM_DCA_EN                            (1U << 31)
 #define  TDM_DCA_MODE                          0xF
 
 #define TX_INTR_MODERATION_CTL_REG(i)          (0x8980 + (i) * 4)
@@ -418,7 +418,7 @@
 #define  AQ2_MIF_BOOT_CRASH_INIT               (1 << 27)
 #define  AQ2_MIF_BOOT_BOOT_CODE_FAILED         (1 << 28)
 #define  AQ2_MIF_BOOT_FW_INIT_FAILED           (1 << 29)
-#define  AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS     (1 << 31)
+#define  AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS     (1U << 31)
 
 /* AQ2 action resolver table */
 #define AQ2_ART_ACTION_ACT_SHIFT               8

diff --git a/sys/dev/pci/if_mcx.c b/sys/dev/pci/if_mcx.c
index dd30a6b..cd6f78d 100644 (file)
--- a/sys/dev/pci/if_mcx.c
+++ b/sys/dev/pci/if_mcx.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: if_mcx.c,v 1.107 2023/06/06 01:40:04 dlg Exp $ */
+/*     $OpenBSD: if_mcx.c,v 1.108 2023/08/15 08:27:30 miod Exp $ */
 
 /*
  * Copyright (c) 2017 David Gwynne <dlg@openbsd.org>
@@ -149,8 +149,8 @@ CTASSERT(MCX_MAX_QUEUES * MCX_WQ_DOORBELL_STRIDE <
 #define MCX_CMDQ_DOORBELL              0x0018
 
 #define MCX_STATE                      0x01fc
-#define MCX_STATE_MASK                         (1 << 31)
-#define MCX_STATE_INITIALIZING                 (1 << 31)
+#define MCX_STATE_MASK                         (1U << 31)
+#define MCX_STATE_INITIALIZING                 (1U << 31)
 #define MCX_STATE_READY                                (0 << 31)
 #define MCX_STATE_INTERFACE_MASK               (0x3 << 24)
 #define MCX_STATE_INTERFACE_FULL_DRIVER                (0x0 << 24)
@@ -1405,7 +1405,7 @@ struct mcx_cmd_create_tir_mb_in {
 #define MCX_TIR_CTX_HASH_SEL_SPORT     (1 << 2)
 #define MCX_TIR_CTX_HASH_SEL_DPORT     (1 << 3)
 #define MCX_TIR_CTX_HASH_SEL_IPV4      (0 << 31)
-#define MCX_TIR_CTX_HASH_SEL_IPV6      (1 << 31)
+#define MCX_TIR_CTX_HASH_SEL_IPV6      (1U << 31)
 #define MCX_TIR_CTX_HASH_SEL_TCP       (0 << 30)
 #define MCX_TIR_CTX_HASH_SEL_UDP       (1 << 30)
        uint32_t                cmd_rx_hash_sel_inner;
@@ -1675,7 +1675,7 @@ CTASSERT(sizeof(struct mcx_wq_ctx) == 0xC0);
 
 struct mcx_sq_ctx {
        uint32_t                sq_flags;
-#define MCX_SQ_CTX_RLKEY                       (1 << 31)
+#define MCX_SQ_CTX_RLKEY                       (1U << 31)
 #define MCX_SQ_CTX_FRE_SHIFT                   (1 << 29)
 #define MCX_SQ_CTX_FLUSH_IN_ERROR              (1 << 28)
 #define MCX_SQ_CTX_MIN_WQE_INLINE_SHIFT                24
@@ -1722,7 +1722,7 @@ struct mcx_sq_entry {
        /* ethernet segment */
        uint32_t                sqe_reserved1;
        uint32_t                sqe_mss_csum;
-#define MCX_SQE_L4_CSUM                                (1 << 31)
+#define MCX_SQE_L4_CSUM                                (1U << 31)
 #define MCX_SQE_L3_CSUM                                (1 << 30)
        uint32_t                sqe_reserved2;
        uint16_t                sqe_inline_header_size;
@@ -1789,7 +1789,7 @@ struct mcx_cmd_destroy_sq_out {
 
 struct mcx_rq_ctx {
        uint32_t                rq_flags;
-#define MCX_RQ_CTX_RLKEY                       (1 << 31)
+#define MCX_RQ_CTX_RLKEY                       (1U << 31)
 #define MCX_RQ_CTX_VLAN_STRIP_DIS              (1 << 28)
 #define MCX_RQ_CTX_MEM_RQ_TYPE_SHIFT           24
 #define MCX_RQ_CTX_STATE_SHIFT                 20

diff --git a/sys/dev/pci/igc_regs.h b/sys/dev/pci/igc_regs.h
index b3d4b8e..715b4b3 100644 (file)
--- a/sys/dev/pci/igc_regs.h
+++ b/sys/dev/pci/igc_regs.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: igc_regs.h,v 1.1 2021/10/31 14:52:57 patrick Exp $    */
+/*     $OpenBSD: igc_regs.h,v 1.2 2023/08/15 08:27:30 miod Exp $       */
 /*-
  * Copyright 2021 Intel Corp
  * Copyright 2021 Rubicon Communications, LLC (Netgate)
@@ -333,7 +333,7 @@
 /* ETQF register bit definitions */
 #define IGC_ETQF_FILTER_ENABLE (1 << 26)
 #define IGC_ETQF_IMM_INT       (1 << 29)
-#define IGC_ETQF_QUEUE_ENABLE  (1 << 31)
+#define IGC_ETQF_QUEUE_ENABLE  (1U << 31)
 #define IGC_ETQF_QUEUE_SHIFT   16
 #define IGC_ETQF_QUEUE_MASK    0x00070000
 #define IGC_ETQF_ETYPE_MASK    0x0000FFFF

diff --git a/sys/dev/pci/ixgbe_type.h b/sys/dev/pci/ixgbe_type.h
index 4b4dcb7..edc569b 100644 (file)
--- a/sys/dev/pci/ixgbe_type.h
+++ b/sys/dev/pci/ixgbe_type.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: ixgbe_type.h,v 1.37 2023/05/18 08:22:37 jan Exp $     */
+/*     $OpenBSD: ixgbe_type.h,v 1.38 2023/08/15 08:27:30 miod Exp $    */
 
 /******************************************************************************
   SPDX-License-Identifier: BSD-3-Clause
@@ -4454,7 +4454,7 @@ struct ixgbe_bypass_eeprom {
 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR          (1 << 26)
 #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE              (1 << 28)
 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE           (1 << 29)
-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART          (1 << 31)
+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART          (1U << 31)
 
 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE                  (1 << 28)
 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE                  (1 << 29)
@@ -4484,7 +4484,7 @@ struct ixgbe_bypass_eeprom {
 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN     (1 << 1)
 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN      (1 << 2)
 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN             (1 << 3)
-#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN             (1 << 31)
+#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN             (1U << 31)
 
 #define IXGBE_SB_IOSF_INDIRECT_CTRL    0x00011144
 #define IXGBE_SB_IOSF_INDIRECT_DATA    0x00011148

diff --git a/sys/dev/usb/dwc2/dwc2_hw.h b/sys/dev/usb/dwc2/dwc2_hw.h
index a551c2d..1853d80 100644 (file)
--- a/sys/dev/usb/dwc2/dwc2_hw.h
+++ b/sys/dev/usb/dwc2/dwc2_hw.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: dwc2_hw.h,v 1.4 2022/09/04 08:42:40 mglocker Exp $    */
+/*     $OpenBSD: dwc2_hw.h,v 1.5 2023/08/15 08:27:30 miod Exp $        */
 /*     $NetBSD: dwc2_hw.h,v 1.2 2013/09/25 06:19:22 skrll Exp $        */
 
 /*
@@ -127,7 +127,7 @@
 #define GUSBCFG_TOUTCAL(_x)            ((_x) << 0)
 
 #define GRSTCTL                                HSOTG_REG(0x010)
-#define GRSTCTL_AHBIDLE                        (1 << 31)
+#define GRSTCTL_AHBIDLE                        (1U << 31)
 #define GRSTCTL_DMAREQ                 (1 << 30)
 #define GRSTCTL_CSFTRST_DONE           (1 << 29)
 #define GRSTCTL_TXFNUM_MASK            (0x1f << 6)
@@ -143,7 +143,7 @@
 
 #define GINTSTS                                HSOTG_REG(0x014)
 #define GINTMSK                                HSOTG_REG(0x018)
-#define GINTSTS_WKUPINT                        (1 << 31)
+#define GINTSTS_WKUPINT                        (1U << 31)
 #define GINTSTS_SESSREQINT             (1 << 30)
 #define GINTSTS_DISCONNINT             (1 << 29)
 #define GINTSTS_CONIDSTSCHNG           (1 << 28)
@@ -219,7 +219,7 @@
 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)      (((_v) >> 0) & 0xffff)
 
 #define GI2CCTL                                HSOTG_REG(0x0030)
-#define GI2CCTL_BSYDNE                 (1 << 31)
+#define GI2CCTL_BSYDNE                 (1U << 31)
 #define GI2CCTL_RW                     (1 << 30)
 #define GI2CCTL_I2CDATSE0              (1 << 28)
 #define GI2CCTL_I2CDEVADDR_MASK                (0x3 << 26)
@@ -246,7 +246,7 @@
 #define GSNPSID_ID_MASK                        0xffff0000
 
 #define GHWCFG2                                HSOTG_REG(0x0048)
-#define GHWCFG2_OTG_ENABLE_IC_USB              (1 << 31)
+#define GHWCFG2_OTG_ENABLE_IC_USB              (1U << 31)
 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK         (0x1f << 26)
 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT                26
 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK     (0x3 << 24)
@@ -307,7 +307,7 @@
 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT     0
 
 #define GHWCFG4                                HSOTG_REG(0x0050)
-#define GHWCFG4_DESC_DMA_DYN                   (1 << 31)
+#define GHWCFG4_DESC_DMA_DYN                   (1U << 31)
 #define GHWCFG4_DESC_DMA                       (1 << 30)
 #define GHWCFG4_NUM_IN_EPS_MASK                        (0xf << 26)
 #define GHWCFG4_NUM_IN_EPS_SHIFT               26
@@ -336,7 +336,7 @@
 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT      0
 
 #define GLPMCFG                                HSOTG_REG(0x0054)
-#define GLPMCFG_INVSELHSIC             (1 << 31)
+#define GLPMCFG_INVSELHSIC             (1U << 31)
 #define GLPMCFG_HSICCON                        (1 << 30)
 #define GLPMCFG_RSTRSLPSTS             (1 << 29)
 #define GLPMCFG_ENBESL                 (1 << 28)
@@ -554,7 +554,7 @@
 #define D0EPCTL_MPS_16                 2
 #define D0EPCTL_MPS_8                  3
 
-#define DXEPCTL_EPENA                  (1 << 31)
+#define DXEPCTL_EPENA                  (1U << 31)
 #define DXEPCTL_EPDIS                  (1 << 30)
 #define DXEPCTL_SETD1PID               (1 << 29)
 #define DXEPCTL_SETODDFR               (1 << 29)
@@ -652,7 +652,7 @@
 #define DTXFSTS(_a)                    HSOTG_REG(0x918 + ((_a) * 0x20))
 
 #define PCGCTL                         HSOTG_REG(0x0e00)
-#define PCGCTL_IF_DEV_MODE             (1 << 31)
+#define PCGCTL_IF_DEV_MODE             (1U << 31)
 #define PCGCTL_P2HD_PRT_SPD_MASK       (0x3 << 29)
 #define PCGCTL_P2HD_PRT_SPD_SHIFT      29
 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK  (0x3 << 27)
@@ -688,7 +688,7 @@
 /* Host Mode Registers */
 
 #define HCFG                           HSOTG_REG(0x0400)
-#define HCFG_MODECHTIMEN               (1 << 31)
+#define HCFG_MODECHTIMEN               (1U << 31)
 #define HCFG_PERSCHEDENA               (1 << 26)
 #define HCFG_FRLISTEN_MASK             (0x3 << 24)
 #define HCFG_FRLISTEN_SHIFT            24
@@ -724,7 +724,7 @@
 #define HFNUM_MAX_FRNUM                        0x3fff
 
 #define HPTXSTS                                HSOTG_REG(0x0410)
-#define TXSTS_QTOP_ODD                 (1 << 31)
+#define TXSTS_QTOP_ODD                 (1U << 31)
 #define TXSTS_QTOP_CHNEP_MASK          (0xf << 27)
 #define TXSTS_QTOP_CHNEP_SHIFT         27
 #define TXSTS_QTOP_TOKEN_MASK          (0x3 << 25)
@@ -761,7 +761,7 @@
 #define HPRT0_CONNSTS                  (1 << 0)
 
 #define HCCHAR(_ch)                    HSOTG_REG(0x0500 + 0x20 * (_ch))
-#define HCCHAR_CHENA                   (1 << 31)
+#define HCCHAR_CHENA                   (1U << 31)
 #define HCCHAR_CHDIS                   (1 << 30)
 #define HCCHAR_ODDFRM                  (1 << 29)
 #define HCCHAR_DEVADDR_MASK            (0x7f << 22)
@@ -778,7 +778,7 @@
 #define HCCHAR_MPS_SHIFT               0
 
 #define HCSPLT(_ch)                    HSOTG_REG(0x0504 + 0x20 * (_ch))
-#define HCSPLT_SPLTENA                 (1 << 31)
+#define HCSPLT_SPLTENA                 (1U << 31)
 #define HCSPLT_COMPSPLT                        (1 << 16)
 #define HCSPLT_XACTPOS_MASK            (0x3 << 14)
 #define HCSPLT_XACTPOS_SHIFT           14
@@ -810,7 +810,7 @@
 #define HCINTMSK_XFERCOMPL             (1 << 0)
 
 #define HCTSIZ(_ch)                    HSOTG_REG(0x0510 + 0x20 * (_ch))
-#define TSIZ_DOPNG                     (1 << 31)
+#define TSIZ_DOPNG                     (1U << 31)
 #define TSIZ_SC_MC_PID_MASK            (0x3 << 29)
 #define TSIZ_SC_MC_PID_SHIFT           29
 #define TSIZ_SC_MC_PID_DATA0           0
@@ -850,7 +850,7 @@ struct dwc2_dma_desc {
 
 /* Host Mode DMA descriptor status quadlet */
 
-#define HOST_DMA_A                     (1 << 31)
+#define HOST_DMA_A                     (1U << 31)
 #define HOST_DMA_STS_MASK              (0x3 << 28)
 #define HOST_DMA_STS_SHIFT             28
 #define HOST_DMA_STS_PKTERR            (1 << 28)

diff --git a/sys/dev/usb/if_urereg.h b/sys/dev/usb/if_urereg.h
index 4d61531..18aa96f 100644 (file)
--- a/sys/dev/usb/if_urereg.h
+++ b/sys/dev/usb/if_urereg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: if_urereg.h,v 1.12 2023/05/06 08:07:10 kevlo Exp $    */
+/*     $OpenBSD: if_urereg.h,v 1.13 2023/08/15 08:27:30 miod Exp $     */
 /*-
  * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
  * All rights reserved.
@@ -567,11 +567,11 @@ struct ure_rxpkt {
 
 struct ure_txpkt {
        uint32_t ure_pktlen;
-#define        URE_TXPKT_TX_FS         (1 << 31)
+#define        URE_TXPKT_TX_FS         (1U << 31)
 #define        URE_TXPKT_TX_LS         (1 << 30)
 #define        URE_TXPKT_LEN_MASK      0xffff
        uint32_t ure_vlan;
-#define        URE_TXPKT_UDP           (1 << 31)
+#define        URE_TXPKT_UDP           (1U << 31)
 #define        URE_TXPKT_TCP           (1 << 30)
 #define        URE_TXPKT_IPV4          (1 << 29)
 #define        URE_TXPKT_IPV6          (1 << 28)

diff --git a/sys/dev/wscons/wstpad.c b/sys/dev/wscons/wstpad.c
index c3735cf..3a6e310 100644 (file)
--- a/sys/dev/wscons/wstpad.c
+++ b/sys/dev/wscons/wstpad.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: wstpad.c,v 1.32 2023/07/02 21:44:04 bru Exp $ */
+/* $OpenBSD: wstpad.c,v 1.33 2023/08/15 08:27:30 miod Exp $ */
 
 /*
  * Copyright (c) 2015, 2016 Ulf Brosziewski
@@ -151,7 +151,7 @@ struct tpad_touch {
 #define WSTPAD_DISABLE         (1 << 7)
 #define WSTPAD_MTBUTTONS       (1 << 8)
 
-#define WSTPAD_MT              (1 << 31)
+#define WSTPAD_MT              (1U << 31)
 
 
 struct wstpad {

diff --git a/sys/sys/videoio.h b/sys/sys/videoio.h
index a2b69bb..32d9409 100644 (file)
--- a/sys/sys/videoio.h
+++ b/sys/sys/videoio.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: videoio.h,v 1.17 2020/11/20 05:27:29 mglocker Exp $   */
+/*     $OpenBSD: videoio.h,v 1.18 2023/08/15 08:27:30 miod Exp $       */
 /*
  *  Video for Linux Two header file
  *
@@ -1070,7 +1070,7 @@ enum v4l2_detect_md_mode {
 /*  Four-character-code (FOURCC) */
 #define v4l2_fourcc(a, b, c, d)\
        ((u_int32_t)(a) | ((u_int32_t)(b) << 8) | ((u_int32_t)(c) << 16) | ((u_int32_t)(d) << 24))
-#define v4l2_fourcc_be(a, b, c, d)     (v4l2_fourcc(a, b, c, d) | (1 << 31))
+#define v4l2_fourcc_be(a, b, c, d)     (v4l2_fourcc(a, b, c, d) | (1U << 31))
 
 /*
  *     E N U M S