drm/i915: Change intel_pipe_update_{start,end}() calling convention
authorjsg <jsg@openbsd.org>
Mon, 29 Apr 2024 06:16:30 +0000 (06:16 +0000)
committerjsg <jsg@openbsd.org>
Mon, 29 Apr 2024 06:16:30 +0000 (06:16 +0000)
From Ville Syrjala
e19dc8c49e97b5cd84ee5753c301d64cde98c6aa in linux-6.6.y/6.6.29
09f390d4e2f38f8433431f4da31ca0a17a5c7853 in mainline linux

sys/dev/pci/drm/i915/display/intel_crtc.c
sys/dev/pci/drm/i915/display/intel_crtc.h
sys/dev/pci/drm/i915/display/intel_display.c

index 182c6dd..65d91c7 100644 (file)
@@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
 
 /**
  * intel_pipe_update_start() - start update of a set of display registers
- * @new_crtc_state: the new crtc state
+ * @state: the atomic state
+ * @crtc: the crtc
  *
  * Mark the start of an update to pipe registers that should be updated
  * atomically regarding vblank. If the next vblank will happens within
@@ -480,10 +481,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
  * until a subsequent call to intel_pipe_update_end(). That is done to
  * avoid random delays.
  */
-void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_start(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc)
 {
-       struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       struct intel_crtc_state *new_crtc_state =
+               intel_atomic_get_new_crtc_state(state, crtc);
        const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
        long timeout = msecs_to_jiffies_timeout(1);
        int scanline, min, max, vblank_start;
@@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
 
 /**
  * intel_pipe_update_end() - end update of a set of display registers
- * @new_crtc_state: the new crtc state
+ * @state: the atomic state
+ * @crtc: the crtc
  *
  * Mark the end of an update started with intel_pipe_update_start(). This
  * re-enables interrupts and verifies the update was actually completed
  * before a vblank.
  */
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_end(struct intel_atomic_state *state,
+                          struct intel_crtc *crtc)
 {
-       struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+       struct intel_crtc_state *new_crtc_state =
+               intel_atomic_get_new_crtc_state(state, crtc);
        enum pipe pipe = crtc->pipe;
        int scanline_end = intel_get_crtc_scanline(crtc);
        u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
index 785ee36..14c73db 100644 (file)
@@ -37,8 +37,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
-void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_start(struct intel_atomic_state *state,
+                            struct intel_crtc *crtc);
+void intel_pipe_update_end(struct intel_atomic_state *state,
+                          struct intel_crtc *crtc);
 void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
 struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
 struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
index e09a827..f1b01d4 100644 (file)
@@ -6616,7 +6616,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
        intel_crtc_planes_update_noarm(state, crtc);
 
        /* Perform vblank evasion around commit operation */
-       intel_pipe_update_start(new_crtc_state);
+       intel_pipe_update_start(state, crtc);
 
        commit_pipe_pre_planes(state, crtc);
 
@@ -6624,7 +6624,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 
        commit_pipe_post_planes(state, crtc);
 
-       intel_pipe_update_end(new_crtc_state);
+       intel_pipe_update_end(state, crtc);
 
        /*
         * We usually enable FIFO underrun interrupts as part of the