Remove unused code and definitions.

diff --git a/sys/arch/armv7/sunxi/sxiccmu.c b/sys/arch/armv7/sunxi/sxiccmu.c
index 5cf08d9..67a97d5 100644 (file)
--- a/sys/arch/armv7/sunxi/sxiccmu.c
+++ b/sys/arch/armv7/sunxi/sxiccmu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: sxiccmu.c,v 1.12 2016/08/22 19:29:32 kettenis Exp $   */
+/*     $OpenBSD: sxiccmu.c,v 1.13 2016/08/22 19:43:49 kettenis Exp $   */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -42,63 +42,6 @@
 #define DPRINTF(x)
 #endif
 
-#define        CCMU_SCLK_GATING                (1U << 31)
-#define        CCMU_GET_CLK_DIV_RATIO_N(x)     (((x) >> 16) & 0x03)
-#define        CCMU_GET_CLK_DIV_RATIO_M(x)     ((x) & 0x07)
-
-#define        CCMU_PLL6_CFG                   0x28
-#define        CCMU_PLL6_EN                    (1U << 31)
-#define        CCMU_PLL6_BYPASS_EN             (1 << 30)
-#define        CCMU_PLL6_SATA_CLK_EN           (1 << 14)
-#define        CCMU_PLL6_FACTOR_N              (31 << 8)
-#define        CCMU_PLL6_FACTOR_K              (3 << 4)
-#define        CCMU_PLL6_FACTOR_M              (3 << 0)
-
-#define        CCMU_AHB_GATING0                0x60
-#define        CCMU_AHB_GATING_USB0            (1 << 0)
-#define        CCMU_AHB_GATING_EHCI0           (1 << 1)
-#define        CCMU_AHB_GATING_OHCI0           (1 << 2)
-#define        CCMU_AHB_GATING_EHCI1           (1 << 3)
-#define        CCMU_AHB_GATING_OHCI1           (1 << 4)
-#define        CCMU_AHB_GATING_SS              (1 << 5)
-#define        CCMU_AHB_GATING_DMA             (1 << 6)
-#define        CCMU_AHB_GATING_BIST            (1 << 7)
-#define        CCMU_AHB_GATING_SDMMCx(x)       (1 << (8 + (x)))
-#define        CCMU_AHB_GATING_NAND            (1 << 13)
-#define        CCMU_AHB_GATING_EMAC            (1 << 17)
-#define        CCMU_AHB_GATING_SATA            (1 << 25)
-
-#define        CCMU_AHB_GATING1                0x64
-#define        CCMU_AHB_GATING_MALI400         (1 << 20)
-#define        CCMU_AHB_GATING_MP              (1 << 18)
-#define        CCMU_AHB_GATING_GMAC            (1 << 17)
-#define        CCMU_AHB_GATING_DE_FE1          (1 << 15)
-#define        CCMU_AHB_GATING_DE_FE0          (1 << 14)
-#define        CCMU_AHB_GATING_DE_BE1          (1 << 13)
-#define        CCMU_AHB_GATING_DE_BE0          (1 << 12)
-#define        CCMU_AHB_GATING_HDMI            (1 << 11)
-#define        CCMU_AHB_GATING_CSI1            (1 << 9)
-#define        CCMU_AHB_GATING_CSI0            (1 << 8)
-#define        CCMU_AHB_GATING_LCD1            (1 << 5)
-#define        CCMU_AHB_GATING_LCD0            (1 << 4)
-#define        CCMU_AHB_GATING_TVE1            (1 << 3)
-#define        CCMU_AHB_GATING_TVE0            (1 << 2)
-#define        CCMU_AHB_GATING_TVD             (1 << 1)
-#define        CCMU_AHB_GATING_VE              (1 << 0)
-
-#define        CCMU_APB_GATING0                0x68
-#define        CCMU_APB_GATING_PIO             (1 << 5)
-#define        CCMU_APB_GATING1                0x6c
-#define        CCMU_APB_GATING_UARTx(x)        (1 << (16 + (x)))
-#define        CCMU_APB_GATING_TWIx(x)         (1 << (x))
-#define        CCMU_APB_GATING_TWI4            (1 << 15)
-
-#define        CCMU_NAND_CLK                   0x80
-#define        CCMU_NAND_CLK_SRC_GATING_OSC24M (0 << 24)
-#define        CCMU_NAND_CLK_SRC_GATING_PLL6   (1 << 24)
-#define        CCMU_NAND_CLK_SRC_GATING_PLL5   (2 << 24)
-#define        CCMU_NAND_CLK_SRC_GATING_MASK   (3 << 24)
-
 #define CCMU_SDx_CLK(x)                        (0x88 + (x) * 4)
 #define CCMU_SDx_CLK_GATING            (1U << 31)
 #define CCMU_SDx_CLK_SRC_GATING_OSC24M (0 << 24)
@@ -110,32 +53,6 @@
 #define CCMU_SDx_CLK_FACTOR_M          (7 << 0)
 #define CCMU_SDx_CLK_FACTOR_M_SHIFT    0
 
-#define        CCMU_SATA_CLK                   0xc8
-#define        CCMU_SATA_CLK_SRC_GATING        (1 << 24)
-
-#define        CCMU_USB_CLK                    0xcc
-#define        CCMU_USB_PHY                    (1 << 8)
-#define        CCMU_SCLK_GATING_OHCI1          (1 << 7)
-#define        CCMU_SCLK_GATING_OHCI0          (1 << 6)
-#define        CCMU_OHCI_CLK_SRC               (1 << 4)
-#define        CCMU_USB2_RESET                 (1 << 2)
-#define        CCMU_USB1_RESET                 (1 << 1)
-#define        CCMU_USB0_RESET                 (1 << 0)
-
-#define        CCMU_GMAC_CLK_REG               0x164
-#define        CCMU_GMAC_CLK_TXC_DIV           (0x3 << 8)
-#define        CCMU_GMAC_CLK_TXC_DIV_1000      0
-#define        CCMU_GMAC_CLK_TXC_DIV_100       1
-#define        CCMU_GMAC_CLK_TXC_DIV_10        2
-#define        CCMU_GMAC_CLK_RXDC              (0x7 << 5)
-#define        CCMU_GMAC_CLK_RXIE              (1 << 4)
-#define        CCMU_GMAC_CLK_TXIE              (1 << 3)
-#define        CCMU_GMAC_CLK_PIT               (1 << 2)
-#define        CCMU_GMAC_CLK_TCS               (0x3 << 0)
-#define        CCMU_GMAC_CLK_TCS_MII           0
-#define        CCMU_GMAC_CLK_TCS_EXT_125       1
-#define        CCMU_GMAC_CLK_TCS_INT_RGMII     2
-
 struct sxiccmu_softc {
        struct device           sc_dev;
        bus_space_tag_t         sc_iot;
@@ -494,175 +411,6 @@ sxiccmu_reset(void *cookie, uint32_t *cells, int assert)
                SXISET4(sc, reg * 4, (1U << bit));
 }
 
-/* XXX spl? */
-void
-sxiccmu_enablemodule(int mod)
-{
-       struct sxiccmu_softc *sc = sxiccmu_cd.cd_devs[0];
-       uint32_t reg;
-
-       DPRINTF(("\nsxiccmu_enablemodule: mod %d\n", mod));
-
-       /* XXX reorder? */
-       switch (mod) {
-       case CCMU_EHCI0:
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI0);
-               SXISET4(sc, CCMU_USB_CLK, CCMU_USB1_RESET | CCMU_USB_PHY);
-               break;
-       case CCMU_EHCI1:
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI1);
-               SXISET4(sc, CCMU_USB_CLK, CCMU_USB2_RESET | CCMU_USB_PHY);
-               break;
-       case CCMU_OHCI0:
-               SXISET4(sc, CCMU_USB_CLK, CCMU_OHCI_CLK_SRC);
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_OHCI0);
-               SXISET4(sc, CCMU_USB_CLK, CCMU_SCLK_GATING_OHCI0);
-               break;
-       case CCMU_OHCI1:
-               SXISET4(sc, CCMU_USB_CLK, CCMU_OHCI_CLK_SRC);
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_OHCI1);
-               SXISET4(sc, CCMU_USB_CLK, CCMU_SCLK_GATING_OHCI1);
-               break;
-       case CCMU_AHCI:
-               reg = SXIREAD4(sc, CCMU_PLL6_CFG);
-               reg &= ~(CCMU_PLL6_BYPASS_EN | CCMU_PLL6_FACTOR_M |
-                   CCMU_PLL6_FACTOR_N);
-               reg |= CCMU_PLL6_EN | CCMU_PLL6_SATA_CLK_EN;
-               reg |= 25 << 8;
-               reg |= (reg >> 4 & 3);
-               SXIWRITE4(sc, CCMU_PLL6_CFG, reg);
-
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_SATA);
-               delay(1000);
-
-               SXIWRITE4(sc, CCMU_SATA_CLK, CCMU_SCLK_GATING);
-               break;
-       case CCMU_EMAC:
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EMAC);
-               break;
-       case CCMU_GMAC_MII:
-               SXISET4(sc, CCMU_AHB_GATING1, CCMU_AHB_GATING_GMAC);
-               SXICMS4(sc, CCMU_GMAC_CLK_REG,
-                   CCMU_GMAC_CLK_PIT|CCMU_GMAC_CLK_TCS,
-                   CCMU_GMAC_CLK_TCS_MII);
-               break;
-       case CCMU_GMAC_RGMII:
-               SXISET4(sc, CCMU_AHB_GATING1, CCMU_AHB_GATING_GMAC);
-               SXICMS4(sc, CCMU_GMAC_CLK_REG,
-                   CCMU_GMAC_CLK_PIT|CCMU_GMAC_CLK_TCS,
-                   CCMU_GMAC_CLK_PIT|CCMU_GMAC_CLK_TCS_INT_RGMII);
-               break;
-       case CCMU_DMA:
-               SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_DMA);
-               break;
-       case CCMU_UART0:
-       case CCMU_UART1:
-       case CCMU_UART2:
-       case CCMU_UART3:
-       case CCMU_UART4:
-       case CCMU_UART5:
-       case CCMU_UART6:
-       case CCMU_UART7:
-               SXISET4(sc, CCMU_APB_GATING1,
-                   CCMU_APB_GATING_UARTx(mod - CCMU_UART0));
-               break;
-       case CCMU_SDMMC0:
-       case CCMU_SDMMC1:
-       case CCMU_SDMMC2:
-       case CCMU_SDMMC3:
-               SXISET4(sc, CCMU_AHB_GATING0,
-                   CCMU_AHB_GATING_SDMMCx(mod - CCMU_SDMMC0));
-               break;
-       case CCMU_TWI0:
-       case CCMU_TWI1:
-       case CCMU_TWI2:
-       case CCMU_TWI3:
-       case CCMU_TWI4:
-               SXISET4(sc, CCMU_APB_GATING1, mod == CCMU_TWI4
-                   ? CCMU_APB_GATING_TWI4
-                   : CCMU_APB_GATING_TWIx(mod - CCMU_TWI0));
-               break;
-       case CCMU_PIO:
-               SXISET4(sc, CCMU_APB_GATING0, CCMU_APB_GATING_PIO);
-               break;
-       default:
-               break;
-       }
-}
-
-void
-sxiccmu_disablemodule(int mod)
-{
-       struct sxiccmu_softc *sc = sxiccmu_cd.cd_devs[0];
-
-       DPRINTF(("\nsxiccmu_disablemodule: mod %d\n", mod));
-
-       switch (mod) {
-       case CCMU_EHCI0:
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI0);
-               SXICLR4(sc, CCMU_USB_CLK, CCMU_USB1_RESET | CCMU_USB_PHY);
-               break;
-       case CCMU_EHCI1:
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI1);
-               SXICLR4(sc, CCMU_USB_CLK, CCMU_USB2_RESET | CCMU_USB_PHY);
-               break;
-       case CCMU_OHCI0:
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_OHCI0);
-               SXICLR4(sc, CCMU_USB_CLK, CCMU_SCLK_GATING_OHCI0);
-       case CCMU_OHCI1:
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_OHCI1);
-               SXICLR4(sc, CCMU_USB_CLK, CCMU_SCLK_GATING_OHCI1);
-               break;
-       case CCMU_AHCI:
-               /* XXX possibly wrong */
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_SATA);
-               SXIWRITE4(sc, CCMU_SATA_CLK, 0);
-               break;
-       case CCMU_EMAC:
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EMAC);
-               break;
-       case CCMU_GMAC_MII:
-       case CCMU_GMAC_RGMII:
-               SXICLR4(sc, CCMU_AHB_GATING1, CCMU_AHB_GATING_GMAC);
-               break;
-       case CCMU_DMA:
-               SXICLR4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_DMA);
-               break;
-       case CCMU_UART0:
-       case CCMU_UART1:
-       case CCMU_UART2:
-       case CCMU_UART3:
-       case CCMU_UART4:
-       case CCMU_UART5:
-       case CCMU_UART6:
-       case CCMU_UART7:
-               SXICLR4(sc, CCMU_APB_GATING1,
-                   CCMU_APB_GATING_UARTx(mod - CCMU_UART0));
-               break;
-       case CCMU_SDMMC0:
-       case CCMU_SDMMC1:
-       case CCMU_SDMMC2:
-       case CCMU_SDMMC3:
-               SXICLR4(sc, CCMU_AHB_GATING0,
-                   CCMU_AHB_GATING_SDMMCx(mod - CCMU_SDMMC0));
-               break;
-       case CCMU_TWI0:
-       case CCMU_TWI1:
-       case CCMU_TWI2:
-       case CCMU_TWI3:
-       case CCMU_TWI4:
-               SXICLR4(sc, CCMU_APB_GATING1, mod == CCMU_TWI4
-                   ? CCMU_APB_GATING_TWI4
-                   : CCMU_APB_GATING_TWIx(mod - CCMU_TWI0));
-               break;
-       case CCMU_PIO:
-               SXICLR4(sc, CCMU_APB_GATING0, CCMU_APB_GATING_PIO);
-               break;
-       default:
-               break;
-       }
-}
-
 void
 sxiccmu_set_sd_clock(int mod, int freq)
 {

diff --git a/sys/arch/armv7/sunxi/sxiccmuvar.h b/sys/arch/armv7/sunxi/sxiccmuvar.h
index 0a6e1bd..9cd081f 100644 (file)
--- a/sys/arch/armv7/sunxi/sxiccmuvar.h
+++ b/sys/arch/armv7/sunxi/sxiccmuvar.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: sxiccmuvar.h,v 1.4 2016/08/20 19:34:44 kettenis Exp $ */
+/*     $OpenBSD: sxiccmuvar.h,v 1.5 2016/08/22 19:43:49 kettenis Exp $ */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  *
@@ -15,37 +15,11 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-void sxiccmu_enablemodule(int);
-void sxiccmu_disablemodule(int);
-
 void sxiccmu_set_sd_clock(int, int);
 
 enum CCMU_MODULES {
-       CCMU_EHCI0,
-       CCMU_EHCI1,
-       CCMU_OHCI0,
-       CCMU_OHCI1,
-       CCMU_AHCI,
-       CCMU_EMAC,
-       CCMU_GMAC_MII,
-       CCMU_GMAC_RGMII,
-       CCMU_DMA,
-       CCMU_UART0,
-       CCMU_UART1,
-       CCMU_UART2,
-       CCMU_UART3,
-       CCMU_UART4,
-       CCMU_UART5,
-       CCMU_UART6,
-       CCMU_UART7,
-       CCMU_TWI0,
-       CCMU_TWI1,
-       CCMU_TWI2,
-       CCMU_TWI3,
-       CCMU_TWI4,
        CCMU_SDMMC0,
        CCMU_SDMMC1,
        CCMU_SDMMC2,
-       CCMU_SDMMC3,
-       CCMU_PIO
+       CCMU_SDMMC3
 };