Rename the XCR0_* #defines to XFEATURE_* and add the new supervisor-state

features: while all are appropriate for xsaves/xrstors, the
supervisor-state features aren't for xcr0 but rather for the new XSS_MSR,
making the current names kinda confusing.

Add #defines for masking bits for xcr0 vs XSS.

Add and report the new XSAVE_XFD xsave subfeature bit.

ok mlarkin@

diff --git a/sys/arch/amd64/amd64/cpu.c b/sys/arch/amd64/amd64/cpu.c
index de9e889..75d4eee 100644 (file)
--- a/sys/arch/amd64/amd64/cpu.c
+++ b/sys/arch/amd64/amd64/cpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cpu.c,v 1.166 2023/04/17 00:42:04 jsg Exp $   */
+/*     $OpenBSD: cpu.c,v 1.167 2023/04/22 18:27:28 guenther Exp $      */
 /* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */
 
 /*-
@@ -317,7 +317,7 @@ replacemds(void)
                         * CascadeLake
                         */
                        /* XXX mds_handler_skl_avx512 */
-                       if (xgetbv(0) & XCR0_AVX) {
+                       if (xgetbv(0) & XFEATURE_AVX) {
                                handler = &mds_handler_skl_avx;
                                type = "Skylake AVX";
                        } else {
@@ -751,10 +751,9 @@ cpu_init(struct cpu_info *ci)
        if ((cpu_ecxfeature & CPUIDECX_XSAVE) && cpuid_level >= 0xd) {
                u_int32_t eax, ebx, ecx, edx;
 
-               xsave_mask = XCR0_X87 | XCR0_SSE;
+               xsave_mask = XFEATURE_X87 | XFEATURE_SSE;
                CPUID_LEAF(0xd, 0, eax, ebx, ecx, edx);
-               if (eax & XCR0_AVX)
-                       xsave_mask |= XCR0_AVX;
+               xsave_mask |= eax & XFEATURE_AVX;
                xsetbv(0, xsave_mask);
                CPUID_LEAF(0xd, 0, eax, ebx, ecx, edx);
                if (CPU_IS_PRIMARY(ci)) {

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index 2c18350..98fdda9 100644 (file)
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: identcpu.c,v 1.132 2023/03/26 18:12:45 mlarkin Exp $  */
+/*     $OpenBSD: identcpu.c,v 1.133 2023/04/22 18:27:28 guenther Exp $ */
 /*     $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $        */
 
 /*
@@ -241,6 +241,7 @@ const struct {
        { XSAVE_XSAVEC,         "XSAVEC" },
        { XSAVE_XGETBV1,        "XGETBV1" },
        { XSAVE_XSAVES,         "XSAVES" },
+       { XSAVE_XFD,            "XFD" },
 };
 
 int

diff --git a/sys/arch/amd64/amd64/mds.S b/sys/arch/amd64/amd64/mds.S
index a57f863..e4967fb 100644 (file)
--- a/sys/arch/amd64/amd64/mds.S
+++ b/sys/arch/amd64/amd64/mds.S
@@ -1,4 +1,4 @@
-/*     $OpenBSD: mds.S,v 1.3 2021/09/04 22:15:33 bluhm Exp $   */
+/*     $OpenBSD: mds.S,v 1.4 2023/04/22 18:27:28 guenther Exp $        */
 /*
  * Copyright (c) 2019 Philip Guenther <guenther@openbsd.org>
  *
@@ -77,7 +77,7 @@ END(mds_handler_bdw)
 ENTRY(mds_handler_skl)
        xorl    %ecx,%ecx
        xgetbv
-       testb   $XCR0_AVX,%al
+       testb   $XFEATURE_AVX,%al
        jne     mds_handler_skl_avx
        jmp     mds_handler_skl_sse
 END(mds_handler_skl)

diff --git a/sys/arch/amd64/amd64/vmm.c b/sys/arch/amd64/amd64/vmm.c
index 8db981f..22dce4e 100644 (file)
--- a/sys/arch/amd64/amd64/vmm.c
+++ b/sys/arch/amd64/amd64/vmm.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: vmm.c,v 1.338 2023/04/16 01:50:12 dv Exp $    */
+/*     $OpenBSD: vmm.c,v 1.339 2023/04/22 18:27:28 guenther Exp $      */
 /*
  * Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
  *
@@ -2722,7 +2722,7 @@ vcpu_reset_regs_svm(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
        ret = vcpu_writeregs_svm(vcpu, VM_RWREGS_ALL, vrs);
 
        /* xcr0 power on default sets bit 0 (x87 state) */
-       vcpu->vc_gueststate.vg_xcr0 = XCR0_X87 & xsave_mask;
+       vcpu->vc_gueststate.vg_xcr0 = XFEATURE_X87 & xsave_mask;
 
        vcpu->vc_parent->vm_map->pmap->eptp = 0;
 
@@ -3523,7 +3523,7 @@ vcpu_reset_regs_vmx(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
        /* XXX CR4 shadow */
 
        /* xcr0 power on default sets bit 0 (x87 state) */
-       vcpu->vc_gueststate.vg_xcr0 = XCR0_X87 & xsave_mask;
+       vcpu->vc_gueststate.vg_xcr0 = XFEATURE_X87 & xsave_mask;
 
        /* XXX PAT shadow */
        vcpu->vc_shadow_pat = rdmsr(MSR_CR_PAT);

diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index 703c9ea..e24c532 100644 (file)
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: specialreg.h,v 1.101 2023/04/15 01:22:50 jsg Exp $    */
+/*     $OpenBSD: specialreg.h,v 1.102 2023/04/22 18:27:28 guenther Exp $       */
 /*     $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $      */
 /*     $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $  */
 
@@ -91,19 +91,40 @@
 #define        CR4_UINTR       0x02000000      /* user interrupts enable bit */
 
 /*
- * Extended Control Register XCR0
+ * Extended state components, for xsave/xrstor family of instructions.
  */
-#define        XCR0_X87        0x00000001      /* x87 FPU/MMX state */
-#define        XCR0_SSE        0x00000002      /* SSE state */
-#define        XCR0_AVX        0x00000004      /* AVX state */
-#define        XCR0_BNDREG     0x00000008      /* MPX state */
-#define        XCR0_BNDCSR     0x00000010      /* MPX state */
-#define        XCR0_OPMASK     0x00000020      /* AVX-512 opmask */
-#define        XCR0_ZMM_HI256  0x00000040      /* AVX-512 ZMM0-7 */
-#define        XCR0_HI16_ZMM   0x00000080      /* AVX-512 ZMM16-31 */
-#define        XCR0_PKRU       0x00000200      /* user page key */
-#define        XCR0_TILECFG    0x00020000      /* AMX state */
-#define        XCR0_TILEDATA   0x00040000      /* AMX state */
+#define        XFEATURE_X87            0x00000001      /* x87 FPU/MMX state */
+#define        XFEATURE_SSE            0x00000002      /* SSE state */
+#define        XFEATURE_AVX            0x00000004      /* AVX state */
+#define        XFEATURE_BNDREG         0x00000008      /* MPX state */
+#define        XFEATURE_BNDCSR         0x00000010      /* MPX state */
+#define        XFEATURE_MPX            (XFEATURE_BNDREG | XFEATURE_BNDCSR)
+#define        XFEATURE_OPMASK         0x00000020      /* AVX-512 opmask */
+#define        XFEATURE_ZMM_HI256      0x00000040      /* AVX-512 ZMM0-7 */
+#define        XFEATURE_HI16_ZMM       0x00000080      /* AVX-512 ZMM16-31 */
+#define        XFEATURE_AVX512         (XFEATURE_OPMASK | XFEATURE_ZMM_HI256 | \
+                                XFEATURE_HI16_ZMM)
+#define        XFEATURE_PT             0x00000100      /* processor trace */
+#define        XFEATURE_PKRU           0x00000200      /* user page key */
+#define        XFEATURE_PASID          0x00000400      /* Process ASIDs */
+#define        XFEATURE_CET_U          0x00000800      /* ctrl-flow enforce user */
+#define        XFEATURE_CET_S          0x00001000      /* ctrl-flow enforce system */
+#define        XFEATURE_CET            (XFEATURE_CET_U | XFEATURE_CET_S)
+#define        XFEATURE_HDC            0x00002000      /* HW duty cycling */
+#define        XFEATURE_UINTR          0x00004000      /* user interrupts */
+#define        XFEATURE_LBR            0x00008000      /* last-branch record */
+#define        XFEATURE_HWP            0x00010000      /* HW P-states */
+#define        XFEATURE_TILECFG        0x00020000      /* AMX state */
+#define        XFEATURE_TILEDATA       0x00040000      /* AMX state */
+#define        XFEATURE_AMX            (XFEATURE_TILEDATA | XFEATURE_TILEDATA)
+
+/* which bits are for XCR0 and which for the XSS MSR? */
+#define XFEATURE_XCR0_MASK \
+       (XFEATURE_X87 | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
+        XFEATURE_AVX512 | XFEATURE_PKRU | XFEATURE_AMX)
+#define        XFEATURE_XSS_MASK \
+       (XFEATURE_PT | XFEATURE_PASID | XFEATURE_CET | XFEATURE_HDC | \
+        XFEATURE_UINTR | XFEATURE_LBR | XFEATURE_HWP)
 
 /*
  * CPUID "features" bits (CPUID function 0x1):
@@ -506,6 +527,7 @@
 #define MSR_CET_ENDBR_EN               (1 << 2)
 #define MSR_S_CET              0x6a2
 #define MSR_PKRS               0x6e1
+#define MSR_XSS                        0xda0
 
 /* VIA MSR */
 #define MSR_CENT_TMTEMPERATURE 0x1423  /* Thermal monitor temperature */
@@ -1457,10 +1479,11 @@
 /*
  * XSAVE subfeatures (cpuid 0xd, leaf 1)
  */
-#define XSAVE_XSAVEOPT         0x1UL
-#define XSAVE_XSAVEC           0x2UL
-#define XSAVE_XGETBV1          0x4UL
-#define XSAVE_XSAVES           0x8UL
+#define XSAVE_XSAVEOPT         0x01UL
+#define XSAVE_XSAVEC           0x02UL
+#define XSAVE_XGETBV1          0x04UL
+#define XSAVE_XSAVES           0x08UL
+#define XSAVE_XFD              0x10UL
 
 /*
  * Default cr0 and cr4 flags.