Introduce BUS_SPACE_MAP_POSTED such that we can distinguish between

posted and non-posted device memory mappings and set the right memory
attributes for them.  Needed because on the Apple M1 using the wrong
mapping will fault.

ok patrick@, dlg@

diff --git a/sys/arch/arm64/arm64/locore.S b/sys/arch/arm64/arm64/locore.S
index cfd8708..2e646b2 100644 (file)
--- a/sys/arch/arm64/arm64/locore.S
+++ b/sys/arch/arm64/arm64/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.32 2020/10/19 17:57:40 naddy Exp $ */
+/* $OpenBSD: locore.S,v 1.33 2021/02/16 12:33:22 kettenis Exp $ */
 /*-
  * Copyright (c) 2012-2014 Andrew Turner
  * All rights reserved.
@@ -233,9 +233,10 @@ switch_mmu_kernel:
 mair:
        /* Device | Normal (no cache, write-back, write-through) */
        .quad   MAIR_ATTR(0x00, 0) |    \
-               MAIR_ATTR(0x44, 1) |    \
-               MAIR_ATTR(0xff, 2) |    \
-               MAIR_ATTR(0x88, 3)
+               MAIR_ATTR(0x04, 1) |    \
+               MAIR_ATTR(0x44, 2) |    \
+               MAIR_ATTR(0xff, 3) |    \
+               MAIR_ATTR(0x88, 4)
 tcr:
        .quad (TCR_T1SZ(64 - VIRT_BITS) | TCR_T0SZ(64 - 48) | \
            TCR_AS | TCR_TG1_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS)

diff --git a/sys/arch/arm64/arm64/locore0.S b/sys/arch/arm64/arm64/locore0.S
index 8b71848..974243e 100644 (file)
--- a/sys/arch/arm64/arm64/locore0.S
+++ b/sys/arch/arm64/arm64/locore0.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore0.S,v 1.5 2019/05/28 20:32:30 patrick Exp $ */
+/* $OpenBSD: locore0.S,v 1.6 2021/02/16 12:33:22 kettenis Exp $ */
 /*-
  * Copyright (c) 2012-2014 Andrew Turner
  * All rights reserved.
@@ -34,8 +34,8 @@
 #include <machine/pte.h>
 
 #define        DEVICE_MEM      0
-#define        NORMAL_UNCACHED 1
-#define        NORMAL_MEM      2
+#define        NORMAL_UNCACHED 2
+#define        NORMAL_MEM      3
 
 /*
  * We assume:

diff --git a/sys/arch/arm64/arm64/machdep.c b/sys/arch/arm64/arm64/machdep.c
index dc5530d..be9969b 100644 (file)
--- a/sys/arch/arm64/arm64/machdep.c
+++ b/sys/arch/arm64/arm64/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.57 2021/02/11 23:55:48 patrick Exp $ */
+/* $OpenBSD: machdep.c,v 1.58 2021/02/16 12:33:22 kettenis Exp $ */
 /*
  * Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
  *
@@ -1188,7 +1188,7 @@ pmap_bootstrap_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
 
        for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE)
                pmap_kenter_cache(va, pa, PROT_READ | PROT_WRITE,
-                   PMAP_CACHE_DEV);
+                   PMAP_CACHE_DEV_NGNRNE);
 
        virtual_avail = va;
 

diff --git a/sys/arch/arm64/arm64/pmap.c b/sys/arch/arm64/arm64/pmap.c
index d6ed226..f224fae 100644 (file)
--- a/sys/arch/arm64/arm64/pmap.c
+++ b/sys/arch/arm64/arm64/pmap.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap.c,v 1.70 2021/01/25 19:37:17 kettenis Exp $ */
+/* $OpenBSD: pmap.c,v 1.71 2021/02/16 12:33:22 kettenis Exp $ */
 /*
  * Copyright (c) 2008-2009,2014-2016 Dale Rahn <drahn@dalerahn.com>
  *
@@ -472,7 +472,7 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags)
        if (pa & PMAP_NOCACHE)
                cache = PMAP_CACHE_CI;
        if (pa & PMAP_DEVICE)
-               cache = PMAP_CACHE_DEV;
+               cache = PMAP_CACHE_DEV_NGNRNE;
        pg = PHYS_TO_VM_PAGE(pa);
 
        pmap_lock(pm);
@@ -648,7 +648,7 @@ _pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, int flags, int cache)
        pmap_pte_insert(pted);
 
        ttlb_flush(pm, va & ~PAGE_MASK);
-       if (cache == PMAP_CACHE_CI || cache == PMAP_CACHE_DEV)
+       if (cache == PMAP_CACHE_CI || cache == PMAP_CACHE_DEV_NGNRNE)
                cpu_idcache_wbinv_range(va & ~PAGE_MASK, PAGE_SIZE);
 }
 
@@ -735,7 +735,9 @@ pmap_fill_pte(pmap_t pm, vaddr_t va, paddr_t pa, struct pte_desc *pted,
                break;
        case PMAP_CACHE_CI:
                break;
-       case PMAP_CACHE_DEV:
+       case PMAP_CACHE_DEV_NGNRNE:
+               break;
+       case PMAP_CACHE_DEV_NGNRE:
                break;
        default:
                panic("pmap_fill_pte:invalid cache mode");
@@ -1637,8 +1639,12 @@ pmap_pte_update(struct pte_desc *pted, uint64_t *pl3)
                attr |= ATTR_IDX(PTE_ATTR_CI);
                attr |= ATTR_SH(SH_INNER);
                break;
-       case PMAP_CACHE_DEV:
-               attr |= ATTR_IDX(PTE_ATTR_DEV);
+       case PMAP_CACHE_DEV_NGNRNE:
+               attr |= ATTR_IDX(PTE_ATTR_DEV_NGNRNE);
+               attr |= ATTR_SH(SH_INNER);
+               break;
+       case PMAP_CACHE_DEV_NGNRE:
+               attr |= ATTR_IDX(PTE_ATTR_DEV_NGNRE);
                attr |= ATTR_SH(SH_INNER);
                break;
        default:

diff --git a/sys/arch/arm64/dev/arm64_bus_space.c b/sys/arch/arm64/dev/arm64_bus_space.c
index 34c57e6..e4847cb 100644 (file)
--- a/sys/arch/arm64/dev/arm64_bus_space.c
+++ b/sys/arch/arm64/dev/arm64_bus_space.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: arm64_bus_space.c,v 1.7 2018/08/20 19:38:07 kettenis Exp $ */
+/*     $OpenBSD: arm64_bus_space.c,v 1.8 2021/02/16 12:33:22 kettenis Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -191,8 +191,12 @@ generic_space_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size,
 {
        u_long startpa, endpa, pa;
        vaddr_t va;
-       int cache = flags & BUS_SPACE_MAP_CACHEABLE ?
-           PMAP_CACHE_WB : PMAP_CACHE_DEV;
+       int cache = PMAP_CACHE_DEV_NGNRNE;
+
+       if (flags & BUS_SPACE_MAP_CACHEABLE)
+               cache = PMAP_CACHE_WB;
+       if (flags & BUS_SPACE_MAP_POSTED)
+               cache = PMAP_CACHE_DEV_NGNRE;
 
        startpa = trunc_page(offs);
        endpa = round_page(offs + size);

diff --git a/sys/arch/arm64/include/bus.h b/sys/arch/arm64/include/bus.h
index 73678b5..092a486 100644 (file)
--- a/sys/arch/arm64/include/bus.h
+++ b/sys/arch/arm64/include/bus.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: bus.h,v 1.7 2020/04/13 21:34:54 kettenis Exp $ */
+/* $OpenBSD: bus.h,v 1.8 2021/02/16 12:33:22 kettenis Exp $ */
 /*
  * Copyright (c) 2003-2004 Opsycon AB Sweden.  All rights reserved.
  *
@@ -129,10 +129,10 @@ struct bus_space {
 #define        bus_space_subregion(t, h, o, s, p) \
     (*(t)->_space_subregion)((t), (h), (o), (s), (p))
 
-#define        BUS_SPACE_MAP_CACHEABLE         0x01
-#define BUS_SPACE_MAP_KSEG0            0x02
-#define        BUS_SPACE_MAP_LINEAR            0x04
-#define        BUS_SPACE_MAP_PREFETCHABLE      0x08
+#define BUS_SPACE_MAP_CACHEABLE                0x01
+#define BUS_SPACE_MAP_POSTED           0x02
+#define BUS_SPACE_MAP_LINEAR           0x04
+#define BUS_SPACE_MAP_PREFETCHABLE     0x08
 
 #define        bus_space_vaddr(t, h)   (*(t)->_space_vaddr)((t), (h))
 #define        bus_space_mmap(t, a, o, p, f) \

diff --git a/sys/arch/arm64/include/pmap.h b/sys/arch/arm64/include/pmap.h
index 28f76b5..d0c486a 100644 (file)
--- a/sys/arch/arm64/include/pmap.h
+++ b/sys/arch/arm64/include/pmap.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap.h,v 1.15 2021/02/15 20:44:08 kettenis Exp $ */
+/* $OpenBSD: pmap.h,v 1.16 2021/02/16 12:33:22 kettenis Exp $ */
 /*
  * Copyright (c) 2008,2009,2014 Dale Rahn <drahn@dalerahn.com>
  *
@@ -42,7 +42,8 @@
 #define PMAP_CACHE_CI          (PMAP_MD0)              /* cache inhibit */
 #define PMAP_CACHE_WT          (PMAP_MD1)              /* writethru */
 #define PMAP_CACHE_WB          (PMAP_MD1|PMAP_MD0)     /* writeback */
-#define PMAP_CACHE_DEV         (PMAP_MD2)              /* device mapping */
+#define PMAP_CACHE_DEV_NGNRNE  (PMAP_MD2)              /* device nGnRnE */
+#define PMAP_CACHE_DEV_NGNRE   (PMAP_MD2|PMAP_MD0)     /* device nGnRE */
 #define PMAP_CACHE_BITS                (PMAP_MD0|PMAP_MD1|PMAP_MD2)    
 
 #define PTED_VA_MANAGED_M      (PMAP_MD3)

diff --git a/sys/arch/arm64/include/pte.h b/sys/arch/arm64/include/pte.h
index 10500ac..9c566b8 100644 (file)
--- a/sys/arch/arm64/include/pte.h
+++ b/sys/arch/arm64/include/pte.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pte.h,v 1.5 2017/04/13 23:29:02 kettenis Exp $ */
+/* $OpenBSD: pte.h,v 1.6 2021/02/16 12:33:22 kettenis Exp $ */
 /*
  * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com>
  *
@@ -53,11 +53,11 @@
 #define                ATTR_IDX(x)     ((x) << 2)
 #define                ATTR_IDX_MASK   (7 << 2)
 
-#define                PTE_ATTR_DEV    0
-#define                PTE_ATTR_CI     1
-#define                PTE_ATTR_WB     2
-#define                PTE_ATTR_WT     3
-
+#define                PTE_ATTR_DEV_NGNRNE     0
+#define                PTE_ATTR_DEV_NGNRE      1
+#define                PTE_ATTR_CI             2
+#define                PTE_ATTR_WB             3
+#define                PTE_ATTR_WT             4
 
 #define                SH_INNER        3
 #define                SH_OUTER        2