drm/amd/display: Check if modulo is 0 before dividing.

From David Galiffi
10ef82d6e0af5536ec64770c07f6bbabfdd6977c in linux 5.15.y/5.15.47
49947b906a6bd9668eaf4f9cf691973c25c26955 in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c b/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
index cd82a11..74f8bc7 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1013,9 +1013,12 @@ static bool get_pixel_clk_frequency_100hz(
                         * not be programmed equal to DPREFCLK
                         */
                        modulo_hz = REG_READ(MODULO[inst]);
-                       *pixel_clk_khz = div_u64((uint64_t)clock_hz*
-                               clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
-                               modulo_hz);
+                       if (modulo_hz)
+                               *pixel_clk_khz = div_u64((uint64_t)clock_hz*
+                                       clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
+                                       modulo_hz);
+                       else
+                               *pixel_clk_khz = 0;
                } else {
                        /* NOTE: There is agreement with VBIOS here that MODULO is
                         * programmed equal to DPREFCLK, in which case PHASE will be