Add clocks for the RK3588 I2C controllers.

ok kettenis@

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 4f92fd1..b72d85e 100644 (file)
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rkclock.c,v 1.78 2023/07/07 16:52:09 patrick Exp $    */
+/*     $OpenBSD: rkclock.c,v 1.79 2023/07/07 16:52:57 patrick Exp $    */
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -3839,6 +3839,46 @@ const struct rkclock rk3588_clocks[] = {
                SEL(5, 5), DIV(4, 0),
                { RK3588_PLL_GPLL, RK3588_PLL_CPLL }
        },
+       {
+               RK3588_CLK_I2C1, RK3588_CRU_CLKSEL_CON(38),
+               SEL(6, 6), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C2, RK3588_CRU_CLKSEL_CON(38),
+               SEL(7, 7), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C3, RK3588_CRU_CLKSEL_CON(38),
+               SEL(8, 8), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C4, RK3588_CRU_CLKSEL_CON(38),
+               SEL(9, 9), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C5, RK3588_CRU_CLKSEL_CON(38),
+               SEL(10, 10), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C6, RK3588_CRU_CLKSEL_CON(38),
+               SEL(11, 11), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C7, RK3588_CRU_CLKSEL_CON(38),
+               SEL(12, 12), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
+       {
+               RK3588_CLK_I2C8, RK3588_CRU_CLKSEL_CON(38),
+               SEL(13, 13), 0,
+               { RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
+       },
        {
                RK3588_CLK_UART1_SRC, RK3588_CRU_CLKSEL_CON(41),
                SEL(14, 14), DIV(13, 9),
@@ -4066,6 +4106,11 @@ const struct rkclock rk3588_clocks[] = {
                { RK3588_ACLK_VOP_ROOT, 0 /* RK3588_ACLK_VOP_DIV2_SRC */ },
                SET_PARENT
        },
+       {
+               RK3588_CLK_I2C0, RK3588_CRU_CLKSEL_CON(3),
+               SEL(6, 6), 0,
+               { RK3588_CLK_PMU1_200M_SRC, RK3588_CLK_PMU1_100M_SRC },
+       },
        {
                RK3588_CLK_PMU1_50M_SRC, RK3588_PMUCRU_CLKSEL_CON(0),
                0, DIV(3, 0),

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 4639dd0..000c722 100644 (file)
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -394,6 +394,14 @@
 #define RK3588_PLL_PPLL                        8
 
 #define RK3588_ACLK_BUS_ROOT           113
+#define RK3588_CLK_I2C1                        131
+#define RK3588_CLK_I2C2                        132
+#define RK3588_CLK_I2C3                        133
+#define RK3588_CLK_I2C4                        134
+#define RK3588_CLK_I2C5                        135
+#define RK3588_CLK_I2C6                        136
+#define RK3588_CLK_I2C7                        137
+#define RK3588_CLK_I2C8                        138
 #define RK3588_CLK_UART1_SRC           168
 #define RK3588_CLK_UART1_FRAC          169
 #define RK3588_CLK_UART1               170
@@ -449,6 +457,7 @@
 #define RK3588_ACLK_VOP_ROOT           600
 #define RK3588_ACLK_VOP                        605
 #define RK3588_ACLK_VOP_SUB_SRC                619
+#define RK3588_CLK_I2C0                        628
 #define RK3588_CLK_PMU1_50M_SRC                639
 #define RK3588_CLK_PMU1_100M_SRC       640
 #define RK3588_CLK_PMU1_200M_SRC       641