Allegedly a "Marvell Armada 3700 Functional Errata, Guidelines, and

Restrictions" document exists that discusses an errata #251 in section
"3.12 PCIe Completion Timeout" and suggests that setting the DIS_ORD_CHK
flag in the Debug Mux Control register is necessary as a workaround:

https://lore.kernel.org/linux-pci/20210624222621.4776-6-pali@kernel.org

This workaround is still being discussed by the Linux developers, but it
does fix an issue I am seeing with athn(4), where an external abort
happens under load.  So apply this workaround since its potential side
effects seem to be significantly less severe than provoking an
external abort that hangs the machine.

ok patrick@

diff --git a/sys/dev/fdt/mvkpcie.c b/sys/dev/fdt/mvkpcie.c
index 011531a..fd49ef2 100644 (file)
--- a/sys/dev/fdt/mvkpcie.c
+++ b/sys/dev/fdt/mvkpcie.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: mvkpcie.c,v 1.10 2021/05/17 17:25:13 kettenis Exp $   */
+/*     $OpenBSD: mvkpcie.c,v 1.11 2021/10/04 19:04:12 kettenis Exp $   */
 /*
  * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
  * Copyright (c) 2020 Patrick Wildt <patrick@blueri.se>
@@ -113,6 +113,8 @@
 #define LMI_CFG                                0x6000
 #define  LMI_CFG_LTSSM_VAL(x)                  (((x) >> 24) & 0x3f)
 #define  LMI_CFG_LTSSM_L0                      0x10
+#define LMI_DEBUG_CTRL                 0x6208
+#define  LMI_DEBUG_CTRL_DIS_ORD_CHK            (1 << 30)
 #define CTRL_CORE_CONFIG               0x18000
 #define  CTRL_CORE_CONFIG_MODE_DIRECT          (0 << 0)
 #define  CTRL_CORE_CONFIG_MODE_COMMAND         (1 << 0)
@@ -392,6 +394,10 @@ mvkpcie_attach(struct device *parent, struct device *self, void *aux)
            PCIE_CORE_CTRL2_RESERVED |
            PCIE_CORE_CTRL2_TD_ENABLE);
 
+       reg = HREAD4(sc, LMI_DEBUG_CTRL);
+       reg |= LMI_DEBUG_CTRL_DIS_ORD_CHK;
+       HWRITE4(sc, LMI_DEBUG_CTRL, reg);
+
        reg = HREAD4(sc, PCIE_CORE_CTRL0);
        reg &= ~PCIE_CORE_CTRL0_GEN_MASK;
        reg |= PCIE_CORE_CTRL0_GEN_2;