-/* $OpenBSD: pluart.c,v 1.8 2022/03/11 06:45:22 anton Exp $ */
+/* $OpenBSD: pluart.c,v 1.9 2022/03/13 21:17:52 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
* Copyright (c) 2005 Dale Rahn <drahn@dalerahn.com>
#define UART_CR_CTSE (1 << 14) /* CTS hardware flow control enable */
#define UART_CR_RTSE (1 << 15) /* RTS hardware flow control enable */
#define UART_IFLS 0x34 /* Interrupt FIFO level select register */
-#define UART_IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */
-#define UART_IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */
-#define UART_IFLS_1_8 0 /* FIFO 1/8 full */
-#define UART_IFLS_1_4 1 /* FIFO 1/4 full */
-#define UART_IFLS_1_2 2 /* FIFO 1/2 full */
-#define UART_IFLS_3_4 3 /* FIFO 3/4 full */
-#define UART_IFLS_7_8 4 /* FIFO 7/8 full */
#define UART_IMSC 0x38 /* Interrupt mask set/clear register */
#define UART_IMSC_RIMIM (1 << 0)
#define UART_IMSC_CTSMIM (1 << 1)
#define UART_MIS 0x40 /* Masked interrupt status register */
#define UART_ICR 0x44 /* Interrupt clear register */
#define UART_DMACR 0x48 /* DMA control register */
-#define UART_PID0 0xfe0 /* Peripheral identification register 0 */
-#define UART_PID1 0xfe4 /* Peripheral identification register 1 */
-#define UART_PID2 0xfe8 /* Peripheral identification register 2 */
-#define UART_PID2_REV(x) (((x) & 0xf0) >> 4)
-#define UART_PID3 0xfec /* Peripheral identification register 3 */
#define UART_SPACE 0x100
-#define UART_FIFO_SIZE 16
-#define UART_FIFO_SIZE_R3 32
-
void pluartcnprobe(struct consdev *cp);
void pluartcninit(struct consdev *cp);
int pluartcngetc(dev_t dev);
void
pluart_attach_common(struct pluart_softc *sc, int console)
{
- int fifolen, maj;
- int lcr;
-
- if ((sc->sc_hwflags & COM_HW_SBSA) == 0) {
- int rev;
-
- rev = UART_PID2_REV(bus_space_read_4(sc->sc_iot, sc->sc_ioh,
- UART_PID2));
- if (rev < 3)
- fifolen = UART_FIFO_SIZE;
- else
- fifolen = UART_FIFO_SIZE_R3;
- printf(": rev %d, %d byte fifo\n", rev, fifolen);
- } else {
- /*
- * The SBSA UART is PL011 r1p5 compliant which implies revision
- * 3 with a 32 byte FIFO. However, we cannot expect to configure
- * RX/TX interrupt levels using the UARTIFLS register making it
- * impossible to make assumptions about the number of available
- * bytes in the FIFO. Therefore disable FIFO support for such
- * devices.
- */
- fifolen = 0;
- printf("\n");
- }
+ int maj;
if (console) {
/* Locate the major number. */
break;
cn_tab->cn_dev = makedev(maj, sc->sc_dev.dv_unit);
- printf("%s: console\n", sc->sc_dev.dv_xname);
+ printf(": console");
SET(sc->sc_hwflags, COM_HW_CONSOLE);
}
panic("%s: can't establish soft interrupt.",
sc->sc_dev.dv_xname);
- if (fifolen > 0) {
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_IFLS,
- (UART_IFLS_3_4 << UART_IFLS_RX_SHIFT) |
- (UART_IFLS_1_4 << UART_IFLS_TX_SHIFT));
- }
- sc->sc_imsc = UART_IMSC_RXIM | UART_IMSC_RTIM | UART_IMSC_TXIM;
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_IMSC, sc->sc_imsc);
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_IMSC, (UART_IMSC_RXIM | UART_IMSC_TXIM));
bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_ICR, 0x7ff);
- lcr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, UART_LCR_H);
- if (fifolen > 0)
- lcr |= UART_LCR_H_FEN;
- else
- lcr &= ~UART_LCR_H_FEN;
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_LCR_H, lcr);
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_LCR_H,
+ bus_space_read_4(sc->sc_iot, sc->sc_ioh, UART_LCR_H) &
+ ~UART_LCR_H_FEN);
+
+ printf("\n");
}
int
if (sc->sc_tty == NULL)
return 0;
- if (!ISSET(is, UART_IMSC_RXIM) && !ISSET(is, UART_IMSC_RTIM) &&
- !ISSET(is, UART_IMSC_TXIM))
+ if (!ISSET(is, UART_IMSC_RXIM) && !ISSET(is, UART_IMSC_TXIM))
return 0;
- if (ISSET(is, UART_IMSC_TXIM)) {
- /* Disable transmit interrupt. */
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_IMSC,
- sc->sc_imsc & ~UART_IMSC_TXIM);
-
- if (ISSET(tp->t_state, TS_BUSY)) {
- CLR(tp->t_state, TS_BUSY | TS_FLUSH);
- if (sc->sc_halt > 0)
- wakeup(&tp->t_outq);
- (*linesw[tp->t_line].l_start)(tp);
- }
+ if (ISSET(is, UART_IMSC_TXIM) && ISSET(tp->t_state, TS_BUSY)) {
+ CLR(tp->t_state, TS_BUSY | TS_FLUSH);
+ if (sc->sc_halt > 0)
+ wakeup(&tp->t_outq);
+ (*linesw[tp->t_line].l_start)(tp);
}
p = sc->sc_ibufp;
- while (!ISSET(bus_space_read_4(iot, ioh, UART_FR), UART_FR_RXFE)) {
+ while (ISSET(bus_space_read_4(iot, ioh, UART_FR), UART_FR_RXFF)) {
c = bus_space_read_2(iot, ioh, UART_DR);
if (c & UART_DR_BE) {
#ifdef DDB
struct pluart_softc *sc = pluart_cd.cd_devs[DEVUNIT(tp->t_dev)];
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
+ u_int16_t fr;
int s;
s = spltty();
goto out;
SET(tp->t_state, TS_BUSY);
- /* Enable transmit interrupt. */
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, UART_IMSC, sc->sc_imsc);
-
- while (tp->t_outq.c_cc > 0) {
- uint16_t fr;
-
- fr = bus_space_read_4(iot, ioh, UART_FR);
- if (ISSET(fr, UART_FR_TXFF))
- break;
-
+ fr = bus_space_read_4(iot, ioh, UART_FR);
+ while (tp->t_outq.c_cc != 0 && ISSET(fr, UART_FR_TXFE)) {
bus_space_write_4(iot, ioh, UART_DR, getc(&tp->t_outq));
+ fr = bus_space_read_4(iot, ioh, UART_FR);
}
-
out:
splx(s);
}