-/* $OpenBSD: if_de.c,v 1.16 1996/12/19 12:49:53 mickey Exp $ */
+/* $OpenBSD: if_de.c,v 1.17 1997/04/10 16:33:05 pefo Exp $ */
/* $NetBSD: if_de.c,v 1.29 1996/10/25 21:33:30 cgd Exp $ */
/*-
#if defined(__NetBSD__) || defined(__OpenBSD__)
#include <machine/bus.h>
#include <machine/intr.h>
+#if defined(__mips__)
+#include <machine/cpu.h>
+#endif
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
* but we gone to directly DMA'ing into MBUFs because with 100Mb
* cards the copying is just too much of a hit.
*/
-#if defined(__alpha__)
+#if defined(__alpha__) || defined(__mips__)
#define TULIP_COPY_RXDATA 1
#endif
TULIP_DC21140_COGENT_EM100,
TULIP_DC21140_ZNYX_ZX34X,
TULIP_DC21041_GENERIC,
+ TULIP_DC21041_P4032,
TULIP_DC21041_DE450
} tulip_board_t;
tulip_dc21041_media_probe,
tulip_dc21041_media_select
};
+
+#if defined(__mips__)
+static void
+tulip_p4032_media_select(
+ tulip_softc_t * const sc)
+{
+ /* This board is AUI only! */
+ sc->tulip_media = TULIP_MEDIA_AUI;
+ sc->tulip_probe_state = TULIP_PROBE_INACTIVE;
+
+ sc->tulip_cmdmode |= TULIP_CMD_CAPTREFFCT|TULIP_CMD_ENHCAPTEFFCT
+ /* |TULIP_CMD_FULLDUPLEX */ |TULIP_CMD_THRSHLD160;
+ TULIP_WRITE_CSR(sc, csr_command, sc->tulip_cmdmode);
+
+ sc->tulip_intrmask |= TULIP_STS_NORMALINTR
+ |TULIP_STS_ABNRMLINTR|TULIP_STS_LINKPASS|TULIP_STS_LINKFAIL;
+ TULIP_WRITE_CSR(sc, csr_intr, sc->tulip_intrmask);
+
+ TULIP_WRITE_CSR(sc, csr_sia_connectivity, TULIP_SIACONN_RESET);
+ TULIP_WRITE_CSR(sc, csr_sia_tx_rx, TULIP_DC21041_SIATXRX_AUI);
+ TULIP_WRITE_CSR(sc, csr_sia_general, TULIP_DC21041_SIAGEN_AUI);
+ TULIP_WRITE_CSR(sc, csr_sia_connectivity, TULIP_DC21041_SIACONN_AUI);
+ DELAY(10000); /* Wait 10 millisecs */
+}
+
+
+static const tulip_boardsw_t tulip_p4032_boardsw = {
+ TULIP_DC21041_P4032,
+ "P4032 ",
+ tulip_dc21041_media_probe,
+ tulip_p4032_media_select
+};
+#endif
+
\f
static void
tulip_reset(
sc->tulip_intrmask = 0;
TULIP_WRITE_CSR(sc, csr_intr, sc->tulip_intrmask);
- TULIP_WRITE_CSR(sc, csr_txlist, vtophys(&sc->tulip_txinfo.ri_first[0]));
- TULIP_WRITE_CSR(sc, csr_rxlist, vtophys(&sc->tulip_rxinfo.ri_first[0]));
+ TULIP_WRITE_CSR(sc, csr_txlist, vtophys(&sc->tulip_txinfo.ri_first[0]) | 0xc0000000);
+ TULIP_WRITE_CSR(sc, csr_rxlist, vtophys(&sc->tulip_rxinfo.ri_first[0]) | 0xc0000000);
TULIP_WRITE_CSR(sc, csr_busmode,
(1 << (TULIP_BURSTSIZE(sc->tulip_unit) + 8))
- |TULIP_BUSMODE_CACHE_ALIGN8
+ |TULIP_BUSMODE_CACHE_ALIGN8|TULIP_BUSMODE_BURSTLEN_8LW /*XXX*/
|(BYTE_ORDER != LITTLE_ENDIAN ? TULIP_BUSMODE_BIGENDIAN : 0));
sc->tulip_txq.ifq_maxlen = TULIP_TXDESCS;
ri = &sc->tulip_txinfo;
ri->ri_nextin = ri->ri_nextout = ri->ri_first;
ri->ri_free = ri->ri_max;
- for (di = ri->ri_first; di < ri->ri_last; di++)
+ for (di = ri->ri_first; di < ri->ri_last; di++) {
di->d_status = 0;
+ }
/*
* We need to collect all the mbufs were on the
if (sc->tulip_rxq.ifq_len < TULIP_RXQ_TARGET)
goto queue_mbuf;
- if (((volatile tulip_desc_t *) eop)->d_status & TULIP_DSTS_OWNER)
+ if (((volatile tulip_desc_t *) eop)->d_status & TULIP_DSTS_OWNER) {
return;
+ }
/*
* It is possible (though improbable unless the BIG_PACKET support
while ((((volatile tulip_desc_t *) eop)->d_status & TULIP_DSTS_RxLASTDESC) == 0) {
if (++eop == ri->ri_last)
eop = ri->ri_first;
- if (((volatile tulip_desc_t *) eop)->d_status & TULIP_DSTS_OWNER)
+ if (((volatile tulip_desc_t *) eop)->d_status & TULIP_DSTS_OWNER) {
return;
+ }
total_len++;
}
*/
do {
ri->ri_nextout->d_length1 = TULIP_RX_BUFLEN;
- ri->ri_nextout->d_addr1 = vtophys(mtod(ms, caddr_t));
+ ri->ri_nextout->d_addr1 = vtophys(mtod(ms, caddr_t)) | 0xc0000000;
ri->ri_nextout->d_status = TULIP_DSTS_OWNER;
+#if defined(__mips__)
+ R4K_HitFlushDCache(mtod(ms, caddr_t),TULIP_RX_BUFLEN);
+#endif
if (++ri->ri_nextout == ri->ri_last)
ri->ri_nextout = ri->ri_first;
me = ms->m_next;
ri->ri_nextout->d_flag &= TULIP_DFLAG_ENDRING|TULIP_DFLAG_CHAIN;
ri->ri_nextout->d_flag |= TULIP_DFLAG_TxFIRSTSEG|TULIP_DFLAG_TxLASTSEG
|TULIP_DFLAG_TxSETUPPKT|TULIP_DFLAG_TxWANTINTR;
+#if defined(__mips__)
+ R4K_HitFlushDCache(sc->tulip_setupbuf, sizeof(sc->tulip_setupbuf));
+#endif
if (sc->tulip_flags & TULIP_WANTHASH)
ri->ri_nextout->d_flag |= TULIP_DFLAG_TxHASHFILT;
ri->ri_nextout->d_length1 = sizeof(sc->tulip_setupbuf);
- ri->ri_nextout->d_addr1 = vtophys(sc->tulip_setupbuf);
+ ri->ri_nextout->d_addr1 = vtophys(sc->tulip_setupbuf) | 0xc0000000;
ri->ri_nextout->d_length2 = 0;
ri->ri_nextout->d_addr2 = 0;
ri->ri_nextout->d_status = TULIP_DSTS_OWNER;
nextout = ri->ri_first;
eop->d_flag &= TULIP_DFLAG_ENDRING|TULIP_DFLAG_CHAIN;
eop->d_status = d_status;
- eop->d_addr1 = vtophys(addr); eop->d_length1 = slen;
+ eop->d_addr1 = vtophys(addr) | 0xc0000000; eop->d_length1 = slen;
} else {
/*
* Fill in second half of descriptor
*/
- eop->d_addr2 = vtophys(addr); eop->d_length2 = slen;
+ eop->d_addr2 = vtophys(addr) | 0xc0000000; eop->d_length2 = slen;
}
+#if defined(__mips__)
+ R4K_HitFlushDCache(addr, slen);
+#endif
d_status = TULIP_DSTS_OWNER;
len -= slen;
addr += slen;
unsigned char tmpbuf[8];
static const u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
+#if defined(__mips__) /* XXX Oh well */
+ if (sc->tulip_chipid == TULIP_DC21041 && sc->tulip_unit == 0 &&
+ pci_ether_hw_addr(sc->tulip_pc, (u_int8_t *)&sc->tulip_hwaddr) == 0) {
+ sc->tulip_boardsw = &tulip_p4032_boardsw;
+ return 0;
+ }
+#endif
if (sc->tulip_chipid == TULIP_DC21040) {
TULIP_WRITE_CSR(sc, csr_enetrom, 1);
for (idx = 0; idx < 32; idx++) {
tulip_desc_t *descs,
int ndescs)
{
+#if defined(__mips__)
+ R4K_HitFlushDCache(descs, ndescs * sizeof(tulip_desc_t));
+ descs = (tulip_desc_t *)PHYS_TO_UNCACHED(vtophys(descs));
+#endif
ri->ri_max = ndescs;
ri->ri_first = descs;
ri->ri_last = ri->ri_first + ri->ri_max;
-/* $OpenBSD: ncr.c,v 1.26 1997/03/03 00:25:03 millert Exp $ */
+/* $OpenBSD: ncr.c,v 1.27 1997/04/10 16:33:08 pefo Exp $ */
/* $NetBSD: ncr.c,v 1.55 1997/01/10 05:57:10 perry Exp $ */
/**************************************************************************
** (0=asynchronous)
*/
+#define SCSI_NCR_MAX_SYNC 0
#ifndef SCSI_NCR_MAX_SYNC
#define SCSI_NCR_MAX_SYNC (10000)
#endif /* SCSI_NCR_MAX_SYNC */
#include <dev/pci/ncr_reg.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
-#ifndef __alpha__
+#if !defined __alpha__ && !defined __mips__
#define DELAY(x) delay(x)
#endif
#endif /* __NetBSD__ || __OpenBSD__ */
#if 0
static char ident[] =
- "\n$OpenBSD: ncr.c,v 1.26 1997/03/03 00:25:03 millert Exp $\n";
+ "\n$OpenBSD: ncr.c,v 1.27 1997/04/10 16:33:08 pefo Exp $\n";
#endif
static const u_long ncr_version = NCR_VERSION * 11
#else /* !(__NetBSD__ || __OpenBSD__) */
np->script = (struct script *)
malloc (sizeof (struct script), M_DEVBUF, M_WAITOK);
+#if defined(__mips__)
+ R4K_HitFlushDCache(np->script, sizeof (struct script));
+ np->script = (struct script *)PHYS_TO_UNCACHED(vtophys(np->script));
+#endif /* __mips__ */
#endif /* __NetBSD__ || __OpenBSD__ */
np->p_script = vtophys(np->script);
int wide = 0;
u_char rev = pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
+#if defined(__mips__)
+ R4K_HitFlushDCache(np, sizeof (struct ncb));
+ np = (struct ncb *)PHYS_TO_UNCACHED(vtophys(np));
+#endif /* __mips__ */
+
printf(": NCR ");
switch (pa->pa_id) {
case NCR_810_ID:
np->rv_dcntl = INB (nc_dcntl) | CLSE | PFEN | NOCOM;
np->rv_ctest3 = INB (nc_ctest3);
np->rv_ctest5 = 0;
+#if defined(__mips__)
+ np->rv_scntl3 = 0x24; /* default: 67MHz clock */
+#else
np->rv_scntl3 = 0x13; /* default: 40MHz clock */
+#endif
/*
** Do chip dependent initialization.
*/
np->maxwide = 0;
+#if defined(__mips__)
+ np->ns_sync = 22; /* in units of 4ns */
+#else
np->ns_sync = 25; /* in units of 4ns */
+#endif
np->maxoffs = 8;
/*
"succeeded" : "failed");
}
#endif /* NCR_TEKRAM_EEPROM */
- ncr_getclock(np);
break;
}
**----------------------------------------------------
*/
+#if defined(__mips__)
+ if (xp->data && xp->datalen) {
+ R4K_HitFlushDCache(xp->data, xp->datalen);
+ }
+ R4K_HitFlushDCache(xp->cmd, xp->cmdlen);
+ R4K_HitFlushDCache(&xp->sense, sizeof(struct scsi_sense_data));
+#endif /* __mips__ */
+
oldspl = splbio();
if (!(cp=ncr_get_ccb (np, flags, xp->sc_link->target, xp->sc_link->lun))) {
OUTB (nc_scid , RRE|np->myaddr);/* host adapter SCSI address */
OUTW (nc_respid, 1ul<<np->myaddr);/* id to respond to */
OUTB (nc_istat , SIGP ); /* Signal Process */
- OUTB (nc_dmode , np->rv_dmode); /* XXX modify burstlen ??? */
+ OUTB (nc_dmode , 0x80 /*np->rv_dmode*/);/* XXX modify burstlen ??? */
OUTB (nc_dcntl , np->rv_dcntl);
OUTB (nc_ctest3, np->rv_ctest3);
OUTB (nc_ctest5, np->rv_ctest5);
OUTB (nc_ctest4, MPEE ); /* enable master parity checking */
+#if defined(__mips__)
+ OUTB (nc_stest1, 0x80 ); /* Disable external SCSI clock */
+#endif
OUTB (nc_stest2, EXT ); /* Extended Sreq/Sack filtering */
OUTB (nc_stest3, TE ); /* TolerANT enable */
OUTB (nc_stime0, 0x0b ); /* HTH = disabled, STO = 0.1 sec. */
if (SCSI_NCR_MAX_SYNC) {
u_long period;
period =1000000/SCSI_NCR_MAX_SYNC; /* ns = 10e6 / kHz */
+
+ /* Don't negotiate a period that we cant't handle !!! */
+ if(period % np->ns_sync) {
+ period = ((period / np->ns_sync) + 1) * np->ns_sync;
+ }
+
if (period <= 11 * np->ns_sync) {
if (period < 4 * np->ns_sync)
usrsync = np->ns_sync;
lp = (lcb_p) malloc (sizeof (struct lcb), M_DEVBUF, M_NOWAIT);
if (!lp) return;
+#if defined(__mips__)
+ R4K_HitFlushDCache(lp, sizeof (struct lcb));
+ lp = (struct lcb *)PHYS_TO_UNCACHED(vtophys(lp));
+#endif /* __mips__ */
/*
** Initialize it
*/
** Allocate a ccb
*/
cp = (ccb_p) malloc (sizeof (struct ccb), M_DEVBUF, M_NOWAIT);
-
if (!cp)
return;
+#if defined(__mips__)
+ R4K_HitFlushDCache(cp, sizeof (struct ccb));
+ cp = (struct ccb *)PHYS_TO_UNCACHED(vtophys(cp));
+#endif /* __mips__ */
+
if (DEBUG_FLAGS & DEBUG_ALLOC) {
printf ("new ccb @%p.\n", cp);
}
** Set memory and register.
*/
ncr_cache = host_wr;
+#if defined(__mips__)
+ R4K_HitFlushDCache(&ncr_cache, sizeof (ncr_cache));
+#endif /* __mips__ */
OUTL (nc_temp, ncr_wr);
/*
** Start script (exchange values)