drm/amd/display: Do not update DRR while BW optimizations pending

From Aric Cyr
a905b0b318ad7d37c3041573454129923e0a0723 in linux-6.1.y/6.1.38
32953485c558cecf08f33fbfa251e80e44cef981 in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
index 2e93693..277ccee 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
+++ b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
@@ -401,6 +401,13 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 {
        int i;
 
+       /*
+        * Don't adjust DRR while there's bandwidth optimizations pending to
+        * avoid conflicting with firmware updates.
+        */
+       if (dc->optimized_required || dc->wm_optimized_required)
+               return false;
+
        stream->adjust.v_total_max = adjust->v_total_max;
        stream->adjust.v_total_mid = adjust->v_total_mid;
        stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
@@ -2021,27 +2028,33 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
 
        post_surface_trace(dc);
 
-       if (dc->ctx->dce_version >= DCE_VERSION_MAX)
-               TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
-       else
+       /*
+        * Only relevant for DCN behavior where we can guarantee the optimization
+        * is safe to apply - retain the legacy behavior for DCE.
+        */
+
+       if (dc->ctx->dce_version < DCE_VERSION_MAX)
                TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
+       else {
+               TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
 
-       if (is_flip_pending_in_pipes(dc, context))
-               return;
+               if (is_flip_pending_in_pipes(dc, context))
+                       return;
 
-       for (i = 0; i < dc->res_pool->pipe_count; i++)
-               if (context->res_ctx.pipe_ctx[i].stream == NULL ||
-                   context->res_ctx.pipe_ctx[i].plane_state == NULL) {
-                       context->res_ctx.pipe_ctx[i].pipe_idx = i;
-                       dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
-               }
+               for (i = 0; i < dc->res_pool->pipe_count; i++)
+                       if (context->res_ctx.pipe_ctx[i].stream == NULL ||
+                                       context->res_ctx.pipe_ctx[i].plane_state == NULL) {
+                               context->res_ctx.pipe_ctx[i].pipe_idx = i;
+                               dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
+                       }
 
-       process_deferred_updates(dc);
+               process_deferred_updates(dc);
 
-       dc->hwss.optimize_bandwidth(dc, context);
+               dc->hwss.optimize_bandwidth(dc, context);
 
-       if (dc->debug.enable_double_buffered_dsc_pg_support)
-               dc->hwss.update_dsc_pg(dc, context, true);
+               if (dc->debug.enable_double_buffered_dsc_pg_support)
+                       dc->hwss.update_dsc_pg(dc, context, true);
+       }
 
        dc->optimized_required = false;
        dc->wm_optimized_required = false;
@@ -3866,12 +3879,9 @@ void dc_commit_updates_for_stream(struct dc *dc,
                        if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
                                new_pipe->plane_state->force_full_update = true;
                }
-       } else if (update_type == UPDATE_TYPE_FAST && dc_ctx->dce_version >= DCE_VERSION_MAX) {
+       } else if (update_type == UPDATE_TYPE_FAST) {
                /*
                 * Previous frame finished and HW is ready for optimization.
-                *
-                * Only relevant for DCN behavior where we can guarantee the optimization
-                * is safe to apply - retain the legacy behavior for DCE.
                 */
                dc_post_update_surfaces_to_stream(dc);
        }