-# $OpenBSD: files.sparc64,v 1.155 2022/12/14 23:50:31 jsg Exp $
+# $OpenBSD: files.sparc64,v 1.156 2024/03/29 21:11:31 miod Exp $
# $NetBSD: files.sparc64,v 1.50 2001/08/10 20:53:50 eeh Exp $
# maxpartitions must be first item in files.${ARCH}
file arch/sparc64/sparc64/autoconf.c
file arch/sparc64/sparc64/busop.c
-file arch/sparc64/sparc64/cache.c
file arch/sparc64/sparc64/conf.c
file arch/sparc64/sparc64/disksubr.c
file arch/sparc64/sparc64/emul.c
+++ /dev/null
-/* $OpenBSD: cache.c,v 1.5 2022/10/16 01:22:39 jsg Exp $ */
-/* $NetBSD: cache.c,v 1.5 2000/12/06 01:47:50 mrg Exp $ */
-
-/*
- * Copyright (c) 1996
- * The President and Fellows of Harvard College. All rights reserved.
- * Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * This software was developed by the Computer Systems Engineering group
- * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
- * contributed to Berkeley.
- *
- * All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Harvard University.
- * This product includes software developed by the University of
- * California, Lawrence Berkeley Laboratory.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Aaron Brown and
- * Harvard University.
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)cache.c 8.2 (Berkeley) 10/30/93
- *
- */
-
-/*
- * Cache routines.
- *
- * UltraSPARC has VIPT D$ and PIPT I$.
- *
- * TODO:
- * - rework range flush
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-
-#include <machine/ctlreg.h>
-#include <machine/pte.h>
-
-#include <sparc64/sparc64/cache.h>
-
-enum vactype vactype;
-struct cachestats cachestats;
-int cachedebug = 0;
-
-/*
- * Enable the cache.
- * The prom does this for us.
- */
-void
-cache_enable(void)
-{
- /*
- * No point in implementing this unless we have a cache_disable().
- * Anyway, sun4u ECC is generated in the E$, so we can't disable that
- * and expect to use any RAM.
- */
- cacheinfo.c_enabled = 1; /* enable cache flushing */
-}
-
-/*
- * Flush the given virtual page from the cache.
- * (va is the actual address, and must be aligned on a page boundary.)
- * To get the E$ we read to each cache line.
- */
-int
-cache_flush_page(paddr_t pa)
-{
- register int i, j, ls;
- register char *p;
- register int *kp;
-
-#ifdef DEBUG
- if (cachedebug)
- printf("cache_flush_page %llx\n", (unsigned long long)pa);
- if (pa & PGOFSET)
- panic("cache_flush_page: asked to flush misaligned pa %llx", (unsigned long long)pa);
-#endif
-
- /* Don't flush if not enabled or not probed. */
- if (!cacheinfo.c_enabled) return 0;
-
- cachestats.cs_npgflush++;
- p = (char *)(u_long)pa;
- ls = cacheinfo.c_linesize;
- i = NBPG >> cacheinfo.dc_l2linesize;
- /* Assume E$ takes care of itself*/
- kp = (int *)(u_long)((pa & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
- j = 0; /* defeat optimizer? */
- for (; --i >= 0; p += ls) {
- flush(p); /* Take care of I$. */
- j += kp[i]; /* Take care of E$. */
- }
- return j;
-}
-
-/*
- * Flush a range of virtual addresses (in the current context).
- * The first byte is at (base&~PGOFSET) and the last one is just
- * before byte (base+len).
- *
- * We may need to get more complex if we need to flush E$ because
- * the virtual color may not match the physical color. Assume cache
- * coherence is handled by H/W.
- */
-
-#define CACHE_FLUSH_MAGIC (cacheinfo.ec_totalsize / NBPG)
-
-int
-cache_flush(vaddr_t base, size_t len)
-{
- int i, j, ls;
- vaddr_t baseoff;
- char *p;
- int *kp;
-
-#ifdef DEBUG
- if (cachedebug)
- printf("cache_flush %p %x\n", (void *)(u_long)base, (u_int)len);
-#endif
-
- /* Don't flush if not enabled or not probed. */
- if (!cacheinfo.c_enabled) return 0;
-
- baseoff = (vaddr_t)base & PGOFSET;
- i = (baseoff + len + PGOFSET) >> PGSHIFT;
-
- cachestats.cs_nraflush++;
-
- i = min(i,CACHE_FLUSH_MAGIC);
-
- p = (char *)((vaddr_t)base & ~baseoff);
- ls = cacheinfo.dc_linesize;
- i >>= cacheinfo.dc_l2linesize;
- /* Pick right physical color for E$ */
- kp = (int *)(((vaddr_t)p & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
- j = 0; /* defeat optimizer? */
- for (; --i >= 0; p += ls) {
- flush(p); /* Take care of I$. */
- j += kp[i]; /* Take care of E$. */
- }
- return j;
-}
-/* $OpenBSD: cache.h,v 1.6 2008/03/30 12:30:01 kettenis Exp $ */
+/* $OpenBSD: cache.h,v 1.7 2024/03/29 21:11:32 miod Exp $ */
/* $NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp $ */
/*
* @(#)cache.h 8.1 (Berkeley) 6/11/93
*/
-enum vactype { VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK };
-
-extern enum vactype vactype; /* XXX move into cacheinfo struct */
-
/*
- * Cache tags can be written in control space, and must be set to 0
- * (or invalid anyway) before turning on the cache. The tags are
- * addressed as an array of 32-bit structures of the form:
- *
- * struct cache_tag {
- * u_int :7, (unused; must be zero)
- * ct_cid:3, (context ID)
- * ct_w:1, (write flag from PTE)
- * ct_s:1, (supervisor flag from PTE)
- * ct_v:1, (set => cache entry is valid)
- * :3, (unused; must be zero)
- * ct_tid:14, (cache tag ID)
- * :2; (unused; must be zero)
- * };
- *
- * The SPARCstation 1 cache sees virtual addresses as:
- *
- * struct cache_va {
- * u_int :2, (unused; probably copies of va_tid<13>)
- * cva_tid:14, (tag ID)
- * cva_line:12, (cache line number)
- * cva_byte:4; (byte in cache line)
- * };
- *
- * (The SS2 cache is similar but has half as many lines, each twice as long.)
- *
- * Note that, because the 12-bit line ID is `wider' than the page offset,
- * it is possible to have one page map to two different cache lines.
- * This can happen whenever two different physical pages have the same bits
- * in the part of the virtual address that overlaps the cache line ID, i.e.,
- * bits <15:12>. In order to prevent cache duplication, we have to
- * make sure that no one page has more than one virtual address where
- * (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v
- * when a cache miss occurs on a write, i.e., if va1 is in the cache and
- * va2 is not, and you write to va2, va1 goes out of the cache. If va1
- * is in the cache and va2 is not, reading va2 also causes va1 to become
- * uncached, and the [same] data is then read from main memory into the
- * cache.)
- *
- * The other alternative, of course, is to disable caching of aliased
- * pages. (In a few cases this might be faster anyway, but we do it
- * only when forced.)
- *
- * The Sun4, since it has an 8K pagesize instead of 4K, needs to check
- * bits that are one position higher.
- */
-
-/*
- * The spitfire has a 16K two-way set associative level-1 I$ and a separate
- * 16K level-1 D$. The I$ can be invalidated using the FLUSH instructions,
+ * The spitfire has a 16K two-way set associative level-1 I$ and a separate
+ * 16K level-1 D$. The I$ can be invalidated using the FLUSH instructions,
* so we don't really need to worry about it much. The D$ is 16K write-through
- * direct mapped virtually addressed cache with two 16-byte sub-blocks per line.
- * The E$ is a 512KB-4MB direct mapped physically indexed physically tagged cache.
- * Since the level-1 caches are write-through, they don't need flushing and can be
- * invalidated directly.
+ * direct mapped virtually addressed cache with two 16-byte sub-blocks per line.
+ * The E$ is a 512KB-4MB direct mapped physically indexed physically tagged
+ * cache.
+ * Since the level-1 caches are write-through, they don't need flushing and can
+ * be invalidated directly.
*
* The spitfire sees virtual addresses as:
*
* struct cache_va {
- * u_int64_t :22, (unused; we only have 40-bit addresses)
- * cva_tag:28, (tag ID)
- * cva_line:9, (cache line number)
- * cva_byte:5; (byte within line)
+ * u_int64_t :22, (unused; we only have 40-bit addresses)
+ * cva_tag:28, (tag ID)
+ * cva_line:9, (cache line number)
+ * cva_byte:5; (byte within line)
* };
*
* Since there is one bit of overlap between the page offset and the line index,
- * all we need to do is make sure that bit 14 of the va remains constant and we have
- * no aliasing problems.
+ * all we need to do is make sure that bit 14 of the va remains constant and we
+ * have no aliasing problems.
*
- * Let me try again. Page size is 8K, cache size is 16K so if (va1&0x3fff != va2&0x3fff)
- * we have a problem. Bit 14 *must* be the same for all mappings of a page to be cacheable
- * in the D$. (The I$ is 16K 2-way associative--each bank is 8K. No conflict there.)
+ * Let me try again. Page size is 8K, cache size is 16K so if (va1&0x3fff !=
+ * va2&0x3fff) we have a problem. Bit 14 *must* be the same for all mappings
+ * of a page to be cacheable in the D$. (The I$ is 16K 2-way associative--each
+ * bank is 8K. No conflict there.)
*/
-/* Some more well-known values: */
-#define CACHE_ALIAS_MASK 0x7fff
-#define CACHE_ALIAS_BITS 0x4000
-
-/*
- * True iff a1 and a2 are `bad' aliases (will cause cache duplication).
- */
-#define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & CACHE_ALIAS_BITS)
-
/*
* Routines for dealing with the cache.
*/
-void cache_enable(void); /* turn it on */
-int cache_flush_page(paddr_t); /* flush page from E$ */
-int cache_flush(vaddr_t, vsize_t); /* flush region */
/* The following are for D$ flushes and are in locore.s */
#define dcache_flush_page(pa) cacheinfo.c_dcache_flush_page(pa)
/* The following flush a range from the D$ and I$ but not E$. */
void cache_flush_virt(vaddr_t, vsize_t);
-void cache_flush_phys(paddr_t, psize_t, int);
/*
* Cache control information.
struct cacheinfo {
void (*c_dcache_flush_page)(paddr_t);
- int c_totalsize; /* total size, in bytes */
- /* if split, MAX(icache,dcache) */
- int c_enabled; /* true => cache is enabled */
- int c_hwflush; /* true => have hardware flush */
- int c_linesize; /* line size, in bytes */
- int c_l2linesize; /* log2(linesize) */
- int c_physical; /* true => cache is physical */
- int c_split; /* true => cache is split */
int ic_totalsize; /* instruction cache */
- int ic_enabled;
int ic_linesize;
- int ic_l2linesize;
int dc_totalsize; /* data cache */
- int dc_enabled;
int dc_linesize;
- int dc_l2linesize;
int ec_totalsize; /* external cache info */
- int ec_enabled;
int ec_linesize;
- int ec_l2linesize;
};
extern struct cacheinfo cacheinfo;
-
-/*
- * Cache control statistics.
- */
-struct cachestats {
- int cs_npgflush; /* # page flushes */
- int cs_nraflush; /* # range flushes */
-#ifdef notyet
- int cs_ra[65]; /* pages/range */
-#endif
-};
-/* $OpenBSD: cpu.c,v 1.75 2023/10/24 13:20:10 claudio Exp $ */
+/* $OpenBSD: cpu.c,v 1.76 2024/03/29 21:11:32 miod Exp $ */
/* $NetBSD: cpu.c,v 1.13 2001/05/26 21:27:15 chs Exp $ */
/*
#include <sparc64/dev/starfire.h>
-/* This is declared here so that you must include a CPU for the cache code. */
struct cacheinfo cacheinfo = {
- us_dcache_flush_page
+ .c_dcache_flush_page = us_dcache_flush_page
};
void (*cpu_start_clock)(void);
if (ci->ci_upaid == cpu_myid())
cpu_init(ci);
- cacheinfo.c_physical = 1; /* Dunno... */
- cacheinfo.c_split = 1;
l = getpropint(node, "icache-line-size", 0);
if (l == 0)
l = getpropint(node, "l1-icache-line-size", 0);
/* void */;
if ((1 << i) != l && l)
panic("bad icache line size %d", l);
- cacheinfo.ic_l2linesize = i;
cacheinfo.ic_totalsize = getpropint(node, "icache-size", 0);
if (cacheinfo.ic_totalsize == 0)
cacheinfo.ic_totalsize = getpropint(node, "l1-icache-size", 0);
/* void */;
if ((1 << i) != l && l)
panic("bad dcache line size %d", l);
- cacheinfo.dc_l2linesize = i;
cacheinfo.dc_totalsize = getpropint(node, "dcache-size", 0);
if (cacheinfo.dc_totalsize == 0)
cacheinfo.dc_totalsize = getpropint(node, "l1-dcache-size", 0);
/* void */;
if ((1 << i) != l && l)
panic("bad ecache line size %d", l);
- cacheinfo.ec_l2linesize = i;
cacheinfo.ec_totalsize = getpropint(node, "ecache-size", 0);
if (cacheinfo.ec_totalsize == 0)
cacheinfo.ec_totalsize = getpropint(node, "l2-cache-size", 0);
* XXX - The following will have to do until
* we have per-cpu cache handling.
*/
- cacheinfo.c_l2linesize =
- min(cacheinfo.ic_l2linesize,
- cacheinfo.dc_l2linesize);
- cacheinfo.c_linesize =
- min(cacheinfo.ic_linesize,
- cacheinfo.dc_linesize);
- cacheinfo.c_totalsize =
- cacheinfo.ic_totalsize +
- cacheinfo.dc_totalsize;
-
- if (cacheinfo.c_totalsize == 0)
+ if (cacheinfo.ic_totalsize + cacheinfo.dc_totalsize == 0)
return;
sep = " ";
#endif
printf("\n");
- cache_enable();
}
int
-/* $OpenBSD: locore.s,v 1.206 2024/03/29 21:09:04 miod Exp $ */
+/* $OpenBSD: locore.s,v 1.207 2024/03/29 21:11:32 miod Exp $ */
/* $NetBSD: locore.s,v 1.137 2001/08/13 06:10:10 jdolecek Exp $ */
/*
FTYPE(us_dcache_flush_page)
us_dcache_flush_page:
- !! Try using cache_flush_phys for a change.
-
mov -1, %o1 ! Generate mask for tag: bits [29..2]
srlx %o0, 13-2, %o2 ! Tag is VA bits <40:13> in bits <29:2>
clr %o4
nop
END(cache_flush_virt)
-/*
- * cache_flush_phys(paddr_t, psize_t, int);
- *
- * Clear a set of paddrs from the D$ and if param3 is
- * non-zero, E$. (E$ is not supported yet).
- */
-
- .align 8
- .globl cache_flush_phys
- .proc 1
- FTYPE(cache_flush_phys)
-cache_flush_phys:
-#ifdef DEBUG
- tst %o2 ! Want to clear E$?
- tnz 1 ! Error!
-#endif /* DEBUG */
- add %o0, %o1, %o1 ! End PA
-
- !!
- !! D$ tags match pa bits 40-13.
- !! Generate a mask for them.
- !!
-
- mov -1, %o2 ! Generate mask for tag: bits [40..13]
- srl %o2, 5, %o2 ! 32-5 = [27..0]
- sllx %o2, 13, %o2 ! 27+13 = [40..13]
-
- and %o2, %o0, %o0 ! Mask away uninteresting bits
- and %o2, %o1, %o1 ! (probably not necessary)
-
- set (2*NBPG), %o5
- clr %o4
-1:
- ldxa [%o4] ASI_DCACHE_TAG, %o3
- sllx %o3, 40-29, %o3 ! Shift D$ tag into place
- and %o3, %o2, %o3 ! Mask out trash
- cmp %o0, %o3
- blt,pt %xcc, 2f ! Too low
- cmp %o1, %o3
- bgt,pt %xcc, 2f ! Too high
- nop
-
- membar #LoadStore
-dlflush4:
- stxa %g0, [%o4] ASI_DCACHE_TAG ! Just right
-2:
- membar #StoreLoad
- dec 16, %o5
- brgz,pt %o5, 1b
- inc 16, %o4
-
- sethi %hi(KERNBASE), %o5
- flush %o5
- membar #Sync
- retl
- nop
-END(cache_flush_phys)
-
/*
* XXXXX Still needs lotsa cleanup after sendsig is complete and offsets are known
*
dec 8, %o2
stxa %g0, [%o0] ASI_PHYS_CACHED
inc 8, %o0
-dlflush5:
+dlflush4:
stxa %g0, [%o1] ASI_DCACHE_TAG
brgz %o2, 1b
inc 16, %o1
.xword dlflush2
.xword dlflush3
.xword dlflush4
- .xword dlflush5
.xword 0
-/* $OpenBSD: machdep.c,v 1.211 2024/03/29 21:09:49 miod Exp $ */
+/* $OpenBSD: machdep.c,v 1.212 2024/03/29 21:11:32 miod Exp $ */
/* $NetBSD: machdep.c,v 1.108 2001/07/24 19:30:14 eeh Exp $ */
/*-
#include <machine/openfirm.h>
#include <machine/sparc64.h>
-#include <sparc64/sparc64/cache.h>
-
#include "pckbc.h"
#include "pckbd.h"
#if (NPCKBC > 0) && (NPCKBD == 0)
-/* $OpenBSD: pmap.c,v 1.112 2024/03/29 21:06:14 miod Exp $ */
+/* $OpenBSD: pmap.c,v 1.113 2024/03/29 21:11:32 miod Exp $ */
/* $NetBSD: pmap.c,v 1.107 2001/08/31 16:47:41 eeh Exp $ */
/*
*
#include <machine/openfirm.h>
#include <machine/kcore.h>
-#include "cache.h"
+#include <sparc64/sparc64/cache.h>
#ifdef DDB
#include <machine/db_machdep.h>
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