-/* $OpenBSD: conf.c,v 1.14 1996/10/19 13:26:03 mickey Exp $ */
+/* $OpenBSD: conf.c,v 1.15 1996/11/28 23:33:02 niklas Exp $ */
/* $NetBSD: conf.c,v 1.36 1996/05/19 21:04:18 veego Exp $ */
/*-
return (makedev(blkmaj, minor(dev)));
}
+/*
+ * Convert a character device number to a block device number.
+ */
+dev_t
+blktochr(dev)
+ dev_t dev;
+{
+ int blkmaj = major(dev);
+ int i;
+
+ if (blkmaj >= nblkdev)
+ return (NODEV);
+ for (i = 0; i < sizeof(chrtoblktab)/sizeof(chrtoblktab[0]); i++)
+ if (blkmaj == chrtoblktab[i])
+ return (makedev(i, minor(dev)));
+ return (NODEV);
+}
+
/*
* This entire table could be autoconfig()ed but that would mean that
* the kernel's idea of the console would be out of sync with that of
-/* $OpenBSD: trap.c,v 1.6 1996/06/07 05:18:40 niklas Exp $ */
+/* $OpenBSD: trap.c,v 1.7 1996/11/28 23:33:03 niklas Exp $ */
/* $NetBSD: trap.c,v 1.47 1996/05/10 14:31:08 is Exp $ */
/*
type, code);
panictrap(type, code, v, fp);
}
- trapsignal(p, (rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV, v);
+ trapsignal(p, SIGSEGV, v);
if ((type & T_USER) == 0)
return;
userret(p, fp->f_pc, sticks);
-# $OpenBSD: FILIPPA,v 1.10 1996/09/20 06:44:55 deraadt Exp $
+# $OpenBSD: FILIPPA,v 1.11 1996/11/28 23:33:04 niklas Exp $
#
# Niklas' AMIGA with ISA support
ggbus* at zbus0 # Goldengate bridge
isa* at ggbus?
-cross* at zbus0 # CrossLink bridge
-isa* at cross?
+#cross* at zbus0 # CrossLink bridge
+#isa* at cross?
com0 at isa? port 0x3f8 irq 4 # Standard PC serial ports
com1 at isa? port 0x2f8 irq 3
-/* $OpenBSD: bus.h,v 1.2 1996/08/04 01:34:38 niklas Exp $ */
+/* $OpenBSD: bus.h,v 1.3 1996/11/28 23:33:05 niklas Exp $ */
/*
* Copyright (c) 1996 Niklas Hallqvist.
* SUCH DAMAGE.
*/
-#ifndef _MACHINE_BUS_H_
-#define _MACHINE_BUS_H_
+#ifndef _AMIGA_BUS_H_
+#define _AMIGA_BUS_H_
-/* I/O access types. */
-typedef u_long bus_io_addr_t;
-typedef u_long bus_io_size_t;
-typedef u_long bus_io_handle_t;
+#ifdef __STDC__
+#define CAT(a,b) a##b
+#define CAT3(a,b,c) a##b##c
+#else
+#define CAT(a,b) a/**/b
+#define CAT3(a,b,c) a/**/b/**/c
+#endif
-/* Memory access types. */
-typedef u_long bus_mem_addr_t;
-typedef u_long bus_mem_size_t;
-typedef u_long bus_mem_handle_t;
+/* Bus access types. */
+typedef u_int32_t bus_addr_t;
+typedef u_int32_t bus_size_t;
+typedef u_int32_t bus_space_handle_t;
-/*
- * The big switch, that delegates each bus operation to the right
- * implementation.
- */
-typedef struct amiga_bus_chipset *bus_chipset_tag_t;
-
-struct amiga_bus_chipset {
- void *bc_data;
-
- int (*bc_io_map)(bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t,
- bus_io_handle_t *);
- int (*bc_io_unmap)(bus_io_handle_t, bus_io_size_t);
-
- u_int8_t (*bc_io_read_1)(bus_io_handle_t, bus_io_size_t);
- u_int16_t (*bc_io_read_2)(bus_io_handle_t, bus_io_size_t);
- u_int32_t (*bc_io_read_4)(bus_io_handle_t, bus_io_size_t);
- u_int64_t (*bc_io_read_8)(bus_io_handle_t, bus_io_size_t);
-
- void (*bc_io_read_multi_1)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
- void (*bc_io_read_multi_2)(bus_io_handle_t, bus_io_size_t,
- u_int16_t *, bus_io_size_t);
- void (*bc_io_read_multi_4)(bus_io_handle_t, bus_io_size_t,
- u_int32_t *, bus_io_size_t);
- void (*bc_io_read_multi_8)(bus_io_handle_t, bus_io_size_t,
- u_int64_t *, bus_io_size_t);
-
- void (*bc_io_write_1)(bus_io_handle_t, bus_io_size_t, u_int8_t);
- void (*bc_io_write_2)(bus_io_handle_t, bus_io_size_t, u_int16_t);
- void (*bc_io_write_4)(bus_io_handle_t, bus_io_size_t, u_int32_t);
- void (*bc_io_write_8)(bus_io_handle_t, bus_io_size_t, u_int64_t);
-
- void (*bc_io_write_multi_1)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
- void (*bc_io_write_multi_2)(bus_io_handle_t, bus_io_size_t,
- const u_int16_t *, bus_io_size_t);
- void (*bc_io_write_multi_4)(bus_io_handle_t, bus_io_size_t,
- const u_int32_t *, bus_io_size_t);
- void (*bc_io_write_multi_8)(bus_io_handle_t, bus_io_size_t,
- const u_int64_t *, bus_io_size_t);
-
- int (*bc_mem_map)(bus_chipset_tag_t, bus_mem_addr_t,
- bus_mem_size_t, int, bus_mem_handle_t *);
- int (*bc_mem_unmap)(bus_mem_handle_t, bus_mem_size_t);
-
- u_int8_t (*bc_mem_read_1)(bus_mem_handle_t, bus_mem_size_t);
- u_int16_t (*bc_mem_read_2)(bus_mem_handle_t, bus_mem_size_t);
- u_int32_t (*bc_mem_read_4)(bus_mem_handle_t, bus_mem_size_t);
- u_int64_t (*bc_mem_read_8)(bus_mem_handle_t, bus_mem_size_t);
-
- void (*bc_mem_write_1)(bus_mem_handle_t, bus_mem_size_t, u_int8_t);
- void (*bc_mem_write_2)(bus_mem_handle_t, bus_mem_size_t, u_int16_t);
- void (*bc_mem_write_4)(bus_mem_handle_t, bus_mem_size_t, u_int32_t);
- void (*bc_mem_write_8)(bus_mem_handle_t, bus_mem_size_t, u_int64_t);
-
- /* These are extensions to the general NetBSD bus interface. */
- void (*bc_io_read_raw_multi_2)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
- void (*bc_io_read_raw_multi_4)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
- void (*bc_io_read_raw_multi_8)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
-
- void (*bc_io_write_raw_multi_2)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
- void (*bc_io_write_raw_multi_4)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
- void (*bc_io_write_raw_multi_8)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
+typedef struct amiga_bus_space *bus_space_tag_t;
+
+struct amiga_bus_space {
+ void *bs_data;
+
+ int (*bs_map)(bus_space_tag_t, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *);
+ int (*bs_unmap)(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+
+ /* We need swapping of 16-bit entities */
+ int bs_swapped;
};
-#define bus_io_map(t, port, size, iohp) \
- (*(t)->bc_io_map)((t), (port), (size), (iohp))
-#define bus_io_unmap(t, iohp, size) \
- (*(t)->bc_io_unmap)((iohp), (size))
-
-#define bus_io_read_1(t, h, o) \
- (*(t)->bc_io_read_1)((h), (o))
-#define bus_io_read_2(t, h, o) \
- (*(t)->bc_io_read_2)((h), (o))
-#define bus_io_read_4(t, h, o) \
- (*(t)->bc_io_read_4)((h), (o))
-#define bus_io_read_8(t, h, o) \
- (*(t)->bc_io_read_8)((h), (o))
-
-#define bus_io_read_multi_1(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_1)((h), (o), (a), (s))
-#define bus_io_read_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_2)((h), (o), (a), (s))
-#define bus_io_read_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_4)((h), (o), (a), (s))
-#define bus_io_read_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_8)((h), (o), (a), (s))
-
-#define bus_io_write_1(t, h, o, v) \
- (*(t)->bc_io_write_1)((h), (o), (v))
-#define bus_io_write_2(t, h, o, v) \
- (*(t)->bc_io_write_2)((h), (o), (v))
-#define bus_io_write_4(t, h, o, v) \
- (*(t)->bc_io_write_4)((h), (o), (v))
-#define bus_io_write_8(t, h, o, v) \
- (*(t)->bc_io_write_8)((h), (o), (v))
-
-#define bus_io_write_multi_1(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_1)((h), (o), (a), (s))
-#define bus_io_write_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_2)((h), (o), (a), (s))
-#define bus_io_write_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_4)((h), (o), (a), (s))
-#define bus_io_write_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_8)((h), (o), (a), (s))
-
-#define bus_mem_map(t, port, size, cacheable, mhp) \
- (*(t)->bc_mem_map)((t), (port), (size), (cacheable), (mhp))
-#define bus_mem_unmap(t, mhp, size) \
- (*(t)->bc_mem_unmap)((mhp), (size))
-
-#define bus_mem_read_1(t, h, o) \
- (*(t)->bc_mem_read_1)((h), (o))
-#define bus_mem_read_2(t, h, o) \
- (*(t)->bc_mem_read_2)((h), (o))
-#define bus_mem_read_4(t, h, o) \
- (*(t)->bc_mem_read_4)((h), (o))
-#define bus_mem_read_8(t, h, o) \
- (*(t)->bc_mem_read_8)((h), (o))
-
-#define bus_mem_write_1(t, h, o, v) \
- (*(t)->bc_mem_write_1)((h), (o), (v))
-#define bus_mem_write_2(t, h, o, v) \
- (*(t)->bc_mem_write_2)((h), (o), (v))
-#define bus_mem_write_4(t, h, o, v) \
- (*(t)->bc_mem_write_4)((h), (o), (v))
-#define bus_mem_write_8(t, h, o, v) \
- (*(t)->bc_mem_write_8)((h), (o), (v))
+#define bus_space_map(t, port, size, cacheable, bshp) \
+ (*(t)->bs_map)((t), (port), (size), (cacheable), (bshp))
+#define bus_space_unmap(t, bshp, size) \
+ (*(t)->bs_unmap)((t), (bshp), (size))
+
+/* Swap bytes in a short word. */
+static __inline u_int16_t
+swap(u_int16_t x)
+{
+ __asm("rolw #8,%0" : "=r" (x) : "0" (x));
+ return x;
+}
+
+static __inline u_int8_t
+bus_space_read_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba)
+{
+ return *(volatile u_int8_t *)(bsh + (ba << 1));
+}
+
+static __inline u_int16_t
+bus_space_read_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba)
+{
+ register u_int16_t x = *(volatile u_int16_t *)((bsh & ~1) + (ba << 1));
+
+ return bst->bs_swapped ? swap(x) : x;
+}
+
+static __inline u_int32_t
+bus_space_read_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba)
+{
+ panic("bus_space_read_4: operation not allowed on this bus (tag %x)",
+ bst);
+ return 0;
+}
+
+#define bus_space_read_8 !!! bus_space_read_8 not implemented !!!
+
+#define bus_space_read_multi(n, m) \
+static __inline void \
+CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
+{ \
+ while (cnt--) \
+ *buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
+}
+
+bus_space_read_multi(1,8)
+bus_space_read_multi(2,16)
+bus_space_read_multi(4,32)
+
+#define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
+
+static __inline void
+bus_space_write_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba,
+ u_int8_t x)
+{
+ *(volatile u_int8_t *)(bsh + (ba << 1)) = x;
+}
+
+static __inline void
+bus_space_write_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba,
+ u_int16_t x)
+{
+ *(volatile u_int16_t *)((bsh & ~1) + (ba << 1)) =
+ bst->bs_swapped ? swap(x) : x;
+}
+
+static __inline void
+bus_space_write_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba,
+ u_int32_t x)
+{
+ panic("bus_space_write_4: operation not allowed on this bus (tag %x)",
+ bst);
+}
+
+#define bus_space_write_8 !!! bus_space_write_8 not implemented !!!
+
+#define bus_space_write_multi(n, m) \
+static __inline void \
+CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
+{ \
+ while (cnt--) \
+ CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \
+}
+
+bus_space_write_multi(1,8)
+bus_space_write_multi(2,16)
+bus_space_write_multi(4,32)
+
+#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
/* OpenBSD extensions */
-#define bus_io_read_raw_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_read_raw_multi_2)((h), (o), (a), (s))
-#define bus_io_read_raw_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_read_raw_multi_4)((h), (o), (a), (s))
-#define bus_io_read_raw_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_read_raw_multi_8)((h), (o), (a), (s))
-
-#define bus_io_write_raw_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_write_raw_multi_2)((h), (o), (a), (s))
-#define bus_io_write_raw_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_write_raw_multi_4)((h), (o), (a), (s))
-#define bus_io_write_raw_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_write_raw_multi_8)((h), (o), (a), (s))
-
-#endif /* _MACHINE_BUS_H_ */
+static __inline void
+bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, u_int8_t *buf, bus_size_t cnt)
+{
+ register u_int16_t *buf16 = (u_int16_t *)buf;
+
+ while (cnt) {
+ register u_int16_t x =
+ *(volatile u_int16_t *)((bsh & ~1) + (ba << 1));
+
+ *buf16++ = bst->bs_swapped ? x : swap(x);
+ cnt -= 2;
+ }
+}
+
+static __inline void
+bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, u_int8_t *buf, bus_size_t cnt)
+{
+ panic("%s: operation not allowed on this bus (tag %x)",
+ "bus_space_read_raw_multi_4", bst);
+}
+
+#define bus_space_read_raw_multi_8 \
+ !!! bus_space_read_raw_multi_8 not implemented !!!
+
+static __inline void
+bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, const u_int8_t *buf, bus_size_t cnt)
+{
+ register const u_int16_t *buf16 = (const u_int16_t *)buf;
+
+ while (cnt) {
+ *(volatile u_int16_t *)((bsh & ~1) + (ba << 1)) =
+ bst->bs_swapped ? *buf16 : swap(*buf16);
+ buf16++;
+ cnt -= 2;
+ }
+}
+
+static __inline void
+bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, const u_int8_t *buf, bus_size_t cnt)
+{
+ panic("%s: operation not allowed on this bus (tag %x)",
+ "bus_space_write_raw_multi_4", bst);
+}
+
+#define bus_space_write_raw_multi_8 \
+ !!! bus_space_write_raw_multi_8 not implemented !!!
+
+#endif /* _AMIGA_BUS_H_ */
+++ /dev/null
-/* $OpenBSD: bus.old.h,v 1.1 1996/11/12 20:29:46 niklas Exp $ */
-
-/*
- * Copyright (c) 1996 Niklas Hallqvist.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the Niklas Hallqvist.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _MACHINE_BUS_H_
-#define _MACHINE_BUS_H_
-
-/* I/O access types. */
-typedef u_long bus_io_addr_t;
-typedef u_long bus_io_size_t;
-typedef u_long bus_io_handle_t;
-
-/* Memory access types. */
-typedef u_long bus_mem_addr_t;
-typedef u_long bus_mem_size_t;
-typedef u_long bus_mem_handle_t;
-
-/*
- * The big switch, that delegates each bus operation to the right
- * implementation.
- */
-typedef struct amiga_bus_chipset *bus_chipset_tag_t;
-
-struct amiga_bus_chipset {
- void *bc_data;
-
- int (*bc_io_map)(bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t,
- bus_io_handle_t *);
- int (*bc_io_unmap)(bus_io_handle_t, bus_io_size_t);
-
- u_int8_t (*bc_io_read_1)(bus_io_handle_t, bus_io_size_t);
- u_int16_t (*bc_io_read_2)(bus_io_handle_t, bus_io_size_t);
- u_int32_t (*bc_io_read_4)(bus_io_handle_t, bus_io_size_t);
- u_int64_t (*bc_io_read_8)(bus_io_handle_t, bus_io_size_t);
-
- void (*bc_io_read_multi_1)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
- void (*bc_io_read_multi_2)(bus_io_handle_t, bus_io_size_t,
- u_int16_t *, bus_io_size_t);
- void (*bc_io_read_multi_4)(bus_io_handle_t, bus_io_size_t,
- u_int32_t *, bus_io_size_t);
- void (*bc_io_read_multi_8)(bus_io_handle_t, bus_io_size_t,
- u_int64_t *, bus_io_size_t);
-
- void (*bc_io_write_1)(bus_io_handle_t, bus_io_size_t, u_int8_t);
- void (*bc_io_write_2)(bus_io_handle_t, bus_io_size_t, u_int16_t);
- void (*bc_io_write_4)(bus_io_handle_t, bus_io_size_t, u_int32_t);
- void (*bc_io_write_8)(bus_io_handle_t, bus_io_size_t, u_int64_t);
-
- void (*bc_io_write_multi_1)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
- void (*bc_io_write_multi_2)(bus_io_handle_t, bus_io_size_t,
- const u_int16_t *, bus_io_size_t);
- void (*bc_io_write_multi_4)(bus_io_handle_t, bus_io_size_t,
- const u_int32_t *, bus_io_size_t);
- void (*bc_io_write_multi_8)(bus_io_handle_t, bus_io_size_t,
- const u_int64_t *, bus_io_size_t);
-
- int (*bc_mem_map)(bus_chipset_tag_t, bus_mem_addr_t,
- bus_mem_size_t, int, bus_mem_handle_t *);
- int (*bc_mem_unmap)(bus_mem_handle_t, bus_mem_size_t);
-
- u_int8_t (*bc_mem_read_1)(bus_mem_handle_t, bus_mem_size_t);
- u_int16_t (*bc_mem_read_2)(bus_mem_handle_t, bus_mem_size_t);
- u_int32_t (*bc_mem_read_4)(bus_mem_handle_t, bus_mem_size_t);
- u_int64_t (*bc_mem_read_8)(bus_mem_handle_t, bus_mem_size_t);
-
- void (*bc_mem_write_1)(bus_mem_handle_t, bus_mem_size_t, u_int8_t);
- void (*bc_mem_write_2)(bus_mem_handle_t, bus_mem_size_t, u_int16_t);
- void (*bc_mem_write_4)(bus_mem_handle_t, bus_mem_size_t, u_int32_t);
- void (*bc_mem_write_8)(bus_mem_handle_t, bus_mem_size_t, u_int64_t);
-
- /* These are extensions to the general NetBSD bus interface. */
- void (*bc_io_read_raw_multi_2)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
- void (*bc_io_read_raw_multi_4)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
- void (*bc_io_read_raw_multi_8)(bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t);
-
- void (*bc_io_write_raw_multi_2)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
- void (*bc_io_write_raw_multi_4)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
- void (*bc_io_write_raw_multi_8)(bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t);
-};
-
-#define bus_io_map(t, port, size, iohp) \
- (*(t)->bc_io_map)((t), (port), (size), (iohp))
-#define bus_io_unmap(t, iohp, size) \
- (*(t)->bc_io_unmap)((iohp), (size))
-
-#define bus_io_read_1(t, h, o) \
- (*(t)->bc_io_read_1)((h), (o))
-#define bus_io_read_2(t, h, o) \
- (*(t)->bc_io_read_2)((h), (o))
-#define bus_io_read_4(t, h, o) \
- (*(t)->bc_io_read_4)((h), (o))
-#define bus_io_read_8(t, h, o) \
- (*(t)->bc_io_read_8)((h), (o))
-
-#define bus_io_read_multi_1(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_1)((h), (o), (a), (s))
-#define bus_io_read_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_2)((h), (o), (a), (s))
-#define bus_io_read_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_4)((h), (o), (a), (s))
-#define bus_io_read_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_read_multi_8)((h), (o), (a), (s))
-
-#define bus_io_write_1(t, h, o, v) \
- (*(t)->bc_io_write_1)((h), (o), (v))
-#define bus_io_write_2(t, h, o, v) \
- (*(t)->bc_io_write_2)((h), (o), (v))
-#define bus_io_write_4(t, h, o, v) \
- (*(t)->bc_io_write_4)((h), (o), (v))
-#define bus_io_write_8(t, h, o, v) \
- (*(t)->bc_io_write_8)((h), (o), (v))
-
-#define bus_io_write_multi_1(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_1)((h), (o), (a), (s))
-#define bus_io_write_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_2)((h), (o), (a), (s))
-#define bus_io_write_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_4)((h), (o), (a), (s))
-#define bus_io_write_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_write_multi_8)((h), (o), (a), (s))
-
-#define bus_mem_map(t, port, size, cacheable, mhp) \
- (*(t)->bc_mem_map)((t), (port), (size), (cacheable), (mhp))
-#define bus_mem_unmap(t, mhp, size) \
- (*(t)->bc_mem_unmap)((mhp), (size))
-
-#define bus_mem_read_1(t, h, o) \
- (*(t)->bc_mem_read_1)((h), (o))
-#define bus_mem_read_2(t, h, o) \
- (*(t)->bc_mem_read_2)((h), (o))
-#define bus_mem_read_4(t, h, o) \
- (*(t)->bc_mem_read_4)((h), (o))
-#define bus_mem_read_8(t, h, o) \
- (*(t)->bc_mem_read_8)((h), (o))
-
-#define bus_mem_write_1(t, h, o, v) \
- (*(t)->bc_mem_write_1)((h), (o), (v))
-#define bus_mem_write_2(t, h, o, v) \
- (*(t)->bc_mem_write_2)((h), (o), (v))
-#define bus_mem_write_4(t, h, o, v) \
- (*(t)->bc_mem_write_4)((h), (o), (v))
-#define bus_mem_write_8(t, h, o, v) \
- (*(t)->bc_mem_write_8)((h), (o), (v))
-
-/* OpenBSD extensions */
-#define bus_io_read_raw_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_read_raw_multi_2)((h), (o), (a), (s))
-#define bus_io_read_raw_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_read_raw_multi_4)((h), (o), (a), (s))
-#define bus_io_read_raw_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_read_raw_multi_8)((h), (o), (a), (s))
-
-#define bus_io_write_raw_multi_2(t, h, o, a, s) \
- (*(t)->bc_io_write_raw_multi_2)((h), (o), (a), (s))
-#define bus_io_write_raw_multi_4(t, h, o, a, s) \
- (*(t)->bc_io_write_raw_multi_4)((h), (o), (a), (s))
-#define bus_io_write_raw_multi_8(t, h, o, a, s) \
- (*(t)->bc_io_write_raw_multi_8)((h), (o), (a), (s))
-
-#endif /* _MACHINE_BUS_H_ */
-/* $OpenBSD: cross.c,v 1.7 1996/11/23 21:45:26 kstailey Exp $ */
+/* $OpenBSD: cross.c,v 1.8 1996/11/28 23:33:06 niklas Exp $ */
/*
* Copyright (c) 1994, 1996 Niklas Hallqvist, Carsten Hammer
#include <sys/syslog.h>
#include <sys/systm.h>
-#include <machine/bus.old.h>
+#include <vm/vm.h>
+#include <vm/vm.h>
+#include <vm/vm.h>
+
+#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <amiga/amiga/isr.h>
#include <amiga/dev/zbusvar.h>
#include <amiga/isa/isa_machdep.h>
-#include <amiga/isa/crossvar.h>
#include <amiga/isa/crossreg.h>
+#include <amiga/isa/crossvar.h>
extern int cold;
int crossmatch __P((struct device *, void *, void *));
int crossprint __P((void *, const char *));
-int cross_io_map __P((bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t,
- bus_io_handle_t *));
-int cross_mem_map __P((bus_chipset_tag_t, bus_mem_addr_t, bus_mem_size_t,
- int, bus_mem_handle_t *));
-
-void cross_io_read_multi_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t *,
- bus_io_size_t));
-void cross_io_read_multi_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t *,
- bus_io_size_t));
-
-void cross_io_write_multi_1 __P((bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t));
-void cross_io_write_multi_2 __P((bus_io_handle_t, bus_io_size_t,
- const u_int16_t *, bus_io_size_t));
-
-void cross_io_read_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t));
-void cross_io_write_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t));
-
-/*
- * Note that the following unified access functions are prototyped for the
- * I/O access case. We use casts to get type correctness.
- */
-int cross_unmap __P((bus_io_handle_t, bus_io_size_t));
-
-__inline u_int8_t cross_read_1 __P((bus_io_handle_t, bus_io_size_t));
-__inline u_int16_t cross_read_2 __P((bus_io_handle_t, bus_io_size_t));
-
-__inline void cross_write_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t));
-__inline void cross_write_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t));
-
-/*
- * In order to share the access function implementations for I/O and memory
- * access we cast the functions for the memory access case. These typedefs
- * make that casting look nicer.
- */
-typedef int (*bus_mem_unmap_t) __P((bus_mem_handle_t, bus_mem_size_t));
-typedef u_int8_t (*bus_mem_read_1_t) __P((bus_mem_handle_t, bus_mem_size_t));
-typedef u_int16_t (*bus_mem_read_2_t) __P((bus_mem_handle_t, bus_mem_size_t));
-typedef void (*bus_mem_write_1_t) __P((bus_mem_handle_t, bus_mem_size_t,
- u_int8_t));
-typedef void (*bus_mem_write_2_t) __P((bus_mem_handle_t, bus_mem_size_t,
- u_int16_t));
+int cross_io_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+int cross_mem_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+int cross_io_unmap __P((bus_space_handle_t, bus_size_t));
+int cross_mem_unmap __P((bus_space_handle_t, bus_size_t));
int crossintr __P((void *));
void *, char *));
void cross_intr_disestablish __P((void *, void *));
-static u_int16_t swap __P((u_int16_t));
-
-struct amiga_bus_chipset cross_chipset = {
- 0 /* bc_data */,
-
- cross_io_map, cross_unmap,
- cross_read_1, cross_read_2,
- 0 /* bc_io_read_4 */, 0 /* bc_io_read_8 */,
- cross_io_read_multi_1, cross_io_read_multi_2,
- 0 /* bc_io_multi_4 */, 0 /* bc_io_multi_8 */,
- cross_write_1, cross_write_2,
- 0 /* bc_io_write_4 */, 0 /* bc_io_write_8 */,
- cross_io_write_multi_1, cross_io_write_multi_2,
- 0 /* bc_io_write_multi_4 */, 0 /* bc_io_write_multi_8 */,
-
- cross_mem_map, (bus_mem_unmap_t)cross_unmap,
- (bus_mem_read_1_t)cross_read_1, (bus_mem_read_2_t)cross_read_2,
- 0 /* bc_mem_read_4 */, 0 /* bc_mem_read_8 */,
- (bus_mem_write_1_t)cross_write_1, (bus_mem_write_2_t)cross_write_2,
- 0 /* bc_mem_write_4 */, 0 /* bc_mem_write_8 */,
-
- /* These are extensions to the general NetBSD bus interface. */
- cross_io_read_raw_multi_2,
- 0 /* bc_io_read_raw_multi_4 */, 0 /* bc_io_read_raw_multi_8 */,
-
- cross_io_write_raw_multi_2,
- 0 /* bc_io_write_raw_multi_4 */, 0 /* bc_io_write_raw_multi_8 */,
-};
+int cross_pager_get_pages __P((vm_pager_t, vm_page_t *, int, boolean_t));
struct cfattach cross_ca = {
sizeof(struct cross_softc), crossmatch, crossattach
NULL, "cross", DV_DULL, 0
};
+struct pagerops crosspagerops = {
+ NULL,
+ NULL,
+ NULL,
+ cross_pager_get_pages,
+ NULL,
+ NULL,
+ vm_pager_clusternull,
+ NULL,
+ NULL,
+ NULL
+};
+
+struct vm_pager crosspager;
+
int
crossmatch(parent, match, aux)
struct device *parent;
struct cross_softc *sc = (struct cross_softc *)self;
struct zbus_args *zap = aux;
struct isabus_attach_args iba;
+ int i;
bcopy(zap, &sc->sc_zargs, sizeof(struct zbus_args));
- bcopy(&cross_chipset, &sc->sc_bc, sizeof(struct amiga_bus_chipset));
- sc->sc_bc.bc_data = sc;
+ sc->sc_iot.bs_data = sc;
+ sc->sc_iot.bs_map = cross_io_map;
+ sc->sc_iot.bs_unmap = cross_io_unmap;
+ sc->sc_iot.bs_swapped = 1;
+ sc->sc_memt.bs_data = sc;
+ sc->sc_memt.bs_map = cross_mem_map;
+ sc->sc_memt.bs_unmap = cross_mem_unmap;
+ sc->sc_memt.bs_swapped = 1;
sc->sc_status = CROSS_STATUS_ADDR(zap->va);
sc->sc_imask = 1 << CROSS_MASTER;
/* Enable interrupts lazily in cross_intr_establish. */
CROSS_ENABLE_INTS(zap->va, 0);
+
/* Default 16 bit tranfer */
- *CROSS_HANDLE_TO_XLP_LATCH((bus_io_handle_t)zap->va) = CROSS_SBHE;
+ *CROSS_HANDLE_TO_XLP_LATCH((bus_space_handle_t)zap->va) = CROSS_SBHE;
printf(": pa 0x%08x va 0x%08x size 0x%x\n", zap->pa, zap->va,
zap->size);
sc->sc_ic.ic_intr_establish = cross_intr_establish;
sc->sc_ic.ic_intr_disestablish = cross_intr_disestablish;
+ /* Allocate a bunch of pages used for the bank-switching logic. */
+ for (i = 0; i < CROSS_BANK_SIZE / NBPG; i++) {
+ VM_PAGE_INIT(&sc->sc_page[i], NULL, 0);
+ sc->sc_page[i].phys_addr = zap->pa + CROSS_XL_MEM + i * NBPG;
+ sc->sc_page[i].flags |= PG_FICTITIOUS;
+ vm_page_free(&sc->sc_page[i]);
+ }
+
iba.iba_busname = "isa";
- iba.iba_bc = &sc->sc_bc;
+ iba.iba_iot = &sc->sc_iot;
+ iba.iba_memt = &sc->sc_memt;
iba.iba_ic = &sc->sc_ic;
config_found(self, &iba, crossprint);
}
int
-cross_io_map(bct, addr, sz, handle)
- bus_chipset_tag_t bct;
- bus_io_addr_t addr;
- bus_io_size_t sz;
- bus_io_handle_t *handle;
-{
- *handle = (bus_io_handle_t)
- ((struct cross_softc *)bct->bc_data)->sc_zargs.va + 2 * addr;
-#if 0
- printf("io_map %x %d -> %x\n", addr, sz, *handle);
-#endif
- return 0;
-}
-
-int
-cross_mem_map(bct, addr, sz, cacheable, handle)
- bus_chipset_tag_t bct;
- bus_mem_addr_t addr;
- bus_mem_size_t sz;
+cross_io_map(bst, addr, sz, cacheable, handle)
+ bus_space_tag_t bst;
+ bus_addr_t addr;
+ bus_size_t sz;
int cacheable;
- bus_mem_handle_t *handle;
+ bus_space_handle_t *handle;
{
- *handle = (bus_mem_handle_t)
- ((struct cross_softc *)bct->bc_data)->sc_zargs.va + 2 * addr +
- CROSS_MEMORY_OFFSET;
-#if 0
- printf("mem_map %x %d -> %x\n", addr, sz, *handle);
-#endif
+ *handle = (bus_space_handle_t)
+ ((struct cross_softc *)bst->bs_data)->sc_zargs.va + 2 * addr;
return 0;
}
int
-cross_unmap(handle, sz)
- bus_io_handle_t handle;
- bus_io_size_t sz;
-{
- return 0;
-}
-
-__inline u_int8_t
-cross_read_1(handle, addr)
- bus_io_handle_t handle;
- bus_io_size_t addr;
-{
- u_int8_t val;
-
- /* generate A13-A19 for correct page */
- *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE;
- val = *(volatile u_int8_t *)(handle + 2 * addr);
-
-#if 0
- printf("read_1 @%x handle %x -> %d\n", addr, handle, val);
-#endif
- return val;
-}
-
-__inline u_int16_t
-cross_read_2(handle, addr)
- bus_io_handle_t handle;
- bus_io_size_t addr;
-{
- /* generate A13-A19 for correct page */
- *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE;
- return *(volatile u_int16_t *)(handle + 2 * addr);
-}
-
-void
-cross_io_read_multi_1(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int8_t *buf;
- bus_io_size_t cnt;
-{
- while (cnt--)
- *buf++ = cross_read_1(handle, addr);
-}
-
-void
-cross_io_read_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int16_t *buf;
- bus_io_size_t cnt;
+cross_mem_map(bst, addr, sz, cacheable, handle)
+ bus_space_tag_t bst;
+ bus_addr_t addr;
+ bus_size_t sz;
+ int cacheable;
+ bus_space_handle_t *handle;
{
- while (cnt--)
- *buf++ = cross_read_2(handle, addr);
-}
+ bus_addr_t banked_start;
+ bus_size_t banked_size;
+ vm_object_t object;
+ vm_offset_t kva;
+ int error;
-void
-cross_io_read_raw_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int8_t *buf;
- bus_io_size_t cnt;
-{
- u_int16_t *buf16 = (u_int16_t *)buf;
+ /*
+ * XXX When we do have a good enough extent-manager do extent
+ * checking here.
+ */
- while (cnt) {
- cnt -= 2;
- *buf16++ = swap(cross_read_2(handle, addr));
- }
-}
+ /*
+ * Compute the bank range. Note that we need to shift bus-addresses
+ * and sizes left one bit.
+ */
+ banked_start = (addr << 1) & ~(CROSS_BANK_SIZE - 1);
+ banked_size = ((sz << 1) + CROSS_BANK_SIZE - 1) &
+ ~(CROSS_BANK_SIZE - 1);
-__inline void
-cross_write_1(handle, addr, val)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int8_t val;
-{
- /* generate A13-A19 for correct page */
- *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE;
-#if 0
- printf("write_1 @%x handle %x: %d\n", addr, handle, val);
-#endif
- *(volatile u_int8_t *)(handle + 2 * addr + 1) = val;
-}
+ /* Create the object that will take care of the bankswitching. */
+ object = vm_allocate_object(banked_size);
+ if (object == NULL)
+ goto fail_obj;
+ vm_object_setpager(object, cross_pager, 0, 0);
-__inline void
-cross_write_2(handle, addr, val)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int16_t val;
-{
- /* generate A13-A19 for correct page */
- *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE;
- *(volatile u_int16_t *)(handle + 2 * addr) = val;
-}
+ /*
+ * When done like this double mappings will be possible, thus
+ * wasting a little mapping space. This happens when several
+ * bus_space_map maps stuff from the same bank. But I don't care.
+ */
+ kva = kmem_alloc_pageable(kernel_map, banked_size);
+ if (kva == 0)
+ goto fail_alloc;
+ vm_map_lock(kernel_map);
+ error = vm_map_insert(kernel_map, object, 0, kva, kva + banked_size);
+ vm_map_unlock(kernel_map);
+ if (error != KERN_SUCCESS)
+ goto fail_insert;
+
+ /* Tell caller where to find his data. */
+ *handle = (bus_space_handle_t)(kva + (addr << 1) - banked_addr));
+ return 0;
-void
-cross_io_write_multi_1(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- const u_int8_t *buf;
- bus_io_size_t cnt;
-{
- while (cnt--)
- cross_write_1(handle, addr, *buf++);
+fail_insert:
+ kmem_free(kernel_map, kva, banked_size);
+fail_alloc:
+ vm_object_deallocate(object);
+fail_obj:
+ return -1;
}
-void
-cross_io_write_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- const u_int16_t *buf;
- bus_io_size_t cnt;
+int
+cross_io_unmap(bst, handle, sz)
+ bus_space_tag_t bst;
+ bus_space_handle_t handle;
+ bus_size_t sz;
{
- while (cnt--)
- cross_write_2(handle, addr, *buf++);
+ return 0;
}
-void
-cross_io_write_raw_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- const u_int8_t *buf;
- bus_io_size_t cnt;
+int
+cross_mem_unmap(bst, handle, sz)
+ bus_space_tag_t bst;
+ bus_space_handle_t handle;
+ bus_size_t sz;
{
- const u_int16_t *buf16 = (const u_int16_t *)buf;
-
- while (cnt) {
- cnt -= 2;
- cross_write_2(handle, addr, swap(*buf16++));
- }
+ /* Remove traphandler */
+ return 0;
}
static cross_int_map[] = {
sc->sc_intrsharetype[irq] = IST_NONE;
}
-/* Swap bytes in a short word. */
-static u_short
-swap(u_short x)
+int
+cross_pager_get_pages(pager, mlist, npages, sync)
+ vm_pager_t pager;
+ vm_page_t *mlist;
+ int npages;
+ boolean_t sync;
{
- __asm("rolw #8,%0" : "=r" (x) : "0" (x));
- return x;
+ int i;
+ vm_object_t object, old_object;
+ vm_offset_t offset;
+
+ while(npages--) {
+ i = ((*mlist)->offset & (CROSS_BANK_SIZE - 1)) / NBPG;
+ object = (*mlist)->object;
+ old_object = sc->sc_page[i].offset;
+ offset = (*mlist)->offset;
+ vm_page_lock_queues();
+ vm_object_lock(object);
+ if (old_object)
+ vm_object_lock(old_object);
+ vm_page_free(*mlist);
+
+ /* generate A13-A19 for correct page */
+ *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE;
+
+ vm_page_rename(sc->sc_page[i], object, offset);
+ if (old_object)
+ vm_object_unlock(old_object);
+ vm_object_unlock(object);
+ vm_page_unlock_queues();
+ mlist++:
+ }
+ return VM_PAGER_OK;
}
-/* $OpenBSD: crossreg.h,v 1.3 1996/06/04 13:40:13 niklas Exp $ */
+/* $OpenBSD: crossreg.h,v 1.4 1996/11/28 23:33:07 niklas Exp $ */
/*
* Copyright (c) 1994, 1996 Niklas Hallqvist, Carsten Hammer
/* hardware offsets from config address */
-#define CROSS_XL_ROM 0x8000
-#define CROSS_XL_MEM 0x4000
-#define CROSS_XL_IO 0x0000
+#define CROSS_XL_ROM 0x8000
+#define CROSS_XL_MEM 0x4000
+#define CROSS_XL_IO 0x0000
-#define CROSS_XLP_INTSTAT 0
-#define CROSS_XLP_INTABLE 0
-#define CROSS_XLP_LATCH 2
+#define CROSS_BANK_SIZE (CROSS_XL_ROM - CROSS_XL_MEM)
+
+#define CROSS_XLP_INTSTAT 0
+#define CROSS_XLP_INTABLE 0
+#define CROSS_XLP_LATCH 2
#define CROSS_HANDLE_TO_XLP_LATCH(va) \
((volatile u_int16_t *)(((va) & 0xffff) | CROSS_XLP_LATCH))
-#define CROSS_MEMORY_OFFSET (CROSS_XL_MEM - 2 * 0x90000)
-#define CROSS_SBHE 0x40
+#define CROSS_MEMORY_OFFSET (CROSS_XL_MEM - 2 * 0x90000)
+#define CROSS_SBHE 0x40
#define CROSS_STATUS_ADDR(va) \
((volatile u_int16_t *)((va) + CROSS_XLP_INTSTAT))
-#define CROSS_MASTER 5
+#define CROSS_MASTER 5
-#define CROSS_IRQ9 10 /* IRQ9 is an alias of IRQ2 */
-#define CROSS_IRQ3 11
-#define CROSS_IRQ4 12
-#define CROSS_IRQ5 13
-#define CROSS_IRQ6 14
-#define CROSS_IRQ7 15
-#define CROSS_IRQ10 2
-#define CROSS_IRQ11 3
-#define CROSS_IRQ12 4
-#define CROSS_IRQ14 6
-#define CROSS_IRQ15 7
-#define CROSS_IRQMASK 0xfcdc
+#define CROSS_IRQ9 10 /* IRQ9 is an alias of IRQ2 */
+#define CROSS_IRQ3 11
+#define CROSS_IRQ4 12
+#define CROSS_IRQ5 13
+#define CROSS_IRQ6 14
+#define CROSS_IRQ7 15
+#define CROSS_IRQ10 2
+#define CROSS_IRQ11 3
+#define CROSS_IRQ12 4
+#define CROSS_IRQ14 6
+#define CROSS_IRQ15 7
+#define CROSS_IRQMASK 0xfcdc
#define CROSS_GET_INT_STATUS(va) (CROSS_GET_STATUS(va) & CROSS_IRQMASK)
#define CROSS_ENABLE_INTS(va, ints) \
-/* $OpenBSD: crossvar.h,v 1.3 1996/06/04 13:40:14 niklas Exp $ */
+/* $OpenBSD: crossvar.h,v 1.4 1996/11/28 23:33:08 niklas Exp $ */
/*
* Copyright (c) 1994, 1996 Niklas Hallqvist
int sc_intrsharetype[ICU_LEN];
u_int16_t sc_imask;
volatile u_int16_t *sc_status;
+ struct vm_page sc_page[CROSS_BANK_SIZE / NBPG];
- struct amiga_bus_chipset sc_bc;
+ struct amiga_bus_space sc_iot;
+ struct amiga_bus_space sc_memt;
struct amiga_isa_chipset sc_ic;
};
-/* $OpenBSD: ggbus.c,v 1.7 1996/11/23 21:45:26 kstailey Exp $ */
+/* $OpenBSD: ggbus.c,v 1.8 1996/11/28 23:33:08 niklas Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Niklas Hallqvist
int ggbusmatch __P((struct device *, void *, void *));
int ggbusprint __P((void *, const char *));
-int ggbus_io_map __P((bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t,
- bus_io_handle_t *));
-int ggbus_mem_map __P((bus_chipset_tag_t, bus_mem_addr_t, bus_mem_size_t,
- int, bus_mem_handle_t *));
-
-void ggbus_io_read_multi_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t *,
- bus_io_size_t));
-void ggbus_io_read_multi_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t *,
- bus_io_size_t));
-
-void ggbus_io_write_multi_1 __P((bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t));
-void ggbus_io_write_multi_2 __P((bus_io_handle_t, bus_io_size_t,
- const u_int16_t *, bus_io_size_t));
-
-/*
- * Note that the following unified access functions are prototyped for the
- * I/O access case. We use casts to get type correctness.
- */
-int ggbus_unmap __P((bus_io_handle_t, bus_io_size_t));
-
-__inline u_int8_t ggbus_read_1 __P((bus_io_handle_t, bus_io_size_t));
-__inline u_int16_t ggbus_read_2 __P((bus_io_handle_t, bus_io_size_t));
-
-__inline void ggbus_write_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t));
-__inline void ggbus_write_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t));
-
-void ggbus_io_read_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t,
- u_int8_t *, bus_io_size_t));
-void ggbus_io_write_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t,
- const u_int8_t *, bus_io_size_t));
-
-/*
- * In order to share the access function implementations for I/O and memory
- * access we cast the functions for the memory access case. These typedefs
- * make that casting look nicer.
- */
-typedef int (*bus_mem_unmap_t) __P((bus_mem_handle_t, bus_mem_size_t));
-typedef u_int8_t (*bus_mem_read_1_t) __P((bus_mem_handle_t, bus_mem_size_t));
-typedef u_int16_t (*bus_mem_read_2_t) __P((bus_mem_handle_t, bus_mem_size_t));
-typedef void (*bus_mem_write_1_t) __P((bus_mem_handle_t, bus_mem_size_t,
- u_int8_t));
-typedef void (*bus_mem_write_2_t) __P((bus_mem_handle_t, bus_mem_size_t,
- u_int16_t));
+int ggbus_io_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+int ggbus_mem_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+int ggbus_cannot_mem_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+int ggbus_unmap __P((bus_space_tag_t, bus_space_handle_t, bus_size_t));
int ggbusintr __P((void *));
void *, char *));
void ggbus_intr_disestablish __P((void *, void *));
-static u_int16_t swap __P((u_int16_t));
-
-/* Golden Gate I. */
-struct amiga_bus_chipset ggbus1_chipset = {
- 0 /* bc_data */,
-
- ggbus_io_map, ggbus_unmap,
- ggbus_read_1, ggbus_read_2,
- 0 /* bc_io_read_4 */, 0 /* bc_io_read_8 */,
- ggbus_io_read_multi_1, ggbus_io_read_multi_2,
- 0 /* bc_io_multi_4 */, 0 /* bc_io_multi_8 */,
- ggbus_write_1, ggbus_write_2,
- 0 /* bc_io_write_4 */, 0 /* bc_io_write_8 */,
- ggbus_io_write_multi_1, ggbus_io_write_multi_2,
- 0 /* bc_io_write_multi_4 */, 0 /* bc_io_write_multi_8 */,
-
- 0 /* bc_mem_map */, 0 /* bc_mem_unmap */,
- 0 /* bc_mem_read_1 */, 0 /* bc_mem_read_2 */,
- 0 /* bc_mem_read_4 */, 0 /* bc_mem_read_8 */,
- 0 /* bc_mem_write_1 */, 0 /* bc_mem_write_2 */,
- 0 /* bc_mem_write_4 */, 0 /* bc_mem_write_8 */,
-
- 0 /* bc_io_read_raw_multi_2 */,
- 0 /* bc_io_read_raw_multi_4 */, 0 /* bc_io_read_raw_multi_8 */,
-
- 0 /* bc_io_write_raw_multi_2 */,
- 0 /* bc_io_write_raw_multi_4 */, 0 /* bc_io_write_raw_multi_8 */,
-};
-
-/* Golden Gate II. */
-struct amiga_bus_chipset ggbus2_chipset = {
- 0 /* bc_data */,
-
- ggbus_io_map, ggbus_unmap,
- ggbus_read_1, ggbus_read_2,
- 0 /* bc_io_read_4 */, 0 /* bc_io_read_8 */,
- ggbus_io_read_multi_1, ggbus_io_read_multi_2,
- 0 /* bc_io_multi_4 */, 0 /* bc_io_multi_8 */,
- ggbus_write_1, ggbus_write_2,
- 0 /* bc_io_write_4 */, 0 /* bc_io_write_8 */,
- ggbus_io_write_multi_1, ggbus_io_write_multi_2,
- 0 /* bc_io_write_multi_4 */, 0 /* bc_io_write_multi_8 */,
-
- ggbus_mem_map, (bus_mem_unmap_t)ggbus_unmap,
- (bus_mem_read_1_t)ggbus_read_1, (bus_mem_read_2_t)ggbus_read_2,
- 0 /* bc_mem_read_4 */, 0 /* bc_mem_read_8 */,
- (bus_mem_write_1_t)ggbus_write_1, (bus_mem_write_2_t)ggbus_write_2,
- 0 /* bc_mem_write_4 */, 0 /* bc_mem_write_8 */,
-
- ggbus_io_read_raw_multi_2,
- 0 /* bc_io_read_raw_multi_4 */, 0 /* bc_io_read_raw_multi_8 */,
-
- ggbus_io_write_raw_multi_2,
- 0 /* bc_io_write_raw_multi_4 */, 0 /* bc_io_write_raw_multi_8 */,
-};
-
struct cfattach ggbus_ca = {
sizeof(struct ggbus_softc), ggbusmatch, ggbusattach
};
struct isabus_attach_args iba;
bcopy(zap, &sc->sc_zargs, sizeof(struct zbus_args));
- /* XXX Is serno reliable? */
- bcopy(zap->serno < 2 ? &ggbus1_chipset : &ggbus2_chipset,
- &sc->sc_bc, sizeof(struct amiga_bus_chipset));
- sc->sc_bc.bc_data = sc;
- sc->sc_status = GG2_STATUS_ADDR(sc->sc_zargs.va);
-
+ sc->sc_iot.bs_data = sc;
+ sc->sc_iot.bs_map = ggbus_io_map;
+ sc->sc_iot.bs_unmap = ggbus_unmap;
+ sc->sc_iot.bs_swapped = 0;
if (sc->sc_zargs.serno >= 2) {
+ sc->sc_memt.bs_data = sc;
+ sc->sc_memt.bs_map = ggbus_mem_map;
+ sc->sc_memt.bs_unmap = ggbus_unmap;
+ sc->sc_memt.bs_swapped = 0;
+ sc->sc_status = GG2_STATUS_ADDR(sc->sc_zargs.va);
+
/* XXX turn on wait states unconditionally for now. */
GG2_ENABLE_WAIT(zap->va);
GG2_ENABLE_INTS(zap->va);
- }
+ } else
+ sc->sc_memt.bs_map = ggbus_cannot_mem_map;
printf(": pa 0x%08x va 0x%08x size 0x%x\n", zap->pa, zap->va,
zap->size);
sc->sc_ic.ic_intr_disestablish = ggbus_intr_disestablish;
iba.iba_busname = "isa";
- iba.iba_bc = &sc->sc_bc;
+ iba.iba_iot = &sc->sc_iot;
+ iba.iba_memt = &sc->sc_memt;
iba.iba_ic = &sc->sc_ic;
config_found(self, &iba, ggbusprint);
}
}
int
-ggbus_io_map(bct, addr, sz, handle)
- bus_chipset_tag_t bct;
- bus_io_addr_t addr;
- bus_io_size_t sz;
- bus_io_handle_t *handle;
+ggbus_io_map(bst, addr, sz, cacheable, handle)
+ bus_space_tag_t bst;
+ bus_addr_t addr;
+ bus_size_t sz;
+ int cacheable;
+ bus_space_handle_t *handle;
{
- *handle = (bus_io_handle_t)
- ((struct ggbus_softc *)bct->bc_data)->sc_zargs.va + 2 * addr;
-#if 0
- printf("io_map %x %d -> %x\n", addr, sz, *handle);
-#endif
+ *handle = (bus_space_handle_t)
+ ((struct ggbus_softc *)bst->bs_data)->sc_zargs.va + 2 * addr + 1;
return 0;
}
int
-ggbus_mem_map(bct, addr, sz, cacheable, handle)
- bus_chipset_tag_t bct;
- bus_mem_addr_t addr;
- bus_mem_size_t sz;
+ggbus_mem_map(bst, addr, sz, cacheable, handle)
+ bus_space_tag_t bst;
+ bus_addr_t addr;
+ bus_size_t sz;
int cacheable;
- bus_mem_handle_t *handle;
+ bus_space_handle_t *handle;
{
- *handle = (bus_mem_handle_t)
- ((struct ggbus_softc *)bct->bc_data)->sc_zargs.va + 2 * addr +
+ *handle = (bus_space_handle_t)
+ ((struct ggbus_softc *)bst->bs_data)->sc_zargs.va + 2 * addr +
GG2_MEMORY_OFFSET;
-#if 0
- printf("mem_map %x %d -> %x\n", addr, sz, *handle);
-#endif
return 0;
}
int
-ggbus_unmap(handle, sz)
- bus_io_handle_t handle;
- bus_io_size_t sz;
-{
- return 0;
-}
-
-__inline u_int8_t
-ggbus_read_1(handle, addr)
- bus_io_handle_t handle;
- bus_io_size_t addr;
-{
- u_int8_t val = *(volatile u_int8_t *)(handle + 2 * addr + 1);
-
-#if 0
- printf("read_1 @%x handle %x -> %d\n", addr, handle, val);
-#endif
- return val;
-}
-
-__inline u_int16_t
-ggbus_read_2(handle, addr)
- bus_io_handle_t handle;
- bus_io_size_t addr;
-{
- return *(volatile u_int16_t *)(handle + 2 * addr);
-}
-
-void
-ggbus_io_read_multi_1(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int8_t *buf;
- bus_io_size_t cnt;
-{
- while (cnt--)
- *buf++ = ggbus_read_1(handle, addr);
-}
-
-void
-ggbus_io_read_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int16_t *buf;
- bus_io_size_t cnt;
-{
- while (cnt--)
- *buf++ = ggbus_read_2(handle, addr);
-}
-
-void
-ggbus_io_read_raw_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int8_t *buf;
- bus_io_size_t cnt;
-{
- u_int16_t *buf16 = (u_int16_t *)buf;
-
- while (cnt) {
- cnt -= 2;
- *buf16++ = swap(ggbus_read_2(handle, addr));
- }
-}
-
-__inline void
-ggbus_write_1(handle, addr, val)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int8_t val;
-{
-#if 0
- printf("write_1 @%x handle %x: %d\n", addr, handle, val);
-#endif
- *(volatile u_int8_t *)(handle + 2 * addr + 1) = val;
-}
-
-__inline void
-ggbus_write_2(handle, addr, val)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- u_int16_t val;
-{
- *(volatile u_int16_t *)(handle + 2 * addr) = val;
-}
-
-void
-ggbus_io_write_multi_1(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- const u_int8_t *buf;
- bus_io_size_t cnt;
+ggbus_cannot_mem_map(bst, addr, sz, cacheable, handle)
+ bus_space_tag_t bst;
+ bus_addr_t addr;
+ bus_size_t sz;
+ int cacheable;
+ bus_space_handle_t *handle;
{
- while (cnt--)
- ggbus_write_1(handle, addr, *buf++);
-}
+ static int have_warned = 0;
-void
-ggbus_io_write_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- const u_int16_t *buf;
- bus_io_size_t cnt;
-{
- while (cnt--)
- ggbus_write_2(handle, addr, *buf++);
+ if (!have_warned++)
+ printf("The Golden Gate 1 cannot map ISA memory.\n");
+ return -1;
}
-void
-ggbus_io_write_raw_multi_2(handle, addr, buf, cnt)
- bus_io_handle_t handle;
- bus_io_size_t addr;
- const u_int8_t *buf;
- bus_io_size_t cnt;
+int
+ggbus_unmap(bst, handle, sz)
+ bus_space_tag_t bst;
+ bus_space_handle_t handle;
+ bus_size_t sz;
{
- const u_int16_t *buf16 = (const u_int16_t *)buf;
-
- while (cnt) {
- cnt -= 2;
- ggbus_write_2(handle, addr, swap(*buf16++));
- }
+ return 0;
}
static ggbus_int_map[] = {
if (sc->sc_intrsharetype[irq] == NULL)
sc->sc_intrsharetype[irq] = IST_NONE;
}
-
-/* Swap bytes in a short word. */
-static u_int16_t
-swap(u_int16_t x)
-{
- __asm("rolw #8,%0" : "=r" (x) : "0" (x));
- return x;
-}
-/* $OpenBSD: ggbusvar.h,v 1.3 1996/06/04 13:40:14 niklas Exp $ */
+/* $OpenBSD: ggbusvar.h,v 1.4 1996/11/28 23:33:09 niklas Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Niklas Hallqvist
int sc_intrsharetype[ICU_LEN];
volatile u_int16_t *sc_status;
- struct amiga_bus_chipset sc_bc;
+ struct amiga_bus_space sc_iot;
+ struct amiga_bus_space sc_memt;
struct amiga_isa_chipset sc_ic;
};
-/* $OpenBSD: if_isaed.c,v 1.13 1996/11/12 20:29:51 niklas Exp $ */
+/* $OpenBSD: if_isaed.c,v 1.14 1996/11/28 23:33:09 niklas Exp $ */
/*
* Derived from sys/dev/isa/if_ed.c:
- * $NetBSD: if_ed.c,v 1.100 1996/05/12 23:52:19 mycroft Exp $
+ * $NetBSD: if_ed.c,v 1.105 1996/10/21 22:40:45 thorpej Exp $
*/
/*
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isareg.h>
*/
struct ed_softc {
struct device sc_dev;
- void *sc_ih;
+ void *sc_ih;
struct arpcom sc_arpcom; /* ethernet common */
- void *sc_sh; /* shutdown hook */
+ void *sc_sh; /* shutdown hook */
char *type_str; /* pointer to type string */
u_char vendor; /* interface vendor */
#define ED_NOTPRESENT 0x0002 /* card not present; do not allow
reconfiguration */
- bus_chipset_tag_t sc_bc; /* bus identifier */
- bus_io_handle_t sc_ioh; /* io handle */
- bus_io_handle_t sc_delayioh; /* io handle for `delay port' */
- bus_mem_handle_t sc_memh; /* bus memory handle */
+ bus_space_tag_t sc_iot; /* bus identifier */
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_ioh; /* io handle */
+ bus_space_handle_t sc_delaybah; /* io handle for `delay port' */
+ bus_space_handle_t sc_memh; /* bus memory handle */
- bus_io_size_t asic_base; /* offset of ASIC I/O port */
- bus_io_size_t nic_base; /* offset of NIC (DS8390) I/O port */
+ bus_size_t asic_base; /* offset of ASIC I/O port */
+ bus_size_t nic_base; /* offset of NIC (DS8390) I/O port */
/*
* The following 'proto' variable is part of a work-around for 8013EBT asics
void edattach __P((struct device *, struct device *, void *));
int ed_find __P((struct ed_softc *, struct cfdata *,
struct isa_attach_args *ia));
-int ed_probe_generic8390 __P((bus_chipset_tag_t, bus_io_handle_t, int));
+int ed_probe_generic8390 __P((bus_space_tag_t, bus_space_handle_t, int));
int ed_find_WD80x3 __P((struct ed_softc *, struct cfdata *,
struct isa_attach_args *ia));
int ed_find_3Com __P((struct ed_softc *, struct cfdata *,
shutdownhook_disestablish(sc->sc_sh);
ifp->if_flags &= ~(IFF_RUNNING|IFF_UP);
sc->spec_flags |= ED_NOTPRESENT;
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
+ isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
return PCMCIA_BUS_UNCONFIG(pc_link->adapter, pc_link);
}
#endif
-#define NIC_PUT(bc, ioh, nic, reg, val) \
- bus_io_write_1((bc), (ioh), ((nic) + (reg)), (val))
-#define NIC_GET(bc, ioh, nic, reg) \
- bus_io_read_1((bc), (ioh), ((nic) + (reg)))
+#define NIC_PUT(t, bah, nic, reg, val) \
+ bus_space_write_1((t), (bah), ((nic) + (reg)), (val))
+#define NIC_GET(t, bah, nic, reg) \
+ bus_space_read_1((t), (bah), ((nic) + (reg)))
/*
* Determine if the device is present.
* Return 1 if 8390 was found, 0 if not.
*/
int
-ed_probe_generic8390(bc, ioh, nicbase)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ed_probe_generic8390(t, bah, nicbase)
+ bus_space_tag_t t;
+ bus_space_handle_t bah;
int nicbase;
{
- if ((NIC_GET(bc, ioh, nicbase, ED_P0_CR) &
+ if ((NIC_GET(t, bah, nicbase, ED_P0_CR) &
(ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
(ED_CR_RD2 | ED_CR_STP))
return (0);
- if ((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
+ if ((NIC_GET(t, bah, nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
return (0);
return (1);
struct cfdata *cf;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- bus_io_handle_t delayioh = ia->ia_delayioh;
- bus_mem_handle_t memh;
+ bus_space_tag_t iot;
+ bus_space_tag_t memt;
+ bus_space_handle_t ioh;
+ bus_space_handle_t delaybah = ia->ia_delaybah;
+ bus_space_handle_t memh;
u_int memsize;
u_char iptr, isa16bit, sum;
int i, rv, memfail, mapped_mem = 0;
int asicbase, nicbase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
+ memt = ia->ia_memt;
rv = 0;
/* Set initial values for width/size. */
memsize = 8192;
isa16bit = 0;
- if (bus_io_map(bc, ia->ia_iobase, ED_WD_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ED_WD_IO_PORTS, 0, &ioh))
return (0);
sc->asic_base = asicbase = 0;
sc->is790 = 0;
#ifdef TOSH_ETHER
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_POW);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_POW);
delay(10000);
#endif
* Danpex boards for one.
*/
for (sum = 0, i = 0; i < 8; ++i)
- sum += bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + i);
+ sum += bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + i);
if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
/*
* clones. In this case, the checksum byte (the eighth byte)
* seems to always be zero.
*/
- if (bus_io_read_1(bc, ioh, asicbase + ED_WD_CARD_ID) !=
+ if (bus_space_read_1(iot, ioh, asicbase + ED_WD_CARD_ID) !=
ED_TYPE_WD8003E ||
- bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + 7) != 0)
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + 7) != 0)
goto out;
}
/* Reset card to force it into a known state. */
#ifdef TOSH_ETHER
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
ED_WD_MSR_RST | ED_WD_MSR_POW);
#else
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST);
#endif
delay(100);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
- bus_io_read_1(bc, ioh, asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST);
/* Wait in the case this card is reading it's EEROM. */
delay(5000);
sc->vendor = ED_VENDOR_WD_SMC;
- sc->type = bus_io_read_1(bc, ioh, asicbase + ED_WD_CARD_ID);
+ sc->type = bus_space_read_1(iot, ioh, asicbase + ED_WD_CARD_ID);
switch (sc->type) {
case ED_TYPE_WD8003S:
isa16bit = 1;
break;
case ED_TYPE_WD8013EP: /* also WD8003EP */
- if (bus_io_read_1(bc, ioh, asicbase + ED_WD_ICR)
+ if (bus_space_read_1(iot, ioh, asicbase + ED_WD_ICR)
& ED_WD_ICR_16BIT) {
isa16bit = 1;
memsize = 16384;
case ED_TYPE_SMC8216T:
sc->type_str = (sc->type == ED_TYPE_SMC8216C) ?
"SMC8216/SMC8216C" : "SMC8216T";
- bus_io_write_1(bc, ioh, asicbase + ED_WD790_HWR,
- bus_io_read_1(bc, ioh, asicbase + ED_WD790_HWR)
+ bus_space_write_1(iot, ioh, asicbase + ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, asicbase + ED_WD790_HWR)
| ED_WD790_HWR_SWH);
- switch (bus_io_read_1(bc, ioh, asicbase + ED_WD790_RAR) &
+ switch (bus_space_read_1(iot, ioh, asicbase + ED_WD790_RAR) &
ED_WD790_RAR_SZ64) {
case ED_WD790_RAR_SZ64:
memsize = 65536;
memsize = 8192;
break;
}
- bus_io_write_1(bc, ioh, asicbase + ED_WD790_HWR,
- bus_io_read_1(bc, ioh,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD790_HWR,
+ bus_space_read_1(iot, ioh,
asicbase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
isa16bit = 1;
#ifdef TOSH_ETHER
(sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) &&
#endif
- ((bus_io_read_1(bc, ioh,
+ ((bus_space_read_1(iot, ioh,
asicbase + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
isa16bit = 0;
memsize = 8192;
sc->type, sc->type_str ?: "unknown", isa16bit, memsize,
ia->ia_msize);
for (i = 0; i < 8; i++)
- printf("%x -> %x\n", i, bus_io_read_1(bc, ioh, asicbase + i));
+ printf("%x -> %x\n", i,
+ bus_space_read_1(iot, ioh, asicbase + i));
#endif
/* Allow the user to override the autoconfiguration. */
if (ia->ia_msize)
if (sc->is790) {
u_char x;
/* Assemble together the encoded interrupt number. */
- bus_io_write_1(bc, ioh, ED_WD790_HWR,
- bus_io_read_1(bc, ioh, ED_WD790_HWR) | ED_WD790_HWR_SWH);
- x = bus_io_read_1(bc, ioh, ED_WD790_GCR);
+ bus_space_write_1(iot, ioh, ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, ED_WD790_HWR) | ED_WD790_HWR_SWH);
+ x = bus_space_read_1(iot, ioh, ED_WD790_GCR);
iptr = ((x & ED_WD790_GCR_IR2) >> 4) |
((x & (ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2);
- bus_io_write_1(bc, ioh, ED_WD790_HWR,
- bus_io_read_1(bc, ioh, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+ bus_space_write_1(iot, ioh, ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
/*
* Translate it using translation table, and check for
* correctness.
} else
ia->ia_irq = ed_wd790_irq[iptr];
/* Enable the interrupt. */
- bus_io_write_1(bc, ioh, ED_WD790_ICR,
- bus_io_read_1(bc, ioh, ED_WD790_ICR) | ED_WD790_ICR_EIL);
+ bus_space_write_1(iot, ioh, ED_WD790_ICR,
+ bus_space_read_1(iot, ioh, ED_WD790_ICR) | ED_WD790_ICR_EIL);
} else if (sc->type & ED_WD_SOFTCONFIG) {
/* Assemble together the encoded interrupt number. */
- iptr = (bus_io_read_1(bc, ioh, ED_WD_ICR) & ED_WD_ICR_IR2) |
- ((bus_io_read_1(bc, ioh, ED_WD_IRR) &
+ iptr = (bus_space_read_1(iot, ioh, ED_WD_ICR) & ED_WD_ICR_IR2) |
+ ((bus_space_read_1(iot, ioh, ED_WD_IRR) &
(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
/*
* Translate it using translation table, and check for
} else
ia->ia_irq = ed_wd584_irq[iptr];
/* Enable the interrupt. */
- bus_io_write_1(bc, ioh, ED_WD_IRR,
- bus_io_read_1(bc, ioh, ED_WD_IRR) | ED_WD_IRR_IEN);
+ bus_space_write_1(iot, ioh, ED_WD_IRR,
+ bus_space_read_1(iot, ioh, ED_WD_IRR) | ED_WD_IRR_IEN);
} else {
if (ia->ia_irq == IRQUNK) {
printf("%s: %s does not have soft configuration\n",
sc->isa16bit = isa16bit;
sc->mem_shared = 1;
ia->ia_msize = memsize;
- if (bus_mem_map(bc, ia->ia_maddr, memsize, 0, &memh))
+ if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh))
goto out;
mapped_mem = 1;
sc->mem_start = 0; /* offset */
/* Get station address from on-board ROM. */
for (i = 0; i < ETHER_ADDR_LEN; ++i)
sc->sc_arpcom.ac_enaddr[i] =
- bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + i);
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + i);
/*
* Set upper address bits and 8/16 bit access to shared memory.
if (isa16bit) {
if (sc->is790) {
sc->wd_laar_proto =
- bus_io_read_1(bc, ioh, asicbase + ED_WD_LAAR) &
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_LAAR) &
~ED_WD_LAAR_M16EN;
} else {
sc->wd_laar_proto =
((ia->ia_maddr >> 19) &
ED_WD_LAAR_ADDRHI);
}
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
} else {
if ((sc->type & ED_WD_SOFTCONFIG) ||
sc->wd_laar_proto =
((ia->ia_maddr >> 19) &
ED_WD_LAAR_ADDRHI);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
}
}
*/
if (!sc->is790) {
#ifdef TOSH_ETHER
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR + 1,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR + 1,
((ia->ia_maddr >> 8) & 0xe0) | 4);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR + 2,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR + 2,
((ia->ia_maddr >> 16) & 0x0f));
sc->wd_msr_proto = ED_WD_MSR_POW;
#else
#endif
sc->cr_proto = ED_CR_RD2;
} else {
- bus_io_write_1(bc, ioh, asicbase + 0x04,
- bus_io_read_1(bc, ioh, asicbase + 0x04) | 0x80);
- bus_io_write_1(bc, ioh, asicbase + 0x0b,
+ bus_space_write_1(iot, ioh, asicbase + 0x04,
+ bus_space_read_1(iot, ioh, asicbase + 0x04) | 0x80);
+ bus_space_write_1(iot, ioh, asicbase + 0x0b,
((ia->ia_maddr >> 13) & 0x0f) |
((ia->ia_maddr >> 11) & 0x40) |
- (bus_io_read_1(bc, ioh, asicbase + 0x0b) & 0xb0));
- bus_io_write_1(bc, ioh, asicbase + 0x04,
- bus_io_read_1(bc, ioh, asicbase + 0x04) & ~0x80);
+ (bus_space_read_1(iot, ioh, asicbase + 0x0b) & 0xb0));
+ bus_space_write_1(iot, ioh, asicbase + 0x04,
+ bus_space_read_1(iot, ioh, asicbase + 0x04) & ~0x80);
sc->wd_msr_proto = 0x00;
sc->cr_proto = 0;
}
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
- (void) bus_io_read_1(bc, delayioh, 0);
- (void) bus_io_read_1(bc, delayioh, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
/* Now zero memory and verify that it is clear. */
if (isa16bit) {
for (i = 0; i < memsize; i += 2)
- bus_mem_write_2(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_2(memt, memh, sc->mem_start + i, 0);
} else {
for (i = 0; i < memsize; ++i)
- bus_mem_write_1(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_1(memt, memh, sc->mem_start + i, 0);
}
memfail = 0;
if (isa16bit) {
for (i = 0; i < memsize; i += 2) {
- if (bus_mem_read_2(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_2(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
}
} else {
for (i = 0; i < memsize; ++i) {
- if (bus_mem_read_1(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_1(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
(ia->ia_maddr + sc->mem_start + i));
/* Disable 16 bit access to shared memory. */
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc, delayioh, 0);
- (void) bus_io_read_1(bc, delayioh, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
goto out;
}
* and 2) so that other 8 bit devices with shared memory can be
* used in this 128k region, too.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto);
if (isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc, delayioh, 0);
- (void) bus_io_read_1(bc, delayioh, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
ia->ia_iosize = ED_WD_IO_PORTS;
rv = 1;
* XXX Need to squish "indirect" first.
*/
if (rv == 0) {
- bus_io_unmap(bc, ioh, ED_WD_IO_PORTS);
+ bus_space_unmap(iot, ioh, ED_WD_IO_PORTS);
if (mapped_mem)
- bus_mem_unmap(bc, memh, memsize);
+ bus_space_unmap(memt, memh, memsize);
} else {
/* XXX this is all "indirect" brokenness */
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
+ sc->sc_memt = memt;
sc->sc_ioh = ioh;
sc->sc_memh = memh;
}
return (rv);
}
-int ed_3com_iobase[] = {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300};
-int ed_3com_maddr[] = {MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000};
+int ed_3com_iobase[] =
+ {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300};
+int ed_3com_maddr[] = {
+ MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000
+};
#if 0
int ed_3com_irq[] = {IRQUNK, IRQUNK, IRQUNK, IRQUNK, 9, 3, 4, 5};
#endif
struct cfdata *cf;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- bus_mem_handle_t memh;
+ bus_space_tag_t iot;
+ bus_space_tag_t memt;
+ bus_space_handle_t ioh;
+ bus_space_handle_t memh;
int i;
u_int memsize, memfail;
u_char isa16bit, x;
*/
memsize = 8192;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
+ memt = ia->ia_memt;
- if (bus_io_map(bc, ia->ia_iobase, ED_WD_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ED_3COM_IO_PORTS, 0, &ioh))
return (0);
sc->asic_base = asicbase = ED_3COM_ASIC_OFFSET;
* board is there; after all, we are already talking it at that
* address.
*/
- x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_BCFR);
+ x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_BCFR);
if (x == 0 || (x & (x - 1)) != 0)
goto err;
ptr = ffs(x) - 1;
} else
ia->ia_iobase = ed_3com_iobase[ptr]; /* XXX --thorpej */
- x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_PCFR);
- if (x == 0 || (x & (x - 1)) != 0)
+ x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_PCFR);
+ if (x == 0 || (x & (x - 1)) != 0) {
+ printf("%s: The 3c503 is not currently supported with memory "
+ "mapping disabled.\n%s: Reconfigure the card to "
+ "enable memory mapping.\n",
+ sc->sc_dev.dv_xname, sc->sc_dev.dv_xname);
goto err;
+ }
ptr = ffs(x) - 1;
if (ia->ia_maddr != MADDRUNK) {
if (ia->ia_maddr != ed_3com_maddr[ptr]) {
ia->ia_maddr = ed_3com_maddr[ptr];
#if 0
- x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_IDCFR) &
+ x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_IDCFR) &
ED_3COM_IDCFR_IRQ;
if (x == 0 || (x & (x - 1)) != 0)
goto out;
* sequence because it'll lock up if the cable isn't connected if we
* don't.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR,
ED_3COM_CR_RST | ED_3COM_CR_XSEL);
/* Wait for a while, then un-reset it. */
* reset - it's important to set it again after the following outb
* (this is done when we map the PROM below).
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
/* Wait a bit for the NIC to recover from the reset. */
delay(5000);
* First, map ethernet address PROM over the top of where the NIC
* registers normally appear.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR,
ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
for (i = 0; i < ETHER_ADDR_LEN; ++i)
- sc->sc_arpcom.ac_enaddr[i] = NIC_GET(bc, ioh, nicbase, i);
+ sc->sc_arpcom.ac_enaddr[i] = NIC_GET(iot, ioh, nicbase, i);
/*
* Unmap PROM - select NIC registers. The proper setting of the
* tranceiver is set in edinit so that the attach code is given a
* chance to set the default based on a compile-time config option.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
/* Determine if this is an 8bit or 16bit board. */
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
/*
* Attempt to clear WTS bit. If it doesn't clear, then this is a
* 16-bit board.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, 0);
/* Select page 2 registers. */
- NIC_PUT(bc, ioh, nicbase,
+ NIC_PUT(iot, ioh, nicbase,
ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_2 | ED_CR_STP);
/* The 3c503 forces the WTS bit to a one if this is a 16bit board. */
- if (NIC_GET(bc, ioh, nicbase, ED_P2_DCR) & ED_DCR_WTS)
+ if (NIC_GET(iot, ioh, nicbase, ED_P2_DCR) & ED_DCR_WTS)
isa16bit = 1;
else
isa16bit = 0;
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P2_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P2_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
- if (bus_mem_map(bc, ia->ia_maddr, memsize, 0, &memh))
+ if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh))
goto err;
sc->mem_start = 0; /* offset */
sc->mem_size = memsize;
* Initialize GA page start/stop registers. Probably only needed if
* doing DMA, but what the Hell.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_PSTR, sc->rec_page_start);
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_PSPR, sc->rec_page_stop);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_PSTR, sc->rec_page_start);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_PSPR, sc->rec_page_stop);
/* Set IRQ. 3c503 only allows a choice of irq 3-5 or 9. */
switch (ia->ia_irq) {
case 9:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ2);
break;
case 3:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ3);
break;
case 4:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ4);
break;
case 5:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ5);
break;
default:
* Initialize GA configuration register. Set bank and enable shared
* mem.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_GACFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
/*
* shared memory is disabled. We set them to 0xffff0...allegedly the
* reset vector.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR2, 0xff);
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR1, 0xff);
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR0, 0x00);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR2, 0xff);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR1, 0xff);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR0, 0x00);
/* Now zero memory and verify that it is clear. */
if (isa16bit) {
for (i = 0; i < memsize; i += 2)
- bus_mem_write_2(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_2(memt, memh, sc->mem_start + i, 0);
} else {
for (i = 0; i < memsize; ++i)
- bus_mem_write_1(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_1(memt, memh, sc->mem_start + i, 0);
}
memfail = 0;
if (isa16bit) {
for (i = 0; i < memsize; i += 2) {
- if (bus_mem_read_2(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_2(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
}
} else {
for (i = 0; i < memsize; ++i) {
- if (bus_mem_read_1(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_1(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
* XXX Sould always unmap, but we can't yet.
* XXX Need to squish "indirect" first.
*/
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
+ sc->sc_memt = memt;
sc->sc_ioh = ioh;
sc->sc_memh = memh;
return 1;
out:
- bus_mem_unmap(bc, memh, memsize);
+ bus_space_unmap(memt, memh, memsize);
err:
- bus_io_unmap(bc, ioh, ED_3COM_IO_PORTS);
+ bus_space_unmap(iot, ioh, ED_3COM_IO_PORTS);
return 0;
}
struct cfdata *cf;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int memsize, n;
u_char romdata[16], tmp;
static u_char test_pattern[32] = "THIS is A memory TEST pattern";
u_char test_buffer[32];
int asicbase, nicbase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
- if (bus_io_map(bc, ia->ia_iobase, ED_NOVELL_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ED_NOVELL_IO_PORTS, 0, &ioh))
return (0);
sc->asic_base = asicbase = ED_NOVELL_ASIC_OFFSET;
/* Reset the board. */
#ifdef GWETHER
- bus_io_write_1(bc, ioh, asicbase + ED_NOVELL_RESET, 0);
+ bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, 0);
delay(200);
#endif /* GWETHER */
- tmp = bus_io_read_1(bc, ioh, asicbase + ED_NOVELL_RESET);
+ tmp = bus_space_read_1(iot, ioh, asicbase + ED_NOVELL_RESET);
/*
* I don't know if this is necessary; probably cruft leftover from
* complete documentation on what the 'right' thing to do is...so we do
* the invasive thing for now. Yuck.]
*/
- bus_io_write_1(bc, ioh, asicbase + ED_NOVELL_RESET, tmp);
+ bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, tmp);
delay(5000);
/*
* XXX - this makes the probe invasive! ...Done against my better
* judgement. -DLG
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
delay(5000);
/* Make sure that we really have an 8390 based board. */
- if (!ed_probe_generic8390(bc, ioh, nicbase))
+ if (!ed_probe_generic8390(iot, ioh, nicbase))
goto out;
sc->vendor = ED_VENDOR_NOVELL;
* This prevents packets from being stored in the NIC memory when the
* readmem routine turns on the start bit in the CR.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
/* Temporarily initialize DCR for byte operations. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
sc->isa16bit = 0;
/*
* XXX indirect brokenness, used by ed_pio{read,write}mem()
*/
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
/*
if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
/* not an NE1000 - try NE2000 */
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR,
ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
sc->isa16bit = 1;
#endif /* GWETHER */
/* Clear any pending interrupts that might have occurred above. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, 0xff);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff);
ia->ia_iosize = ED_NOVELL_IO_PORTS;
* XXX Sould always unmap, but we can't yet.
* XXX Need to squish "indirect" first.
*/
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
/* sc_memh is not used by this driver */
return 1;
out:
- bus_io_unmap(bc, ioh, ED_NOVELL_IO_PORTS);
+ bus_space_unmap(iot, ioh, ED_NOVELL_IO_PORTS);
return 0;
}
struct device *parent, *self;
void *aux;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct ed_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
struct cfdata *cf = sc->sc_dev.dv_cfdata;
* XXX Should re-map io and mem, but can't
* XXX until we squish "indirect" brokenness.
*/
- bc = sc->sc_bc; /* XXX */
+ iot = sc->sc_iot; /* XXX */
ioh = sc->sc_ioh; /* XXX */
asicbase = sc->asic_base;
- sc->sc_delayioh = ia->ia_delayioh;
+ sc->sc_delaybah = ia->ia_delaybah;
/* Set interface to stopped condition (reset). */
edstop(sc);
case ED_VENDOR_WD_SMC:
if ((sc->type & ED_WD_SOFTCONFIG) == 0)
break;
- if ((bus_io_read_1(bc, ioh, asicbase + ED_WD_IRR) &
+ if ((bus_space_read_1(iot, ioh, asicbase + ED_WD_IRR) &
ED_WD_IRR_OUT2) == 0)
ifp->if_flags |= IFF_LINK0;
break;
edstop(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
int n = 5000;
/* Stop everything on the interface, and select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
/*
* 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
* just in case it's an old one.
*/
- while (((NIC_GET(bc, ioh, nicbase,
+ while (((NIC_GET(iot, ioh, nicbase,
ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
}
edinit(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int nicbase = sc->nic_base, asicbase = sc->asic_base;
int i;
sc->txb_next_tx = 0;
/* Set interface for page 0, remote DMA complete, stopped. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
if (sc->isa16bit) {
* Set FIFO threshold to 8, No auto-init Remote DMA, byte
* order=80x86, word-wide DMA xfers,
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR,
ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
} else {
/* Same as above, but byte-wide DMA xfers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
}
/* Clear remote byte count registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, 0);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, 0);
/* Tell RCR to do nothing for now. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
/* Place NIC in internal loopback mode. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TCR, ED_TCR_LB0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TCR, ED_TCR_LB0);
/* Set lower bits of byte addressable framing to 0. */
if (sc->is790)
- NIC_PUT(bc, ioh, nicbase, 0x09, 0);
+ NIC_PUT(iot, ioh, nicbase, 0x09, 0);
/* Initialize receive buffer ring. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_BNRY, sc->rec_page_start);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, sc->rec_page_start);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, sc->rec_page_stop);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_BNRY, sc->rec_page_start);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, sc->rec_page_start);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, sc->rec_page_stop);
/*
* Clear all interrupts. A '1' in each bit position clears the
* corresponding flag.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, 0xff);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff);
/*
* Enable the following interrupts: receive/transmit complete,
*
* Counter overflow and Remote DMA complete are *not* enabled.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_IMR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_IMR,
ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE |
ED_IMR_OVWE);
/* Program command register for page 1. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
/* Copy out our station address. */
for (i = 0; i < ETHER_ADDR_LEN; ++i)
- NIC_PUT(bc, ioh, nicbase, ED_P1_PAR0 + i,
+ NIC_PUT(iot, ioh, nicbase, ED_P1_PAR0 + i,
sc->sc_arpcom.ac_enaddr[i]);
/* Set multicast filter on chip. */
isaed_getmcaf(&sc->sc_arpcom, mcaf);
for (i = 0; i < 8; i++)
- NIC_PUT(bc, ioh, nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
+ NIC_PUT(iot, ioh, nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
/*
* Set current page pointer to one page after the boundary pointer, as
* recommended in the National manual.
*/
sc->next_packet = sc->rec_page_start + 1;
- NIC_PUT(bc, ioh, nicbase, ED_P1_CURR, sc->next_packet);
+ NIC_PUT(iot, ioh, nicbase, ED_P1_CURR, sc->next_packet);
/* Program command register for page 0. */
- NIC_PUT(bc, ioh, nicbase, ED_P1_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P1_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
i = ED_RCR_AB | ED_RCR_AM;
*/
i |= ED_RCR_PRO | ED_RCR_AR | ED_RCR_SEP;
}
- NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, i);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, i);
/* Take interface out of loopback. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TCR, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TCR, 0);
/*
* If this is a 3Com board, the tranceiver must be software enabled
u_char x;
case ED_VENDOR_3COM:
if (ifp->if_flags & IFF_LINK0)
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, 0);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, 0);
else
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR,
ED_3COM_CR_XSEL);
break;
case ED_VENDOR_WD_SMC:
if ((sc->type & ED_WD_SOFTCONFIG) == 0)
break;
- x = bus_io_read_1(bc, ioh, asicbase + ED_WD_IRR);
+ x = bus_space_read_1(iot, ioh, asicbase + ED_WD_IRR);
if (ifp->if_flags & IFF_LINK0)
x &= ~ED_WD_IRR_OUT2;
else
x |= ED_WD_IRR_OUT2;
- bus_io_write_1(bc, ioh, asicbase + ED_WD_IRR, x);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_IRR, x);
break;
}
/* Fire up the interface. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/* Set 'running' flag, and clear output active flag. */
ed_xmit(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int nicbase = sc->nic_base;
u_short len;
len = sc->txb_len[sc->txb_next_tx];
/* Set NIC for page 0 register access. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/* Set TX buffer start page. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TPSR, sc->tx_page_start +
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TPSR, sc->tx_page_start +
sc->txb_next_tx * ED_TXBUF_SIZE);
/* Set TX length. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TBCR0, len);
- NIC_PUT(bc, ioh, nicbase, ED_P0_TBCR1, len >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TBCR0, len);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TBCR1, len >> 8);
/* Set page 0, remote DMA complete, transmit packet, and *start*. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA);
/* Point to next transmit buffer slot and wrap if necessary. */
struct ifnet *ifp;
{
struct ed_softc *sc = ifp->if_softc;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct mbuf *m0, *m;
int buffer;
int asicbase = sc->asic_base;
*/
case ED_VENDOR_3COM:
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL);
break;
*/
case ED_VENDOR_WD_SMC:
if (sc->isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
break;
}
switch (sc->vendor) {
case ED_VENDOR_3COM:
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
break;
case ED_VENDOR_WD_SMC:
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (sc->isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
break;
}
} else
ed_rint(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
u_int8_t boundary, current;
u_int16_t len;
loop:
/* Set NIC to page 1 registers to get 'current' pointer. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
/*
* until the logical beginning equals the logical end (or in other
* words, until the ring-buffer is empty).
*/
- current = NIC_GET(bc, ioh, nicbase, ED_P1_CURR);
+ current = NIC_GET(iot, ioh, nicbase, ED_P1_CURR);
if (sc->next_packet == current)
return;
/* Set NIC to page 0 registers to update boundary register. */
- NIC_PUT(bc, ioh, nicbase, ED_P1_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P1_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
do {
boundary = sc->next_packet - 1;
if (boundary < sc->rec_page_start)
boundary = sc->rec_page_stop - 1;
- NIC_PUT(bc, ioh, nicbase, ED_P0_BNRY, boundary);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_BNRY, boundary);
} while (sc->next_packet != current);
goto loop;
void *arg;
{
struct ed_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int nicbase = sc->nic_base, asicbase = sc->asic_base;
u_char isr;
/* Set NIC to page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
- isr = NIC_GET(bc, ioh, nicbase, ED_P0_ISR);
+ isr = NIC_GET(iot, ioh, nicbase, ED_P0_ISR);
if (!isr)
return (0);
* '1' to each bit position that was set.
* (Writing a '1' *clears* the bit.)
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, isr);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, isr);
/*
* Handle transmitter interrupts. Handle these first because
* the receiver will reset the board under some conditions.
*/
if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
- u_char collisions = NIC_GET(bc, ioh, nicbase,
+ u_char collisions = NIC_GET(iot, ioh, nicbase,
ED_P0_NCR) & 0x0f;
/*
* course, with UDP we're screwed, but this is expected
* when a network is heavily loaded.
*/
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_TSR);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_TSR);
if (isr & ED_ISR_TXE) {
/*
* Excessive collisions (16).
*/
- if ((NIC_GET(bc, ioh, nicbase, ED_P0_TSR) &
+ if ((NIC_GET(iot, ioh, nicbase, ED_P0_TSR) &
ED_TSR_ABT) && (collisions == 0)) {
/*
* When collisions total 16, the P0_NCR
*/
if (sc->vendor == ED_VENDOR_WD_SMC) {
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_LAAR,
sc->wd_laar_proto |
ED_WD_LAAR_M16EN);
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
}
ed_rint(sc);
/* Disable 16-bit access. */
if (sc->vendor == ED_VENDOR_WD_SMC) {
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
}
}
}
* set in the transmit routine, is *okay* - it is 'edge'
* triggered from low to high).
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/*
* otherwise - resulting in an infinite loop.
*/
if (isr & ED_ISR_CNT) {
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR0);
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR1);
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR2);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR0);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR1);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR2);
}
- isr = NIC_GET(bc, ioh, nicbase, ED_P0_ISR);
+ isr = NIC_GET(iot, ioh, nicbase, ED_P0_ISR);
if (!isr)
return (1);
}
caddr_t dst;
u_short amount;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Round up to a word. */
++amount;
/* Set up DMA byte count. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, amount);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, amount >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, amount);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, amount >> 8);
/* Set up source address in NIC mem. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, src);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, src >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, src);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, src >> 8);
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
if (sc->isa16bit)
- bus_io_read_raw_multi_2(bc, ioh,
+ bus_space_read_raw_multi_2(iot, ioh,
sc->asic_base + ED_NOVELL_DATA, dst, amount);
else
- bus_io_read_multi_1(bc, ioh, sc->asic_base + ED_NOVELL_DATA,
- dst, amount);
+ bus_space_read_multi_1(iot, ioh,
+ sc->asic_base + ED_NOVELL_DATA, dst, amount);
}
/*
u_short dst;
u_short len;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
int maxwait = 100; /* about 120us */
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Reset remote DMA complete flag. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
/* Set up DMA byte count. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, len);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, len >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8);
/* Set up destination address in NIC mem. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, dst);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
/* Set remote DMA write. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
if (sc->isa16bit)
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
sc->asic_base + ED_NOVELL_DATA, src, len);
else
- bus_io_write_multi_1(bc, ioh, sc->asic_base + ED_NOVELL_DATA,
- src, len);
+ bus_space_write_multi_1(iot, ioh,
+ sc->asic_base + ED_NOVELL_DATA, src, len);
/*
* Wait for remote DMA complete. This is necessary because on the
* waiting causes really bad things to happen - like the NIC
* irrecoverably jamming the ISA bus.
*/
- while (((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
+ while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
ED_ISR_RDC) && --maxwait);
}
struct mbuf *m;
u_short dst;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base, asicbase = sc->asic_base;
u_short len;
int maxwait = 100; /* about 120us */
len = m->m_pkthdr.len;
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Reset remote DMA complete flag. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
/* Set up DMA byte count. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, len);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, len >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8);
/* Set up destination address in NIC mem. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, dst);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
/* Set remote DMA write. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
/*
/* NE1000s are easy. */
for (; m != 0; m = m->m_next) {
if (m->m_len) {
- bus_io_write_multi_1(bc, ioh,
+ bus_space_write_multi_1(iot, ioh,
asicbase + ED_NOVELL_DATA,
mtod(m, u_char *), m->m_len);
}
/* Finish the last word. */
if (wantbyte) {
savebyte[1] = *data;
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
asicbase + ED_NOVELL_DATA, savebyte, 2);
data++;
len--;
}
/* Output contiguous words. */
if (len > 1) {
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
asicbase + ED_NOVELL_DATA, data, len & ~1);
}
/* Save last byte, if necessary. */
if (wantbyte) {
savebyte[1] = 0;
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
asicbase + ED_NOVELL_DATA, savebyte, 2);
}
}
* waiting causes really bad things to happen - like the NIC
* irrecoverably jamming the ISA bus.
*/
- while (((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
+ while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
ED_ISR_RDC) && --maxwait);
if (!maxwait) {
caddr_t from;
int card, len;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_mem_handle_t memh = sc->sc_memh;
+ bus_space_tag_t memt = sc->sc_memt;
+ bus_space_handle_t memh = sc->sc_memh;
u_int16_t word;
/*
if (sc->isa16bit) {
while (len > 1) {
word = (u_int8_t)from[0] | (u_int8_t)from[1] << 8;
- bus_mem_write_2(bc, memh, card, word);
+ bus_space_write_2(memt, memh, card, word);
from += 2;
card += 2;
len -= 2;
}
if (len == 1) {
word = *from;
- bus_mem_write_2(bc, memh, card, word);
+ bus_space_write_2(memt, memh, card, word);
}
} else {
while (len--)
- bus_mem_write_1(bc, memh, card++, *from++);
+ bus_space_write_1(memt, memh, card++, *from++);
}
}
caddr_t to;
int card, len;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_mem_handle_t memh = sc->sc_memh;
+ bus_space_tag_t memt = sc->sc_memt;
+ bus_space_handle_t memh = sc->sc_memh;
u_int16_t word;
/*
* See comment above re. 16-bit cards.
*/
if (sc->isa16bit) {
+ /* XXX I think maybe a bus_space_read_raw_region is needed. */
while (len > 1) {
- word = bus_mem_read_2(bc, memh, card);
+ word = bus_space_read_2(memt, memh, card);
*to++ = word & 0xff;
*to++ = word >> 8 & 0xff;
card += 2;
len -= 2;
}
if (len == 1)
- *to = bus_mem_read_2(bc, memh, card) & 0xff;
+ *to = bus_space_read_2(memt, memh, card) & 0xff;
} else {
while (len--)
- *to++ = bus_mem_read_1(bc, memh, card++);
+ *to++ = bus_space_read_1(memt, memh, card++);
}
}
-/* $OpenBSD: conf.c,v 1.10 1996/11/25 14:52:57 niklas Exp $ */
+/* $OpenBSD: conf.c,v 1.11 1996/11/28 23:35:38 niklas Exp $ */
/*
* Copyright (c) 1992, 1993
* SUCH DAMAGE.
*
* from: @(#)conf.c 8.2 (Berkeley) 11/14/93
- * $Id: conf.c,v 1.10 1996/11/25 14:52:57 niklas Exp $
+ * $Id: conf.c,v 1.11 1996/11/28 23:35:38 niklas Exp $
*/
#include <sys/param.h>
dev_init(c,n,tty), ttselect, dev_init(c,n,mmap), D_TTY }
/* open, close, write, ioctl */
-#define cdev_lpr_init(c,n) { \
+#define cdev_lpt_init(c,n) { \
dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
dev_init(c,n,write), dev_init(c,n,ioctl), (dev_type_stop((*))) enodev, \
0, seltrue, (dev_type_mmap((*))) enodev }
cdev_decl(vnd);
#include "bpfilter.h"
cdev_decl(bpf);
-#include "ace.h"
-cdev_decl(ace);
-#include "lpr.h"
-cdev_decl(lpr);
+#include "com.h"
+cdev_decl(com);
+#include "lpt.h"
+cdev_decl(lpt);
cdev_decl(sd);
#include "pc.h"
cdev_decl(pc);
cdev_disk_init(NFDC,fd), /* 13: Floppy disk */
cdev_pc_init(NPC,pc), /* 14: builtin pc style console dev */
cdev_mouse_init(1,pms), /* 15: builtin PS2 style mouse */
- cdev_lpr_init(NLPR,lpr), /* 16: lpr parallel printer interface */
- cdev_tty_init(NACE,ace), /* 17: ace 16C450 serial interface */
+ cdev_lpt_init(NLPT,lpt), /* 16: Parallel printer interface */
+ cdev_tty_init(NCOM,com), /* 17: 16C450 serial interface */
cdev_disk_init(NWDC,wd), /* 18: ST506/ESDI/IDE disk */
cdev_disk_init(NACD,acd), /* 19: ATAPI CD-ROM */
cdev_tty_init(NPTY,pts), /* 20: pseudo-tty slave */
#include <dev/cons.h>
cons_decl(pc);
-cons_decl(ace);
+cons_decl(com);
struct consdev constab[] = {
#if NPC + NVT > 0
cons_init(pc),
#endif
#if NACE > 0
- cons_init(ace),
+ cons_init(com),
#endif
{ 0 },
};
-# $OpenBSD: ARCTIC,v 1.4 1996/11/12 08:44:08 niklas Exp $
+# $OpenBSD: ARCTIC,v 1.5 1996/11/28 23:35:39 niklas Exp $
#
# Generic configuration file for MIPS R4x00 ARC Systems
#
clock0 at isa? port 0x70 irq 0
pc0 at isa? port 0x60 irq 1 # generic PC console device
-ace0 at isa? port 0x3f8 irq 4
-ace1 at isa? port 0x2f8 irq 3
-ace2 at isa? port 0x3e8 irq 4
-ace3 at isa? port 0x2e8 irq 3
+com0 at isa? port 0x3f8 irq 4
+com1 at isa? port 0x2f8 irq 3
+com2 at isa? port 0x3e8 irq 4
+com3 at isa? port 0x2e8 irq 3
wdc0 at isa? port 0x1f0 irq 14 # ST506, ESDI, and IDE controllers
wdc1 at isa? port 0x170 irq 15
-# $OpenBSD: GENERIC,v 1.10 1996/10/01 21:26:03 pefo Exp $
+# $OpenBSD: GENERIC,v 1.11 1996/11/28 23:35:39 niklas Exp $
#
# Generic configuration file for MIPS R4x00 ARC Systems
#
clock0 at pica?
pc0 at pica?
pms0 at pica?
-ace0 at pica?
-ace1 at pica?
-lpr0 at pica?
+com0 at pica?
+com1 at pica?
+lpt0 at pica?
sn0 at pica?
fdc0 at pica?
clock0 at isa? port 0x70 irq 0
pc0 at isa? port 0x60 irq 1 # generic PC console device
-ace0 at isa? port 0x3f8 irq 4
-ace1 at isa? port 0x2f8 irq 3
-ace2 at isa? port 0x3e8 irq 4
-ace3 at isa? port 0x2e8 irq 3
+com0 at isa? port 0x3f8 irq 4
+com1 at isa? port 0x2f8 irq 3
+com2 at isa? port 0x3e8 irq 4
+com3 at isa? port 0x2e8 irq 3
wdc0 at isa? port 0x1f0 irq 14 # ST506, ESDI, and IDE controllers
#wdc1 at isa? port 0x170 irq 15
clock0 at pica?
pc0 at pica?
pms0 at pica?
-ace0 at pica?
-ace1 at pica?
-lpr0 at pica?
+com0 at pica?
+com1 at pica?
+lpt0 at pica?
sn0 at pica?
fdc0 at pica?
isa* at isabr?
-ace2 at isa? port 0x3f8 irq 4
-ace3 at isa? port 0x2f8 irq 3
+com2 at isa? port 0x3f8 irq 4
+com3 at isa? port 0x2f8 irq 3
pseudo-device sl 2 # serial-line IP ports
-# $OpenBSD: files.arc,v 1.8 1996/09/24 21:30:00 niklas Exp $
+# $OpenBSD: files.arc,v 1.9 1996/11/28 23:35:40 niklas Exp $
#
# maxpartitions must be first item in files.${ARCH}
#
device isabr {} : isabus
attach isabr at mainbus
file arch/arc/isa/isabus.c isabr
-file arch/arc/isa/isadma.c isadma needs-flag
+#file arch/arc/isa/isadma.c isadma needs-flag
+file dev/isa/isadma.c isadma needs-flag
# Ethernet chip
device sn
attach pms at pica
file arch/arc/dev/pccons.c pc & (pc_pica | pc_isa) needs-flag
-# Serial driver for both ISA and LOCAL bus.
-device ace: tty
-attach ace at isa with ace_isa
-attach ace at commulti with ace_commulti
-attach ace at pica with ace_pica
-file arch/arc/dev/ace.c ace & (ace_isa | ace_commulti | ace_pica) needs-flag
-
-# Parallel ports (XXX what chip?)
-device lpr
-attach lpr at isa with lpr_isa
-attach lpr at pica with lpr_pica
-file arch/arc/dev/lpr.c lpr & (lpr_isa | lpr_pica) needs-flag
-
# BusLogic BT-445C VLB SCSI Controller. Special on TYNE local bus.
device btl: scsi
attach btl at isa
file arch/arc/dti/btl.c btl needs-count
+# 8250/16[45]50-based "com" ports
+attach com at pica with com_pica
+
# National Semiconductor DS8390/WD83C690-based boards
# (WD/SMC 80x3 family, SMC Ultra [8216], 3Com 3C503, NE[12]000, and clones)
# XXX conflicts with other ports; can't be in files.isa
attach ed at pcmcia with ed_pcmcia
file dev/isa/if_ed.c ed & (ed_isa | ed_pcmcia) needs-flag
+# PC parallel ports (XXX what chip?)
+attach lpt at pica with lpt_pica
+file arch/arc/pica/lpt_pica.c lpt_pica
+
#
file dev/cons.c
+++ /dev/null
-/* $OpenBSD: ace.c,v 1.7 1996/11/12 20:29:53 niklas Exp $ */
-/* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */
-
-/*-
- * Copyright (c) 1993, 1994, 1995, 1996
- * Charles M. Hannum. All rights reserved.
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)com.c 7.5 (Berkeley) 5/16/91
- */
-
-/*
- * ACE driver, based on HP dca driver
- * uses National Semiconductor NS16450/NS16550AF UART
- */
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/ioctl.h>
-#include <sys/select.h>
-#include <sys/tty.h>
-#include <sys/proc.h>
-#include <sys/user.h>
-#include <sys/conf.h>
-#include <sys/file.h>
-#include <sys/uio.h>
-#include <sys/kernel.h>
-#include <sys/syslog.h>
-#include <sys/types.h>
-#include <sys/device.h>
-
-#include <arc/arc/arctype.h>
-#include <machine/bus.old.h>
-#include <machine/intr.h>
-
-#include <dev/isa/isavar.h>
-#include <dev/isa/comreg.h>
-#include <dev/isa/comvar.h>
-#include <dev/ic/ns16550reg.h>
-#ifdef COM_HAYESP
-#include <dev/ic/hayespreg.h>
-#endif
-#define com_lcr com_cfcr
-
-#include "ace.h"
-
-
-#define COM_IBUFSIZE (2 * 512)
-#define COM_IHIGHWATER ((3 * COM_IBUFSIZE) / 4)
-
-struct com_softc {
- struct device sc_dev;
- void *sc_ih;
- bus_chipset_tag_t sc_bc;
- struct tty *sc_tty;
-
- int sc_overflows;
- int sc_floods;
- int sc_errors;
-
- int sc_halt;
-
- int sc_iobase;
-#ifdef COM_HAYESP
- int sc_hayespbase;
-#endif
-
- bus_io_handle_t sc_ioh;
- bus_io_handle_t sc_hayespioh;
-
- u_char sc_hwflags;
-#define COM_HW_NOIEN 0x01
-#define COM_HW_FIFO 0x02
-#define COM_HW_HAYESP 0x04
-#define COM_HW_ABSENT_PENDING 0x08 /* reattached, awaiting close/reopen */
-#define COM_HW_ABSENT 0x10 /* configure actually failed, or removed */
-#define COM_HW_REATTACH 0x20 /* reattaching */
-#define COM_HW_CONSOLE 0x40
- u_char sc_swflags;
-#define COM_SW_SOFTCAR 0x01
-#define COM_SW_CLOCAL 0x02
-#define COM_SW_CRTSCTS 0x04
-#define COM_SW_MDMBUF 0x08
- u_char sc_msr, sc_mcr, sc_lcr, sc_ier;
- u_char sc_dtr;
-
- u_char sc_cua;
-
- u_char *sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend;
- u_char sc_ibufs[2][COM_IBUFSIZE];
-};
-
-#ifdef COM_HAYESP
-int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc));
-#endif
-void comdiag __P((void *));
-int comspeed __P((long));
-int comparam __P((struct tty *, struct termios *));
-void comstart __P((struct tty *));
-void compoll __P((void *));
-
-/* XXX: These belong elsewhere */
-cdev_decl(com);
-bdev_decl(com);
-
-struct consdev;
-void acecnprobe __P((struct consdev *));
-void acecninit __P((struct consdev *));
-int acecngetc __P((dev_t));
-void acecnputc __P((dev_t, int));
-void acecnpollc __P((dev_t, int));
-
-static u_char tiocm_xxx2mcr __P((int));
-
-/*
- * XXX the following two cfattach structs should be different, and possibly
- * XXX elsewhere.
- */
-int comprobe __P((struct device *, void *, void *));
-void comattach __P((struct device *, struct device *, void *));
-void com_absent_notify __P((struct com_softc *sc));
-void comstart_pending __P((void *));
-
-#if NACE_ISA
-struct cfattach ace_isa_ca = {
- sizeof(struct com_softc), comprobe, comattach
-};
-#endif
-
-#if NACE_COMMULTI
-struct cfattach ace_commulti_ca = {
- sizeof(struct com_softc), comprobe, comattach
-};
-#endif
-
-#if NACE_PICA
-#undef CONADDR /* This is stupid but using devs before config .. */
-#define CONADDR 0xe0006000
-
-struct cfattach ace_pica_ca = {
- sizeof(struct com_softc), comprobe, comattach
-};
-#endif
-
-
-struct cfdriver ace_cd = {
- NULL, "ace", DV_TTY
-};
-
-void cominit __P((bus_chipset_tag_t, bus_io_handle_t, int));
-
-#ifndef CONSPEED
-#define CONSPEED B9600
-#endif
-
-#ifdef COMCONSOLE
-int comdefaultrate = CONSPEED; /* XXX why set default? */
-#else
-int comdefaultrate = TTYDEF_SPEED;
-#endif
-int comconsaddr;
-int comconsinit;
-int comconsattached;
-bus_chipset_tag_t comconsbc;
-bus_io_handle_t comconsioh;
-tcflag_t comconscflag = TTYDEF_CFLAG;
-
-int commajor;
-int comsopen = 0;
-int comevents = 0;
-
-#ifdef KGDB
-#include <machine/remote-sl.h>
-extern int kgdb_dev;
-extern int kgdb_rate;
-extern int kgdb_debug_init;
-#endif
-
-#define DEVUNIT(x) (minor(x) & 0x7f)
-#define DEVCUA(x) (minor(x) & 0x80)
-
-/* Macros to clear/set/test flags. */
-#define SET(t, f) (t) |= (f)
-#define CLR(t, f) (t) &= ~(f)
-#define ISSET(t, f) ((t) & (f))
-
-#if NACE_PCMCIA
-#include <dev/pcmcia/pcmciavar.h>
-
-int com_pcmcia_match __P((struct device *, void *, void *));
-void com_pcmcia_attach __P((struct device *, struct device *, void *));
-int com_pcmcia_detach __P((struct device *));
-
-struct cfattach ace_pcmcia_ca = {
- sizeof(struct com_softc), com_pcmcia_match, comattach,
- com_pcmcia_detach
-};
-
-int com_pcmcia_mod __P((struct pcmcia_link *pc_link, struct device *self,
- struct pcmcia_conf *pc_cf, struct cfdata *cf));
-
-/* additional setup needed for pcmcia devices */
-/* modify config entry */
-int
-com_pcmcia_mod(pc_link, self, pc_cf, cf)
- struct pcmcia_link *pc_link;
- struct device *self;
- struct pcmcia_conf *pc_cf;
- struct cfdata *cf;
-{
- int err;
- struct pcmciadevs *dev = pc_link->device;
- struct ed_softc *sc = (void *)self;
- if (!(err = PCMCIA_BUS_CONFIG(pc_link->adapter, pc_link, self,
- pc_cf, cf))) {
- pc_cf->memwin = 0;
- if (pc_cf->cfgtype == 0)
- pc_cf->cfgtype = CFGENTRYID; /* determine from ioaddr */
- }
- return err;
-}
-
-int com_pcmcia_isa_attach __P((struct device *, void *, void *,
- struct pcmcia_link *));
-int com_pcmcia_remove __P((struct pcmcia_link *, struct device *));
-
-static struct pcmcia_com {
- struct pcmcia_device pcd;
-} pcmcia_com = {
- {"PCMCIA Modem card", com_pcmcia_mod, com_pcmcia_isa_attach,
- NULL, com_pcmcia_remove}
-};
-
-
-struct pcmciadevs pcmcia_com_devs[] = {
- { "com", 0,
- NULL, "*MODEM*", NULL, NULL,
- NULL, (void *)&pcmcia_com
- },
- { "com", 0,
- NULL, NULL, "*MODEM*", NULL,
- NULL, (void *)&pcmcia_com
- },
- { "com", 0,
- NULL, NULL, NULL, "*MODEM*",
- NULL, (void *)&pcmcia_com
- },
- {NULL}
-};
-#define ncom_pcmcia_devs sizeof(pcmcia_com_devs)/sizeof(pcmcia_com_devs[0])
-
-int
-com_pcmcia_match(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- return pcmcia_slave_match(parent, match, aux, pcmcia_com_devs,
- ncom_pcmcia_devs);
-}
-
-int
-com_pcmcia_isa_attach(parent, match, aux, pc_link)
- struct device *parent;
- void *match;
- void *aux;
- struct pcmcia_link *pc_link;
-{
- struct isa_attach_args *ia = aux;
- struct com_softc *sc = match;
-
- int rval;
- if (rval = comprobe(parent, sc->sc_dev.dv_cfdata, ia)) {
- if (ISSET(pc_link->flags, PCMCIA_REATTACH)) {
-#ifdef COM_DEBUG
- printf("comreattach, hwflags=%x\n", sc->sc_hwflags);
-#endif
- sc->sc_hwflags = COM_HW_REATTACH |
- (sc->sc_hwflags & (COM_HW_ABSENT_PENDING|COM_HW_CONSOLE));
- } else
- sc->sc_hwflags = 0;
- }
- return rval;
-}
-
-
-/*
- * Called by config_detach attempts, shortly after com_pcmcia_remove
- * was called.
- */
-int
-com_pcmcia_detach(self)
- struct device *self;
-{
- struct com_softc *sc = (void *)self;
-
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT_PENDING)) {
- /* don't let it really be detached, it is still open */
- return EBUSY;
- }
- return 0; /* OK! */
-}
-
-/*
- * called by pcmcia framework to accept/reject remove attempts.
- * If we return 0, then the detach will proceed.
- */
-int
-com_pcmcia_remove(pc_link, self)
- struct pcmcia_link *pc_link;
- struct device *self;
-{
- struct com_softc *sc = (void *)self;
- struct tty *tp;
- int s;
-
- if (!sc->sc_tty)
- goto ok;
- tp = sc->sc_tty;
-
- /* not in use ? if so, return "OK" */
- if (!ISSET(tp->t_state, TS_ISOPEN) &&
- !ISSET(tp->t_state, TS_WOPEN)) {
- ttyfree(sc->sc_tty);
- sc->sc_tty = NULL;
- ok:
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
- sc->sc_ih = NULL;
- SET(sc->sc_hwflags, COM_HW_ABSENT);
- return 0; /* OK! */
- }
- /*
- * Not easily removed. Put device into a dead state, clean state
- * as best we can. notify all waiters.
- */
- SET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING);
-#ifdef COM_DEBUG
- printf("pending detach flags %x\n", sc->sc_hwflags);
-#endif
-
- s = spltty();
- com_absent_notify(sc);
- splx(s);
-
- return 0;
-}
-
-#if 0
-void
-com_pcmcia_attach(parent, self, aux)
- struct device *parent, *self;
- void *aux;
-{
- struct pcmcia_attach_args *paa = aux;
-
- printf("com_pcmcia_attach %p %p %p\n", parent, self, aux);
- delay(2000000);
- if (!pcmcia_configure(parent, self, paa->paa_link)) {
- struct com_softc *sc = (void *)self;
- sc->sc_hwflags |= COM_HW_ABSENT;
- printf(": not attached\n");
- }
-}
-#endif
-#endif
-
-/*
- * must be called at spltty() or higher.
- */
-void
-com_absent_notify(sc)
- struct com_softc *sc;
-{
- struct tty *tp = sc->sc_tty;
-
- if (tp) {
- CLR(tp->t_state, TS_CARR_ON|TS_BUSY);
- ttyflush(tp, FREAD|FWRITE);
- }
-}
-
-int
-comspeed(speed)
- long speed;
-{
-#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
-
- int x, err;
-
- if (speed == 0)
- return 0;
- if (speed < 0)
- return -1;
- x = divrnd((COM_FREQ / 16), speed);
- if (x <= 0)
- return -1;
- err = divrnd((COM_FREQ / 16) * 1000, speed * x) - 1000;
- if (err < 0)
- err = -err;
- if (err > COM_TOLERANCE)
- return -1;
- return x;
-
-#undef divrnd(n, q)
-}
-
-int
-comprobe1(bc, ioh, iobase)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- int iobase;
-{
- int i, k;
-
- /* force access to id reg */
- bus_io_write_1(bc, ioh, com_lcr, 0);
- bus_io_write_1(bc, ioh, com_iir, 0);
- for (i = 0; i < 32; i++) {
- k = bus_io_read_1(bc, ioh, com_iir);
- if (k & 0x38) {
- bus_io_read_1(bc, ioh, com_data); /* cleanup */
- } else
- break;
- }
- if (i >= 32)
- return 0;
-
- return 1;
-}
-
-#ifdef COM_HAYESP
-int
-comprobeHAYESP(hayespioh, sc)
- bus_io_handle_t hayespioh;
- struct com_softc *sc;
-{
- char val, dips;
- int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
- bus_chipset_tag_t bc = sc->sc_bc;
-
- /*
- * Hayes ESP cards have two iobases. One is for compatibility with
- * 16550 serial chips, and at the same ISA PC base addresses. The
- * other is for ESP-specific enhanced features, and lies at a
- * different addressing range entirely (0x140, 0x180, 0x280, or 0x300).
- */
-
- /* Test for ESP signature */
- if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0)
- return 0;
-
- /*
- * ESP is present at ESP enhanced base address; unknown com port
- */
-
- /* Get the dip-switch configurations */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
- dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1);
-
- /* Determine which com port this ESP card services: bits 0,1 of */
- /* dips is the port # (0-3); combaselist[val] is the com_iobase */
- if (sc->sc_iobase != combaselist[dips & 0x03])
- return 0;
-
- printf(": ESP");
-
- /* Check ESP Self Test bits. */
- /* Check for ESP version 2.0: bits 4,5,6 == 010 */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2);
- if ((val & 0x70) < 0x20) {
- printf("-old (%o)", val & 0x70);
- /* we do not support the necessary features */
- return 0;
- }
-
- /* Check for ability to emulate 16550: bit 8 == 1 */
- if ((dips & 0x80) == 0) {
- printf(" slave");
- /* XXX Does slave really mean no 16550 support?? */
- return 0;
- }
-
- /*
- * If we made it this far, we are a full-featured ESP v2.0 (or
- * better), at the correct com port address.
- */
-
- SET(sc->sc_hwflags, COM_HW_HAYESP);
- printf(", 1024 byte fifo\n");
- return 1;
-}
-#endif
-
-int
-comprobe(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- int iobase, needioh;
- int rv = 1;
-
-#if NACE_ISA || NACE_PCMCIA
-#define IS_ISA(parent) \
- (!strcmp((parent)->dv_cfdata->cf_driver->cd_name, "isa") || \
- !strcmp((parent)->dv_cfdata->cf_driver->cd_name, "pcmcia"))
-#elif NACE_ISA
-#define IS_ISA(parent) \
- !strcmp((parent)->dv_cfdata->cf_driver->cd_name, "isa")
-#endif
-#if NACE_PICA
-#define IS_PICA(parent) \
- !strcmp((parent)->dv_cfdata->cf_driver->cd_name, "pica")
-#endif
- /*
- * XXX should be broken out into functions for isa probe and
- * XXX for commulti probe, with a helper function that contains
- * XXX most of the interesting stuff.
- */
-#if NACE_ISA || NACE_PCMCIA
- if (IS_ISA(parent)) {
- struct isa_attach_args *ia = aux;
-
- bc = ia->ia_bc;
- iobase = ia->ia_iobase;
- needioh = 1;
- } else
-#endif
-#if NACE_PICA
- if(IS_PICA(parent)) {
- struct confargs *ca = aux;
- if(!BUS_MATCHNAME(ca, "com"))
- return(0);
- iobase = (long)BUS_CVTADDR(ca);
- bc = 0;
- needioh = 1;
- } else
-#endif
-#if NACE_COMMULTI
- if (1) {
- struct cfdata *cf = match;
- struct commulti_attach_args *ca = aux;
-
- if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave)
- return (0);
-
- bc = ca->ca_bc;
- iobase = ca->ca_iobase;
- ioh = ca->ca_ioh;
- needioh = 0;
- } else
-#endif
- return(0); /* This cannot happen */
-
- /* if it's in use as console, it's there. */
- if (iobase == comconsaddr && !comconsattached)
- goto out;
-
- if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
- rv = 0;
- goto out;
- }
- rv = comprobe1(bc, ioh, iobase);
- if (needioh)
- bus_io_unmap(bc, ioh, COM_NPORTS);
-
-out:
-#if NACE_ISA || NACE_PCMCIA
- if (rv && IS_ISA(parent)) {
- struct isa_attach_args *ia = aux;
-
- ia->ia_iosize = COM_NPORTS;
- ia->ia_msize = 0;
- }
-#endif
- return (rv);
-}
-
-void
-comattach(parent, self, aux)
- struct device *parent, *self;
- void *aux;
-{
- struct com_softc *sc = (void *)self;
- int iobase, irq;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
-#ifdef COM_HAYESP
- int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
- int *hayespp;
-#endif
-
- /*
- * XXX should be broken out into functions for isa attach and
- * XXX for commulti attach, with a helper function that contains
- * XXX most of the interesting stuff.
- */
- if (ISSET(sc->sc_hwflags, COM_HW_REATTACH)) {
- int s;
- s = spltty();
- com_absent_notify(sc);
- splx(s);
- } else
- sc->sc_hwflags = 0;
- sc->sc_swflags = 0;
-#if NACE_ISA || NACE_PCMCIA
- if (IS_ISA(parent)) {
- struct isa_attach_args *ia = aux;
-
- /*
- * We're living on an isa.
- */
- iobase = ia->ia_iobase;
- bc = ia->ia_bc;
- if (iobase != comconsaddr) {
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh))
- panic("comattach: io mapping failed");
- } else
- ioh = comconsioh;
- irq = ia->ia_irq;
- } else
-#endif
-#if NACE_PICA
- if(IS_PICA(parent)) {
- struct confargs *ca = aux;
- iobase = (long)BUS_CVTADDR(ca);
- bc = 0;
- irq = 0;
- ioh = iobase;
- } else
-#endif
-#if NACE_COMMULTI
- if (1) {
- struct commulti_attach_args *ca = aux;
-
- /*
- * We're living on a commulti.
- */
- iobase = ca->ca_iobase;
- bc = ca->ca_bc;
- ioh = ca->ca_ioh;
- irq = IRQUNK;
-
- if (ca->ca_noien)
- SET(sc->sc_hwflags, COM_HW_NOIEN);
- } else
-#endif
- panic("comattach: impossible");
-
- sc->sc_bc = bc;
- sc->sc_ioh = ioh;
- sc->sc_iobase = iobase;
-
- if (iobase == comconsaddr) {
- comconsattached = 1;
-
- /*
- * Need to reset baud rate, etc. of next print so reset
- * comconsinit. Also make sure console is always "hardwired".
- */
- delay(1000); /* wait for output to finish */
- comconsinit = 0;
- SET(sc->sc_hwflags, COM_HW_CONSOLE);
- SET(sc->sc_swflags, COM_SW_SOFTCAR);
- }
-
-#ifdef COM_HAYESP
- /* Look for a Hayes ESP board. */
- for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
- bus_io_handle_t hayespioh;
-
-#define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */
- if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh))
- continue;
- if (comprobeHAYESP(hayespioh, sc)) {
- sc->sc_hayespbase = *hayespp;
- sc->sc_hayespioh = hayespioh;
- break;
- }
- bus_io_unmap(bc, hayespioh, HAYESP_NPORTS);
- }
- /* No ESP; look for other things. */
- if (*hayespp == 0) {
-#endif
-
- /* look for a NS 16550AF UART with FIFOs */
- bus_io_write_1(bc, ioh, com_fifo,
- FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
- delay(100);
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) ==
- IIR_FIFO_MASK)
- if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) ==
- FIFO_TRIGGER_14) {
- SET(sc->sc_hwflags, COM_HW_FIFO);
- printf(": ns16550a, working fifo\n");
- } else
- printf(": ns16550, broken fifo\n");
- else
- printf(": ns8250 or ns16450, no fifo\n");
- bus_io_write_1(bc, ioh, com_fifo, 0);
-#ifdef COM_HAYESP
- }
-#endif
-
- /* disable interrupts */
- bus_io_write_1(bc, ioh, com_ier, 0);
- bus_io_write_1(bc, ioh, com_mcr, 0);
-
- if (irq != IRQUNK) {
-#if NACE_ISA || NACE_PCMCIA
- if (IS_ISA(parent)) {
- struct isa_attach_args *ia = aux;
-
- sc->sc_ih = isa_intr_establish(ia->ia_ic, irq,
- IST_EDGE, IPL_TTY, comintr, sc,
- sc->sc_dev.dv_xname);
- } else
-#endif
-#if NACE_PICA
- if (IS_PICA(parent)) {
- struct confargs *ca = aux;
- BUS_INTR_ESTABLISH(ca, comintr, (void *)(long)sc);
- } else
-#endif
- panic("comattach: IRQ but can't have one");
- }
-
-#ifdef KGDB
- if (kgdb_dev == makedev(commajor, unit)) {
- if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
- kgdb_dev = -1; /* can't debug over console port */
- else {
- cominit(bc, ioh, kgdb_rate);
- if (kgdb_debug_init) {
- /*
- * Print prefix of device name,
- * let kgdb_connect print the rest.
- */
- printf("%s: ", sc->sc_dev.dv_xname);
- kgdb_connect(1);
- } else
- printf("%s: kgdb enabled\n",
- sc->sc_dev.dv_xname);
- }
- }
-#endif
-
- /* XXX maybe move up some? */
- if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
- printf("%s: console\n", sc->sc_dev.dv_xname);
-}
-
-int
-aceopen(dev, flag, mode, p)
- dev_t dev;
- int flag, mode;
- struct proc *p;
-{
- int unit = DEVUNIT(dev);
- struct com_softc *sc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- struct tty *tp;
- int s;
- int error = 0;
-
- if (unit >= ace_cd.cd_ndevs)
- return ENXIO;
- sc = ace_cd.cd_devs[unit];
- if (!sc || ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING))
- return ENXIO;
-
- s = spltty();
- if (!sc->sc_tty) {
- tp = sc->sc_tty = ttymalloc();
- tty_attach(tp);
- } else
- tp = sc->sc_tty;
- splx(s);
-
- tp->t_oproc = comstart;
- tp->t_param = comparam;
- tp->t_dev = dev;
- if (!ISSET(tp->t_state, TS_ISOPEN)) {
- SET(tp->t_state, TS_WOPEN);
- ttychars(tp);
- tp->t_iflag = TTYDEF_IFLAG;
- tp->t_oflag = TTYDEF_OFLAG;
- if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
- tp->t_cflag = comconscflag;
- else
- tp->t_cflag = TTYDEF_CFLAG;
- if (ISSET(sc->sc_swflags, COM_SW_CLOCAL))
- SET(tp->t_cflag, CLOCAL);
- if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS))
- SET(tp->t_cflag, CRTSCTS);
- if (ISSET(sc->sc_swflags, COM_SW_MDMBUF))
- SET(tp->t_cflag, MDMBUF);
- tp->t_lflag = TTYDEF_LFLAG;
- tp->t_ispeed = tp->t_ospeed = comdefaultrate;
-
- s = spltty();
-
- comparam(tp, &tp->t_termios);
- ttsetwater(tp);
-
- if (comsopen++ == 0)
- timeout(compoll, NULL, 1);
-
- sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0];
- sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER;
- sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
-
- bc = sc->sc_bc;
- ioh = sc->sc_ioh;
-#ifdef COM_HAYESP
- /* Setup the ESP board */
- if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- bus_io_handle_t hayespioh = sc->sc_hayespioh;
-
- bus_io_write_1(bc, ioh, com_fifo,
- FIFO_DMA_MODE|FIFO_ENABLE|
- FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
-
- /* Set 16550 compatibility mode */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
- HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
- HAYESP_MODE_SCALE);
-
- /* Set RTS/CTS flow control */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
-
- /* Set flow control levels */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
- HAYESP_HIBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
- HAYESP_LOBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
- HAYESP_HIBYTE(HAYESP_RXLOWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
- HAYESP_LOBYTE(HAYESP_RXLOWMARK));
- } else
-#endif
- if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
- /* Set the FIFO threshold based on the receive speed. */
- bus_io_write_1(bc, ioh, com_fifo,
- FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
- (tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
- /* flush any pending I/O */
- while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
- (void) bus_io_read_1(bc, ioh, com_data);
- /* you turn me on, baby */
- sc->sc_mcr = MCR_DTR | MCR_RTS;
- if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
- SET(sc->sc_mcr, MCR_IENABLE);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
-
- sc->sc_msr = bus_io_read_1(bc, ioh, com_msr);
- if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) ||
- ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF))
- SET(tp->t_state, TS_CARR_ON);
- else
- CLR(tp->t_state, TS_CARR_ON);
- } else if (ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0)
- return EBUSY;
- else
- s = spltty();
-
- if (DEVCUA(dev)) {
- if (ISSET(tp->t_state, TS_ISOPEN)) {
- /* Ah, but someone already is dialed in... */
- splx(s);
- return EBUSY;
- }
- sc->sc_cua = 1; /* We go into CUA mode */
- }
-
- /* wait for carrier if necessary */
- if (ISSET(flag, O_NONBLOCK)) {
- if (!DEVCUA(dev) && sc->sc_cua) {
- /* Opening TTY non-blocking... but the CUA is busy */
- splx(s);
- return EBUSY;
- }
- } else {
- while (!(DEVCUA(dev) && sc->sc_cua) &&
- !ISSET(tp->t_cflag, CLOCAL) &&
- !ISSET(tp->t_state, TS_CARR_ON)) {
- SET(tp->t_state, TS_WOPEN);
- error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH,
- ttopen, 0);
- if (error) {
- /* XXX should turn off chip if we're the
- only waiter */
- if (DEVCUA(dev))
- sc->sc_cua = 0;
- splx(s);
- return error;
- }
- }
- }
- splx(s);
-
- return (*linesw[tp->t_line].l_open)(dev, tp);
-}
-
-int
-aceclose(dev, flag, mode, p)
- dev_t dev;
- int flag, mode;
- struct proc *p;
-{
- int unit = DEVUNIT(dev);
- struct com_softc *sc = ace_cd.cd_devs[unit];
- struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- int s;
-
- /* XXX This is for cons.c. */
- if (!ISSET(tp->t_state, TS_ISOPEN))
- return 0;
-
- (*linesw[tp->t_line].l_close)(tp, flag);
- s = spltty();
- if (!ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
- /* can't do any of this stuff .... */
- CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
- bus_io_write_1(bc, ioh, com_ier, 0);
- if (ISSET(tp->t_cflag, HUPCL) &&
- !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) {
- /* XXX perhaps only clear DTR */
- bus_io_write_1(bc, ioh, com_mcr, 0);
- }
- }
- CLR(tp->t_state, TS_BUSY | TS_FLUSH);
- if (--comsopen == 0)
- untimeout(compoll, NULL);
- sc->sc_cua = 0;
- splx(s);
- ttyclose(tp);
-#ifdef COM_DEBUG
- /* mark it ready for more use if reattached earlier */
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT_PENDING)) {
- printf("aceclose pending cleared\n");
- }
-#endif
- CLR(sc->sc_hwflags, COM_HW_ABSENT_PENDING);
-
-#ifdef notyet /* XXXX */
- if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
- ttyfree(tp);
- sc->sc_tty = 0;
- }
-#endif
- return 0;
-}
-
-int
-aceread(dev, uio, flag)
- dev_t dev;
- struct uio *uio;
- int flag;
-{
- struct com_softc *sc = ace_cd.cd_devs[DEVUNIT(dev)];
- struct tty *tp = sc->sc_tty;
-
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
- int s = spltty();
- com_absent_notify(sc);
- splx(s);
- return EIO;
- }
-
- return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
-}
-
-int
-acewrite(dev, uio, flag)
- dev_t dev;
- struct uio *uio;
- int flag;
-{
- struct com_softc *sc = ace_cd.cd_devs[DEVUNIT(dev)];
- struct tty *tp = sc->sc_tty;
-
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
- int s = spltty();
- com_absent_notify(sc);
- splx(s);
- return EIO;
- }
-
- return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
-}
-
-struct tty *
-acetty(dev)
- dev_t dev;
-{
- struct com_softc *sc = ace_cd.cd_devs[DEVUNIT(dev)];
- struct tty *tp = sc->sc_tty;
-
- return (tp);
-}
-
-static u_char
-tiocm_xxx2mcr(data)
- int data;
-{
- u_char m = 0;
-
- if (ISSET(data, TIOCM_DTR))
- SET(m, MCR_DTR);
- if (ISSET(data, TIOCM_RTS))
- SET(m, MCR_RTS);
- return m;
-}
-
-int
-aceioctl(dev, cmd, data, flag, p)
- dev_t dev;
- u_long cmd;
- caddr_t data;
- int flag;
- struct proc *p;
-{
- int unit = DEVUNIT(dev);
- struct com_softc *sc = ace_cd.cd_devs[unit];
- struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- int error;
-
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
- int s = spltty();
- com_absent_notify(sc);
- splx(s);
- return EIO;
- }
-
- error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
- if (error >= 0)
- return error;
- error = ttioctl(tp, cmd, data, flag, p);
- if (error >= 0)
- return error;
-
- switch (cmd) {
- case TIOCSBRK:
- SET(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
- break;
- case TIOCCBRK:
- CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
- break;
- case TIOCSDTR:
- SET(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- break;
- case TIOCCDTR:
- CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- break;
- case TIOCMSET:
- CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
- case TIOCMBIS:
- SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- break;
- case TIOCMBIC:
- CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- break;
- case TIOCMGET: {
- u_char m;
- int bits = 0;
-
- m = sc->sc_mcr;
- if (ISSET(m, MCR_DTR))
- SET(bits, TIOCM_DTR);
- if (ISSET(m, MCR_RTS))
- SET(bits, TIOCM_RTS);
- m = sc->sc_msr;
- if (ISSET(m, MSR_DCD))
- SET(bits, TIOCM_CD);
- if (ISSET(m, MSR_CTS))
- SET(bits, TIOCM_CTS);
- if (ISSET(m, MSR_DSR))
- SET(bits, TIOCM_DSR);
- if (ISSET(m, MSR_RI | MSR_TERI))
- SET(bits, TIOCM_RI);
- if (bus_io_read_1(bc, ioh, com_ier))
- SET(bits, TIOCM_LE);
- *(int *)data = bits;
- break;
- }
- case TIOCGFLAGS: {
- int driverbits, userbits = 0;
-
- driverbits = sc->sc_swflags;
- if (ISSET(driverbits, COM_SW_SOFTCAR))
- SET(userbits, TIOCFLAG_SOFTCAR);
- if (ISSET(driverbits, COM_SW_CLOCAL))
- SET(userbits, TIOCFLAG_CLOCAL);
- if (ISSET(driverbits, COM_SW_CRTSCTS))
- SET(userbits, TIOCFLAG_CRTSCTS);
- if (ISSET(driverbits, COM_SW_MDMBUF))
- SET(userbits, TIOCFLAG_MDMBUF);
-
- *(int *)data = userbits;
- break;
- }
- case TIOCSFLAGS: {
- int userbits, driverbits = 0;
-
- error = suser(p->p_ucred, &p->p_acflag);
- if (error != 0)
- return(EPERM);
-
- userbits = *(int *)data;
- if (ISSET(userbits, TIOCFLAG_SOFTCAR) ||
- ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
- SET(driverbits, COM_SW_SOFTCAR);
- if (ISSET(userbits, TIOCFLAG_CLOCAL))
- SET(driverbits, COM_SW_CLOCAL);
- if (ISSET(userbits, TIOCFLAG_CRTSCTS))
- SET(driverbits, COM_SW_CRTSCTS);
- if (ISSET(userbits, TIOCFLAG_MDMBUF))
- SET(driverbits, COM_SW_MDMBUF);
-
- sc->sc_swflags = driverbits;
- break;
- }
- default:
- return ENOTTY;
- }
-
- return 0;
-}
-
-int
-comparam(tp, t)
- struct tty *tp;
- struct termios *t;
-{
- struct com_softc *sc = ace_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- int ospeed = comspeed(t->c_ospeed);
- u_char lcr;
- tcflag_t oldcflag;
- int s;
-
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
- int s = spltty();
- com_absent_notify(sc);
- splx(s);
- return EIO;
- }
-
- /* check requested parameters */
- if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
- return EINVAL;
-
- lcr = ISSET(sc->sc_lcr, LCR_SBREAK);
-
- switch (ISSET(t->c_cflag, CSIZE)) {
- case CS5:
- SET(lcr, LCR_5BITS);
- break;
- case CS6:
- SET(lcr, LCR_6BITS);
- break;
- case CS7:
- SET(lcr, LCR_7BITS);
- break;
- case CS8:
- SET(lcr, LCR_8BITS);
- break;
- }
- if (ISSET(t->c_cflag, PARENB)) {
- SET(lcr, LCR_PENAB);
- if (!ISSET(t->c_cflag, PARODD))
- SET(lcr, LCR_PEVEN);
- }
- if (ISSET(t->c_cflag, CSTOPB))
- SET(lcr, LCR_STOPB);
-
- sc->sc_lcr = lcr;
-
- s = spltty();
-
- if (ospeed == 0) {
- CLR(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- }
-
- /*
- * Set the FIFO threshold based on the receive speed, if we are
- * changing it.
- */
-#if 0 /* XXX CHECK WHY SPEED IS NOT INIT CORRECTLY */
- if (tp->t_ispeed != t->c_ispeed) {
-#else
- if (1) {
-#endif
- if (ospeed != 0) {
- /*
- * Make sure the transmit FIFO is empty before
- * proceeding. If we don't do this, some revisions
- * of the UART will hang. Interestingly enough,
- * even if we do this will the last character is
- * still being pushed out, they don't hang. This
- * seems good enough.
- */
- while (ISSET(tp->t_state, TS_BUSY)) {
- int error;
-
- ++sc->sc_halt;
- error = ttysleep(tp, &tp->t_outq,
- TTOPRI | PCATCH, "comprm", 0);
- --sc->sc_halt;
- if (error) {
- splx(s);
- comstart(tp);
- return (error);
- }
- }
-
- bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB);
- bus_io_write_1(bc, ioh, com_dlbl, ospeed);
- bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8);
- bus_io_write_1(bc, ioh, com_lcr, lcr);
- SET(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- } else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
-
- if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) &&
- ISSET(sc->sc_hwflags, COM_HW_FIFO))
- bus_io_write_1(bc, ioh, com_fifo,
- FIFO_ENABLE |
- (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
- } else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
-
- /* When not using CRTSCTS, RTS follows DTR. */
- if (!ISSET(t->c_cflag, CRTSCTS)) {
- if (ISSET(sc->sc_mcr, MCR_DTR)) {
- if (!ISSET(sc->sc_mcr, MCR_RTS)) {
- SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- }
- } else {
- if (ISSET(sc->sc_mcr, MCR_RTS)) {
- CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- }
- }
- sc->sc_dtr = MCR_DTR | MCR_RTS;
- } else
- sc->sc_dtr = MCR_DTR;
-
- /* and copy to tty */
- tp->t_ispeed = t->c_ispeed;
- tp->t_ospeed = t->c_ospeed;
- oldcflag = tp->t_cflag;
- tp->t_cflag = t->c_cflag;
-
- /*
- * If DCD is off and MDMBUF is changed, ask the tty layer if we should
- * stop the device.
- */
- if (!ISSET(sc->sc_msr, MSR_DCD) &&
- !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) &&
- ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
- (*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
- CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- }
-
- /* Just to be sure... */
- splx(s);
- comstart(tp);
- return 0;
-}
-
-void
-comstart_pending(arg)
- void *arg;
-{
- struct com_softc *sc = arg;
- int s;
-
- s = spltty();
- com_absent_notify(sc);
- splx(s);
-}
-
-void
-comstart(tp)
- struct tty *tp;
-{
- struct com_softc *sc = ace_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- int s;
-
- s = spltty();
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
- /*
- * not quite good enough: if caller is ttywait() it will
- * go to sleep immediately, so hang out a bit and then
- * prod caller again.
- */
- com_absent_notify(sc);
- timeout(comstart_pending, sc, 1);
- goto out;
- }
- if (ISSET(tp->t_state, TS_BUSY))
- goto out;
- if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) ||
- sc->sc_halt > 0)
- goto stopped;
- if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS))
- goto stopped;
- if (tp->t_outq.c_cc <= tp->t_lowat) {
- if (ISSET(tp->t_state, TS_ASLEEP)) {
- CLR(tp->t_state, TS_ASLEEP);
- wakeup(&tp->t_outq);
- }
- if (tp->t_outq.c_cc == 0)
- goto stopped;
- selwakeup(&tp->t_wsel);
- }
- SET(tp->t_state, TS_BUSY);
-
- if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
- SET(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
- }
-#ifdef COM_HAYESP
- if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- u_char buffer[1024], *cp = buffer;
- int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
- do
- bus_io_write_1(bc, ioh, com_data, *cp++);
- while (--n);
- }
- else
-#endif
- if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) {
- u_char buffer[16], *cp = buffer;
- int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
- do {
- bus_io_write_1(bc, ioh, com_data, *cp++);
- } while (--n);
- } else
- bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq));
-out:
- splx(s);
- return;
-stopped:
- if (ISSET(sc->sc_ier, IER_ETXRDY)) {
- CLR(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
- }
- splx(s);
-}
-
-/*
- * Stop output on a line.
- */
-int
-acestop(tp, flag)
- struct tty *tp;
- int flag;
-{
- int s;
-
- s = spltty();
- if (ISSET(tp->t_state, TS_BUSY))
- if (!ISSET(tp->t_state, TS_TTSTOP))
- SET(tp->t_state, TS_FLUSH);
- splx(s);
- return 0;
-}
-
-void
-comdiag(arg)
- void *arg;
-{
- struct com_softc *sc = arg;
- int overflows, floods;
- int s;
-
- s = spltty();
- sc->sc_errors = 0;
- overflows = sc->sc_overflows;
- sc->sc_overflows = 0;
- floods = sc->sc_floods;
- sc->sc_floods = 0;
- splx(s);
-
- log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s\n",
- sc->sc_dev.dv_xname,
- overflows, overflows == 1 ? "" : "s",
- floods, floods == 1 ? "" : "s");
-}
-
-void
-compoll(arg)
- void *arg;
-{
- int unit;
- struct com_softc *sc;
- struct tty *tp;
- register u_char *ibufp;
- u_char *ibufend;
- register int c;
- int s;
- static int lsrmap[8] = {
- 0, TTY_PE,
- TTY_FE, TTY_PE|TTY_FE,
- TTY_FE, TTY_PE|TTY_FE,
- TTY_FE, TTY_PE|TTY_FE
- };
-
- s = spltty();
- if (comevents == 0) {
- splx(s);
- goto out;
- }
- comevents = 0;
- splx(s);
-
- for (unit = 0; unit < ace_cd.cd_ndevs; unit++) {
- sc = ace_cd.cd_devs[unit];
- if (sc == 0 || sc->sc_ibufp == sc->sc_ibuf)
- continue;
-
- tp = sc->sc_tty;
-
- s = spltty();
-
- ibufp = sc->sc_ibuf;
- ibufend = sc->sc_ibufp;
-
- if (ibufp == ibufend) {
- splx(s);
- continue;
- }
-
- sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ?
- sc->sc_ibufs[1] : sc->sc_ibufs[0];
- sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER;
- sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
-
- if (tp == 0 || !ISSET(tp->t_state, TS_ISOPEN)) {
- splx(s);
- continue;
- }
-
- if (ISSET(tp->t_cflag, CRTSCTS) &&
- !ISSET(sc->sc_mcr, MCR_RTS)) {
- /* XXX */
- SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr,
- sc->sc_mcr);
- }
-
- splx(s);
-
- while (ibufp < ibufend) {
- c = *ibufp++;
- if (*ibufp & LSR_OE) {
- sc->sc_overflows++;
- if (sc->sc_errors++ == 0)
- timeout(comdiag, sc, 60 * hz);
- }
- /* This is ugly, but fast. */
- c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2];
- (*linesw[tp->t_line].l_rint)(c, tp);
- }
- }
-
-out:
- timeout(compoll, NULL, 1);
-}
-
-int
-comintr(arg)
- void *arg;
-{
- struct com_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- struct tty *tp;
- u_char lsr, data, msr, delta;
-#ifdef COM_DEBUG
- int n;
- struct {
- u_char iir, lsr, msr;
- } iter[32];
-#endif
-
- if (ISSET(sc->sc_hwflags, COM_HW_ABSENT) || !sc->sc_tty)
- return 0; /* can't do squat. */
-
-#ifdef COM_DEBUG
- n = 0;
- if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
- return (0);
-#else
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
- return (0);
-#endif
-
- tp = sc->sc_tty;
-
- for (;;) {
-#ifdef COM_DEBUG
- iter[n].lsr =
-#endif
- lsr = bus_io_read_1(bc, ioh, com_lsr);
-
- if (ISSET(lsr, LSR_RXRDY)) {
- register u_char *p = sc->sc_ibufp;
-
- comevents = 1;
- do {
- data = bus_io_read_1(bc, ioh, com_data);
- if (ISSET(lsr, LSR_BI)) {
-#ifdef notdef
- printf("break %02x %02x %02x %02x\n",
- sc->sc_msr, sc->sc_mcr, sc->sc_lcr,
- sc->sc_dtr);
-#endif
-#ifdef DDB
- if (ISSET(sc->sc_hwflags,
- COM_HW_CONSOLE)) {
- Debugger();
- goto next;
- }
-#endif
- }
- if (p >= sc->sc_ibufend) {
- sc->sc_floods++;
- if (sc->sc_errors++ == 0)
- timeout(comdiag, sc, 60 * hz);
- } else {
- *p++ = data;
- *p++ = lsr;
- if (p == sc->sc_ibufhigh &&
- ISSET(tp->t_cflag, CRTSCTS)) {
- /* XXX */
- CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr,
- sc->sc_mcr);
- }
- }
- next:
-#ifdef COM_DEBUG
- if (++n >= 32)
- goto ohfudge;
- iter[n].lsr =
-#endif
- lsr = bus_io_read_1(bc, ioh, com_lsr);
- } while (ISSET(lsr, LSR_RXRDY));
-
- sc->sc_ibufp = p;
- }
-#ifdef COM_DEBUG
- else if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE))
- printf("weird lsr %02x\n", lsr);
-#endif
-
-#ifdef COM_DEBUG
- iter[n].msr =
-#endif
- msr = bus_io_read_1(bc, ioh, com_msr);
-
- if (msr != sc->sc_msr) {
- delta = msr ^ sc->sc_msr;
- sc->sc_msr = msr;
- if (ISSET(delta, MSR_DCD) &&
- !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) &&
- (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) {
- CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
- }
- if (ISSET(delta & msr, MSR_CTS) &&
- ISSET(tp->t_cflag, CRTSCTS)) {
- /* the line is up and we want to do rts/cts flow control */
- (*linesw[tp->t_line].l_start)(tp);
- }
- }
-
- if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) {
- CLR(tp->t_state, TS_BUSY | TS_FLUSH);
- if (sc->sc_halt > 0)
- wakeup(&tp->t_outq);
- (*linesw[tp->t_line].l_start)(tp);
- }
-
-#ifdef COM_DEBUG
- if (++n >= 32)
- goto ohfudge;
- if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
- return (1);
-#else
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
- return (1);
-#endif
- }
-#ifdef COM_DEBUG
-ohfudge:
- printf("comintr: too many iterations");
- for (n = 0; n < 32; n++) {
- if ((n % 4) == 0)
- printf("\ncomintr: iter[%02d]", n);
- printf(" %02x %02x %02x", iter[n].iir, iter[n].lsr, iter[n].msr);
- }
- printf("\n");
- printf("comintr: msr %02x mcr %02x lcr %02x ier %02x\n",
- sc->sc_msr, sc->sc_mcr, sc->sc_lcr, sc->sc_ier);
- printf("comintr: state %08x cc %d\n", sc->sc_tty->t_state,
- sc->sc_tty->t_outq.c_cc);
-#endif
-}
-
-/*
- * Following are all routines needed for COM to act as console
- */
-#include <dev/cons.h>
-
-void
-acecnprobe(cp)
- struct consdev *cp;
-{
- /* XXX NEEDS TO BE FIXED XXX */
- extern int cputype;
- bus_chipset_tag_t bc = 0;
- bus_io_handle_t ioh;
- int found;
-
- cp->cn_pri = CN_DEAD;
-
- if(cputype != ACER_PICA_61)
- return;
-
- if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) {
- cp->cn_pri = CN_DEAD;
- return;
- }
- ioh = CONADDR;
- found = comprobe1(bc, ioh, CONADDR);
- if (!found) {
- return;
- }
-
- /* locate the major number */
- for (commajor = 0; commajor < nchrdev; commajor++)
- if (cdevsw[commajor].d_open == aceopen)
- break;
-
- /* initialize required fields */
- cp->cn_dev = makedev(commajor, CONUNIT);
-#ifdef COMCONSOLE
- cp->cn_pri = CN_REMOTE; /* Force a serial port console */
-#else
- cp->cn_pri = CN_NORMAL;
-#endif
-}
-
-void
-acecninit(cp)
- struct consdev *cp;
-{
-
-#if 0
- XXX NEEDS TO BE FIXED XXX
- comconsbc = ???;
-#endif
- if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh))
- panic("acecninit: mapping failed");
-
- cominit(comconsbc, comconsioh, comdefaultrate);
- comconsaddr = CONADDR;
- comconsinit = 0;
-}
-
-void
-cominit(bc, ioh, rate)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- int rate;
-{
- int s = splhigh();
- u_char stat;
-
- bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB);
- rate = comspeed(comdefaultrate);
- bus_io_write_1(bc, ioh, com_dlbl, rate);
- bus_io_write_1(bc, ioh, com_dlbh, rate >> 8);
- bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS);
- bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
- stat = bus_io_read_1(bc, ioh, com_iir);
- splx(s);
-}
-
-int
-acecngetc(dev)
- dev_t dev;
-{
- int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
- u_char stat, c;
-
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
- ;
- c = bus_io_read_1(bc, ioh, com_data);
- stat = bus_io_read_1(bc, ioh, com_iir);
- splx(s);
- return c;
-}
-
-/*
- * Console kernel output character routine.
- */
-void
-acecnputc(dev, c)
- dev_t dev;
- int c;
-{
- int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
- u_char stat;
- register int timo;
-
-#ifdef KGDB
- if (dev != kgdb_dev)
-#endif
- if (comconsinit == 0) {
- cominit(bc, ioh, comdefaultrate);
- comconsinit = 1;
- }
- /* wait for any pending transmission to finish */
- timo = 50000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
- ;
- bus_io_write_1(bc, ioh, com_data, c);
- /* wait for this transmission to complete */
- timo = 1500000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
- ;
- /* clear any interrupts generated by this transmission */
- stat = bus_io_read_1(bc, ioh, com_iir);
- splx(s);
-}
-
-void
-acecnpollc(dev, on)
- dev_t dev;
- int on;
-{
-
-}
+++ /dev/null
-/* $OpenBSD: lpr.c,v 1.3 1996/11/12 20:29:54 niklas Exp $ */
-
-/*
- * Copyright (c) 1993, 1994 Charles Hannum.
- * Copyright (c) 1990 William F. Jolitz, TeleMuse
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This software is a component of "386BSD" developed by
- * William F. Jolitz, TeleMuse.
- * 4. Neither the name of the developer nor the name "386BSD"
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ
- * AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS
- * SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT.
- * THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT
- * NOT MAKE USE OF THIS WORK.
- *
- * FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED
- * BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN
- * REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES
- * (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING
- * JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND
- * LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE
- * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
- * OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992.
- *
- * THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPER BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Device Driver for AT parallel printer port
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/proc.h>
-#include <sys/user.h>
-#include <sys/buf.h>
-#include <sys/kernel.h>
-#include <sys/ioctl.h>
-#include <sys/uio.h>
-#include <sys/device.h>
-#include <sys/conf.h>
-#include <sys/syslog.h>
-
-#include <machine/bus.old.h>
-#include <machine/intr.h>
-
-#include <dev/isa/isavar.h>
-#include <dev/isa/lptreg.h>
-
-#include <lpr.h>
-
-#define TIMEOUT hz*16 /* wait up to 16 seconds for a ready */
-#define STEP hz/4
-
-#define LPTPRI (PZERO+8)
-#define LPT_BSIZE 1024
-
-#if !defined(DEBUG) || !defined(notdef)
-#define LPRINTF(a)
-#else
-#define LPRINTF if (lprdebug) printf a
-int lprdebug = 1;
-#endif
-
-struct lpr_softc {
- struct device sc_dev;
- void *sc_ih;
-
- size_t sc_count;
- struct buf *sc_inbuf;
- u_char *sc_cp;
- int sc_spinmax;
- int sc_iobase;
- bus_chipset_tag_t sc_bc;
- bus_io_handle_t sc_ioh;
- int sc_irq;
- u_char sc_state;
-#define LPT_OPEN 0x01 /* device is open */
-#define LPT_OBUSY 0x02 /* printer is busy doing output */
-#define LPT_INIT 0x04 /* waiting to initialize for open */
- u_char sc_flags;
-#define LPT_AUTOLF 0x20 /* automatic LF on CR */
-#define LPT_NOPRIME 0x40 /* don't prime on open */
-#define LPT_NOINTR 0x80 /* do not use interrupt */
- u_char sc_control;
- u_char sc_laststatus;
-};
-
-/* XXX does not belong here */
-cdev_decl(lpr);
-
-int lprintr __P((void *));
-
-#if NLPR_ISA
-int lpr_isa_probe __P((struct device *, void *, void *));
-void lpr_isa_attach __P((struct device *, struct device *, void *));
-struct cfattach lpr_isa_ca = {
- sizeof(struct lpr_softc), lpr_isa_probe, lpr_isa_attach
-};
-#endif
-
-#if NLPR_PICA
-int lpr_pica_probe __P((struct device *, void *, void *));
-void lpr_pica_attach __P((struct device *, struct device *, void *));
-struct cfattach lpr_pica_ca = {
- sizeof(struct lpr_softc), lpr_pica_probe, lpr_pica_attach
-};
-#endif
-
-struct cfdriver lpr_cd = {
- NULL, "lpr", DV_TTY
-};
-
-#define LPTUNIT(s) (minor(s) & 0x1f)
-#define LPTFLAGS(s) (minor(s) & 0xe0)
-
-#define LPS_INVERT (LPS_SELECT|LPS_NERR|LPS_NBSY|LPS_NACK)
-#define LPS_MASK (LPS_SELECT|LPS_NERR|LPS_NBSY|LPS_NACK|LPS_NOPAPER)
-#define NOT_READY() ((bus_io_read_1(bc, ioh, lpt_status) ^ LPS_INVERT) & LPS_MASK)
-#define NOT_READY_ERR() not_ready(bus_io_read_1(bc, ioh, lpt_status), sc)
-static int not_ready __P((u_char, struct lpr_softc *));
-
-static void lprwakeup __P((void *arg));
-static int pushbytes __P((struct lpr_softc *));
-
-int lpr_port_test __P((bus_chipset_tag_t, bus_io_handle_t, bus_io_addr_t,
- bus_io_size_t, u_char, u_char));
-
-/*
- * Internal routine to lprprobe to do port tests of one byte value.
- */
-int
-lpr_port_test(bc, ioh, base, off, data, mask)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- bus_io_addr_t base;
- bus_io_size_t off;
- u_char data, mask;
-{
- int timeout;
- u_char temp;
-
- data &= mask;
- bus_io_write_1(bc, ioh, off, data);
- timeout = 1000;
- do {
- delay(10);
- temp = bus_io_read_1(bc, ioh, off) & mask;
- } while (temp != data && --timeout);
- LPRINTF(("lpr: port=0x%x out=0x%x in=0x%x timeout=%d\n", base + off,
- data, temp, timeout));
- return (temp == data);
-}
-
-/*
- * Logic:
- * 1) You should be able to write to and read back the same value
- * to the data port. Do an alternating zeros, alternating ones,
- * walking zero, and walking one test to check for stuck bits.
- *
- * 2) You should be able to write to and read back the same value
- * to the control port lower 5 bits, the upper 3 bits are reserved
- * per the IBM PC technical reference manauls and different boards
- * do different things with them. Do an alternating zeros, alternating
- * ones, walking zero, and walking one test to check for stuck bits.
- *
- * Some printers drag the strobe line down when the are powered off
- * so this bit has been masked out of the control port test.
- *
- * XXX Some printers may not like a fast pulse on init or strobe, I
- * don't know at this point, if that becomes a problem these bits
- * should be turned off in the mask byte for the control port test.
- *
- * 3) Set the data and control ports to a value of 0
- */
-#if NLPR_ISA
-int
-lpr_isa_probe(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- u_long base;
- u_char mask, data;
- int i, rv;
-
-#ifdef DEBUG
-#define ABORT do {printf("lprprobe: mask %x data %x failed\n", mask, data); \
- goto out;} while (0)
-#else
-#define ABORT goto out
-#endif
-
- bc = ia->ia_bc;
- base = ia->ia_iobase;
- if (bus_io_map(bc, base, LPT_NPORTS, &ioh))
- return 0;
-
- rv = 0;
- mask = 0xff;
-
- data = 0x55; /* Alternating zeros */
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
-
- data = 0xaa; /* Alternating ones */
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
-
- for (i = 0; i < CHAR_BIT; i++) { /* Walking zero */
- data = ~(1 << i);
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
- }
-
- for (i = 0; i < CHAR_BIT; i++) { /* Walking one */
- data = (1 << i);
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
- }
-
- bus_io_write_1(bc, ioh, lpt_data, 0);
- bus_io_write_1(bc, ioh, lpt_control, 0);
-
- ia->ia_iosize = LPT_NPORTS;
- ia->ia_msize = 0;
-
- rv = 1;
-
-out:
- bus_io_unmap(bc, ioh, LPT_NPORTS);
- return rv;
-}
-#endif
-
-#if NLPR_PICA
-int
-lpr_pica_probe(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- struct confargs *ca = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- u_long base;
- u_char mask, data;
- int i;
-
-#ifdef DEBUG
-#define ABORT do {printf("lprprobe: mask %x data %x failed\n", mask, data); \
- return 0;} while (0)
-#else
-#define ABORT return 0
-#endif
-
- if(!BUS_MATCHNAME(ca, "lpr"))
- return(0);
-
- bc = 0;
- base = (int)BUS_CVTADDR(ca);
- ioh = base;
-
- mask = 0xff;
-
- data = 0x55; /* Alternating zeros */
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
-
- data = 0xaa; /* Alternating ones */
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
-
- for (i = 0; i < CHAR_BIT; i++) { /* Walking zero */
- data = ~(1 << i);
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
- }
-
- for (i = 0; i < CHAR_BIT; i++) { /* Walking one */
- data = (1 << i);
- if (!lpr_port_test(bc, ioh, base, lpt_data, data, mask))
- ABORT;
- }
-
- bus_io_write_1(bc, ioh, lpt_data, 0);
- bus_io_write_1(bc, ioh, lpt_control, 0);
-
- return 1;
-}
-#endif
-
-#if NLPR_ISA
-void
-lpr_isa_attach(parent, self, aux)
- struct device *parent, *self;
- void *aux;
-{
- struct lpr_softc *sc = (void *)self;
- struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
-
- if (ia->ia_irq != IRQUNK)
- printf("\n");
- else
- printf(": polled\n");
-
- sc->sc_iobase = ia->ia_iobase;
- sc->sc_irq = ia->ia_irq;
- sc->sc_state = 0;
-
- bc = sc->sc_bc = ia->ia_bc;
- if (bus_io_map(bc, sc->sc_iobase, LPT_NPORTS, &ioh))
- panic("lprattach: couldn't map I/O ports");
- sc->sc_ioh = ioh;
-
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
-
- if (ia->ia_irq != IRQUNK)
- sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE,
- IPL_TTY, lprintr, sc, sc->sc_dev.dv_xname);
-}
-#endif
-
-#if NLPR_PICA
-void
-lpr_pica_attach(parent, self, aux)
- struct device *parent, *self;
- void *aux;
-{
- struct lpr_softc *sc = (void *)self;
- struct confargs *ca = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
-
- printf("\n");
-
- sc->sc_iobase = (int)BUS_CVTADDR(ca);
- sc->sc_irq = 0;
- sc->sc_state = 0;
-
- bc = sc->sc_bc = 0;
- sc->sc_ioh = sc->sc_iobase;
-
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
-
- BUS_INTR_ESTABLISH(ca, lprintr, sc);
-}
-#endif
-
-/*
- * Reset the printer, then wait until it's selected and not busy.
- */
-int
-lpropen(dev, flag, mode, p)
- dev_t dev;
- int flag;
- int mode;
- struct proc *p;
-{
- int unit = LPTUNIT(dev);
- u_char flags = LPTFLAGS(dev);
- struct lpr_softc *sc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- u_char control;
- int error;
- int spin;
-
- if (unit >= lpr_cd.cd_ndevs)
- return ENXIO;
- sc = lpr_cd.cd_devs[unit];
- if (!sc)
- return ENXIO;
-
- if (sc->sc_irq == IRQUNK && (flags & LPT_NOINTR) == 0)
- return ENXIO;
-
-#ifdef DIAGNOSTIC
- if (sc->sc_state)
- printf("%s: stat=0x%x not zero\n", sc->sc_dev.dv_xname,
- sc->sc_state);
-#endif
-
- if (sc->sc_state)
- return EBUSY;
-
- sc->sc_state = LPT_INIT;
- sc->sc_flags = flags;
- LPRINTF(("%s: open: flags=0x%x\n", sc->sc_dev.dv_xname, flags));
- bc = sc->sc_bc;
- ioh = sc->sc_ioh;
-
- if ((flags & LPT_NOPRIME) == 0) {
- /* assert INIT for 100 usec to start up printer */
- bus_io_write_1(bc, ioh, lpt_control, LPC_SELECT);
- delay(100);
- }
-
- control = LPC_SELECT | LPC_NINIT;
- bus_io_write_1(bc, ioh, lpt_control, control);
-
- /* wait till ready (printer running diagnostics) */
- for (spin = 0; NOT_READY_ERR(); spin += STEP) {
- if (spin >= TIMEOUT) {
- sc->sc_state = 0;
- return EBUSY;
- }
-
- /* wait 1/4 second, give up if we get a signal */
- error = tsleep((caddr_t)sc, LPTPRI | PCATCH, "lpropen", STEP);
- if (error != EWOULDBLOCK) {
- sc->sc_state = 0;
- return error;
- }
- }
-
- if ((flags & LPT_NOINTR) == 0)
- control |= LPC_IENABLE;
- if (flags & LPT_AUTOLF)
- control |= LPC_AUTOLF;
- sc->sc_control = control;
- bus_io_write_1(bc, ioh, lpt_control, control);
-
- sc->sc_inbuf = geteblk(LPT_BSIZE);
- sc->sc_count = 0;
- sc->sc_state = LPT_OPEN;
-
- if ((sc->sc_flags & LPT_NOINTR) == 0)
- lprwakeup(sc);
-
- LPRINTF(("%s: opened\n", sc->sc_dev.dv_xname));
- return 0;
-}
-
-int
-not_ready(status, sc)
- u_char status;
- struct lpr_softc *sc;
-{
- u_char new;
-
- status = (status ^ LPS_INVERT) & LPS_MASK;
- new = status & ~sc->sc_laststatus;
- sc->sc_laststatus = status;
-
- if (new & LPS_SELECT)
- log(LOG_NOTICE, "%s: offline\n", sc->sc_dev.dv_xname);
- else if (new & LPS_NOPAPER)
- log(LOG_NOTICE, "%s: out of paper\n", sc->sc_dev.dv_xname);
- else if (new & LPS_NERR)
- log(LOG_NOTICE, "%s: output error\n", sc->sc_dev.dv_xname);
-
- return status;
-}
-
-void
-lprwakeup(arg)
- void *arg;
-{
- struct lpr_softc *sc = arg;
- int s;
-
- s = spltty();
- lprintr(sc);
- splx(s);
-
- timeout(lprwakeup, sc, STEP);
-}
-
-/*
- * Close the device, and free the local line buffer.
- */
-int
-lprclose(dev, flag, mode, p)
- dev_t dev;
- int flag;
- int mode;
- struct proc *p;
-{
- int unit = LPTUNIT(dev);
- struct lpr_softc *sc = lpr_cd.cd_devs[unit];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
-
- if (sc->sc_count)
- (void) pushbytes(sc);
-
- if ((sc->sc_flags & LPT_NOINTR) == 0)
- untimeout(lprwakeup, sc);
-
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
- sc->sc_state = 0;
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
- brelse(sc->sc_inbuf);
-
- LPRINTF(("%s: closed\n", sc->sc_dev.dv_xname));
- return 0;
-}
-
-int
-pushbytes(sc)
- struct lpr_softc *sc;
-{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- int error;
-
- if (sc->sc_flags & LPT_NOINTR) {
- int spin, tic;
- u_char control = sc->sc_control;
-
- while (sc->sc_count > 0) {
- spin = 0;
- while (NOT_READY()) {
- if (++spin < sc->sc_spinmax)
- continue;
- tic = 0;
- /* adapt busy-wait algorithm */
- sc->sc_spinmax++;
- while (NOT_READY_ERR()) {
- /* exponential backoff */
- tic = tic + tic + 1;
- if (tic > TIMEOUT)
- tic = TIMEOUT;
- error = tsleep((caddr_t)sc,
- LPTPRI | PCATCH, "lprpsh", tic);
- if (error != EWOULDBLOCK)
- return error;
- }
- break;
- }
-
- bus_io_write_1(bc, ioh, lpt_data, *sc->sc_cp++);
- bus_io_write_1(bc, ioh, lpt_control, control | LPC_STROBE);
- sc->sc_count--;
- bus_io_write_1(bc, ioh, lpt_control, control);
-
- /* adapt busy-wait algorithm */
- if (spin*2 + 16 < sc->sc_spinmax)
- sc->sc_spinmax--;
- }
- } else {
- int s;
-
- while (sc->sc_count > 0) {
- /* if the printer is ready for a char, give it one */
- if ((sc->sc_state & LPT_OBUSY) == 0) {
- LPRINTF(("%s: write %d\n", sc->sc_dev.dv_xname,
- sc->sc_count));
- s = spltty();
- (void) lprintr(sc);
- splx(s);
- }
- error = tsleep((caddr_t)sc, LPTPRI | PCATCH,
- "lprwrite2", 0);
- if (error)
- return error;
- }
- }
- return 0;
-}
-
-/*
- * Copy a line from user space to a local buffer, then call putc to get the
- * chars moved to the output queue.
- */
-int
-lprwrite(dev, uio, flags)
- dev_t dev;
- struct uio *uio;
- int flags;
-{
- struct lpr_softc *sc = lpr_cd.cd_devs[LPTUNIT(dev)];
- size_t n;
- int error = 0;
-
- while ((n = min(LPT_BSIZE, uio->uio_resid)) != 0) {
- uiomove(sc->sc_cp = sc->sc_inbuf->b_data, n, uio);
- sc->sc_count = n;
- error = pushbytes(sc);
- if (error) {
- /*
- * Return accurate residual if interrupted or timed
- * out.
- */
- uio->uio_resid += sc->sc_count;
- sc->sc_count = 0;
- return error;
- }
- }
- return 0;
-}
-
-/*
- * Handle printer interrupts which occur when the printer is ready to accept
- * another char.
- */
-int
-lprintr(arg)
- void *arg;
-{
- struct lpr_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
-
- if (((sc->sc_state & LPT_OPEN) == 0 && sc->sc_count == 0) || (sc->sc_flags & LPT_NOINTR))
- return 0;
-
- /* is printer online and ready for output */
- if (NOT_READY() && NOT_READY_ERR())
- return -1;
-
- if (sc->sc_count) {
- u_char control = sc->sc_control;
- /* send char */
- bus_io_write_1(bc, ioh, lpt_data, *sc->sc_cp++);
- bus_io_write_1(bc, ioh, lpt_control, control | LPC_STROBE);
- sc->sc_count--;
- bus_io_write_1(bc, ioh, lpt_control, control);
- sc->sc_state |= LPT_OBUSY;
- } else
- sc->sc_state &= ~LPT_OBUSY;
-
- if (sc->sc_count == 0) {
- /* none, wake up the top half to get more */
- wakeup((caddr_t)sc);
- }
-
- return 1;
-}
-
-int
-lprioctl(dev, cmd, data, flag, p)
- dev_t dev;
- u_long cmd;
- caddr_t data;
- int flag;
- struct proc *p;
-{
- int error = 0;
-
- switch (cmd) {
- default:
- error = ENODEV;
- }
-
- return error;
-}
-/* $OpenBSD: bus.h,v 1.7 1996/10/17 18:58:58 niklas Exp $ */
+/* $OpenBSD: bus.h,v 1.8 1996/11/28 23:35:42 niklas Exp $ */
/*
- * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ * Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#ifndef _ARC_BUS_H_
#define _ARC_BUS_H_
-#include <machine/autoconf.h>
-#include <machine/pio.h>
-
-/*
- * I/O addresses (in bus space)
- */
-typedef u_long bus_io_addr_t;
-typedef u_long bus_io_size_t;
-typedef u_long bus_io_handle_t;
+#ifdef __STDC__
+#define CAT(a,b) a##b
+#define CAT3(a,b,c) a##b##c
+#else
+#define CAT(a,b) a/**/b
+#define CAT3(a,b,c) a/**/b/**/c
+#endif
/*
- * Memory addresses (in bus space)
+ * Bus access types.
*/
-typedef u_long bus_mem_addr_t;
-typedef u_long bus_mem_size_t;
-typedef caddr_t bus_mem_handle_t;
+typedef u_int32_t bus_addr_t;
+typedef u_int32_t bus_size_t;
+typedef u_int32_t bus_space_handle_t;
+typedef u_int32_t bus_space_tag_t;
/*
- * Access methods for bus resources, I/O space, and memory space.
+ * Access methods for bus resources
*/
-typedef
-struct arc_isa_busmap {
- void *isa_io_base;
- void *isa_mem_base;
-} *bus_chipset_tag_t;
-
-
-#define bus_io_map(t, port, size, iohp) \
- (*iohp = (t == NULL ? port : port + (ulong)(t->isa_io_base)), 0)
-#define bus_io_unmap(t, ioh, size)
-
-#define bus_io_read_1(t, h, o) inb((h) + (o))
-#define bus_io_read_2(t, h, o) inw((h) + (o))
-#define bus_io_read_4(t, h, o) inl((h) + (o))
-#if 0 /* Cause a link error for bus_io_read_8 */
-#define bus_io_read_8(t, h, o) !!! bus_io_read_8 unimplemented !!!
-#endif
-
-#define bus_io_read_multi_1(t, h, o, a, c) \
- insb((h) + (o), (a), (c))
-#define bus_io_read_multi_2(t, h, o, a, c) \
- insw((h) + (o), (a), (c))
-#define bus_io_read_multi_4(t, h, o, a, c) \
- insl((h) + (o), (a), (c))
-#if 0 /* Cause a link error for bus_io_read_multi_8 */
-#define bus_io_read_multi_8(t, h, o, a, c) \
- !!! bus_io_read_multi_8 unimplemented !!!
-#endif
-
-#define bus_io_write_1(t, h, o, v) outb((h) + (o), (v))
-#define bus_io_write_2(t, h, o, v) outw((h) + (o), (v))
-#define bus_io_write_4(t, h, o, v) outl((h) + (o), (v))
-#if 0 /* Cause a link error for bus_io_write_8 */
-#define bus_io_write_8(t, h, o, v) !!! bus_io_write_8 unimplemented !!!
-#endif
-
-#define bus_io_write_multi_1(t, h, o, a, c) \
- outsb((h) + (o), (a), (c))
-#define bus_io_write_multi_2(t, h, o, a, c) \
- outsw((h) + (o), (a), (c))
-#define bus_io_write_multi_4(t, h, o, a, c) \
- outsl((h) + (o), (a), (c))
-#if 0 /* Cause a link error for bus_io_write_multi_8 */
-#define bus_io_write_multi_8(t, h, o, a, c) \
- !!! bus_io_write_multi_8 unimplimented !!!
-#endif
-
-#define bus_mem_map(t, addr, size, cacheable, mhp) \
- (*mhp = (bus_mem_handle_t)(t == NULL ? addr : addr + (ulong)(t->isa_mem_base)), 0)
-#define bus_mem_unmap(t, ioh, size)
-
-#define bus_mem_read_1(t, h, o) (*(volatile u_int8_t *)((h) + (o)))
-#define bus_mem_read_2(t, h, o) (*(volatile u_int16_t *)((h) + (o)))
-#define bus_mem_read_4(t, h, o) (*(volatile u_int32_t *)((h) + (o)))
-#define bus_mem_read_8(t, h, o) (*(volatile u_int64_t *)((h) + (o)))
-
-#define bus_mem_write_1(t, h, o, v) \
- ((void)(*(volatile u_int8_t *)((h) + (o)) = (v)))
-#define bus_mem_write_2(t, h, o, v) \
- ((void)(*(volatile u_int16_t *)((h) + (o)) = (v)))
-#define bus_mem_write_4(t, h, o, v) \
- ((void)(*(volatile u_int32_t *)((h) + (o)) = (v)))
-#define bus_mem_write_8(t, h, o, v) \
- ((void)(*(volatile u_int64_t *)((h) + (o)) = (v)))
-
-/* These are extensions to the general NetBSD bus interface. */
-#define bus_io_read_raw_multi_2(t, h, o, a, c) \
- insw((h) + (o), (a), ((c) >> 1))
-#define bus_io_read_raw_multi_4(t, h, o, a, c) \
- insl((h) + (o), (a), ((c) >> 2))
-#if 0 /* Cause a link error for bus_io_read_raw_multi_8 */
-#define bus_io_read_raw_multi_8(t, h, o, a, c) \
- !!! bus_io_read_raw_multi_8 unimplemented !!!
-#endif
-
-#define bus_io_write_raw_multi_2(t, h, o, a, c) \
- outsw((h) + (o), (a), ((c) >> 1))
-#define bus_io_write_raw_multi_4(t, h, o, a, c) \
- outsl((h) + (o), (a), ((c) >> 2))
-#if 0 /* Cause a link error for bus_io_write_raw_multi_8 */
-#define bus_io_write_raw_multi_8(t, h, o, a, c) \
- !!! bus_io_write_raw_multi_8 unimplimented !!!
-#endif
+#define bus_space_map(t, addr, size, cacheable, bshp) \
+ ((*(bshp) = (t) + (addr)), 0)
+#define bus_space_unmap(t, bsh, size)
+
+#define bus_space_read(n,m) \
+static __inline CAT3(u_int,m,_t) \
+CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba) \
+{ \
+ return *(volatile CAT3(u_int,m,_t) *)(bsh + ba); \
+}
+
+bus_space_read(1,8)
+bus_space_read(2,16)
+bus_space_read(4,32)
+
+#define bus_space_read_8 !!! bus_space_read_8 unimplemented !!!
+
+#define bus_space_read_multi(n, m) \
+static __inline void \
+CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
+{ \
+ while (cnt--) \
+ *buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
+}
+
+bus_space_read_multi(1,8)
+bus_space_read_multi(2,16)
+bus_space_read_multi(4,32)
+
+#define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
+
+#define bus_space_write(n,m) \
+static __inline void \
+CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba, CAT3(u_int,m,_t) x) \
+{ \
+ *(volatile CAT3(u_int,m,_t) *)(bsh + ba) = x; \
+}
+
+bus_space_write(1,8)
+bus_space_write(2,16)
+bus_space_write(4,32)
+
+#define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
+
+#define bus_space_write_multi(n, m) \
+static __inline void \
+CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
+{ \
+ while (cnt--) \
+ CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \
+}
+
+bus_space_write_multi(1,8)
+bus_space_write_multi(2,16)
+bus_space_write_multi(4,32)
+
+#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
+
+/* These are OpenBSD extensions to the general NetBSD bus interface. */
+#define bus_space_read_raw_multi(n,m,l) \
+static __inline void \
+CAT(bus_space_read_raw_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
+ bus_addr_t ba, u_int8_t *buf, bus_size_t cnt) \
+{ \
+ CAT(bus_space_read_multi_,n)(bst, bsh, ba, (CAT3(u_int,m,_t) *)buf, \
+ cnt >> l); \
+}
+
+bus_space_read_raw_multi(2,16,1)
+bus_space_read_raw_multi(4,32,2)
+
+#define bus_space_read_raw_multi_8 \
+ !!! bus_space_read_raw_multi_8 not implemented !!!
+
+#define bus_space_write_raw_multi(n,m,l) \
+static __inline void \
+CAT(bus_space_write_raw_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh,\
+ bus_addr_t ba, const u_int8_t *buf, bus_size_t cnt) \
+{ \
+ CAT(bus_space_write_multi_,n)(bst, bsh, ba, \
+ (const CAT3(u_int,m,_t) *)buf, cnt >> l); \
+}
+
+bus_space_write_raw_multi(2,16,1)
+bus_space_write_raw_multi(4,32,2)
+
+#define bus_space_write_raw_multi_8 \
+ !!! bus_space_write_raw_multi_8 not implemented !!!
#endif /* _ARC_BUS_H_ */
+++ /dev/null
-/* $OpenBSD: bus.old.h,v 1.1 1996/11/12 20:29:56 niklas Exp $ */
-
-/*
- * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Christopher G. Demetriou
- * for the NetBSD Project.
- * 4. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ARC_BUS_H_
-#define _ARC_BUS_H_
-
-#include <machine/autoconf.h>
-#include <machine/pio.h>
-
-/*
- * I/O addresses (in bus space)
- */
-typedef u_long bus_io_addr_t;
-typedef u_long bus_io_size_t;
-typedef u_long bus_io_handle_t;
-
-/*
- * Memory addresses (in bus space)
- */
-typedef u_long bus_mem_addr_t;
-typedef u_long bus_mem_size_t;
-typedef caddr_t bus_mem_handle_t;
-
-/*
- * Access methods for bus resources, I/O space, and memory space.
- */
-typedef
-struct arc_isa_busmap {
- void *isa_io_base;
- void *isa_mem_base;
-} *bus_chipset_tag_t;
-
-
-#define bus_io_map(t, port, size, iohp) \
- (*iohp = (t == NULL ? port : port + (ulong)(t->isa_io_base)), 0)
-#define bus_io_unmap(t, ioh, size)
-
-#define bus_io_read_1(t, h, o) inb((h) + (o))
-#define bus_io_read_2(t, h, o) inw((h) + (o))
-#define bus_io_read_4(t, h, o) inl((h) + (o))
-#if 0 /* Cause a link error for bus_io_read_8 */
-#define bus_io_read_8(t, h, o) !!! bus_io_read_8 unimplemented !!!
-#endif
-
-#define bus_io_read_multi_1(t, h, o, a, c) \
- insb((h) + (o), (a), (c))
-#define bus_io_read_multi_2(t, h, o, a, c) \
- insw((h) + (o), (a), (c))
-#define bus_io_read_multi_4(t, h, o, a, c) \
- insl((h) + (o), (a), (c))
-#if 0 /* Cause a link error for bus_io_read_multi_8 */
-#define bus_io_read_multi_8(t, h, o, a, c) \
- !!! bus_io_read_multi_8 unimplemented !!!
-#endif
-
-#define bus_io_write_1(t, h, o, v) outb((h) + (o), (v))
-#define bus_io_write_2(t, h, o, v) outw((h) + (o), (v))
-#define bus_io_write_4(t, h, o, v) outl((h) + (o), (v))
-#if 0 /* Cause a link error for bus_io_write_8 */
-#define bus_io_write_8(t, h, o, v) !!! bus_io_write_8 unimplemented !!!
-#endif
-
-#define bus_io_write_multi_1(t, h, o, a, c) \
- outsb((h) + (o), (a), (c))
-#define bus_io_write_multi_2(t, h, o, a, c) \
- outsw((h) + (o), (a), (c))
-#define bus_io_write_multi_4(t, h, o, a, c) \
- outsl((h) + (o), (a), (c))
-#if 0 /* Cause a link error for bus_io_write_multi_8 */
-#define bus_io_write_multi_8(t, h, o, a, c) \
- !!! bus_io_write_multi_8 unimplimented !!!
-#endif
-
-#define bus_mem_map(t, addr, size, cacheable, mhp) \
- (*mhp = (bus_mem_handle_t)(t == NULL ? addr : addr + (ulong)(t->isa_mem_base)), 0)
-#define bus_mem_unmap(t, ioh, size)
-
-#define bus_mem_read_1(t, h, o) (*(volatile u_int8_t *)((h) + (o)))
-#define bus_mem_read_2(t, h, o) (*(volatile u_int16_t *)((h) + (o)))
-#define bus_mem_read_4(t, h, o) (*(volatile u_int32_t *)((h) + (o)))
-#define bus_mem_read_8(t, h, o) (*(volatile u_int64_t *)((h) + (o)))
-
-#define bus_mem_write_1(t, h, o, v) \
- ((void)(*(volatile u_int8_t *)((h) + (o)) = (v)))
-#define bus_mem_write_2(t, h, o, v) \
- ((void)(*(volatile u_int16_t *)((h) + (o)) = (v)))
-#define bus_mem_write_4(t, h, o, v) \
- ((void)(*(volatile u_int32_t *)((h) + (o)) = (v)))
-#define bus_mem_write_8(t, h, o, v) \
- ((void)(*(volatile u_int64_t *)((h) + (o)) = (v)))
-
-/* These are extensions to the general NetBSD bus interface. */
-#define bus_io_read_raw_multi_2(t, h, o, a, c) \
- insw((h) + (o), (a), ((c) >> 1))
-#define bus_io_read_raw_multi_4(t, h, o, a, c) \
- insl((h) + (o), (a), ((c) >> 2))
-#if 0 /* Cause a link error for bus_io_read_raw_multi_8 */
-#define bus_io_read_raw_multi_8(t, h, o, a, c) \
- !!! bus_io_read_raw_multi_8 unimplemented !!!
-#endif
-
-#define bus_io_write_raw_multi_2(t, h, o, a, c) \
- outsw((h) + (o), (a), ((c) >> 1))
-#define bus_io_write_raw_multi_4(t, h, o, a, c) \
- outsl((h) + (o), (a), ((c) >> 2))
-#if 0 /* Cause a link error for bus_io_write_raw_multi_8 */
-#define bus_io_write_raw_multi_8(t, h, o, a, c) \
- !!! bus_io_write_raw_multi_8 unimplimented !!!
-#endif
-
-#endif /* _ARC_BUS_H_ */
-/* $OpenBSD: isabus.c,v 1.6 1996/11/23 21:45:33 kstailey Exp $ */
+/* $OpenBSD: isabus.c,v 1.7 1996/11/28 23:35:44 niklas Exp $ */
/* $NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp $ */
/*-
struct isabr_softc {
struct device sc_dv;
struct arc_isa_bus arc_isa_cs;
- struct arc_isa_busmap arc_isa_map;
struct abus sc_bus;
};
sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish;
sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish;
- sc->arc_isa_map.isa_io_base = (void *)isa_io_base;
- sc->arc_isa_map.isa_mem_base = (void *)isa_mem_base;
iba.iba_busname = "isa";
- iba.iba_bc = &sc->arc_isa_map;
+ iba.iba_iot = (bus_space_tag_t)isa_io_base;
+ iba.iba_memt = (bus_space_tag_t)isa_mem_base;
iba.iba_ic = &sc->arc_isa_cs;
config_found(self, &iba, isabrprint);
}
if (pnp)
printf("%s at %s", ca->ca_name, pnp);
- printf(" isa_io_base 0x%lx isa_mem_base 0x%lx", isa_io_base, isa_mem_base);
+ printf(" isa_io_base 0x%lx isa_mem_base 0x%lx", isa_io_base,
+ isa_mem_base);
return (UNCONF);
}
--- /dev/null
+/* $OpenBSD: lpt_pica.c,v 1.1 1996/11/28 23:35:44 niklas Exp $ */
+
+/*
+ * Copyright (c) 1993, 1994 Charles Hannum.
+ * Copyright (c) 1990 William F. Jolitz, TeleMuse
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This software is a component of "386BSD" developed by
+ * William F. Jolitz, TeleMuse.
+ * 4. Neither the name of the developer nor the name "386BSD"
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ
+ * AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS
+ * SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT.
+ * THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT
+ * NOT MAKE USE OF THIS WORK.
+ *
+ * FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED
+ * BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN
+ * REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES
+ * (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING
+ * JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND
+ * LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE
+ * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
+ * OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPER BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Device Driver for AT parallel printer port
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/autoconf.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/isa/lptreg.h>
+
+/* XXX create ic/lptvar.h with this structure and prototypes in it. */
+struct lpt_softc {
+ struct device sc_dev;
+ void *sc_ih;
+
+ size_t sc_count;
+ struct buf *sc_inbuf;
+ u_char *sc_cp;
+ int sc_spinmax;
+ int sc_iobase;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+ int sc_irq;
+ u_char sc_state;
+#define LPT_OPEN 0x01 /* device is open */
+#define LPT_OBUSY 0x02 /* printer is busy doing output */
+#define LPT_INIT 0x04 /* waiting to initialize for open */
+ u_char sc_flags;
+#define LPT_AUTOLF 0x20 /* automatic LF on CR */
+#define LPT_NOPRIME 0x40 /* don't prime on open */
+#define LPT_NOINTR 0x80 /* do not use interrupt */
+ u_char sc_control;
+ u_char sc_laststatus;
+};
+
+int lptintr __P((void *));
+
+int lpt_pica_probe __P((struct device *, void *, void *));
+void lpt_pica_attach __P((struct device *, struct device *, void *));
+
+struct cfattach lpt_pica_ca = {
+ sizeof(struct lpt_softc), lpt_pica_probe, lpt_pica_attach
+};
+
+int
+lpt_pica_probe(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct confargs *ca = aux;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+ u_long base;
+ u_char mask, data;
+ int i;
+
+#ifdef DEBUG
+#define ABORT \
+ do { \
+ printf("lpt_pica_probe: mask %x data %x failed\n", mask, \
+ data); \
+ return 0; \
+ } while (0)
+#else
+#define ABORT return 0
+#endif
+
+ if(!BUS_MATCHNAME(ca, "lpt"))
+ return(0);
+
+ iot = 0;
+ base = (int)BUS_CVTADDR(ca);
+ ioh = base;
+
+ mask = 0xff;
+
+ data = 0x55; /* Alternating zeros */
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
+ ABORT;
+
+ data = 0xaa; /* Alternating ones */
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
+ ABORT;
+
+ for (i = 0; i < CHAR_BIT; i++) { /* Walking zero */
+ data = ~(1 << i);
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
+ ABORT;
+ }
+
+ for (i = 0; i < CHAR_BIT; i++) { /* Walking one */
+ data = (1 << i);
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
+ ABORT;
+ }
+
+ bus_space_write_1(iot, ioh, lpt_data, 0);
+ bus_space_write_1(iot, ioh, lpt_control, 0);
+
+ return 1;
+}
+
+void
+lpt_pica_attach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct lpt_softc *sc = (void *)self;
+ struct confargs *ca = aux;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+
+ printf("\n");
+
+ sc->sc_iobase = (int)BUS_CVTADDR(ca);
+ sc->sc_irq = 0;
+ sc->sc_state = 0;
+
+ iot = sc->sc_iot = 0;
+ sc->sc_ioh = sc->sc_iobase;
+
+ bus_space_write_1(iot, ioh, lpt_control, LPC_NINIT);
+
+ BUS_INTR_ESTABLISH(ca, lptintr, sc);
+}
-# $OpenBSD: OPRAH,v 1.12 1996/11/25 23:09:04 niklas Exp $
+# $OpenBSD: OPRAH,v 1.13 1996/11/28 23:37:35 niklas Exp $
#
# OPRAH -- Niklas Hallqvist's test machine
#
#mms1 at isa? port 0x238 irq 5
#pms0 at isa? port 0x60 irq 12 # PS/2 auxiliary port mouse
-#aha0 at isa? port 0x330 irq ? drq ? # Adaptec 154[02] SCSI controllers
-#aha1 at isa? port 0x334 irq ? drq ? # Adaptec 154[02] SCSI controllers
-#scsibus* at aha?
+aha0 at isa? port 0x230 irq ? drq ? # Adaptec 154[02] SCSI controllers
+aha1 at isa? port 0x234 irq ? drq ? # Adaptec 154[02] SCSI controllers
+scsibus* at aha?
wds0 at isa? port 0x350 irq 15 drq 6 # WD7000 and TMC-7000 controllers
wds1 at isa? port 0x358 irq 11 drq 5
scsibus* at wds?
-/* $OpenBSD: machdep.c,v 1.27 1996/10/25 11:14:12 deraadt Exp $ */
+/* $OpenBSD: machdep.c,v 1.28 1996/11/28 23:37:36 niklas Exp $ */
/* $NetBSD: machdep.c,v 1.202 1996/05/18 15:54:59 christos Exp $ */
/*-
#include <sys/mount.h>
#include <sys/vnode.h>
#include <sys/device.h>
+#include <sys/extent.h>
#include <sys/sysctl.h>
#include <sys/syscallargs.h>
#ifdef SYSVMSG
#include <machine/cpufunc.h>
#include <machine/gdt.h>
#include <machine/pio.h>
+#include <machine/bus.h>
#include <machine/psl.h>
#include <machine/reg.h>
#include <machine/specialreg.h>
static int exec_nomid __P((struct proc *, struct exec_package *));
#endif
+int bus_mem_add_mapping __P((bus_addr_t, bus_size_t,
+ int, bus_space_handle_t *));
+
extern long cnvmem; /* BIOS's conventional memory size */
extern long extmem; /* BIOS's extended memory size */
}
int
-bus_mem_map(t, bpa, size, cacheable, mhp)
- bus_chipset_tag_t t;
- bus_mem_addr_t bpa;
- bus_mem_size_t size;
+bus_space_map(t, bpa, size, cacheable, bshp)
+ bus_space_tag_t t;
+ bus_addr_t bpa;
+ bus_size_t size;
+ int cacheable;
+ bus_space_handle_t *bshp;
+{
+ int error;
+
+ /*
+ * For I/O space, that's all she wrote.
+ */
+ if (t == I386_BUS_SPACE_IO) {
+ *bshp = bpa;
+ return (0);
+ }
+
+ /*
+ * For memory space, map the bus physical address to
+ * a kernel virtual address.
+ */
+ error = bus_mem_add_mapping(bpa, size, cacheable, bshp);
+ return (error);
+}
+
+int
+bus_space_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
+ bpap, bshp)
+ bus_space_tag_t t;
+ bus_addr_t rstart, rend;
+ bus_size_t size, alignment;
+ bus_addr_t boundary;
int cacheable;
- bus_mem_handle_t *mhp;
+ bus_addr_t *bpap;
+ bus_space_handle_t *bshp;
+{
+ u_long bpa;
+ int error;
+
+ /*
+ * For I/O space, that's all she wrote.
+ */
+ if (t == I386_BUS_SPACE_IO) {
+ *bshp = *bpap = bpa;
+ return (0);
+ }
+
+ /*
+ * For memory space, map the bus physical address to
+ * a kernel virtual address.
+ */
+ error = bus_mem_add_mapping(bpa, size, cacheable, bshp);
+
+ *bpap = bpa;
+
+ return (error);
+}
+
+int
+bus_mem_add_mapping(bpa, size, cacheable, bshp)
+ bus_addr_t bpa;
+ bus_size_t size;
+ int cacheable;
+ bus_space_handle_t *bshp;
{
u_long pa, endpa;
vm_offset_t va;
#ifdef DIAGNOSTIC
if (endpa <= pa)
- panic("bus_mem_map: overflow");
+ panic("bus_mem_add_mapping: overflow");
#endif
va = kmem_alloc_pageable(kernel_map, endpa - pa);
if (va == 0)
- return (1);
- *mhp = (caddr_t)(va + (bpa & PGOFSET));
+ return (ENOMEM);
+
+ *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
for (; pa < endpa; pa += NBPG, va += NBPG) {
- pmap_enter(pmap_kernel(), va, pa, VM_PROT_READ | VM_PROT_WRITE,
- TRUE);
- if (!cacheable)
- pmap_changebit(pa, PG_N, ~0);
- else
- pmap_changebit(pa, 0, ~PG_N);
- }
+ pmap_enter(pmap_kernel(), va, pa,
+ VM_PROT_READ | VM_PROT_WRITE, TRUE);
+ if (!cacheable)
+ pmap_changebit(pa, PG_N, ~0);
+ else
+ pmap_changebit(pa, 0, ~PG_N);
+ }
- return 0;
+ return 0;
}
void
-bus_mem_unmap(t, memh, size)
- bus_chipset_tag_t t;
- bus_mem_handle_t memh;
- bus_mem_size_t size;
+bus_space_unmap(t, bsh, size)
+ bus_space_tag_t t;
+ bus_space_handle_t bsh;
+ bus_size_t size;
{
- vm_offset_t va, endva;
+ u_long va, endva;
+ bus_addr_t bpa;
- va = i386_trunc_page(memh);
- endva = i386_round_page((memh + size) - 1);
+ /*
+ * Find the correct bus physical address.
+ */
+ switch (t) {
+ case I386_BUS_SPACE_IO:
+ bpa = bsh;
+ break;
+
+ case I386_BUS_SPACE_MEM:
+ va = i386_trunc_page(bsh);
+ endva = i386_round_page((bsh + size) - 1);
#ifdef DIAGNOSTIC
- if (endva <= va)
- panic("bus_mem_unmap: overflow");
+ if (endva <= va)
+ panic("bus_space_unmap: overflow");
#endif
- kmem_free(kernel_map, va, endva - va);
+ bpa = pmap_extract(pmap_kernel(), va) + (bsh & PGOFSET);
+
+ /*
+ * Free the kernel virtual mapping.
+ */
+ kmem_free(kernel_map, va, endva - va);
+ break;
+
+ default:
+ panic("bus_space_unmap: bad bus space tag");
+ }
+}
+
+void
+bus_space_free(t, bsh, size)
+ bus_space_tag_t t;
+ bus_space_handle_t bsh;
+ bus_size_t size;
+{
+
+ /* bus_space_unmap() does all that we need to do. */
+ bus_space_unmap(t, bsh, size);
+}
+
+int
+bus_space_subregion(t, bsh, offset, size, nbshp)
+ bus_space_tag_t t;
+ bus_space_handle_t bsh;
+ bus_size_t offset, size;
+ bus_space_handle_t *nbshp;
+{
+ *nbshp = bsh + offset;
+ return (0);
}
-/* $OpenBSD: mainbus.c,v 1.7 1996/11/23 21:45:49 kstailey Exp $ */
+/* $OpenBSD: mainbus.c,v 1.8 1996/11/28 23:37:37 niklas Exp $ */
/* $NetBSD: mainbus.c,v 1.8 1996/04/11 22:13:37 cgd Exp $ */
/*
#include <sys/systm.h>
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/eisa/eisavar.h>
if (1 /* XXX ISA NOT YET SEEN */) {
mba.mba_iba.iba_busname = "isa";
- mba.mba_iba.iba_bc = NULL;
- mba.mba_iba.iba_ic = NULL;
+ mba.mba_iba.iba_iot = I386_BUS_SPACE_IO;
+ mba.mba_iba.iba_memt = I386_BUS_SPACE_MEM;
config_found(self, &mba.mba_iba, mainbus_print);
}
if (!bcmp(ISA_HOLE_VADDR(EISA_ID_PADDR), EISA_ID, EISA_ID_LEN)) {
mba.mba_eba.eba_busname = "eisa";
- mba.mba_eba.eba_bc = NULL;
- mba.mba_eba.eba_ec = NULL;
+ mba.mba_eba.eba_iot = I386_BUS_SPACE_IO;
+ mba.mba_eba.eba_memt = I386_BUS_SPACE_MEM;
config_found(self, &mba.mba_eba, mainbus_print);
}
#if NPCI > 0
if (pci_mode_detect() != 0) {
mba.mba_pba.pba_busname = "pci";
- mba.mba_pba.pba_bc = NULL;
+ mba.mba_pba.pba_iot = I386_BUS_SPACE_IO;
+ mba.mba_pba.pba_memt = I386_BUS_SPACE_MEM;
mba.mba_pba.pba_bus = 0;
config_found(self, &mba.mba_pba, mainbus_print);
}
-/* $OpenBSD: bus.h,v 1.6 1996/11/12 22:46:27 niklas Exp $ */
+/* $OpenBSD: bus.h,v 1.7 1996/11/28 23:37:38 niklas Exp $ */
/* $NetBSD: bus.h,v 1.5 1996/10/21 22:26:19 thorpej Exp $ */
/*
#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!!
#endif
+/*
+ * void bus_space_read_raw_multi_N __P((bus_space_tag_t tag,
+ * bus_space_handle_t bsh, bus_size_t offset,
+ * u_int8_t *addr, size_t count));
+ *
+ * Read `count' bytes in 2, 4 or 8 byte wide quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided. The buffer
+ * must have proper alignment for the N byte wide entities. Furthermore
+ * possible byte-swapping should be done by these functions.
+ */
+
+#define bus_space_read_raw_multi_2(t, h, o, a, c) \
+ bus_space_read_multi_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
+#define bus_space_read_raw_multi_4(t, h, o, a, c) \
+ bus_space_read_multi_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
+
+#if 0 /* Cause a link error for bus_space_read_raw_multi_8 */
+#define bus_space_read_raw_multi_8 \
+ !!! bus_space_read_raw_multi_8 unimplemented !!!
+#endif
+
/*
* void bus_space_read_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
!!! bus_space_write_multi_8 unimplimented !!!
#endif
+/*
+ * void bus_space_write_raw_multi_N __P((bus_space_tag_t tag,
+ * bus_space_handle_t bsh, bus_size_t offset,
+ * u_int8_t *addr, size_t count));
+ *
+ * Write `count' bytes in 2, 4 or 8 byte wide quantities from the buffer
+ * provided to bus space described by tag/handle/offset. The buffer
+ * must have proper alignment for the N byte wide entities. Furthermore
+ * possible byte-swapping should be done by these functions.
+ */
+
+#define bus_space_write_raw_multi_2(t, h, o, a, c) \
+ bus_space_write_multi_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
+#define bus_space_write_raw_multi_4(t, h, o, a, c) \
+ bus_space_write_multi_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
+
+#if 0 /* Cause a link error for bus_space_write_raw_multi_8 */
+#define bus_space_write_raw_multi_8 \
+ !!! bus_space_write_raw_multi_8 unimplemented !!!
+#endif
+
/*
* void bus_space_write_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
+++ /dev/null
-/* $OpenBSD: bus.old.h,v 1.1 1996/11/12 20:29:58 niklas Exp $ */
-/* $NetBSD: bus.h,v 1.3 1996/05/03 19:22:18 christos Exp $ */
-
-/*
- * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Christopher G. Demetriou
- * for the NetBSD Project.
- * 4. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _I386_BUS_H_
-#define _I386_BUS_H_
-
-#include <machine/pio.h>
-
-/*
- * I/O addresses (in bus space)
- */
-typedef u_long bus_io_addr_t;
-typedef u_long bus_io_size_t;
-
-/*
- * Memory addresses (in bus space)
- */
-typedef u_long bus_mem_addr_t;
-typedef u_long bus_mem_size_t;
-
-/*
- * Access methods for bus resources, I/O space, and memory space.
- */
-typedef void *bus_chipset_tag_t;
-typedef u_long bus_io_handle_t;
-typedef caddr_t bus_mem_handle_t;
-
-#define bus_io_map(t, port, size, iohp) \
- ((void) t, *iohp = port, 0)
-#define bus_io_unmap(t, ioh, size)
-
-#define bus_io_read_1(t, h, o) ((void) t, inb((h) + (o)))
-#define bus_io_read_2(t, h, o) ((void) t, inw((h) + (o)))
-#define bus_io_read_4(t, h, o) ((void) t, inl((h) + (o)))
-#if 0 /* Cause a link error for bus_io_read_8 */
-#define bus_io_read_8(t, h, o) !!! bus_io_read_8 unimplemented !!!
-#endif
-
-#define bus_io_read_multi_1(t, h, o, a, c) \
- ((void) t, insb((h) + (o), (a), (c)))
-#define bus_io_read_multi_2(t, h, o, a, c) \
- ((void) t, insw((h) + (o), (a), (c)))
-#define bus_io_read_multi_4(t, h, o, a, c) \
- ((void) t, insl((h) + (o), (a), (c)))
-#if 0 /* Cause a link error for bus_io_read_multi_8 */
-#define bus_io_read_multi_8(t, h, o, a, c) \
- !!! bus_io_read_multi_8 unimplemented !!!
-#endif
-
-#define bus_io_write_1(t, h, o, v) ((void) t, outb((h) + (o), (v)))
-#define bus_io_write_2(t, h, o, v) ((void) t, outw((h) + (o), (v)))
-#define bus_io_write_4(t, h, o, v) ((void) t, outl((h) + (o), (v)))
-#if 0 /* Cause a link error for bus_io_write_8 */
-#define bus_io_write_8(t, h, o, v) !!! bus_io_write_8 unimplemented !!!
-#endif
-
-#define bus_io_write_multi_1(t, h, o, a, c) \
- ((void) t, outsb((h) + (o), (a), (c)))
-#define bus_io_write_multi_2(t, h, o, a, c) \
- ((void) t, outsw((h) + (o), (a), (c)))
-#define bus_io_write_multi_4(t, h, o, a, c) \
- ((void) t, outsl((h) + (o), (a), (c)))
-#if 0 /* Cause a link error for bus_io_write_multi_8 */
-#define bus_io_write_multi_8(t, h, o, a, c) \
- !!! bus_io_write_multi_8 unimplimented !!!
-#endif
-
-int bus_mem_map __P((bus_chipset_tag_t t, bus_mem_addr_t bpa,
- bus_mem_size_t size, int cacheable, bus_mem_handle_t *mhp));
-void bus_mem_unmap __P((bus_chipset_tag_t t, bus_mem_handle_t memh,
- bus_mem_size_t size));
-
-#define bus_mem_read_1(t, h, o) ((void) t, (*(volatile u_int8_t *)((h) + (o))))
-#define bus_mem_read_2(t, h, o) ((void) t, (*(volatile u_int16_t *)((h) + (o))))
-#define bus_mem_read_4(t, h, o) ((void) t, (*(volatile u_int32_t *)((h) + (o))))
-#define bus_mem_read_8(t, h, o) ((void) t, (*(volatile u_int64_t *)((h) + (o))))
-
-#define bus_mem_write_1(t, h, o, v) \
- ((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))))
-#define bus_mem_write_2(t, h, o, v) \
- ((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))))
-#define bus_mem_write_4(t, h, o, v) \
- ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
-#define bus_mem_write_8(t, h, o, v) \
- ((void) t, ((void)(*(volatile u_int64_t *)((h) + (o)) = (v))))
-
-#define bus_io_read_raw_multi_2(t, h, o, a, c) \
- ((void) t, insw((h) + (o), (a), (c) >> 1))
-#define bus_io_read_raw_multi_4(t, h, o, a, c) \
- ((void) t, insl((h) + (o), (a), (c) >> 2))
-#if 0 /* Cause a link error for bus_io_read_raw_multi_8 */
-#define bus_io_read_raw_multi_8(t, h, o, a, c) \
- !!! bus_io_read_multi_8 unimplemented !!!
-#endif
-
-#define bus_io_write_raw_multi_2(t, h, o, a, c) \
- ((void) t, outsw((h) + (o), (a), (c) >> 1))
-#define bus_io_write_raw_multi_4(t, h, o, a, c) \
- ((void) t, outsl((h) + (o), (a), (c) >> 2))
-#if 0 /* Cause a link error for bus_io_write_raw_multi_8 */
-#define bus_io_write_raw_multi_8(t, h, o, a, c) \
- !!! bus_io_write_multi_8 unimplimented !!!
-#endif
-
-#endif /* _I386_BUS_H_ */
-/* $OpenBSD: ahc_isa.c,v 1.2 1996/11/12 20:30:00 niklas Exp $ */
-/* $NetBSD: ahc_isa.c,v 1.1 1996/08/05 21:14:29 soda Exp $ */
+/* $OpenBSD: ahc_isa.c,v 1.3 1996/11/28 23:37:39 niklas Exp $ */
+/* $NetBSD: ahc_isa.c,v 1.5 1996/10/21 22:27:39 thorpej Exp $ */
/*
* Product specific probe and attach routines for:
#include <sys/queue.h>
#include <sys/malloc.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <scsi/scsi_all.h>
#define AHC_ISA_PRIMING_VID(index) (AHC_ISA_VID + (index))
#define AHC_ISA_PRIMING_PID(index) (AHC_ISA_PID + (index))
-int ahc_isa_irq __P((bus_chipset_tag_t, bus_io_handle_t));
-int ahc_isa_idstring __P((bus_chipset_tag_t, bus_io_handle_t, char *));
-int ahc_isa_match __P((struct isa_attach_args *, bus_io_addr_t));
+int ahc_isa_irq __P((bus_space_tag_t, bus_space_handle_t));
+int ahc_isa_idstring __P((bus_space_tag_t, bus_space_handle_t, char *));
+int ahc_isa_match __P((struct isa_attach_args *, bus_addr_t));
int ahc_isa_probe __P((struct device *, void *, void *));
void ahc_isa_attach __P((struct device *, struct device *, void *));
* Return irq setting of the board, otherwise -1.
*/
int
-ahc_isa_irq(bc, ioh)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ahc_isa_irq(iot, ioh)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
{
int irq;
u_char intdef;
- ahc_reset("ahc_isa", bc, ioh);
- intdef = bus_io_read_1(bc, ioh, INTDEF);
+ ahc_reset("ahc_isa", iot, ioh);
+ intdef = bus_space_read_1(iot, ioh, INTDEF);
switch (irq = (intdef & 0xf)) {
case 9:
case 10:
}
int
-ahc_isa_idstring(bc, ioh, idstring)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ahc_isa_idstring(iot, ioh, idstring)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
char *idstring;
{
u_int8_t vid[EISA_NVIDREGS], pid[EISA_NPIDREGS];
/* Get the vendor ID bytes */
for (i = 0; i < EISA_NVIDREGS; i++) {
- bus_io_write_1(bc, ioh, AHC_ISA_PRIMING,
+ bus_space_write_1(iot, ioh, AHC_ISA_PRIMING,
AHC_ISA_PRIMING_VID(i));
- vid[i] = bus_io_read_1(bc, ioh, AHC_ISA_VID + i);
+ vid[i] = bus_space_read_1(iot, ioh, AHC_ISA_VID + i);
}
/* Check for device existence */
/* Get the product ID bytes */
for (i = 0; i < EISA_NPIDREGS; i++) {
- bus_io_write_1(bc, ioh, AHC_ISA_PRIMING,
+ bus_space_write_1(iot, ioh, AHC_ISA_PRIMING,
AHC_ISA_PRIMING_PID(i));
- pid[i] = bus_io_read_1(bc, ioh, AHC_ISA_PID + i);
+ pid[i] = bus_space_read_1(iot, ioh, AHC_ISA_PID + i);
}
/* Create the ID string from the vendor and product IDs */
int
ahc_isa_match(ia, iobase)
struct isa_attach_args *ia;
- bus_io_addr_t iobase;
+ bus_addr_t iobase;
{
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int irq;
char idstring[EISA_IDSTRINGLEN];
* space. If we can't, assume nothing's there, but
* warn about it.
*/
- if (bus_io_map(bc, iobase, AHC_ISA_IOSIZE, &ioh)) {
+ if (bus_space_map(iot, iobase, AHC_ISA_IOSIZE, 0, &ioh)) {
#if 0
/*
* Don't print anything out here, since this could
return (0);
}
- if (!ahc_isa_idstring(bc, ioh, idstring))
+ if (!ahc_isa_idstring(iot, ioh, idstring))
irq = -1; /* cannot get the ID string */
else if (strcmp(idstring, "ADP7756") &&
strcmp(idstring, "ADP7757"))
irq = -1; /* unknown ID strings */
else
- irq = ahc_isa_irq(bc, ioh);
+ irq = ahc_isa_irq(iot, ioh);
- bus_io_unmap(bc, ioh, AHC_ISA_IOSIZE);
+ bus_space_unmap(iot, ioh, AHC_ISA_IOSIZE);
if (irq < 0)
return (0);
ahc_type type;
struct ahc_data *ahc = (void *)self;
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int irq;
char idstring[EISA_IDSTRINGLEN];
const char *model;
- if (bus_io_map(bc, ia->ia_iobase, ia->ia_iosize, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ia->ia_iosize, 0, &ioh))
panic("ahc_isa_attach: could not map slot I/O addresses");
- if (!ahc_isa_idstring(bc, ioh, idstring))
+ if (!ahc_isa_idstring(iot, ioh, idstring))
panic("ahc_isa_attach: could not read ID string");
- if ((irq = ahc_isa_irq(bc, ioh)) < 0)
+ if ((irq = ahc_isa_irq(iot, ioh)) < 0)
panic("ahc_isa_attach: ahc_isa_irq failed!");
if (strcmp(idstring, "ADP7756") == 0) {
}
printf(": %s\n", model);
- ahc_construct(ahc, bc, ioh, type, AHC_FNONE);
+ ahc_construct(ahc, iot, ioh, type, AHC_FNONE);
+#ifdef DEBUG
/*
* Tell the user what type of interrupts we're using.
* usefull for debugging irq problems
*/
printf( "%s: Using %s Interrupts\n", ahc_name(ahc),
ahc->pause & IRQMS ? "Level Sensitive" : "Edge Triggered");
+#endif
/*
* Now that we know we own the resources we need, do the
-/* $NetBSD: lms.c,v 1.26 1996/05/12 23:12:11 mycroft Exp $ */
+/* $NetBSD: lms.c,v 1.30 1996/10/21 22:27:41 thorpej Exp $ */
/*-
* Copyright (c) 1993, 1994 Charles Hannum.
#include <sys/device.h>
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <machine/mouse.h>
#include <machine/conf.h>
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc; /* bus chipset identifier */
- bus_io_handle_t sc_ioh; /* bus i/o handle */
+ bus_space_tag_t sc_iot; /* bus i/o space identifier */
+ bus_space_handle_t sc_ioh; /* bus i/o handle */
struct clist sc_q;
struct selinfo sc_rsel;
void *match, *aux;
{
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int rv;
/* Map the i/o space. */
- if (bus_io_map(bc, ia->ia_iobase, LMS_NPORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, LMS_NPORTS, 0, &ioh))
return 0;
rv = 0;
/* Configure and check for port present. */
- bus_io_write_1(bc, ioh, LMS_CONFIG, 0x91);
+ bus_space_write_1(iot, ioh, LMS_CONFIG, 0x91);
delay(10);
- bus_io_write_1(bc, ioh, LMS_SIGN, 0x0c);
+ bus_space_write_1(iot, ioh, LMS_SIGN, 0x0c);
delay(10);
- if (bus_io_read_1(bc, ioh, LMS_SIGN) != 0x0c)
+ if (bus_space_read_1(iot, ioh, LMS_SIGN) != 0x0c)
goto out;
- bus_io_write_1(bc, ioh, LMS_SIGN, 0x50);
+ bus_space_write_1(iot, ioh, LMS_SIGN, 0x50);
delay(10);
- if (bus_io_read_1(bc, ioh, LMS_SIGN) != 0x50)
+ if (bus_space_read_1(iot, ioh, LMS_SIGN) != 0x50)
goto out;
/* Disable interrupts. */
- bus_io_write_1(bc, ioh, LMS_CNTRL, 0x10);
+ bus_space_write_1(iot, ioh, LMS_CNTRL, 0x10);
rv = 1;
ia->ia_iosize = LMS_NPORTS;
ia->ia_msize = 0;
out:
- bus_io_unmap(bc, ioh, LMS_NPORTS);
+ bus_space_unmap(iot, ioh, LMS_NPORTS);
return rv;
}
printf("\n");
/* Other initialization was done by lmsprobe. */
- sc->sc_bc = ia->ia_bc;
- if (bus_io_map(sc->sc_bc, ia->ia_iobase, LMS_NPORTS, &sc->sc_ioh))
+ sc->sc_iot = ia->ia_iot;
+ if (bus_space_map(sc->sc_iot, ia->ia_iobase, LMS_NPORTS, 0,
+ &sc->sc_ioh))
panic("lmsattach: couldn't map I/O ports");
sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_PULSE,
sc->sc_x = sc->sc_y = 0;
/* Enable interrupts. */
- bus_io_write_1(sc->sc_bc, sc->sc_ioh, LMS_CNTRL, 0);
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMS_CNTRL, 0);
return 0;
}
struct lms_softc *sc = lms_cd.cd_devs[LMSUNIT(dev)];
/* Disable interrupts. */
- bus_io_write_1(sc->sc_bc, sc->sc_ioh, LMS_CNTRL, 0x10);
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMS_CNTRL, 0x10);
sc->sc_state &= ~LMS_OPEN;
void *arg;
{
struct lms_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
u_char hi, lo, buttons, changed;
char dx, dy;
u_char buffer[5];
/* Interrupts are not expected. */
return 0;
- bus_io_write_1(bc, ioh, LMS_CNTRL, 0xab);
- hi = bus_io_read_1(bc, ioh, LMS_DATA);
- bus_io_write_1(bc, ioh, LMS_CNTRL, 0x90);
- lo = bus_io_read_1(bc, ioh, LMS_DATA);
+ bus_space_write_1(iot, ioh, LMS_CNTRL, 0xab);
+ hi = bus_space_read_1(iot, ioh, LMS_DATA);
+ bus_space_write_1(iot, ioh, LMS_CNTRL, 0x90);
+ lo = bus_space_read_1(iot, ioh, LMS_DATA);
dx = ((hi & 0x0f) << 4) | (lo & 0x0f);
/* Bounding at -127 avoids a bug in XFree86. */
dx = (dx == -128) ? -127 : dx;
- bus_io_write_1(bc, ioh, LMS_CNTRL, 0xf0);
- hi = bus_io_read_1(bc, ioh, LMS_DATA);
- bus_io_write_1(bc, ioh, LMS_CNTRL, 0xd0);
- lo = bus_io_read_1(bc, ioh, LMS_DATA);
+ bus_space_write_1(iot, ioh, LMS_CNTRL, 0xf0);
+ hi = bus_space_read_1(iot, ioh, LMS_DATA);
+ bus_space_write_1(iot, ioh, LMS_CNTRL, 0xd0);
+ lo = bus_space_read_1(iot, ioh, LMS_DATA);
dy = ((hi & 0x0f) << 4) | (lo & 0x0f);
dy = (dy == -128) ? 127 : -dy;
- bus_io_write_1(bc, ioh, LMS_CNTRL, 0);
+ bus_space_write_1(iot, ioh, LMS_CNTRL, 0);
buttons = (~hi >> 5) & 0x07;
changed = ((buttons ^ sc->sc_status) & 0x07) << 3;
-/* $OpenBSD: pccom.c,v 1.6 1996/11/12 20:30:05 niklas Exp $ */
+/* $OpenBSD: pccom.c,v 1.7 1996/11/28 23:37:41 niklas Exp $ */
/* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */
/*-
#include <sys/device.h>
#include <machine/intr.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/isa/comreg.h>
struct com_softc {
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
+ isa_chipset_tag_t sc_ic;
struct tty *sc_tty;
int sc_overflows;
int sc_hayespbase;
#endif
- bus_io_handle_t sc_ioh;
- bus_io_handle_t sc_hayespioh;
+ bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_hayespioh;
u_char sc_hwflags;
#define COM_HW_NOIEN 0x01
};
#ifdef COM_HAYESP
-int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc));
+int comprobeHAYESP __P((bus_space_handle_t hayespioh, struct com_softc *sc));
#endif
-void comdiag __P((void *));
+void comdiag __P((void *));
int comspeed __P((long));
int comparam __P((struct tty *, struct termios *));
void comstart __P((struct tty *));
NULL, "pccom", DV_TTY
};
-void cominit __P((bus_chipset_tag_t, bus_io_handle_t, int));
+void cominit __P((bus_space_tag_t, bus_space_handle_t, int));
#ifndef CONSPEED
#define CONSPEED B9600
int comconsaddr;
int comconsinit;
int comconsattached;
-bus_chipset_tag_t comconsbc;
-bus_io_handle_t comconsioh;
+bus_space_tag_t comconsiot;
+bus_space_handle_t comconsioh;
tcflag_t comconscflag = TTYDEF_CFLAG;
int commajor;
(sc->sc_hwflags & (COM_HW_ABSENT_PENDING|COM_HW_CONSOLE));
} else
sc->sc_hwflags = 0;
+ sc->sc_ic = ia->ia_ic;
}
return rval;
}
ttyfree(sc->sc_tty);
sc->sc_tty = NULL;
ok:
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
+ isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
sc->sc_ih = NULL;
SET(sc->sc_hwflags, COM_HW_ABSENT);
return 0; /* OK! */
}
int
-comprobe1(bc, ioh, iobase)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+comprobe1(iot, ioh, iobase)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int iobase;
{
int i, k;
/* force access to id reg */
- bus_io_write_1(bc, ioh, com_lcr, 0);
- bus_io_write_1(bc, ioh, com_iir, 0);
+ bus_space_write_1(iot, ioh, com_lcr, 0);
+ bus_space_write_1(iot, ioh, com_iir, 0);
for (i = 0; i < 32; i++) {
- k = bus_io_read_1(bc, ioh, com_iir);
+ k = bus_space_read_1(iot, ioh, com_iir);
if (k & 0x38) {
- bus_io_read_1(bc, ioh, com_data); /* cleanup */
+ bus_space_read_1(iot, ioh, com_data); /* cleanup */
} else
break;
}
#ifdef COM_HAYESP
int
comprobeHAYESP(hayespioh, sc)
- bus_io_handle_t hayespioh;
+ bus_space_handle_t hayespioh;
struct com_softc *sc;
{
char val, dips;
int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
- bus_chipset_tag_t bc = sc->sc_bc;
+ bus_space_tag_t iot = sc->sc_iot;
/*
* Hayes ESP cards have two iobases. One is for compatibility with
*/
/* Test for ESP signature */
- if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0)
+ if ((bus_space_read_1(iot, hayespioh, 0) & 0xf3) == 0)
return 0;
/*
*/
/* Get the dip-switch configurations */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
- dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
+ dips = bus_space_read_1(iot, hayespioh, HAYESP_STATUS1);
/* Determine which com port this ESP card services: bits 0,1 of */
/* dips is the port # (0-3); combaselist[val] is the com_iobase */
/* Check ESP Self Test bits. */
/* Check for ESP version 2.0: bits 4,5,6 == 010 */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
+ val = bus_space_read_1(iot, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
+ val = bus_space_read_1(iot, hayespioh, HAYESP_STATUS2);
if ((val & 0x70) < 0x20) {
printf("-old (%o)", val & 0x70);
/* we do not support the necessary features */
struct device *parent;
void *match, *aux;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int iobase, needioh;
int rv = 1;
if (IS_ISA(parent)) {
struct isa_attach_args *ia = aux;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
iobase = ia->ia_iobase;
needioh = 1;
} else
if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave)
return (0);
- bc = ca->ca_bc;
+ iot = ca->ca_iot;
iobase = ca->ca_iobase;
ioh = ca->ca_ioh;
needioh = 0;
if (iobase == comconsaddr && !comconsattached)
goto out;
- if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (needioh && bus_space_map(iot, iobase, COM_NPORTS, &ioh)) {
rv = 0;
goto out;
}
- rv = comprobe1(bc, ioh, iobase);
+ rv = comprobe1(iot, ioh, iobase);
if (needioh)
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
out:
#if NPCCOM_ISA || NPCCOM_PCMCIA
{
struct com_softc *sc = (void *)self;
int iobase, irq;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
#ifdef COM_HAYESP
int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
int *hayespp;
* We're living on an isa.
*/
iobase = ia->ia_iobase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
if (iobase != comconsaddr) {
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh))
+ if (bus_space_map(iot, iobase, COM_NPORTS, &ioh))
panic("comattach: io mapping failed");
} else
ioh = comconsioh;
* We're living on a commulti.
*/
iobase = ca->ca_iobase;
- bc = ca->ca_bc;
+ iot = ca->ca_iot;
ioh = ca->ca_ioh;
irq = IRQUNK;
#endif
panic("comattach: impossible");
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->sc_iobase = iobase;
#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
- bus_io_handle_t hayespioh;
+ bus_space_handle_t hayespioh;
#define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */
- if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh))
+ if (bus_space_map(iot, *hayespp, HAYESP_NPORTS, &hayespioh))
continue;
if (comprobeHAYESP(hayespioh, sc)) {
sc->sc_hayespbase = *hayespp;
sc->sc_fifolen = 1024;
break;
}
- bus_io_unmap(bc, hayespioh, HAYESP_NPORTS);
+ bus_space_unmap(iot, hayespioh, HAYESP_NPORTS);
}
/* No ESP; look for other things. */
if (*hayespp == 0) {
sc->sc_fifolen = 1;
/* look for a NS 16550AF UART with FIFOs */
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
delay(100);
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) ==
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_FIFO_MASK) ==
IIR_FIFO_MASK)
- if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) ==
+ if (ISSET(bus_space_read_1(iot, ioh, com_fifo), FIFO_TRIGGER_14) ==
FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
printf(": ns16550a, working fifo\n");
printf(": ns16550, broken fifo\n");
else
printf(": ns8250 or ns16450, no fifo\n");
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
#ifdef COM_HAYESP
}
#endif
/* disable interrupts */
- bus_io_write_1(bc, ioh, com_ier, 0);
- bus_io_write_1(bc, ioh, com_mcr, 0);
+ bus_space_write_1(iot, ioh, com_ier, 0);
+ bus_space_write_1(iot, ioh, com_mcr, 0);
if (irq != IRQUNK) {
#if NPCCOM_ISA || NPCCOM_PCMCIA
if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
kgdb_dev = -1; /* can't debug over console port */
else {
- cominit(bc, ioh, kgdb_rate);
+ cominit(iot, ioh, kgdb_rate);
if (kgdb_debug_init) {
/*
* Print prefix of device name,
{
int unit = DEVUNIT(dev);
struct com_softc *sc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct tty *tp;
int s;
int error = 0;
sc->sc_rxput = sc->sc_rxget = sc->sc_tbc = 0;
- bc = sc->sc_bc;
+ iot = sc->sc_iot;
ioh = sc->sc_ioh;
#ifdef COM_HAYESP
/* Setup the ESP board */
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- bus_io_handle_t hayespioh = sc->sc_hayespioh;
+ bus_space_handle_t hayespioh = sc->sc_hayespioh;
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_DMA_MODE|FIFO_ENABLE|
FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
/* Set 16550 compatibility mode */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
HAYESP_MODE_SCALE);
/* Set RTS/CTS flow control */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
/* Set flow control levels */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXLOWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
} else
#endif
* Set the FIFO threshold based on the receive speed.
*/
for (;;) {
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
delay(100);
- (void) bus_io_read_1(bc, ioh, com_data);
- bus_io_write_1(bc, ioh, com_fifo,
+ (void) bus_space_read_1(iot, ioh, com_data);
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
(tp->t_ispeed <= 1200 ?
FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
delay(100);
- if(!ISSET(bus_io_read_1(bc, ioh,
+ if(!ISSET(bus_space_read_1(iot, ioh,
com_lsr), LSR_RXRDY))
break;
}
}
/* flush any pending I/O */
- while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
- (void) bus_io_read_1(bc, ioh, com_data);
+ while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY))
+ (void) bus_space_read_1(iot, ioh, com_data);
/* you turn me on, baby */
sc->sc_mcr = MCR_DTR | MCR_RTS;
if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
SET(sc->sc_mcr, MCR_IENABLE);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
- sc->sc_msr = bus_io_read_1(bc, ioh, com_msr);
+ sc->sc_msr = bus_space_read_1(iot, ioh, com_msr);
if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) ||
ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF))
SET(tp->t_state, TS_CARR_ON);
int unit = DEVUNIT(dev);
struct com_softc *sc = pccom_cd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s;
/* XXX This is for cons.c. */
if (!ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
/* can't do any of this stuff .... */
CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
- bus_io_write_1(bc, ioh, com_ier, 0);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_ier, 0);
if (ISSET(tp->t_cflag, HUPCL) &&
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) {
/* XXX perhaps only clear DTR */
- bus_io_write_1(bc, ioh, com_mcr, 0);
+ bus_space_write_1(iot, ioh, com_mcr, 0);
}
}
CLR(tp->t_state, TS_BUSY | TS_FLUSH);
/*
* FIFO off
*/
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
sc->sc_cua = 0;
splx(s);
ttyclose(tp);
int unit = DEVUNIT(dev);
struct com_softc *sc = pccom_cd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int error;
if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
switch (cmd) {
case TIOCSBRK:
SET(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCCBRK:
CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCSDTR:
SET(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCCDTR:
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMSET:
CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
case TIOCMBIS:
SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMBIC:
CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMGET: {
u_char m;
SET(bits, TIOCM_DSR);
if (ISSET(m, MSR_RI | MSR_TERI))
SET(bits, TIOCM_RI);
- if (bus_io_read_1(bc, ioh, com_ier))
+ if (bus_space_read_1(iot, ioh, com_ier))
SET(bits, TIOCM_LE);
*(int *)data = bits;
break;
struct termios *t;
{
struct com_softc *sc = pccom_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int ospeed = comspeed(t->c_ospeed);
u_char lcr;
tcflag_t oldcflag;
if (ospeed == 0) {
CLR(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
/*
}
}
- bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB);
- bus_io_write_1(bc, ioh, com_dlbl, ospeed);
- bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8);
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB);
+ bus_space_write_1(iot, ioh, com_dlbl, ospeed);
+ bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
SET(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
} else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) &&
ISSET(sc->sc_hwflags, COM_HW_FIFO))
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE |
(t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
} else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
/* When not using CRTSCTS, RTS follows DTR. */
if (!ISSET(t->c_cflag, CRTSCTS)) {
if (ISSET(sc->sc_mcr, MCR_DTR)) {
if (!ISSET(sc->sc_mcr, MCR_RTS)) {
SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
} else {
if (ISSET(sc->sc_mcr, MCR_RTS)) {
CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
}
sc->sc_dtr = MCR_DTR | MCR_RTS;
ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
/* Just to be sure... */
int block;
{
struct com_softc *sc = pccom_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s;
/*
/* When not using CRTSCTS, RTS follows DTR. */
if (ISSET(tp->t_cflag, MDMBUF)) {
CLR(sc->sc_mcr, (MCR_DTR | MCR_RTS));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
else {
CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
}
else {
/* When not using CRTSCTS, RTS follows DTR. */
if (ISSET(tp->t_cflag, MDMBUF)) {
SET(sc->sc_mcr, (MCR_DTR | MCR_RTS));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
else {
SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
}
splx(s);
struct tty *tp;
{
struct com_softc *sc = pccom_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s, count;
s = spltty();
SET(tp->t_state, TS_BUSY);
if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
SET(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
}
n = sc->sc_fifolen;
if (n > count)
n = count;
sc->sc_tba = tp->t_outq.c_cf;
while (--n >= 0) {
- bus_io_write_1(bc, ioh, com_data, *sc->sc_tba++);
+ bus_space_write_1(iot, ioh, com_data, *sc->sc_tba++);
--count;
}
sc->sc_tbc = count;
stopped:
if (ISSET(sc->sc_ier, IER_ETXRDY)) {
CLR(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
}
out:
splx(s);
line->l_modem(tp, 1);
else if (line->l_modem(tp, 0) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(sc->sc_bc,
+ bus_space_write_1(sc->sc_iot,
sc->sc_ioh,
com_mcr,
sc->sc_mcr);
{
struct com_softc *sc = arg;
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
u_char lsr;
u_int rxput;
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (0);
rxput = sc->sc_rxput;
u_char msr, delta;
for (;;) {
- lsr = bus_io_read_1(bc, ioh, com_lsr);
+ lsr = bus_space_read_1(iot, ioh, com_lsr);
if (!ISSET(lsr, LSR_RCV_MASK))
break;
sc->sc_rxbuf[rxput] = lsr;
rxput = (rxput + 1) & RBUFMASK;
- sc->sc_rxbuf[rxput] = bus_io_read_1(bc, ioh, com_data);
+ sc->sc_rxbuf[rxput] = bus_space_read_1(iot, ioh, com_data);
rxput = (rxput + 1) & RBUFMASK;
}
- msr = bus_io_read_1(bc, ioh, com_msr);
+ msr = bus_space_read_1(iot, ioh, com_msr);
delta = msr ^ sc->sc_msr;
if (!ISSET(delta, MSR_DCD | MSR_CTS | MSR_RI | MSR_DSR))
continue;
rxput = (rxput + 1) & RBUFMASK;
sc->sc_rxbuf[rxput] = msr;
rxput = (rxput + 1) & RBUFMASK;
- } while (!ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND));
+ } while (!ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND));
if (ISSET(lsr, LSR_TXRDY)) {
if (sc->sc_tbc > 0) {
int n;
if (n > sc->sc_tbc)
n = sc->sc_tbc;
while (--n >= 0) {
- bus_io_write_1(bc, ioh, com_data, *sc->sc_tba++);
+ bus_space_write_1(iot, ioh, com_data, *sc->sc_tba++);
--sc->sc_tbc;
}
}
struct consdev *cp;
{
/* XXX NEEDS TO BE FIXED XXX */
- bus_chipset_tag_t bc = 0;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = 0;
+ bus_space_handle_t ioh;
int found;
- if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, CONADDR, COM_NPORTS, &ioh)) {
cp->cn_pri = CN_DEAD;
return;
}
- found = comprobe1(bc, ioh, CONADDR);
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ found = comprobe1(iot, ioh, CONADDR);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
if (!found) {
cp->cn_pri = CN_DEAD;
return;
#if 0
XXX NEEDS TO BE FIXED XXX
- comconsbc = ???;
+ comconsiot = ???;
#endif
- if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh))
+ if (bus_space_map(comconsiot, CONADDR, COM_NPORTS, &comconsioh))
panic("comcninit: mapping failed");
- cominit(comconsbc, comconsioh, comdefaultrate);
+ cominit(comconsiot, comconsioh, comdefaultrate);
comconsaddr = CONADDR;
comconsinit = 0;
}
void
-cominit(bc, ioh, rate)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+cominit(iot, ioh, rate)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int rate;
{
int s = splhigh();
u_char stat;
- bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB);
+ bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB);
rate = comspeed(comdefaultrate);
- bus_io_write_1(bc, ioh, com_dlbl, rate);
- bus_io_write_1(bc, ioh, com_dlbh, rate >> 8);
- bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS);
- bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
- stat = bus_io_read_1(bc, ioh, com_iir);
+ bus_space_write_1(iot, ioh, com_dlbl, rate);
+ bus_space_write_1(iot, ioh, com_dlbh, rate >> 8);
+ bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS);
+ bus_space_write_1(iot, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
+ bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
}
dev_t dev;
{
int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
+ bus_space_tag_t iot = comconsiot;
+ bus_space_handle_t ioh = comconsioh;
u_char stat, c;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY))
;
- c = bus_io_read_1(bc, ioh, com_data);
- stat = bus_io_read_1(bc, ioh, com_iir);
+ c = bus_space_read_1(iot, ioh, com_data);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
return c;
}
int c;
{
int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
+ bus_space_tag_t iot = comconsiot;
+ bus_space_handle_t ioh = comconsioh;
u_char stat;
register int timo;
if (dev != kgdb_dev)
#endif
if (comconsinit == 0) {
- cominit(bc, ioh, comdefaultrate);
+ cominit(iot, ioh, comdefaultrate);
comconsinit = 1;
}
/* wait for any pending transmission to finish */
timo = 50000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo)
;
- bus_io_write_1(bc, ioh, com_data, c);
+ bus_space_write_1(iot, ioh, com_data, c);
/* wait for this transmission to complete */
timo = 1500000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo)
;
/* clear any interrupts generated by this transmission */
- stat = bus_io_read_1(bc, ioh, com_iir);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
}
-/* $NetBSD: pci_compat.c,v 1.1 1996/03/27 04:01:13 cgd Exp $ */
+/* $OpenBSD: pci_compat.c,v 1.2 1996/11/28 23:37:42 niklas Exp $ */
+/* $NetBSD: pci_compat.c,v 1.4 1996/10/21 22:28:54 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
int reg;
int *iobasep;
{
- bus_io_addr_t ioaddr;
- bus_io_size_t iosize;
- bus_io_handle_t ioh;
+ bus_addr_t ioaddr;
+ bus_size_t iosize;
+ bus_space_handle_t ioh;
if (pci_io_find(NULL, tag, reg, &ioaddr, &iosize))
return (1);
- if (bus_io_map(NULL, ioaddr, iosize, &ioh))
+ if (bus_space_map(I386_BUS_SPACE_IO, ioaddr, iosize, 0, &ioh))
return (1);
*iobasep = ioh;
int reg;
vm_offset_t *vap, *pap;
{
- bus_mem_addr_t memaddr;
- bus_mem_size_t memsize;
- bus_mem_handle_t memh;
+ bus_addr_t memaddr;
+ bus_size_t memsize;
+ bus_space_handle_t memh;
int cacheable;
if (pci_mem_find(NULL, tag, reg, &memaddr, &memsize, &cacheable))
return (1);
- if (bus_mem_map(NULL, memaddr, memsize, cacheable, &memh))
+ if (bus_space_map(I386_BUS_SPACE_MEM, memaddr, memsize,
+ cacheable, &memh))
return (1);
*vap = (vm_offset_t)memh;
-/* $NetBSD: pci_machdep.c,v 1.23 1996/04/11 22:15:33 cgd Exp $ */
+/* $OpenBSD: pci_machdep.c,v 1.9 1996/11/28 23:37:42 niklas Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.26 1996/10/24 12:32:29 fvdl Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
+#ifndef PCI_CONF_MODE
mode1:
+#endif
if (bus >= 256 || device >= 32 || function >= 8)
panic("pci_make_tag: bad request");
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
+#ifndef PCI_CONF_MODE
mode2:
+#endif
if (bus >= 256 || device >= 16 || function >= 8)
panic("pci_make_tag: bad request");
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
+#ifndef PCI_CONF_MODE
mode1:
+#endif
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
data = inl(PCI_MODE1_DATA_REG);
outl(PCI_MODE1_ADDRESS_REG, 0);
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
+#ifndef PCI_CONF_MODE
mode2:
+#endif
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
data = inl(tag.mode2.port | reg);
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
+#ifndef PCI_CONF_MODE
mode1:
+#endif
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
outl(PCI_MODE1_DATA_REG, data);
outl(PCI_MODE1_ADDRESS_REG, 0);
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
+#ifndef PCI_CONF_MODE
mode2:
+#endif
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
outl(tag.mode2.port | reg, data);
-/* $OpenBSD: aha1742.c,v 1.13 1996/11/23 21:46:30 kstailey Exp $ */
+/* $OpenBSD: aha1742.c,v 1.14 1996/11/28 23:27:36 niklas Exp $ */
/* $NetBSD: aha1742.c,v 1.61 1996/05/12 23:40:01 mycroft Exp $ */
/*
#include <sys/proc.h>
#include <sys/user.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/eisa/eisareg.h>
struct ahb_softc {
struct device sc_dev;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
eisa_chipset_tag_t sc_ec;
- bus_io_handle_t sc_ioh;
+ bus_space_handle_t sc_ioh;
int sc_irq;
void *sc_ih;
void ahb_free_ecb __P((struct ahb_softc *, struct ahb_ecb *, int));
struct ahb_ecb *ahb_get_ecb __P((struct ahb_softc *, int));
struct ahb_ecb *ahb_ecb_phys_kv __P((struct ahb_softc *, physaddr));
-int ahb_find __P((bus_chipset_tag_t, bus_io_handle_t, struct ahb_softc *));
+int ahb_find __P((bus_space_tag_t, bus_space_handle_t, struct ahb_softc *));
void ahb_init __P((struct ahb_softc *));
void ahbminphys __P((struct buf *));
int ahb_scsi_cmd __P((struct scsi_xfer *));
int opcode;
struct ahb_ecb *ecb;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int wait = 300; /* 1ms should be enough */
while (--wait) {
- if ((bus_io_read_1(bc, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
- == (G2STAT_MBOX_EMPTY))
+ if ((bus_space_read_1(iot, ioh, G2STAT) &
+ (G2STAT_BUSY | G2STAT_MBOX_EMPTY)) == (G2STAT_MBOX_EMPTY))
break;
delay(10);
}
Debugger();
}
- bus_io_write_4(bc, ioh, MBOXOUT0, KVTOPHYS(ecb)); /* don't know this will work */
- bus_io_write_1(bc, ioh, ATTN, opcode | ecb->xs->sc_link->target);
+ /* don't know this will work */
+ bus_space_write_4(iot, ioh, MBOXOUT0, KVTOPHYS(ecb));
+ bus_space_write_1(iot, ioh, ATTN, opcode | ecb->xs->sc_link->target);
}
/*
struct scsi_xfer *xs;
int count;
{ /* in msec */
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
while (count) {
/*
* If we had interrupts enabled, would we
* have got an interrupt?
*/
- if (bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND)
+ if (bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND)
ahbintr(sc);
if (xs->flags & ITSDONE)
return 0;
int target;
u_long cmd;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int wait = 100; /* 1 ms enough? */
while (--wait) {
- if ((bus_io_read_1(bc, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
- == (G2STAT_MBOX_EMPTY))
+ if ((bus_space_read_1(iot, ioh, G2STAT) &
+ (G2STAT_BUSY | G2STAT_MBOX_EMPTY)) == (G2STAT_MBOX_EMPTY))
break;
delay(10);
}
Debugger();
}
- bus_io_write_4(bc, ioh, MBOXOUT0, cmd); /* don't know this will work */
- bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_SET_HOST_READY);
- bus_io_write_1(bc, ioh, ATTN, OP_IMMED | target);
+ /* don't know this will work */
+ bus_space_write_4(iot, ioh, MBOXOUT0, cmd);
+ bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_SET_HOST_READY);
+ bus_space_write_1(iot, ioh, ATTN, OP_IMMED | target);
}
/*
void *match, *aux;
{
struct eisa_attach_args *ea = aux;
- bus_chipset_tag_t bc = ea->ea_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
int rv;
/* must match one of our known ID strings */
strcmp(ea->ea_idstring, "ADP0400"))
return (0);
- if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, 0,
+ &ioh))
return (0);
#ifdef notyet
/* This won't compile as-is, anyway. */
- bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
+ bus_space_write_1(iot, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
delay(10);
- bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE);
+ bus_space_write_1(iot, ioh, EISA_CONTROL, EISA_ENABLE);
/* Wait for reset? */
delay(1000);
#endif
- rv = !ahb_find(bc, ioh, NULL);
+ rv = !ahb_find(iot, ioh, NULL);
- bus_io_unmap(ea->ea_bc, ioh, EISA_SLOT_SIZE);
+ bus_space_unmap(ea->ea_iot, ioh, EISA_SLOT_SIZE);
return (rv);
}
{
struct eisa_attach_args *ea = aux;
struct ahb_softc *sc = (void *)self;
- bus_chipset_tag_t bc = ea->ea_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
const char *model, *intrstr;
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ec = ec;
- if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, 0,
+ &ioh))
panic("ahbattach: could not map I/O addresses");
sc->sc_ioh = ioh;
- if (ahb_find(bc, ioh, sc))
+ if (ahb_find(iot, ioh, sc))
panic("ahbattach: ahb_find failed!");
ahb_init(sc);
void *arg;
{
struct ahb_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ahb_ecb *ecb;
u_char ahbstat;
u_long mboxval;
printf("%s: ahbintr ", sc->sc_dev.dv_xname);
#endif /* AHBDEBUG */
- if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
+ if ((bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
return 0;
for (;;) {
* First get all the information and then
* acknowlege the interrupt
*/
- ahbstat = bus_io_read_1(bc, ioh, G2INTST);
- mboxval = bus_io_read_4(bc, ioh, MBOXIN0);
- bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
+ ahbstat = bus_space_read_1(iot, ioh, G2INTST);
+ mboxval = bus_space_read_4(iot, ioh, MBOXIN0);
+ bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
#ifdef AHBDEBUG
printf("status = 0x%x ", ahbstat);
ahb_done(sc, ecb);
}
- if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
+ if ((bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND) ==
+ 0)
return 1;
}
}
* Start the board, ready for normal operation
*/
int
-ahb_find(bc, ioh, sc)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ahb_find(iot, ioh, sc)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct ahb_softc *sc;
{
u_char intdef;
int i, irq, busid;
int wait = 1000; /* 1 sec enough? */
- bus_io_write_1(bc, ioh, PORTADDR, PORTADDR_ENHANCED);
+ bus_space_write_1(iot, ioh, PORTADDR, PORTADDR_ENHANCED);
#define NO_NO 1
#ifdef NO_NO
* reset board, If it doesn't respond, assume
* that it's not there.. good for the probe
*/
- bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_HARD_RESET);
+ bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_HARD_RESET);
delay(1000);
- bus_io_write_1(bc, ioh, G2CNTRL, 0);
+ bus_space_write_1(iot, ioh, G2CNTRL, 0);
delay(10000);
while (--wait) {
- if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_BUSY) == 0)
+ if ((bus_space_read_1(iot, ioh, G2STAT) & G2STAT_BUSY) == 0)
break;
delay(1000);
}
#endif /*AHBDEBUG */
return ENXIO;
}
- i = bus_io_read_1(bc, ioh, MBOXIN0);
+ i = bus_space_read_1(iot, ioh, MBOXIN0);
if (i) {
printf("self test failed, val = 0x%x\n", i);
return EIO;
}
/* Set it again, just to be sure. */
- bus_io_write_1(bc, ioh, PORTADDR, PORTADDR_ENHANCED);
+ bus_space_write_1(iot, ioh, PORTADDR, PORTADDR_ENHANCED);
#endif
- while (bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) {
+ while (bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND) {
printf(".");
- bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
+ bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
delay(10000);
}
- intdef = bus_io_read_1(bc, ioh, INTDEF);
+ intdef = bus_space_read_1(iot, ioh, INTDEF);
switch (intdef & 0x07) {
case INT9:
irq = 9;
return EIO;
}
- bus_io_write_1(bc, ioh, INTDEF, (intdef | INTEN)); /* make sure we can interrupt */
+ /* make sure we can interrupt */
+ bus_space_write_1(iot, ioh, INTDEF, (intdef | INTEN));
/* who are we on the scsi bus? */
- busid = (bus_io_read_1(bc, ioh, SCSIDEF) & HSCSIID);
+ busid = (bus_space_read_1(iot, ioh, SCSIDEF) & HSCSIID);
/* if we want to fill in softc, do so now */
if (sc != NULL) {
+/* $OpenBSD: ahc_eisa.c,v 1.7 1996/11/28 23:27:37 niklas Exp $ */
+/* $NetBSD: ahc_eisa.c,v 1.10 1996/10/21 22:30:58 thorpej Exp $ */
+
/*
* Product specific probe and attach routines for:
* 27/284X and aic7770 motherboard SCSI controllers
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: ahc_eisa.c,v 1.6 1996/11/12 20:30:08 niklas Exp $
+ * $Id: ahc_eisa.c,v 1.7 1996/11/28 23:27:37 niklas Exp $
*/
#if defined(__FreeBSD__)
#if defined(__NetBSD__) || defined(__OpenBSD__)
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
-#endif /* defined(__NetBSD__) */
+#endif /* defined(__NetBSD__) || defined(__OpenBSD__) */
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
break;
default:
printf("aic7770 at slot %d: illegal "
- "irq setting %d\n", e_dev->ioconf.slot,
- intdef);
+ "irq setting %d\n", e_dev->ioconf.slot,
+ intdef);
continue;
}
eisa_add_intr(e_dev, irq);
#elif defined(__NetBSD__) || defined(__OpenBSD__)
+/*
+ * Under normal circumstances, these messages are unnecessary
+ * and not terribly cosmetic.
+ */
+#ifdef DEBUG
#define bootverbose 1
-
+#else
+#define bootverbose 0
+#endif
+
+int ahc_eisa_irq __P((bus_space_tag_t, bus_space_handle_t));
int ahc_eisa_match __P((struct device *, void *, void *));
void ahc_eisa_attach __P((struct device *, struct device *, void *));
sizeof(struct ahc_data), ahc_eisa_match, ahc_eisa_attach
};
-int ahc_eisa_irq __P((bus_chipset_tag_t, bus_io_handle_t));
-
/*
* Return irq setting of the board, otherwise -1.
*/
int
-ahc_eisa_irq(bc, ioh)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ahc_eisa_irq(iot, ioh)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
{
int irq;
u_char intdef;
- ahc_reset("ahc_eisa", bc, ioh);
- intdef = bus_io_read_1(bc, ioh, INTDEF);
+ ahc_reset("ahc_eisa", iot, ioh);
+ intdef = bus_space_read_1(iot, ioh, INTDEF);
switch (irq = (intdef & 0xf)) {
case 9:
case 10:
void *match, *aux;
{
struct eisa_attach_args *ea = aux;
- bus_chipset_tag_t bc = ea->ea_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
int irq;
/* must match one of our known ID strings */
)
return (0);
- if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + AHC_EISA_SLOT_OFFSET,
- AHC_EISA_IOSIZE, &ioh))
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
+ AHC_EISA_SLOT_OFFSET, AHC_EISA_IOSIZE, 0, &ioh))
return (0);
- irq = ahc_eisa_irq(bc, ioh);
+ irq = ahc_eisa_irq(iot, ioh);
- bus_io_unmap(bc, ioh, AHC_EISA_IOSIZE);
+ bus_space_unmap(iot, ioh, AHC_EISA_IOSIZE);
return (irq >= 0);
}
struct ahc_data *ahc = (void *)self;
struct eisa_attach_args *ea = aux;
- bus_chipset_tag_t bc = ea->ea_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
int irq;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
const char *model, *intrstr;
- if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + AHC_EISA_SLOT_OFFSET,
- AHC_EISA_IOSIZE, &ioh))
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
+ AHC_EISA_SLOT_OFFSET, AHC_EISA_IOSIZE, 0, &ioh))
panic("ahc_eisa_attach: could not map I/O addresses");
- if ((irq = ahc_eisa_irq(bc, ioh)) < 0)
+ if ((irq = ahc_eisa_irq(iot, ioh)) < 0)
panic("ahc_eisa_attach: ahc_eisa_irq failed!");
if (strcmp(ea->ea_idstring, "ADP7770") == 0) {
}
printf(": %s\n", model);
- ahc_construct(ahc, bc, ioh, type, AHC_FNONE);
+ ahc_construct(ahc, iot, ioh, type, AHC_FNONE);
if (eisa_intr_map(ec, irq, &ih)) {
printf("%s: couldn't map interrupt (%d)\n",
- ahc->sc_dev.dv_xname, irq);
+ ahc->sc_dev.dv_xname, irq);
return;
}
#endif /* defined(__NetBSD__) */
*/
if(bootverbose) {
printf("%s: Using %s Interrupts\n",
- ahc_name(ahc),
- ahc->pause & IRQMS ?
- "Level Sensitive" : "Edge Triggered");
+ ahc_name(ahc),
+ ahc->pause & IRQMS ? "Level Sensitive" : "Edge Triggered");
}
/*
);
if (ahc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt",
- ahc->sc_dev.dv_xname);
+ ahc->sc_dev.dv_xname);
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
--- /dev/null
+/* $OpenBSD: bha_eisa.c,v 1.1 1996/11/28 23:27:37 niklas Exp $ */
+/* $NetBSD: bha_eisa.c,v 1.5 1996/10/21 22:31:00 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/eisa/eisavar.h>
+#include <dev/eisa/eisadevs.h>
+
+#include <dev/ic/bhareg.h>
+#include <dev/ic/bhavar.h>
+
+#define BHA_EISA_SLOT_OFFSET 0xc00
+#define BHA_EISA_IOSIZE 0x100
+
+int bha_eisa_match __P((struct device *, void *, void *));
+void bha_eisa_attach __P((struct device *, struct device *, void *));
+
+struct cfattach bha_eisa_ca = {
+ sizeof(struct bha_softc), bha_eisa_match, bha_eisa_attach
+};
+
+/*
+ * Check the slots looking for a board we recognise
+ * If we find one, note it's address (slot) and call
+ * the actual probe routine to check it out.
+ */
+int
+bha_eisa_match(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct eisa_attach_args *ea = aux;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
+ int rv;
+
+ /* must match one of our known ID strings */
+ if (strcmp(ea->ea_idstring, "BUS4201") &&
+ strcmp(ea->ea_idstring, "BUS4202"))
+ return (0);
+
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
+ BHA_EISA_SLOT_OFFSET, BHA_EISA_IOSIZE, 0, &ioh))
+ return (0);
+
+ rv = bha_find(iot, ioh, NULL);
+
+ bus_space_unmap(iot, ioh, BHA_EISA_IOSIZE);
+
+ return (rv);
+}
+
+/*
+ * Attach all the sub-devices we can find
+ */
+void
+bha_eisa_attach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct eisa_attach_args *ea = aux;
+ struct bha_softc *sc = (void *)self;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
+ eisa_chipset_tag_t ec = ea->ea_ec;
+ eisa_intr_handle_t ih;
+ const char *model, *intrstr;
+
+ if (!strcmp(ea->ea_idstring, "BUS4201"))
+ model = EISA_PRODUCT_BUS4201;
+ else if (!strcmp(ea->ea_idstring, "BUS4202"))
+ model = EISA_PRODUCT_BUS4202;
+ else
+ model = "unknown model!";
+ printf(": %s\n", model);
+
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
+ BHA_EISA_SLOT_OFFSET, BHA_EISA_IOSIZE, 0, &ioh))
+ panic("bha_attach: could not map I/O addresses");
+
+ sc->sc_iot = iot;
+ sc->sc_ioh = ioh;
+ if (!bha_find(iot, ioh, sc))
+ panic("bha_attach: bha_find failed!");
+
+ if (eisa_intr_map(ec, sc->sc_irq, &ih)) {
+ printf("%s: couldn't map interrupt (%d)\n",
+ sc->sc_dev.dv_xname, sc->sc_irq);
+ return;
+ }
+ intrstr = eisa_intr_string(ec, ih);
+ sc->sc_ih = eisa_intr_establish(ec, ih, IST_LEVEL, IPL_BIO,
+ bha_intr, sc, sc->sc_dev.dv_xname);
+ if (sc->sc_ih == NULL) {
+ printf("%s: couldn't establish interrupt",
+ sc->sc_dev.dv_xname);
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ return;
+ }
+ printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
+
+ bha_attach(sc);
+}
-/* $OpenBSD: eisa.c,v 1.5 1996/11/23 21:46:31 kstailey Exp $ */
-/* $NetBSD: eisa.c,v 1.11 1996/04/09 22:46:11 cgd Exp $ */
+/* $OpenBSD: eisa.c,v 1.6 1996/11/28 23:27:38 niklas Exp $ */
+/* $NetBSD: eisa.c,v 1.15 1996/10/21 22:31:01 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
#include <sys/systm.h>
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/eisa/eisareg.h>
#include <dev/eisa/eisavar.h>
void *aux;
{
struct eisabus_attach_args *eba = aux;
- bus_chipset_tag_t bc;
+ bus_space_tag_t iot, memt;
eisa_chipset_tag_t ec;
int slot, maxnslots;
eisa_attach_hook(parent, self, eba);
printf("\n");
- bc = eba->eba_bc;
+ iot = eba->eba_iot;
+ memt = eba->eba_memt;
ec = eba->eba_ec;
/*
for (slot = 1; slot < maxnslots; slot++) {
struct eisa_attach_args ea;
u_int slotaddr;
- bus_io_handle_t slotioh;
+ bus_space_handle_t slotioh;
int i;
- ea.ea_bc = bc;
+ ea.ea_iot = iot;
+ ea.ea_memt = memt;
ea.ea_ec = ec;
ea.ea_slot = slot;
slotaddr = EISA_SLOT_ADDR(slot);
* space. If we can't, assume nothing's there but warn
* about it.
*/
- if (bus_io_map(bc, slotaddr, EISA_SLOT_SIZE, &slotioh)) {
+ if (bus_space_map(iot, slotaddr, EISA_SLOT_SIZE, 0, &slotioh)) {
printf("%s: can't map I/O space for slot %d\n",
self->dv_xname, slot);
continue;
/* Get the vendor ID bytes */
for (i = 0; i < EISA_NVIDREGS; i++) {
#ifdef EISA_SLOTOFF_PRIMING
- bus_io_write_1(bc, slotioh,
+ bus_space_write_1(iot, slotioh,
EISA_SLOTOFF_PRIMING, EISA_PRIMING_VID(i));
#endif
- ea.ea_vid[i] = bus_io_read_1(bc, slotioh,
+ ea.ea_vid[i] = bus_space_read_1(iot, slotioh,
EISA_SLOTOFF_VID + i);
}
printf("\t(0x%x, 0x%x)\n", ea.ea_vid[0],
ea.ea_vid[1]);
#endif
- bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
+ bus_space_unmap(iot, slotioh, EISA_SLOT_SIZE);
continue;
}
if (EISA_VENDID_IDDELAY(ea.ea_vid)) {
printf("%s slot %d not configured by BIOS?\n",
self->dv_xname, slot);
- bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
+ bus_space_unmap(iot, slotioh, EISA_SLOT_SIZE);
continue;
}
/* Get the product ID bytes */
for (i = 0; i < EISA_NPIDREGS; i++) {
#ifdef EISA_SLOTOFF_PRIMING
- bus_io_write_1(bc, slotioh,
+ bus_space_write_1(iot, slotioh,
EISA_SLOTOFF_PRIMING, EISA_PRIMING_PID(i));
#endif
- ea.ea_pid[i] = bus_io_read_1(bc, slotioh,
+ ea.ea_pid[i] = bus_space_read_1(iot, slotioh,
EISA_SLOTOFF_PID + i);
}
ea.ea_idstring[7] = '\0'; /* sanity */
/* We no longer need the I/O handle; free it. */
- bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
+ bus_space_unmap(iot, slotioh, EISA_SLOT_SIZE);
/* Attach matching device. */
config_found_sm(self, &ea, eisaprint, eisasubmatch);
-$OpenBSD: eisadevs,v 1.4 1996/05/26 00:26:53 deraadt Exp $
-/* $NetBSD: eisadevs,v 1.1 1996/02/26 23:46:22 cgd Exp $ */
+$OpenBSD: eisadevs,v 1.5 1996/11/28 23:27:38 niklas Exp $
+/* $NetBSD: eisadevs,v 1.10 1996/09/06 18:01:07 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
vendor AMI AMI
vendor BUS BusLogic
vendor DEC Digital Equipment
+vendor FSI FORE Systems
+vendor INT Intel
+vendor ETI Microdyne
vendor TCM 3Com
vendor USC UltraStor
product DEC 3003 DEFEA FDDI Controller
product DEC 3004 DEFEA FDDI Controller
+/* FORE Systems products */
+product FSI 2001 ESA-200 ATM
+product FSI 2002 ESA-200A ATM
+product FSI 2003 ESA-200E ATM
+
+/* Intel products */
+product INT 1010 EtherExpress 32 Flash Ethernet
+
+/* ETI products */
+product ETI 1001 NE3300 Ethernet Rev. C & D
+
/* 3Com products */
product TCM 5091 3C509 Ethernet
product TCM 5092 3C579-TP Ethernet
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * OpenBSD: eisadevs,v 1.2 1996/04/21 22:20:29 deraadt Exp
+ * OpenBSD: eisadevs,v 1.4 1996/05/26 00:26:53 deraadt Exp
*/
-/* $NetBSD: eisadevs,v 1.1 1996/02/26 23:46:22 cgd Exp $ */
+/* $NetBSD: eisadevs,v 1.10 1996/09/06 18:01:07 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
#define EISA_PRODUCT_DEC3003 "Digital Equipment DEFEA FDDI Controller"
#define EISA_PRODUCT_DEC3004 "Digital Equipment DEFEA FDDI Controller"
+/* FORE Systems products */
+#define EISA_PRODUCT_FSI2001 "FORE Systems ESA-200 ATM"
+#define EISA_PRODUCT_FSI2002 "FORE Systems ESA-200A ATM"
+#define EISA_PRODUCT_FSI2003 "FORE Systems ESA-200E ATM"
+
+/* Intel products */
+#define EISA_PRODUCT_INT1010 "Intel EtherExpress 32 Flash Ethernet"
+
+/* ETI products */
+#define EISA_PRODUCT_ETI1001 "Microdyne NE3300 Ethernet Rev. C & D"
+
/* 3Com products */
#define EISA_PRODUCT_TCM5091 "3Com 3C509 Ethernet"
#define EISA_PRODUCT_TCM5092 "3Com 3C579-TP Ethernet"
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * OpenBSD: eisadevs,v 1.2 1996/04/21 22:20:29 deraadt Exp
+ * OpenBSD: eisadevs,v 1.4 1996/05/26 00:26:53 deraadt Exp
*/
-/* $NetBSD: eisadevs,v 1.1 1996/02/26 23:46:22 cgd Exp $ */
+/* $NetBSD: eisadevs,v 1.10 1996/09/06 18:01:07 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
"DEC3004",
EISA_PRODUCT_DEC3004,
},
+ {
+ 0,
+ "FSI2001",
+ EISA_PRODUCT_FSI2001,
+ },
+ {
+ 0,
+ "FSI2002",
+ EISA_PRODUCT_FSI2002,
+ },
+ {
+ 0,
+ "FSI2003",
+ EISA_PRODUCT_FSI2003,
+ },
+ {
+ 0,
+ "INT1010",
+ EISA_PRODUCT_INT1010,
+ },
+ {
+ 0,
+ "ETI1001",
+ EISA_PRODUCT_ETI1001,
+ },
{
0,
"TCM5091",
"DEC",
"Digital Equipment",
},
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "FSI",
+ "FORE Systems",
+ },
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "INT",
+ "Intel",
+ },
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "ETI",
+ "Microdyne",
+ },
{
EISA_KNOWNDEV_NOPROD,
"TCM",
-/* $OpenBSD: eisavar.h,v 1.5 1996/11/12 20:30:10 niklas Exp $ */
-/* $NetBSD: eisavar.h,v 1.9 1996/04/12 06:34:36 cgd Exp $ */
+/* $OpenBSD: eisavar.h,v 1.6 1996/11/28 23:27:40 niklas Exp $ */
+/* $NetBSD: eisavar.h,v 1.10 1996/10/21 22:31:03 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
* separated into eisa_machdep.h.
*/
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/eisa/eisareg.h> /* For ID register & string info. */
/*
* EISA bus attach arguments.
*/
struct eisabus_attach_args {
- char *eba_busname; /* XXX should be common */
- bus_chipset_tag_t eba_bc; /* XXX should be common */
+ char *eba_busname; /* XXX should be common */
+ bus_space_tag_t eba_iot; /* eisa i/o space tag */
+ bus_space_tag_t eba_memt; /* eisa mem space tag */
eisa_chipset_tag_t eba_ec;
};
* EISA device attach arguments.
*/
struct eisa_attach_args {
- bus_chipset_tag_t ea_bc;
+ bus_space_tag_t ea_iot; /* eisa i/o space tag */
+ bus_space_tag_t ea_memt; /* eisa mem space tag */
eisa_chipset_tag_t ea_ec;
eisa_slot_t ea_slot;
-# $OpenBSD: files.eisa,v 1.7 1996/10/04 02:51:25 deraadt Exp $
-# $NetBSD: files.eisa,v 1.10 1996/05/20 00:44:11 thorpej Exp $
+# $OpenBSD: files.eisa,v 1.8 1996/11/28 23:27:40 niklas Exp $
+# $NetBSD: files.eisa,v 1.12 1996/09/01 00:10:55 mycroft Exp $
#
# Config.new file and device description for machine-independent EISA code.
# Included by ports that need it. Requires that the SCSI files be
attach ahc at eisa with ahc_eisa
file dev/eisa/ahc_eisa.c ahc_eisa
+# BusLogic BT-7xx EISA family
+# device declaration in sys/conf/files
+attach bha at eisa with bha_eisa
+file dev/eisa/bha_eisa.c bha_eisa
+
+# UltraStor UHA-24f boards
+# device declaration in sys/conf/files
+attach uha at eisa with uha_eisa
+file dev/eisa/uha_eisa.c uha_eisa
+
# 3Com 3c579 and 3c509 masquerading as EISA Ethernet Controllers
# device declaration in sys/conf/files
attach ep at eisa with ep_eisa
-/* $NetBSD: if_ep_eisa.c,v 1.6 1996/05/14 22:21:05 thorpej Exp $ */
+/* $NetBSD: if_ep_eisa.c,v 1.9 1996/10/21 22:31:04 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/ic/elink3var.h>
{
struct ep_softc *sc = (void *)self;
struct eisa_attach_args *ea = aux;
- bus_chipset_tag_t bc = ea->ea_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
u_int16_t k, conn = 0;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
u_int irq;
/* Map i/o space. */
- if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot),
+ EISA_SLOT_SIZE, 0, &ioh))
panic("ep_eisa_attach: can't map i/o space");
sc->bustype = EP_BUS_EISA;
sc->sc_ioh = ioh;
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
/* Reset card. */
- bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
+ bus_space_write_1(iot, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
delay(10);
- bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE);
+ bus_space_write_1(iot, ioh, EISA_CONTROL, EISA_ENABLE);
/* Wait for reset? */
delay(1000);
/* XXX What is this doing?! Reading the i/o address? */
- k = bus_io_read_2(bc, ioh, EP_W0_ADDRESS_CFG);
+ k = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG);
k = (k & 0x1f) * 0x10 + 0x200;
/* Read the IRQ from the card. */
- irq = bus_io_read_2(bc, ioh, EP_W0_RESOURCE_CFG) >> 12;
+ irq = bus_space_read_2(iot, ioh, EP_W0_RESOURCE_CFG) >> 12;
GO_WINDOW(0);
- conn = bus_io_read_2(bc, ioh, EP_W0_CONFIG_CTRL);
+ conn = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL);
if (strcmp(ea->ea_idstring, "TCM5091") == 0)
model = EISA_PRODUCT_TCM5091;
-/* $NetBSD: if_fea.c,v 1.3.2.2 1996/06/09 23:34:52 cgd Exp $ */
+/* $NetBSD: if_fea.c,v 1.9 1996/10/21 22:31:05 thorpej Exp $ */
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
#include <i386/eisa/pdqreg.h>
#elif defined(__NetBSD__) || defined(__OpenBSD__)
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/ic/pdqvar.h>
#include <dev/ic/pdqreg.h>
pdq_softc_t *sc)
{
pdq_uint8_t data;
+ pdq_bus_t tag;
+
+#if defined(__NetBSD__)
+ tag = sc->sc_iotag;
+#else
+ tag = sc->sc_bc;
+#endif
/*
* Do the standard initialization for the DEFEA registers.
*/
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_FUNCTION_CTRL, 0x23);
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CMP_1_1, (sc->sc_iobase >> 8) & 0xF0);
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CMP_0_1, (sc->sc_iobase >> 8) & 0xF0);
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_SLOT_CTRL, 0x01);
- data = PDQ_OS_IORD_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_FUNCTION_CTRL, 0x23);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CMP_1_1, (sc->sc_iobase >> 8) & 0xF0);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CMP_0_1, (sc->sc_iobase >> 8) & 0xF0);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_SLOT_CTRL, 0x01);
+ data = PDQ_OS_IORD_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF);
#if defined(PDQ_IOMAPPED)
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data & ~1);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data & ~1);
#else
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data | 1);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data | 1);
#endif
- data = PDQ_OS_IORD_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0);
- PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE);
+ data = PDQ_OS_IORD_8(tag, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0);
+ PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE);
}
#if defined(__FreeBSD__)
sc->sc_membase = (pdq_bus_memaddr_t) pmap_mapdev(mspace->addr, mspace->size);
if (sc->sc_membase == NULL) {
printf("fea%d: failed to map memory 0x%x-0x%x!\n",
- sc->sc_if.if_unit, mspace->addr, mspace->addr + mspace->size - 1);
+ sc->sc_if.if_unit, mspace->addr, mspace->addr + mspace->size - 1);
return -1;
}
eisa_reg_start(ed);
if (eisa_reg_iospace(ed, iospace)) {
printf("fea%d: failed to register iospace 0x%x-0x%x!\n",
- sc->sc_if.if_unit, iospace->addr, iospace->addr + iospace->size - 1);
+ sc->sc_if.if_unit, iospace->addr, iospace->addr + iospace->size - 1);
return -1;
}
if (eisa_reg_mspace(ed, mspace)) {
printf("fea%d: failed to register memory 0x%x-0x%x!\n",
- sc->sc_if.if_unit, mspace->addr, mspace->addr + mspace->size - 1);
+ sc->sc_if.if_unit, mspace->addr, mspace->addr + mspace->size - 1);
return -1;
}
pdq_eisa_subprobe(PDQ_BUS_EISA, ia->ia_iobase, &maddr, &msize, &irq);
if (ia->ia_irq != IRQUNK && irq != ia->ia_irq) {
printf("fea%d: error: desired IRQ of %d does not match device's actual IRQ (%d),\n",
- cf->cf_unit,
- ffs(ia->ia_irq) - 1, ffs(irq) - 1);
+ cf->cf_unit, ffs(ia->ia_irq) - 1, ffs(irq) - 1);
return 0;
}
if (ia->ia_irq == IRQUNK) {
if ((ia->ia_irq = isa_irqalloc(irq)) == 0) {
if ((ia->ia_irq = isa_irqalloc(IRQ9|IRQ10|IRQ11|IRQ15)) == 0) {
printf("fea%d: error: IRQ %d is already in use\n", cf->cf_unit,
- ffs(irq) - 1);
+ ffs(irq) - 1);
return 0;
}
irq = PDQ_OS_IORD_8(PDQ_BUS_EISA, ia->ia_iobase, PDQ_EISA_IO_CONFIG_STAT_0) & ~3;
}
if (maddr == 0) {
printf("fea%d: error: memory not enabled! ECU reconfiguration required\n",
- cf->cf_unit);
+ cf->cf_unit);
return 0;
}
eisa_intr_handle_t ih;
const char *intrstr;
- sc->sc_bc = ea->ea_bc;
+ sc->sc_iotag = ea->ea_iot;
bcopy(sc->sc_dev.dv_xname, sc->sc_if.if_xname, IFNAMSIZ);
sc->sc_if.if_flags = 0;
sc->sc_if.if_softc = sc;
- if (bus_io_map(sc->sc_bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &sc->sc_iobase)) {
+ /*
+ * NOTE: sc_bc is an alias for sc_csrtag and sc_membase is
+ * an alias for sc_csrhandle. sc_iobase is used here to
+ * check the card's configuration.
+ */
+
+ if (bus_space_map(sc->sc_iotag, EISA_SLOT_ADDR(ea->ea_slot),
+ EISA_SLOT_SIZE, 0, &sc->sc_iobase)) {
printf("\n%s: failed to map I/O!\n", sc->sc_dev.dv_xname);
return;
}
- pdq_eisa_subprobe(sc->sc_bc, sc->sc_iobase, &maddr, &msize, &irq);
+ pdq_eisa_subprobe(sc->sc_iotag, sc->sc_iobase, &maddr, &msize, &irq);
-#if !defined(PDQ_IOMAPPED)
+#if defined(PDQ_IOMAPPED)
+ sc->sc_csrtag = sc->sc_iotag;
+ sc->sc_csrhandle = sc->sc_iobase;
+#else
if (maddr == 0 || msize == 0) {
printf("\n%s: error: memory not enabled! ECU reconfiguration required\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
return;
}
- if (bus_mem_map(sc->sc_bc, maddr, msize, 0, &sc->sc_membase)) {
- bus_io_unmap(sc->sc_bc, sc->sc_iobase, EISA_SLOT_SIZE);
+ if (bus_space_map(sc->sc_csrtag, maddr, msize, 0, &sc->sc_csrhandle)) {
+ bus_space_unmap(sc->sc_iotag, sc->sc_iobase, EISA_SLOT_SIZE);
printf("\n%s: failed to map memory (0x%x-0x%x)!\n",
sc->sc_dev.dv_xname, maddr, maddr + msize - 1);
return;
--- /dev/null
+/* $OpenBSD: uha_eisa.c,v 1.1 1996/11/28 23:27:42 niklas Exp $ */
+/* $NetBSD: uha_eisa.c,v 1.5 1996/10/21 22:31:07 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/proc.h>
+#include <sys/user.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/eisa/eisavar.h>
+#include <dev/eisa/eisadevs.h>
+
+#include <dev/ic/uhareg.h>
+#include <dev/ic/uhavar.h>
+
+#define UHA_EISA_SLOT_OFFSET 0xc80
+#define UHA_EISA_IOSIZE 0x020
+
+int uha_eisa_match __P((struct device *, void *, void *));
+void uha_eisa_attach __P((struct device *, struct device *, void *));
+
+struct cfattach uha_eisa_ca = {
+ sizeof(struct uha_softc), uha_eisa_match, uha_eisa_attach
+};
+
+#define KVTOPHYS(x) vtophys(x)
+
+int u24_find __P((bus_space_tag_t, bus_space_handle_t, struct uha_softc *));
+void u24_start_mbox __P((struct uha_softc *, struct uha_mscp *));
+int u24_poll __P((struct uha_softc *, struct scsi_xfer *, int));
+int u24_intr __P((void *));
+void u24_init __P((struct uha_softc *));
+
+/*
+ * Check the slots looking for a board we recognise
+ * If we find one, note it's address (slot) and call
+ * the actual probe routine to check it out.
+ */
+int
+uha_eisa_match(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct eisa_attach_args *ea = aux;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
+ int rv;
+
+ /* must match one of our known ID strings */
+ if (strncmp(ea->ea_idstring, "USC024", 6))
+ return (0);
+
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
+ UHA_EISA_SLOT_OFFSET, UHA_EISA_IOSIZE, 0, &ioh))
+ return (0);
+
+ rv = u24_find(iot, ioh, NULL);
+
+ bus_space_unmap(iot, ioh, UHA_EISA_IOSIZE);
+
+ return (rv);
+}
+
+/*
+ * Attach all the sub-devices we can find
+ */
+void
+uha_eisa_attach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct eisa_attach_args *ea = aux;
+ struct uha_softc *sc = (void *)self;
+ bus_space_tag_t iot = ea->ea_iot;
+ bus_space_handle_t ioh;
+ eisa_chipset_tag_t ec = ea->ea_ec;
+ eisa_intr_handle_t ih;
+ const char *model, *intrstr;
+
+ if (!strncmp(ea->ea_idstring, "USC024", 6))
+ model = EISA_PRODUCT_USC0240;
+ else
+ model = "unknown model!";
+ printf(": %s\n", model);
+
+ if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
+ UHA_EISA_SLOT_OFFSET, UHA_EISA_IOSIZE, 0, &ioh))
+ panic("uha_attach: could not map I/O addresses");
+
+ sc->sc_iot = iot;
+ sc->sc_ioh = ioh;
+ if (!u24_find(iot, ioh, sc))
+ panic("uha_attach: u24_find failed!");
+
+ if (eisa_intr_map(ec, sc->sc_irq, &ih)) {
+ printf("%s: couldn't map interrupt (%d)\n",
+ sc->sc_dev.dv_xname, sc->sc_irq);
+ return;
+ }
+ intrstr = eisa_intr_string(ec, ih);
+ sc->sc_ih = eisa_intr_establish(ec, ih, IST_LEVEL, IPL_BIO,
+ u24_intr, sc, sc->sc_dev.dv_xname);
+ if (sc->sc_ih == NULL) {
+ printf("%s: couldn't establish interrupt",
+ sc->sc_dev.dv_xname);
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ return;
+ }
+ printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
+
+ /* Save function pointers for later use. */
+ sc->start_mbox = u24_start_mbox;
+ sc->poll = u24_poll;
+ sc->init = u24_init;
+
+ uha_attach(sc);
+}
+
+int
+u24_find(iot, ioh, sc)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+ struct uha_softc *sc;
+{
+ u_int8_t config0, config1, config2;
+ int irq, drq;
+ int resetcount = 4000; /* 4 secs? */
+
+ config0 = bus_space_read_1(iot, ioh, U24_CONFIG + 0);
+ config1 = bus_space_read_1(iot, ioh, U24_CONFIG + 1);
+ config2 = bus_space_read_1(iot, ioh, U24_CONFIG + 2);
+ if ((config0 & U24_MAGIC1) == 0 ||
+ (config1 & U24_MAGIC2) == 0)
+ return (0);
+
+ drq = -1;
+
+ switch (config0 & U24_IRQ_MASK) {
+ case U24_IRQ10:
+ irq = 10;
+ break;
+ case U24_IRQ11:
+ irq = 11;
+ break;
+ case U24_IRQ14:
+ irq = 14;
+ break;
+ case U24_IRQ15:
+ irq = 15;
+ break;
+ default:
+ printf("u24_find: illegal irq setting %x\n",
+ config0 & U24_IRQ_MASK);
+ return (0);
+ }
+
+ bus_space_write_1(iot, ioh, U24_LINT, UHA_ASRST);
+
+ while (--resetcount) {
+ if (bus_space_read_1(iot, ioh, U24_LINT))
+ break;
+ delay(1000); /* 1 mSec per loop */
+ }
+ if (!resetcount) {
+ printf("u24_find: board timed out during reset\n");
+ return (0);
+ }
+
+ /* if we want to fill in softc, do so now */
+ if (sc != NULL) {
+ sc->sc_irq = irq;
+ sc->sc_drq = drq;
+ sc->sc_scsi_dev = config2 & U24_HOSTID_MASK;
+ }
+
+ return (1);
+}
+
+void
+u24_start_mbox(sc, mscp)
+ struct uha_softc *sc;
+ struct uha_mscp *mscp;
+{
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
+ int spincount = 100000; /* 1s should be enough */
+
+ while (--spincount) {
+ if ((bus_space_read_1(iot, ioh, U24_LINT) & U24_LDIP) == 0)
+ break;
+ delay(100);
+ }
+ if (!spincount) {
+ printf("%s: uha_start_mbox, board not responding\n",
+ sc->sc_dev.dv_xname);
+ Debugger();
+ }
+
+ bus_space_write_4(iot, ioh, U24_OGMPTR, KVTOPHYS(mscp));
+ if (mscp->flags & MSCP_ABORT)
+ bus_space_write_1(iot, ioh, U24_OGMCMD, 0x80);
+ else
+ bus_space_write_1(iot, ioh, U24_OGMCMD, 0x01);
+ bus_space_write_1(iot, ioh, U24_LINT, U24_OGMFULL);
+
+ if ((mscp->xs->flags & SCSI_POLL) == 0)
+ timeout(uha_timeout, mscp, (mscp->timeout * hz) / 1000);
+}
+
+int
+u24_poll(sc, xs, count)
+ struct uha_softc *sc;
+ struct scsi_xfer *xs;
+ int count;
+{
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
+
+ while (count) {
+ /*
+ * If we had interrupts enabled, would we
+ * have got an interrupt?
+ */
+ if (bus_space_read_1(iot, ioh, U24_SINT) & U24_SDIP)
+ u24_intr(sc);
+ if (xs->flags & ITSDONE)
+ return (0);
+ delay(1000);
+ count--;
+ }
+ return (1);
+}
+
+int
+u24_intr(arg)
+ void *arg;
+{
+ struct uha_softc *sc = arg;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
+ struct uha_mscp *mscp;
+ u_char uhastat;
+ u_long mboxval;
+
+#ifdef UHADEBUG
+ printf("%s: uhaintr ", sc->sc_dev.dv_xname);
+#endif /*UHADEBUG */
+
+ if ((bus_space_read_1(iot, ioh, U24_SINT) & U24_SDIP) == 0)
+ return (0);
+
+ for (;;) {
+ /*
+ * First get all the information and then
+ * acknowledge the interrupt
+ */
+ uhastat = bus_space_read_1(iot, ioh, U24_SINT);
+ mboxval = bus_space_read_4(iot, ioh, U24_ICMPTR);
+ bus_space_write_1(iot, ioh, U24_SINT, U24_ICM_ACK);
+ bus_space_write_1(iot, ioh, U24_ICMCMD, 0);
+
+#ifdef UHADEBUG
+ printf("status = 0x%x ", uhastat);
+#endif /*UHADEBUG*/
+
+ /*
+ * Process the completed operation
+ */
+ mscp = uha_mscp_phys_kv(sc, mboxval);
+ if (!mscp) {
+ printf("%s: BAD MSCP RETURNED!\n",
+ sc->sc_dev.dv_xname);
+ continue; /* whatever it was, it'll timeout */
+ }
+ untimeout(uha_timeout, mscp);
+ uha_done(sc, mscp);
+
+ if ((bus_space_read_1(iot, ioh, U24_SINT) & U24_SDIP) == 0)
+ return (1);
+ }
+}
+
+void
+u24_init(sc)
+ struct uha_softc *sc;
+{
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
+
+ /* free OGM and ICM */
+ bus_space_write_1(iot, ioh, U24_OGMCMD, 0);
+ bus_space_write_1(iot, ioh, U24_ICMCMD, 0);
+ /* make sure interrupts are enabled */
+#ifdef UHADEBUG
+ printf("u24_init: lmask=%02x, smask=%02x\n",
+ bus_space_read_1(iot, ioh, U24_LMASK),
+ bus_space_read_1(iot, ioh, U24_SMASK));
+#endif
+ bus_space_write_1(iot, ioh, U24_LMASK, 0xd2); /* XXX */
+ bus_space_write_1(iot, ioh, U24_SMASK, 0x92); /* XXX */
+}
-/* $OpenBSD: aic7xxx.c,v 1.13 1996/11/23 21:46:33 kstailey Exp $ */
+/* $OpenBSD: aic7xxx.c,v 1.14 1996/11/28 23:27:43 niklas Exp $ */
+/* $NetBSD: aic7xxx.c,v 1.17 1996/10/21 22:34:04 thorpej Exp $ */
/*
* Generic driver for the aic7xxx based adaptec SCSI controllers
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
+ *
+ * from Id: aic7xxx.c,v 1.75 1996/06/23 20:02:37 gibbs Exp
*/
-
/*
* TODO:
* Implement Target Mode
#include <sys/systm.h>
#if defined(__NetBSD__) || defined(__OpenBSD__)
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
-#endif /* defined(__NetBSD__) */
+#endif /* defined(__NetBSD__) || defined(__OpenBSD__) */
#include <sys/malloc.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <scsi/scsi_all.h>
+#include <scsi/scsi_message.h>
#if defined(__NetBSD__) || defined(__OpenBSD__)
#include <scsi/scsi_debug.h>
#endif
#define DEBUGTARG DEBUGTARGET
#if DEBUGTARG < 0 /* Negative numbrs for disabling cause warnings */
#undef DEBUGTARG
-#define DEBUGTARG 9
+#define DEBUGTARG 17
#endif
-#endif /* defined(__NetBSD__) */
+#endif /* defined(__NetBSD__) || defined(__OpenBSD__) */
#include <sys/kernel.h>
#define KVTOPHYS(x) vtophys(x)
static void ahcminphys __P((struct buf *bp));
static int32_t ahc_scsi_cmd __P((struct scsi_xfer *xs));
+static inline void pause_sequencer __P((struct ahc_data *ahc));
+static inline void unpause_sequencer __P((struct ahc_data *ahc,
+ int unpause_always));
+static inline void restart_sequencer __P((struct ahc_data *ahc));
static struct scsi_adapter ahc_switch =
{
#endif
};
-/*
- * Since the sequencer can disable pausing in a critical section, we
- * must loop until it actually stops.
- * XXX Should add a timeout in here??
- */
-#define PAUSE_SEQUENCER(ahc) \
- AHC_OUTB(ahc, HCNTRL, ahc->pause); \
- \
- while ((AHC_INB(ahc, HCNTRL) & PAUSE) == 0) \
+static inline void
+pause_sequencer(ahc)
+ struct ahc_data *ahc;
+{
+ AHC_OUTB(ahc, HCNTRL, ahc->pause);
+
+ /*
+ * Since the sequencer can disable pausing in a critical section, we
+ * must loop until it actually stops.
+ */
+ while ((AHC_INB(ahc, HCNTRL) & PAUSE) == 0)
;
+}
-#define UNPAUSE_SEQUENCER(ahc) \
- AHC_OUTB(ahc, HCNTRL, ahc->unpause )
+static inline void
+unpause_sequencer(ahc, unpause_always)
+ struct ahc_data *ahc;
+ int unpause_always;
+{
+ if (unpause_always
+ ||(AHC_INB(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
+ AHC_OUTB(ahc, HCNTRL, ahc->unpause);
+}
/*
* Restart the sequencer program from address zero
*/
-#define RESTART_SEQUENCER(ahc) \
- do { \
- AHC_OUTB(ahc, SEQCTL, SEQRESET|FASTMODE); \
- } while((AHC_INB(ahc, SEQADDR0) != 0) \
- || (AHC_INB(ahc, SEQADDR1) != 0)); \
- \
- UNPAUSE_SEQUENCER(ahc);
+static inline void
+restart_sequencer(ahc)
+ struct ahc_data *ahc;
+{
+ do {
+ AHC_OUTB(ahc, SEQCTL, SEQRESET|FASTMODE);
+ } while((AHC_INB(ahc, SEQADDR0) != 0)
+ || (AHC_INB(ahc, SEQADDR1) != 0));
+
+ unpause_sequencer(ahc, /*unpause_always*/TRUE);
+}
#if defined(__NetBSD__) || defined(__OpenBSD__)
/*
((sc_link)->scsibus == (ahc)->sc_link_b.scsibus)
/*
- * convert FreeBSD's SCSI symbols to NetBSD's
+ * convert FreeBSD's SCSI symbols to Net- & OpenBSD's
*/
#define SCSI_NOMASK SCSI_POLL
#define opennings openings
static inline void ahc_page_scb __P((struct ahc_data *ahc, struct scb *out_scb,
struct scb *in_scb));
static inline void ahc_run_waiting_queues __P((struct ahc_data *ahc));
+static void ahc_handle_seqint __P((struct ahc_data *ahc, u_int8_t intstat));
static struct scb *
ahc_get_scb __P((struct ahc_data *ahc, int flags));
static void ahc_loadseq __P((struct ahc_data *ahc));
u_int32_t xs_error));
static void ahc_reset_current_bus __P((struct ahc_data *ahc));
static void ahc_run_done_queue __P((struct ahc_data *ahc));
-static void ahc_scsirate __P((struct ahc_data* ahc, u_char *scsirate,
- int period, int offset, char channel,
- int target));
+static void ahc_scsirate __P((struct ahc_data* ahc, u_int8_t *scsirate,
+ u_int8_t *period, u_int8_t *offset,
+ char channel, int target));
#if defined(__FreeBSD__)
static timeout_t
ahc_timeout;
int target, char channel));
static void ahc_unbusy_target __P((struct ahc_data *ahc,
int target, char channel));
+static void ahc_construct_sdtr __P((struct ahc_data *ahc, int start_byte,
+ u_int8_t period, u_int8_t offset));
+static void ahc_construct_wdtr __P((struct ahc_data *ahc, int start_byte,
+ u_int8_t bus_width));
#if defined(__FreeBSD__)
short sxfr;
/* Rates in Ultra mode have bit 8 of sxfr set */
#define ULTRA_SXFR 0x100
- short period; /* in ns */
+ int period; /* in ns/4 */
char *rate;
} ahc_syncrates[] = {
- { 0x100, 50, "20.0" },
- { 0x110, 62, "16.0" },
- { 0x120, 75, "13.4" },
- { 0x000, 100, "10.0" },
- { 0x010, 125, "8.0" },
- { 0x020, 150, "6.67" },
- { 0x030, 175, "5.7" },
- { 0x040, 200, "5.0" },
- { 0x050, 225, "4.4" },
- { 0x060, 250, "4.0" },
- { 0x070, 275, "3.6" }
+ { 0x100, 12, "20.0" },
+ { 0x110, 15, "16.0" },
+ { 0x120, 18, "13.4" },
+ { 0x000, 25, "10.0" },
+ { 0x010, 31, "8.0" },
+ { 0x020, 37, "6.67" },
+ { 0x030, 43, "5.7" },
+ { 0x040, 50, "5.0" },
+ { 0x050, 56, "4.4" },
+ { 0x060, 62, "4.0" },
+ { 0x070, 68, "3.6" }
};
static int ahc_num_syncrates =
* Allocate a controller structures for a new device and initialize it.
* ahc_reset should be called before now since we assume that the card
* is paused.
- *
*/
#if defined(__FreeBSD__)
struct ahc_data *
u_long iobase;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
void
-ahc_construct(ahc, bc, ioh, type, flags)
+ahc_construct(ahc, iot, ioh, type, flags)
struct ahc_data *ahc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
#endif
ahc_type type;
ahc_flag flags;
#if defined(__FreeBSD__)
ahc->baseport = iobase;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- ahc->sc_bc = bc;
+ ahc->sc_iot = iot;
ahc->sc_ioh = ioh;
#endif
ahc->type = type;
ahc_reset(iobase)
u_long iobase;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
-ahc_reset(devname, bc, ioh)
+ahc_reset(devname, iot, ioh)
char *devname;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
#endif
{
u_char hcntrl;
outb(HCNTRL + iobase, CHIPRST | PAUSE);
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- hcntrl = (bus_io_read_1(bc, ioh, HCNTRL) & IRQMS) | INTEN;
+ hcntrl = (bus_space_read_1(iot, ioh, HCNTRL) & IRQMS) | INTEN;
- bus_io_write_1(bc, ioh, HCNTRL, CHIPRST | PAUSE);
+ bus_space_write_1(iot, ioh, HCNTRL, CHIPRST | PAUSE);
#endif
/*
* Ensure that the reset has finished
#if defined(__FreeBSD__)
while (--wait && !(inb(HCNTRL + iobase) & CHIPRSTACK))
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- while (--wait && !(bus_io_read_1(bc, ioh, HCNTRL) & CHIPRSTACK))
+ while (--wait && !(bus_space_read_1(iot, ioh, HCNTRL) & CHIPRSTACK))
#endif
DELAY(1000);
if(wait == 0) {
#if defined(__FreeBSD__)
outb(HCNTRL + iobase, hcntrl | PAUSE);
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- bus_io_write_1(bc, ioh, HCNTRL, hcntrl | PAUSE);
+ bus_space_write_1(iot, ioh, HCNTRL, hcntrl | PAUSE);
#endif
}
*/
static void
ahc_scsirate(ahc, scsirate, period, offset, channel, target )
- struct ahc_data *ahc;
- u_char *scsirate;
- short period;
- u_char offset;
- char channel;
- int target;
+ struct ahc_data *ahc;
+ u_int8_t *scsirate;
+ u_int8_t *period;
+ u_int8_t *offset;
+ char channel;
+ int target;
{
int i;
+ u_int32_t ultra_enb_addr;
+ u_int8_t sxfrctl0;
+ u_int8_t ultra_enb;
- for (i = 0; i < ahc_num_syncrates; i++) {
- u_char ultra_enb;
- u_char sxfrctl0;
- u_long ultra_enb_addr;
+ i = ahc_num_syncrates; /* Default to async */
+
+ if (*period >= ahc_syncrates[0].period && *offset != 0) {
+ for (i = 0; i < ahc_num_syncrates; i++) {
- if ((ahc_syncrates[i].period - period) >= 0) {
- /*
- * Watch out for Ultra speeds when ultra is not
- * enabled and vice-versa.
- */
- if(!(ahc->type & AHC_ULTRA)
- && (ahc_syncrates[i].sxfr & ULTRA_SXFR)) {
+ if (*period <= ahc_syncrates[i].period) {
/*
- * This should only happen if the
- * drive is the first to negotiate
- * and chooses a high rate. We'll
- * just move down the table util
- * we hit a non ultra speed.
+ * Watch out for Ultra speeds when ultra is not
+ * enabled and vice-versa.
*/
- continue;
- }
- *scsirate = (ahc_syncrates[i].sxfr) | (offset & 0x0f);
-
- /*
- * Ensure Ultra mode is set properly for
- * this target.
- */
- ultra_enb_addr = ULTRA_ENB;
- if(channel == 'B' || target > 7)
- ultra_enb_addr++;
- ultra_enb = AHC_INB(ahc, ultra_enb_addr);
- sxfrctl0 = AHC_INB(ahc, SXFRCTL0);
- if (ahc_syncrates[i].sxfr & ULTRA_SXFR) {
- ultra_enb |= 0x01 << (target & 0x07);
- sxfrctl0 |= ULTRAEN;
- }
- else {
- ultra_enb &= ~(0x01 << (target & 0x07));
- sxfrctl0 &= ~ULTRAEN;
- }
- AHC_OUTB(ahc, ultra_enb_addr, ultra_enb);
- AHC_OUTB(ahc, SXFRCTL0, sxfrctl0);
-
- if(bootverbose) {
- printf("%s: target %d synchronous at %sMHz,"
- " offset = 0x%x\n",
- ahc_name(ahc), target,
- ahc_syncrates[i].rate, offset );
+ if(!(ahc->type & AHC_ULTRA)
+ && (ahc_syncrates[i].sxfr & ULTRA_SXFR)) {
+ /*
+ * This should only happen if the
+ * drive is the first to negotiate
+ * and chooses a high rate. We'll
+ * just move down the table util
+ * we hit a non ultra speed.
+ */
+ continue;
+ }
+ *scsirate = (ahc_syncrates[i].sxfr & 0xF0)
+ | (*offset & 0x0f);
+ *period = ahc_syncrates[i].period;
+
+ if(bootverbose) {
+ printf("%s: target %d synchronous at %sMHz,"
+ " offset = 0x%x\n",
+ ahc_name(ahc), target,
+ ahc_syncrates[i].rate, *offset );
+ }
+ break;
}
- return;
}
}
- /* Default to asyncronous transfers. Also reject this SDTR request. */
- *scsirate = 0;
- if(bootverbose) {
- printf("%s: target %d using asyncronous transfers\n",
- ahc_name(ahc), target );
+ if (i >= ahc_num_syncrates) {
+ /* Use asyncronous transfers. */
+ *scsirate = 0;
+ *period = 0;
+ *offset = 0;
+ if (bootverbose)
+ printf("%s: target %d using asyncronous transfers\n",
+ ahc_name(ahc), target );
}
+ /*
+ * Ensure Ultra mode is set properly for
+ * this target.
+ */
+ ultra_enb_addr = ULTRA_ENB;
+ if(channel == 'B' || target > 7)
+ ultra_enb_addr++;
+ ultra_enb = AHC_INB(ahc, ultra_enb_addr);
+ sxfrctl0 = AHC_INB(ahc, SXFRCTL0);
+ if (*scsirate != 0 && ahc_syncrates[i].sxfr & ULTRA_SXFR) {
+ ultra_enb |= 0x01 << (target & 0x07);
+ sxfrctl0 |= ULTRAEN;
+ }
+ else {
+ ultra_enb &= ~(0x01 << (target & 0x07));
+ sxfrctl0 &= ~ULTRAEN;
+ }
+ AHC_OUTB(ahc, ultra_enb_addr, ultra_enb);
+ AHC_OUTB(ahc, SXFRCTL0, sxfrctl0);
}
-#if defined(__NetBSD__) || defined(__OpenBSD__)
+#if defined(__OpenBSD__)
+/* XXX we'll get rid of this soon */
+#define scsiprint ahcprint
+
int ahcprint __P((void *, const char *));
int
ahc->sc_link.fordriver = 0;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
ahc->sc_link.adapter_target = ahc->our_id;
+#ifndef __OpenBSD__
+ ahc->sc_link.channel = 0;
+#endif
#endif
ahc->sc_link.adapter_softc = ahc;
ahc->sc_link.adapter = &ahc_switch;
ahc->sc_link.opennings = 2;
ahc->sc_link.device = &ahc_dev;
+#ifdef __OpenBSD__
+ ahc->sc_link.flags = SCSIDEBUG_LEVEL;
+#else
ahc->sc_link.flags = DEBUGLEVEL;
+#endif
if(ahc->type & AHC_TWIN) {
/* Configure the second scsi bus */
ahc->sc_link_b.fordriver = (void *)SELBUSB;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
ahc->sc_link_b.adapter_target = ahc->our_id_b;
+#ifndef __OpenBSD__
+ ahc->sc_link_b.channel = 1;
+#endif
#endif
}
scsi_attachdevs(scbus);
scbus = NULL; /* Upper-level SCSI code owns this now */
}
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
+#elif defined(__NetBSD__) || defined (__OpenBSD__)
/*
* XXX - Update MI SCSI code
*
/* make IS_SCSIBUS_B() == false, while probing channel A */
ahc->sc_link_b.scsibus = 0xff;
+ config_found((void *)ahc, &ahc->sc_link, scsiprint);
if (ahc->type & AHC_TWIN)
- printf("%s: Probing channel A\n", ahc_name(ahc));
- config_found((void *)ahc, &ahc->sc_link, ahcprint);
- if (ahc->type & AHC_TWIN) {
- printf("%s: Probing channel B\n", ahc_name(ahc));
- config_found((void *)ahc, &ahc->sc_link_b, ahcprint);
- }
+ config_found((void *)ahc, &ahc->sc_link_b, scsiprint);
} else {
/*
* if implementation of IS_SCSIBUS_B() is changed to use
*/
/* assert(ahc->type & AHC_TWIN); */
- printf("%s: Probing channel B\n", ahc_name(ahc));
- config_found((void *)ahc, &ahc->sc_link_b, ahcprint);
- printf("%s: Probing channel A\n", ahc_name(ahc));
- config_found((void *)ahc, &ahc->sc_link, ahcprint);
+ config_found((void *)ahc, &ahc->sc_link_b, scsiprint);
+ config_found((void *)ahc, &ahc->sc_link, scsiprint);
}
#endif
return 1;
if(!(ahc->assigned_scbs.stqh_first || ahc->waiting_scbs.stqh_first))
return;
- PAUSE_SEQUENCER(ahc);
+ pause_sequencer(ahc);
cur_scb = AHC_INB(ahc, SCBPTR);
/*
}
/* Restore old position */
AHC_OUTB(ahc, SCBPTR, cur_scb);
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/FALSE);
}
/*
*/
#if defined(__FreeBSD__)
void
-#elif defined (__NetBSD__) || defined(__OpenBSD__)
+#elif defined (__NetBSD__) || defined (__OpenBSD__)
int
#endif
ahc_intr(arg)
(AHC_INB(ahc, SEQADDR1) << 8) |
AHC_INB(ahc, SEQADDR0));
}
- if (intstat & SEQINT) {
- u_short targ_mask;
- u_char target = (AHC_INB(ahc, SCSIID) >> 4) & 0x0f;
- u_char scratch_offset = target;
- char channel =
- AHC_INB(ahc, SBLKCTL) & SELBUSB ? 'B': 'A';
-
- if (channel == 'B')
- scratch_offset += 8;
- targ_mask = (0x01 << scratch_offset);
-
- switch (intstat & SEQINT_MASK) {
- case NO_MATCH:
- if(ahc->flags & AHC_PAGESCBS) {
- /* SCB Page-in request */
- u_char tag;
- u_char next;
- u_char disc_scb;
- struct scb *outscb;
- u_char arg_1 = AHC_INB(ahc, ARG_1);
+ if (intstat & SEQINT)
+ ahc_handle_seqint(ahc, intstat);
- /*
- * We should succeed, so set this now.
- * If we don't, and one of the methods
- * we use to aquire an SCB calls ahc_done,
- * we may wind up in our start routine
- * and unpause the adapter without giving
- * it the correct return value, which will
- * cause a hang.
- */
- AHC_OUTB(ahc, RETURN_1, SCB_PAGEDIN);
+ if (intstat & SCSIINT) {
- if(arg_1 == SCB_LIST_NULL) {
- /* Non-tagged command */
- int index = target |
- (channel == 'B' ? SELBUSB : 0);
- scb = ahc->pagedout_ntscbs[index];
- }
- else
- scb = ahc->scbarray[arg_1];
+ int scb_index = AHC_INB(ahc, SCB_TAG);
+ status = AHC_INB(ahc, SSTAT1);
+ scb = ahc->scbarray[scb_index];
+
+ if (status & SCSIRSTI) {
+ char channel;
+ channel = AHC_INB(ahc, SBLKCTL);
+ channel = channel & SELBUSB ? 'B' : 'A';
+ printf("%s: Someone reset channel %c\n",
+ ahc_name(ahc), channel);
+ ahc_reset_channel(ahc,
+ channel,
+ SCB_LIST_NULL,
+ XS_BUSY,
+ /* Initiate Reset */FALSE);
+ scb = NULL;
+ }
+ else if (!(scb && (scb->flags & SCB_ACTIVE))){
+ printf("%s: ahc_intr - referenced scb not "
+ "valid during scsiint 0x%x scb(%d)\n",
+ ahc_name(ahc), status, scb_index);
+ AHC_OUTB(ahc, CLRSINT1, status);
+ unpause_sequencer(ahc, /*unpause_always*/TRUE);
+ AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
+ scb = NULL;
+ }
+ else if (status & SCSIPERR) {
+ /*
+ * Determine the bus phase and
+ * queue an appropriate message
+ */
+ char *phase;
+ u_char mesg_out = MSG_NOOP;
+ u_char lastphase = AHC_INB(ahc, LASTPHASE);
+
+ xs = scb->xs;
+ sc_print_addr(xs->sc_link);
+
+ switch(lastphase) {
+ case P_DATAOUT:
+ phase = "Data-Out";
+ break;
+ case P_DATAIN:
+ phase = "Data-In";
+ mesg_out = MSG_INITIATOR_DET_ERR;
+ break;
+ case P_COMMAND:
+ phase = "Command";
+ break;
+ case P_MESGOUT:
+ phase = "Message-Out";
+ break;
+ case P_STATUS:
+ phase = "Status";
+ mesg_out = MSG_INITIATOR_DET_ERR;
+ break;
+ case P_MESGIN:
+ phase = "Message-In";
+ mesg_out = MSG_PARITY_ERROR;
+ break;
+ default:
+ phase = "unknown";
+ break;
+ }
+ printf("parity error during %s phase.\n", phase);
- if(!(scb->flags & SCB_PAGED_OUT))
- panic("%s: Request to page in a"
- "non paged out SCB.",
- ahc_name(ahc));
+ /*
+ * We've set the hardware to assert ATN if we
+ * get a parity error on "in" phases, so all we
+ * need to do is stuff the message buffer with
+ * the appropriate message. "In" phases have set
+ * mesg_out to something other than MSG_NOP.
+ */
+ if(mesg_out != MSG_NOOP) {
+ AHC_OUTB(ahc, MSG0, mesg_out);
+ AHC_OUTB(ahc, MSG_LEN, 1);
+ }
+ else
/*
- * Now to pick the SCB to page out.
- * Either take a free SCB, an assigned SCB,
- * an SCB that just completed, the first
- * one on the disconnected SCB list, or
- * as a last resort a queued SCB.
+ * Should we allow the target to make
+ * this decision for us?
*/
- if(ahc->free_scbs.stqh_first) {
- outscb = ahc->free_scbs.stqh_first;
- STAILQ_REMOVE_HEAD(&ahc->free_scbs,
- links);
- scb->position = outscb->position;
- outscb->position = SCB_LIST_NULL;
- STAILQ_INSERT_HEAD(&ahc->page_scbs,
- outscb, links);
- AHC_OUTB(ahc, SCBPTR, scb->position);
- ahc_send_scb(ahc, scb);
- scb->flags &= ~SCB_PAGED_OUT;
- goto pagein_done;
- }
- if(ahc->assigned_scbs.stqh_first) {
- outscb = ahc->assigned_scbs.stqh_first;
- STAILQ_REMOVE_HEAD(&ahc->assigned_scbs,
- links);
- outscb->flags ^= SCB_ASSIGNEDQ
- |SCB_WAITINGQ;
+ xs->error = XS_DRIVER_STUFFUP;
+ }
+ else if (status & SELTO) {
+ u_char waiting;
+ u_char flags;
+
+ xs = scb->xs;
+ xs->error = XS_SELTIMEOUT;
+ /*
+ * Clear any pending messages for the timed out
+ * target, and mark the target as free
+ */
+ flags = AHC_INB(ahc, FLAGS);
+ AHC_OUTB(ahc, MSG_LEN, 0);
+ ahc_unbusy_target(ahc, xs->sc_link->target,
+#if defined(__FreeBSD__)
+ ((long)xs->sc_link->fordriver & SELBUSB)
+#elif defined(__NetBSD__) || defined(__OpenBSD__)
+ IS_SCSIBUS_B(ahc, xs->sc_link)
+#endif
+ ? 'B' : 'A');
+ /* Stop the selection */
+ AHC_OUTB(ahc, SCSISEQ, 0);
+
+ AHC_OUTB(ahc, SCB_CONTROL, 0);
+
+ AHC_OUTB(ahc, CLRSINT1, CLRSELTIMEO);
+
+ AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
+
+ /* Shift the waiting for selection queue forward */
+ waiting = AHC_INB(ahc, WAITING_SCBH);
+ AHC_OUTB(ahc, SCBPTR, waiting);
+ waiting = AHC_INB(ahc, SCB_NEXT);
+ AHC_OUTB(ahc, WAITING_SCBH, waiting);
+
+ restart_sequencer(ahc);
+ }
+ else if (!(status & BUSFREE)) {
+ sc_print_addr(scb->xs->sc_link);
+ printf("Unknown SCSIINT. Status = 0x%x\n", status);
+ AHC_OUTB(ahc, CLRSINT1, status);
+ unpause_sequencer(ahc, /*unpause_always*/TRUE);
+ AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
+ scb = NULL;
+ }
+ if(scb != NULL) {
+ /* We want to process the command */
+ untimeout(ahc_timeout, (caddr_t)scb);
+ ahc_done(ahc, scb);
+ }
+ }
+ if (intstat & CMDCMPLT) {
+ int scb_index;
+
+ do {
+ scb_index = AHC_INB(ahc, QOUTFIFO);
+ scb = ahc->scbarray[scb_index];
+ if (!scb || !(scb->flags & SCB_ACTIVE)) {
+ printf("%s: WARNING "
+ "no command for scb %d (cmdcmplt)\n"
+ "QOUTCNT == %d\n",
+ ahc_name(ahc), scb_index,
+ AHC_INB(ahc, QOUTCNT));
+ AHC_OUTB(ahc, CLRINT, CLRCMDINT);
+ continue;
+ }
+ AHC_OUTB(ahc, CLRINT, CLRCMDINT);
+ untimeout(ahc_timeout, (caddr_t)scb);
+ ahc_done(ahc, scb);
+
+ } while (AHC_INB(ahc, QOUTCNT) & ahc->qcntmask);
+
+ ahc_run_waiting_queues(ahc);
+ }
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+ return 1;
+#endif
+}
+
+static void
+ahc_handle_seqint(ahc, intstat)
+ struct ahc_data *ahc;
+ u_int8_t intstat;
+{
+ struct scb *scb;
+ u_short targ_mask;
+ u_char target = (AHC_INB(ahc, SCSIID) >> 4) & 0x0f;
+ u_char scratch_offset = target;
+ char channel = AHC_INB(ahc, SBLKCTL) & SELBUSB ? 'B': 'A';
+
+ if (channel == 'B')
+ scratch_offset += 8;
+ targ_mask = (0x01 << scratch_offset);
+
+ switch (intstat & SEQINT_MASK) {
+ case NO_MATCH:
+ if (ahc->flags & AHC_PAGESCBS) {
+ /* SCB Page-in request */
+ u_char tag;
+ u_char next;
+ u_char disc_scb;
+ struct scb *outscb;
+ u_char arg_1 = AHC_INB(ahc, ARG_1);
+
+ /*
+ * We should succeed, so set this now.
+ * If we don't, and one of the methods
+ * we use to aquire an SCB calls ahc_done,
+ * we may wind up in our start routine
+ * and unpause the adapter without giving
+ * it the correct return value, which will
+ * cause a hang.
+ */
+ AHC_OUTB(ahc, RETURN_1, SCB_PAGEDIN);
+
+ if (arg_1 == SCB_LIST_NULL) {
+ /* Non-tagged command */
+ int index;
+
+ index = target|(channel == 'B' ? SELBUSB : 0);
+ scb = ahc->pagedout_ntscbs[index];
+ } else
+ scb = ahc->scbarray[arg_1];
+
+ if (!(scb->flags & SCB_PAGED_OUT))
+ panic("%s: Request to page in a non paged out "
+ "SCB.", ahc_name(ahc));
+ /*
+ * Now to pick the SCB to page out.
+ * Either take a free SCB, an assigned SCB,
+ * an SCB that just completed, the first
+ * one on the disconnected SCB list, or
+ * as a last resort a queued SCB.
+ */
+ if (ahc->free_scbs.stqh_first) {
+ outscb = ahc->free_scbs.stqh_first;
+ STAILQ_REMOVE_HEAD(&ahc->free_scbs, links);
+ scb->position = outscb->position;
+ outscb->position = SCB_LIST_NULL;
+ STAILQ_INSERT_HEAD(&ahc->page_scbs, outscb,
+ links);
+ AHC_OUTB(ahc, SCBPTR, scb->position);
+ ahc_send_scb(ahc, scb);
+ scb->flags &= ~SCB_PAGED_OUT;
+ goto pagein_done;
+ }
+ if (intstat & CMDCMPLT) {
+ int scb_index;
+
+ AHC_OUTB(ahc, CLRINT, CLRCMDINT);
+ scb_index = AHC_INB(ahc, QOUTFIFO);
+ if (!(AHC_INB(ahc, QOUTCNT) & ahc->qcntmask))
+ intstat &= ~CMDCMPLT;
+
+ outscb = ahc->scbarray[scb_index];
+ if (!outscb || !(outscb->flags & SCB_ACTIVE)) {
+ printf("%s: WARNING no command for "
+ "scb %d (cmdcmplt)\n",
+ ahc_name(ahc),
+ scb_index);
+ /*
+ * Fall through in hopes of finding
+ * another SCB
+ */
+ } else {
scb->position = outscb->position;
outscb->position = SCB_LIST_NULL;
- STAILQ_INSERT_HEAD(&ahc->waiting_scbs,
- outscb, links);
AHC_OUTB(ahc, SCBPTR, scb->position);
ahc_send_scb(ahc, scb);
scb->flags &= ~SCB_PAGED_OUT;
+ untimeout(ahc_timeout,
+ (caddr_t)outscb);
+ ahc_done(ahc, outscb);
goto pagein_done;
}
- if(intstat & CMDCMPLT) {
- int scb_index;
-
- AHC_OUTB(ahc, CLRINT, CLRCMDINT);
- scb_index = AHC_INB(ahc, QOUTFIFO);
- if(!(AHC_INB(ahc, QOUTCNT) & ahc->qcntmask))
- intstat &= ~CMDCMPLT;
-
- outscb = ahc->scbarray[scb_index];
- if (!outscb || !(outscb->flags & SCB_ACTIVE)) {
- printf("%s: WARNING "
- "no command for scb %d (cmdcmplt)\n",
- ahc_name(ahc),
- scb_index);
- /* Fall through in hopes of finding another SCB */
- }
- else {
- scb->position = outscb->position;
- outscb->position = SCB_LIST_NULL;
- AHC_OUTB(ahc, SCBPTR, scb->position);
- ahc_send_scb(ahc, scb);
- scb->flags &= ~SCB_PAGED_OUT;
- untimeout(ahc_timeout, (caddr_t)outscb);
- ahc_done(ahc, outscb);
- goto pagein_done;
- }
- }
- disc_scb = AHC_INB(ahc, DISCONNECTED_SCBH);
- if(disc_scb != SCB_LIST_NULL) {
- AHC_OUTB(ahc, SCBPTR, disc_scb);
- tag = AHC_INB(ahc, SCB_TAG);
- outscb = ahc->scbarray[tag];
- next = AHC_INB(ahc, SCB_NEXT);
- if(next != SCB_LIST_NULL) {
- AHC_OUTB(ahc, SCBPTR, next);
- AHC_OUTB(ahc, SCB_PREV,
- SCB_LIST_NULL);
- AHC_OUTB(ahc, SCBPTR, disc_scb);
- }
- AHC_OUTB(ahc, DISCONNECTED_SCBH, next);
- ahc_page_scb(ahc, outscb, scb);
- }
- else if(AHC_INB(ahc, QINCNT) & ahc->qcntmask) {
- /* Pull one of our queued commands as a last resort */
- disc_scb = AHC_INB(ahc, QINFIFO);
- AHC_OUTB(ahc, SCBPTR, disc_scb);
- tag = AHC_INB(ahc, SCB_TAG);
- outscb = ahc->scbarray[tag];
- if((outscb->control & 0x23) != TAG_ENB) {
- /*
- * This is not a simple tagged command
- * so its position in the queue
- * matters. Take the command at the
- * end of the queue instead.
- */
- int i;
- u_char saved_queue[AHC_SCB_MAX];
- u_char queued = AHC_INB(ahc, QINCNT) & ahc->qcntmask;
-
- /* Count the command we removed already */
- saved_queue[0] = disc_scb;
- queued++;
-
- /* Empty the input queue */
- for (i = 1; i < queued; i++)
- saved_queue[i] = AHC_INB(ahc, QINFIFO);
-
- /* Put everyone back put the last entry */
- queued--;
- for (i = 0; i < queued; i++)
- AHC_OUTB(ahc, QINFIFO, saved_queue[i]);
-
- AHC_OUTB(ahc, SCBPTR, saved_queue[queued]);
- tag = AHC_INB(ahc, SCB_TAG);
- outscb = ahc->scbarray[tag];
- }
- untimeout(ahc_timeout, (caddr_t)outscb);
- scb->position = outscb->position;
- outscb->position = SCB_LIST_NULL;
- STAILQ_INSERT_HEAD(&ahc->waiting_scbs,
- outscb, links);
- outscb->flags |= SCB_WAITINGQ;
- ahc_send_scb(ahc, scb);
- scb->flags &= ~SCB_PAGED_OUT;
- }
- else {
- panic("Page-in request with no candidates");
- AHC_OUTB(ahc, RETURN_1, 0);
- }
-pagein_done:
- }
- else {
- printf("%s:%c:%d: no active SCB for "
- "reconnecting target - "
- "issuing ABORT\n",
- ahc_name(ahc), channel, target);
- printf("SAVED_TCL == 0x%x\n",
- AHC_INB(ahc, SAVED_TCL));
- ahc_unbusy_target(ahc, target, channel);
- AHC_OUTB(ahc, SCB_CONTROL, 0);
- AHC_OUTB(ahc, CLRSINT1, CLRSELTIMEO);
- AHC_OUTB(ahc, RETURN_1, 0);
- }
- break;
- case SEND_REJECT:
- {
- u_char rejbyte = AHC_INB(ahc, REJBYTE);
- if(( rejbyte & 0xf0) == 0x20) {
- /* Tagged Message */
- printf("\n%s:%c:%d: Tagged message "
- "received without identify. "
- "Disabling tagged commands "
- "for this target.\n",
- ahc_name(ahc),
- channel, target);
- ahc->tagenable &= ~targ_mask;
- }
- else
- printf("%s:%c:%d: Warning - "
- "unknown message recieved from "
- "target (0x%x - 0x%x). Rejecting\n",
- ahc_name(ahc), channel, target,
- rejbyte,
- AHC_INB(ahc, REJBYTE_EXT));
- break;
}
- case NO_IDENT:
- panic("%s:%c:%d: Target did not send an IDENTIFY "
- "message. SAVED_TCL == 0x%x\n",
- ahc_name(ahc), channel, target,
- AHC_INB(ahc, SAVED_TCL));
- break;
- case BAD_PHASE:
- printf("%s:%c:%d: unknown scsi bus phase. "
- "Attempting to continue\n",
- ahc_name(ahc), channel, target);
- break;
- case SDTR_MSG:
- {
- short period;
- u_char offset, rate;
- u_char targ_scratch;
- u_char maxoffset;
- /*
- * Help the sequencer to translate the
- * negotiated transfer rate. Transfer is
- * 1/4 the period in ns as is returned by
- * the sync negotiation message. So, we must
- * multiply by four
- */
- period = AHC_INB(ahc, ARG_1) << 2;
- offset = AHC_INB(ahc, ACCUM);
- targ_scratch = AHC_INB(ahc, TARG_SCRATCH
- + scratch_offset);
- if(targ_scratch & WIDEXFER)
- maxoffset = 0x08;
- else
- maxoffset = 0x0f;
- ahc_scsirate(ahc, &rate, period,
- MIN(offset, maxoffset),
- channel, target);
- /* Preserve the WideXfer flag */
- targ_scratch = rate | (targ_scratch & WIDEXFER);
- AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset,
- targ_scratch);
- AHC_OUTB(ahc, SCSIRATE, targ_scratch);
- if( (targ_scratch & 0x0f) == 0 )
- {
- /*
- * The requested rate was so low
- * that asyncronous transfers are
- * faster (not to mention the
- * controller won't support them),
- * so we issue a message reject to
- * ensure we go to asyncronous
- * transfers.
- */
- AHC_OUTB(ahc, RETURN_1, SEND_REJ);
- }
- /* See if we initiated Sync Negotiation */
- else if(ahc->sdtrpending & targ_mask)
- {
- /*
- * Don't send an SDTR back to
- * the target
- */
- AHC_OUTB(ahc, RETURN_1, 0);
- }
- else{
- /*
- * Send our own SDTR in reply
- */
-#ifdef AHC_DEBUG
- if(ahc_debug & AHC_SHOWMISC)
- printf("Sending SDTR!!\n");
-#endif
- AHC_OUTB(ahc, RETURN_1, SEND_SDTR);
+ disc_scb = AHC_INB(ahc, DISCONNECTED_SCBH);
+ if (disc_scb != SCB_LIST_NULL) {
+ AHC_OUTB(ahc, SCBPTR, disc_scb);
+ tag = AHC_INB(ahc, SCB_TAG);
+ outscb = ahc->scbarray[tag];
+ next = AHC_INB(ahc, SCB_NEXT);
+ if (next != SCB_LIST_NULL) {
+ AHC_OUTB(ahc, SCBPTR, next);
+ AHC_OUTB(ahc, SCB_PREV,
+ SCB_LIST_NULL);
+ AHC_OUTB(ahc, SCBPTR, disc_scb);
}
+ AHC_OUTB(ahc, DISCONNECTED_SCBH, next);
+ ahc_page_scb(ahc, outscb, scb);
+ } else if (AHC_INB(ahc, QINCNT) & ahc->qcntmask) {
/*
- * Negate the flags
+ * Pull one of our queued commands
+ * as a last resort
*/
- ahc->needsdtr &= ~targ_mask;
- ahc->sdtrpending &= ~targ_mask;
- break;
- }
- case WDTR_MSG:
- {
- u_char scratch, bus_width;
-
- bus_width = AHC_INB(ahc, ARG_1);
-
- scratch = AHC_INB(ahc, TARG_SCRATCH
- + scratch_offset);
-
- if(ahc->wdtrpending & targ_mask)
- {
- /*
- * Don't send a WDTR back to the
- * target, since we asked first.
- */
- AHC_OUTB(ahc, RETURN_1, 0);
- switch(bus_width)
- {
- case BUS_8_BIT:
- scratch &= 0x7f;
- break;
- case BUS_16_BIT:
- if(bootverbose)
- printf("%s: target "
- "%d using 16Bit "
- "transfers\n",
- ahc_name(ahc),
- target);
- scratch |= 0x80;
- break;
- case BUS_32_BIT:
- /*
- * How can we do 32bit
- * transfers on a 16bit
- * bus?
- */
- AHC_OUTB(ahc, RETURN_1,
- SEND_REJ);
- printf("%s: target "
- "%d requested 32Bit "
- "transfers. "
- "Rejecting...\n",
- ahc_name(ahc),
- target);
- break;
- default:
- break;
- }
- }
- else {
+ disc_scb = AHC_INB(ahc, QINFIFO);
+ AHC_OUTB(ahc, SCBPTR, disc_scb);
+ tag = AHC_INB(ahc, SCB_TAG);
+ outscb = ahc->scbarray[tag];
+ if ((outscb->control & 0x23) != TAG_ENB) {
/*
- * Send our own WDTR in reply
+ * This is not a simple tagged command
+ * so its position in the queue
+ * matters. Take the command at the
+ * end of the queue instead.
*/
- switch(bus_width)
- {
- case BUS_8_BIT:
- scratch &= 0x7f;
- break;
- case BUS_32_BIT:
- case BUS_16_BIT:
- if(ahc->type & AHC_WIDE) {
- /* Negotiate 16_BITS */
- bus_width = BUS_16_BIT;
- if(bootverbose)
- printf("%s: "
- "target %d "
- "using 16Bit "
- "transfers\n",
- ahc_name(ahc),
- target);
- scratch |= 0x80;
- }
- else
- bus_width = BUS_8_BIT;
- break;
- default:
- break;
- }
- AHC_OUTB(ahc, RETURN_1,
- bus_width | SEND_WDTR);
- }
- ahc->needwdtr &= ~targ_mask;
- ahc->wdtrpending &= ~targ_mask;
- AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset,
- scratch);
- AHC_OUTB(ahc, SCSIRATE, scratch);
- break;
- }
- case REJECT_MSG:
- {
- /*
- * What we care about here is if we had an
- * outstanding SDTR or WDTR message for this
- * target. If we did, this is a signal that
- * the target is refusing negotiation.
- */
+ int i;
+ u_char saved_queue[AHC_SCB_MAX];
+ u_char queued = AHC_INB(ahc, QINCNT)
+ & ahc->qcntmask;
- u_char targ_scratch;
-
- targ_scratch = AHC_INB(ahc, TARG_SCRATCH
- + scratch_offset);
-
- if(ahc->wdtrpending & targ_mask){
- /* note 8bit xfers and clear flag */
- targ_scratch &= 0x7f;
- ahc->needwdtr &= ~targ_mask;
- ahc->wdtrpending &= ~targ_mask;
- printf("%s:%c:%d: refuses "
- "WIDE negotiation. Using "
- "8bit transfers\n",
- ahc_name(ahc),
- channel, target);
- }
- else if(ahc->sdtrpending & targ_mask){
- /* note asynch xfers and clear flag */
- targ_scratch &= 0xf0;
- ahc->needsdtr &= ~targ_mask;
- ahc->sdtrpending &= ~targ_mask;
- printf("%s:%c:%d: refuses "
- "syncronous negotiation. Using "
- "asyncronous transfers\n",
- ahc_name(ahc),
- channel, target);
- }
- else {
/*
- * Otherwise, we ignore it.
+ * Count the command we removed
+ * already
*/
-#ifdef AHC_DEBUG
- if(ahc_debug & AHC_SHOWMISC)
- printf("%s:%c:%d: Message "
- "reject -- ignored\n",
- ahc_name(ahc),
- channel, target);
-#endif
- break;
- }
- AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset,
- targ_scratch);
- AHC_OUTB(ahc, SCSIRATE, targ_scratch);
- break;
- }
- case BAD_STATUS:
- {
- int scb_index;
-
- /* The sequencer will notify us when a command
- * has an error that would be of interest to
- * the kernel. This allows us to leave the sequencer
- * running in the common case of command completes
- * without error.
- */
-
- scb_index = AHC_INB(ahc, SCB_TAG);
- scb = ahc->scbarray[scb_index];
-
- /*
- * Set the default return value to 0 (don't
- * send sense). The sense code will change
- * this if needed and this reduces code
- * duplication.
- */
- AHC_OUTB(ahc, RETURN_1, 0);
- if (!(scb && (scb->flags & SCB_ACTIVE))) {
- printf("%s:%c:%d: ahc_intr - referenced scb "
- "not valid during seqint 0x%x scb(%d)\n",
- ahc_name(ahc),
- channel, target, intstat,
- scb_index);
- goto clear;
- }
-
- xs = scb->xs;
-
- scb->status = AHC_INB(ahc, SCB_TARGET_STATUS);
+ saved_queue[0] = disc_scb;
+ queued++;
-#ifdef AHC_DEBUG
- if((ahc_debug & AHC_SHOWSCBS)
- && xs->sc_link->target == DEBUGTARG)
- ahc_print_scb(scb);
-#endif
- xs->status = scb->status;
- switch(scb->status){
- case SCSI_OK:
- printf("%s: Interrupted for staus of"
- " 0???\n", ahc_name(ahc));
- break;
- case SCSI_CHECK:
-#ifdef AHC_DEBUG
- if(ahc_debug & AHC_SHOWSENSE)
- {
- sc_print_addr(xs->sc_link);
- printf("requests Check Status\n");
- }
-#endif
+ /* Empty the input queue */
+ for (i = 1; i < queued; i++)
+ saved_queue[i] = AHC_INB(ahc, QINFIFO);
- if((xs->error == XS_NOERROR) &&
- !(scb->flags & SCB_SENSE)) {
- struct ahc_dma_seg *sg = scb->ahc_dma;
- struct scsi_sense *sc = &(scb->sense_cmd);
-#ifdef AHC_DEBUG
- if(ahc_debug & AHC_SHOWSENSE)
- {
- sc_print_addr(xs->sc_link);
- printf("Sending Sense\n");
- }
-#endif
-#if defined(__FreeBSD__)
- sc->op_code = REQUEST_SENSE;
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
- sc->opcode = REQUEST_SENSE;
-#endif
- sc->byte2 = xs->sc_link->lun << 5;
- sc->length = sizeof(struct scsi_sense_data);
- sc->control = 0;
-
- sg->addr = KVTOPHYS(&xs->sense);
- sg->len = sizeof(struct scsi_sense_data);
-
- scb->control &= DISCENB;
- scb->status = 0;
- scb->SG_segment_count = 1;
- scb->SG_list_pointer = KVTOPHYS(sg);
- scb->data = sg->addr;
- scb->datalen = sg->len;
-#ifdef AHC_BROKEN_CACHE
- if (ahc_broken_cache)
- INVALIDATE_CACHE();
-#endif
- scb->cmdpointer = KVTOPHYS(sc);
- scb->cmdlen = sizeof(*sc);
-
- scb->flags |= SCB_SENSE;
- ahc_send_scb(ahc, scb);
/*
- * Ensure that the target is "BUSY"
- * so we don't get overlapping
- * commands if we happen to be doing
- * tagged I/O.
+ * Put everyone back but the
+ * last entry
*/
- ahc_busy_target(ahc, target, channel);
+ queued--;
+ for (i = 0; i < queued; i++)
+ AHC_OUTB(ahc, QINFIFO,
+ saved_queue[i]);
- /*
- * Make us the next command to run
- */
- ahc_add_waiting_scb(ahc, scb);
- AHC_OUTB(ahc, RETURN_1, SEND_SENSE);
- break;
- }
- /*
- * Clear the SCB_SENSE Flag and have
- * the sequencer do a normal command
- * complete with either a "DRIVER_STUFFUP"
- * error or whatever other error condition
- * we already had.
- */
- scb->flags &= ~SCB_SENSE;
- if(xs->error == XS_NOERROR)
- xs->error = XS_DRIVER_STUFFUP;
- break;
- case SCSI_BUSY:
- xs->error = XS_BUSY;
- sc_print_addr(xs->sc_link);
- printf("Target Busy\n");
- break;
- case SCSI_QUEUE_FULL:
- /*
- * The upper level SCSI code will someday
- * handle this properly.
- */
- sc_print_addr(xs->sc_link);
- printf("Queue Full\n");
- scb->flags |= SCB_ASSIGNEDQ;
- STAILQ_INSERT_TAIL(&ahc->assigned_scbs,
- scb, links);
- break;
- default:
- sc_print_addr(xs->sc_link);
- printf("unexpected targ_status: %x\n",
- scb->status);
- xs->error = XS_DRIVER_STUFFUP;
+ AHC_OUTB(ahc, SCBPTR,
+ saved_queue[queued]);
+ tag = AHC_INB(ahc, SCB_TAG);
+ outscb = ahc->scbarray[tag];
+ }
+ untimeout(ahc_timeout, (caddr_t)outscb);
+ scb->position = outscb->position;
+ outscb->position = SCB_LIST_NULL;
+ STAILQ_INSERT_HEAD(&ahc->waiting_scbs,
+ outscb, links);
+ outscb->flags |= SCB_WAITINGQ;
+ ahc_send_scb(ahc, scb);
+ scb->flags &= ~SCB_PAGED_OUT;
+ }
+ else {
+ panic("Page-in request with no candidates");
+ AHC_OUTB(ahc, RETURN_1, 0);
+ }
+ pagein_done:
+ } else {
+ printf("%s:%c:%d: no active SCB for reconnecting "
+ "target - issuing ABORT\n",
+ ahc_name(ahc), channel, target);
+ printf("SAVED_TCL == 0x%x\n",
+ AHC_INB(ahc, SAVED_TCL));
+ ahc_unbusy_target(ahc, target, channel);
+ AHC_OUTB(ahc, SCB_CONTROL, 0);
+ AHC_OUTB(ahc, CLRSINT1, CLRSELTIMEO);
+ AHC_OUTB(ahc, RETURN_1, 0);
+ }
+ break;
+ case SEND_REJECT:
+ {
+ u_char rejbyte = AHC_INB(ahc, REJBYTE);
+ printf("%s:%c:%d: Warning - unknown message recieved from "
+ "target (0x%x). Rejecting\n",
+ ahc_name(ahc), channel, target, rejbyte);
+ break;
+ }
+ case NO_IDENT:
+ panic("%s:%c:%d: Target did not send an IDENTIFY message. "
+ "SAVED_TCL == 0x%x\n",
+ ahc_name(ahc), channel, target,
+ AHC_INB(ahc, SAVED_TCL));
+ break;
+ case BAD_PHASE:
+ printf("%s:%c:%d: unknown scsi bus phase. Attempting to "
+ "continue\n", ahc_name(ahc), channel, target);
+ break;
+ case EXTENDED_MSG:
+ {
+ u_int8_t message_length;
+ u_int8_t message_code;
+
+ message_length = AHC_INB(ahc, MSGIN_EXT_LEN);
+ message_code = AHC_INB(ahc, MSGIN_EXT_OPCODE);
+ switch(message_code) {
+ case MSG_EXT_SDTR:
+ {
+ u_int8_t period;
+ u_int8_t offset;
+ u_int8_t saved_offset;
+ u_int8_t targ_scratch;
+ u_int8_t maxoffset;
+ u_int8_t rate;
+
+ if (message_length != MSG_EXT_SDTR_LEN) {
+ AHC_OUTB(ahc, RETURN_1, SEND_REJ);
+ ahc->sdtrpending &= ~targ_mask;
break;
}
- break;
- }
- case RESIDUAL:
- {
- int scb_index;
- scb_index = AHC_INB(ahc, SCB_TAG);
- scb = ahc->scbarray[scb_index];
- xs = scb->xs;
+ period = AHC_INB(ahc, MSGIN_EXT_BYTE0);
+ saved_offset = AHC_INB(ahc, MSGIN_EXT_BYTE1);
+ targ_scratch = AHC_INB(ahc, TARG_SCRATCH
+ + scratch_offset);
+ if (targ_scratch & WIDEXFER)
+ maxoffset = MAX_OFFSET_16BIT;
+ else
+ maxoffset = MAX_OFFSET_8BIT;
+ offset = MIN(saved_offset, maxoffset);
+ ahc_scsirate(ahc, &rate, &period, &offset,
+ channel, target);
+ /* Preserve the WideXfer flag */
+ targ_scratch = rate | (targ_scratch & WIDEXFER);
+
/*
- * Don't clobber valid resid info with
- * a resid coming from a check sense
- * operation.
+ * Update both the target scratch area and the
+ * current SCSIRATE.
*/
- if(!(scb->flags & SCB_SENSE)) {
- int resid_sgs;
+ AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset,
+ targ_scratch);
+ AHC_OUTB(ahc, SCSIRATE, targ_scratch);
+ /*
+ * See if we initiated Sync Negotiation
+ * and didn't have to fall down to async
+ * transfers.
+ */
+ if ((ahc->sdtrpending & targ_mask) != 0
+ && (saved_offset == offset)) {
/*
- * Remainder of the SG where the transfer
- * stopped.
+ * Don't send an SDTR back to
+ * the target
*/
- xs->resid =
- (AHC_INB(ahc, SCB_RESID_DCNT2)<<16) |
- (AHC_INB(ahc, SCB_RESID_DCNT1)<<8) |
- AHC_INB(ahc, SCB_RESID_DCNT0);
-
+ AHC_OUTB(ahc, RETURN_1, 0);
+ ahc->needsdtr &= ~targ_mask;
+ ahc->sdtrpending &= ~targ_mask;
+ } else {
/*
- * Add up the contents of all residual
- * SG segments that are after the SG where
- * the transfer stopped.
+ * Send our own SDTR in reply
*/
- resid_sgs = AHC_INB(ahc, SCB_RESID_SGCNT) - 1;
- while(resid_sgs > 0) {
- int sg;
-
- sg = scb->SG_segment_count - resid_sgs;
- xs->resid += scb->ahc_dma[sg].len;
- resid_sgs--;
- }
-
-#if defined(__FreeBSD__)
- xs->flags |= SCSI_RESID_VALID;
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
- /* XXX - Update to do this right */
-#endif
#ifdef AHC_DEBUG
- if(ahc_debug & AHC_SHOWMISC) {
- sc_print_addr(xs->sc_link);
- printf("Handled Residual of %ld bytes\n"
- ,xs->resid);
- }
+ if(ahc_debug & AHC_SHOWMISC)
+ printf("Sending SDTR!!\n");
#endif
- }
- break;
- }
- case ABORT_TAG:
- {
- int scb_index;
- scb_index = AHC_INB(ahc, SCB_TAG);
- scb = ahc->scbarray[scb_index];
- xs = scb->xs;
- /*
- * We didn't recieve a valid tag back from
- * the target on a reconnect.
- */
- sc_print_addr(xs->sc_link);
- printf("invalid tag recieved -- sending ABORT_TAG\n");
- xs->error = XS_DRIVER_STUFFUP;
- untimeout(ahc_timeout, (caddr_t)scb);
- ahc_done(ahc, scb);
- break;
- }
- case AWAITING_MSG:
- {
- int scb_index;
- scb_index = AHC_INB(ahc, SCB_TAG);
- scb = ahc->scbarray[scb_index];
- /*
- * This SCB had a zero length command, informing
- * the sequencer that we wanted to send a special
- * message to this target. We only do this for
- * BUS_DEVICE_RESET messages currently.
- */
- if(scb->flags & SCB_DEVICE_RESET)
- {
- AHC_OUTB(ahc, MSG0,
- MSG_BUS_DEVICE_RESET);
- AHC_OUTB(ahc, MSG_LEN, 1);
- printf("Bus Device Reset Message Sent\n");
- }
- else
- panic("ahc_intr: AWAITING_MSG for an SCB that "
- "does not have a waiting message");
- break;
- }
- case IMMEDDONE:
- {
- /*
- * Take care of device reset messages
- */
- u_char scbindex = AHC_INB(ahc, SCB_TAG);
- scb = ahc->scbarray[scbindex];
- if(scb->flags & SCB_DEVICE_RESET) {
- u_char targ_scratch;
- int found;
+ ahc_construct_sdtr(ahc, /*start_byte*/0,
+ period, offset);
+ AHC_OUTB(ahc, RETURN_1, SEND_MSG);
+
/*
- * Go back to async/narrow transfers and
- * renegotiate.
+ * If we aren't starting a re-negotiation
+ * because we had to go async in response
+ * to a "too low" response from the target
+ * clear the needsdtr flag for this target.
*/
- ahc_unbusy_target(ahc, target, channel);
- ahc->needsdtr |= ahc->needsdtr_orig & targ_mask;
- ahc->needwdtr |= ahc->needwdtr_orig & targ_mask;
- ahc->sdtrpending &= ~targ_mask;
- ahc->wdtrpending &= ~targ_mask;
- targ_scratch = AHC_INB(ahc, TARG_SCRATCH
- + scratch_offset);
- targ_scratch &= SXFR;
- AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset,
- targ_scratch);
- found = ahc_reset_device(ahc, target,
- channel, SCB_LIST_NULL,
- XS_NOERROR);
- sc_print_addr(scb->xs->sc_link);
- printf("Bus Device Reset delivered. "
- "%d SCBs aborted\n", found);
- ahc->in_timeout = FALSE;
- ahc_run_done_queue(ahc);
+ if ((ahc->sdtrpending & targ_mask) == 0)
+ ahc->needsdtr &= ~targ_mask;
+ else
+ ahc->sdtrpending |= targ_mask;
}
- else
- panic("ahc_intr: Immediate complete for "
- "unknown operation.");
- break;
- }
- case DATA_OVERRUN:
- {
- /*
- * When the sequencer detects an overrun, it
- * sets STCNT to 0x00ffffff and allows the
- * target to complete its transfer in
- * BITBUCKET mode.
- */
- u_char scbindex = AHC_INB(ahc, SCB_TAG);
- u_int32_t overrun;
- scb = ahc->scbarray[scbindex];
- overrun = AHC_INB(ahc, STCNT0)
- | (AHC_INB(ahc, STCNT1) << 8)
- | (AHC_INB(ahc, STCNT2) << 16);
- overrun = 0x00ffffff - overrun;
- sc_print_addr(scb->xs->sc_link);
- printf("data overrun of %d bytes detected."
- " Forcing a retry.\n", overrun);
- /*
- * Set this and it will take affect when the
- * target does a command complete.
- */
- scb->xs->error = XS_DRIVER_STUFFUP;
- break;
- }
-#if NOT_YET
- /* XXX Fill these in later */
- case MESG_BUFFER_BUSY:
- break;
- case MSGIN_PHASEMIS:
- break;
-#endif
- default:
- printf("ahc_intr: seqint, "
- "intstat == 0x%x, scsisigi = 0x%x\n",
- intstat, AHC_INB(ahc, SCSISIGI));
break;
}
-clear:
- /*
- * Clear the upper byte that holds SEQINT status
- * codes and clear the SEQINT bit.
- */
- AHC_OUTB(ahc, CLRINT, CLRSEQINT);
-
- /*
- * The sequencer is paused immediately on
- * a SEQINT, so we should restart it when
- * we leave this section.
- */
- UNPAUSE_SEQUENCER(ahc);
- }
-
-
- if (intstat & SCSIINT) {
-
- int scb_index = AHC_INB(ahc, SCB_TAG);
- status = AHC_INB(ahc, SSTAT1);
- scb = ahc->scbarray[scb_index];
-
- if (status & SCSIRSTI) {
- char channel;
- channel = AHC_INB(ahc, SBLKCTL);
- channel = channel & SELBUSB ? 'B' : 'A';
- printf("%s: Someone reset channel %c\n",
- ahc_name(ahc), channel);
- ahc_reset_channel(ahc,
- channel,
- SCB_LIST_NULL,
- XS_BUSY,
- /* Initiate Reset */FALSE);
- scb = NULL;
- }
- else if (!(scb && (scb->flags & SCB_ACTIVE))){
- printf("%s: ahc_intr - referenced scb not "
- "valid during scsiint 0x%x scb(%d)\n",
- ahc_name(ahc), status, scb_index);
- AHC_OUTB(ahc, CLRSINT1, status);
- UNPAUSE_SEQUENCER(ahc);
- AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
- scb = NULL;
- }
- else if (status & SCSIPERR) {
- /*
- * Determine the bus phase and
- * queue an appropriate message
- */
- char *phase;
- u_char mesg_out = MSG_NOP;
- u_char lastphase = AHC_INB(ahc, LASTPHASE);
+ case MSG_EXT_WDTR:
+ {
+ u_int8_t scratch, bus_width;
- xs = scb->xs;
- sc_print_addr(xs->sc_link);
+ if (message_length != MSG_EXT_WDTR_LEN) {
+ AHC_OUTB(ahc, RETURN_1, SEND_REJ);
+ ahc->wdtrpending &= ~targ_mask;
+ break;
+ }
- switch(lastphase) {
- case P_DATAOUT:
- phase = "Data-Out";
+ bus_width = AHC_INB(ahc, MSGIN_EXT_BYTE0);
+ scratch = AHC_INB(ahc, TARG_SCRATCH
+ + scratch_offset);
+
+ if (ahc->wdtrpending & targ_mask) {
+ /*
+ * Don't send a WDTR back to the
+ * target, since we asked first.
+ */
+ AHC_OUTB(ahc, RETURN_1, 0);
+ switch(bus_width){
+ case BUS_8_BIT:
+ scratch &= 0x7f;
break;
- case P_DATAIN:
- phase = "Data-In";
- mesg_out = MSG_INITIATOR_DET_ERROR;
+ case BUS_16_BIT:
+ if(bootverbose)
+ printf("%s: target %d using "
+ "16Bit transfers\n",
+ ahc_name(ahc), target);
+ scratch |= WIDEXFER;
break;
- case P_COMMAND:
- phase = "Command";
+ case BUS_32_BIT:
+ /*
+ * How can we do 32bit transfers
+ * on a 16bit bus?
+ */
+ AHC_OUTB(ahc, RETURN_1, SEND_REJ);
+ printf("%s: target %d requested 32Bit "
+ "transfers. Rejecting...\n",
+ ahc_name(ahc), target);
break;
- case P_MESGOUT:
- phase = "Message-Out";
+ default:
break;
- case P_STATUS:
- phase = "Status";
- mesg_out = MSG_INITIATOR_DET_ERROR;
+ }
+ } else {
+ /*
+ * Send our own WDTR in reply
+ */
+ switch(bus_width) {
+ case BUS_8_BIT:
+ scratch &= 0x7f;
break;
- case P_MESGIN:
- phase = "Message-In";
- mesg_out = MSG_MSG_PARITY_ERROR;
+ case BUS_32_BIT:
+ case BUS_16_BIT:
+ if(ahc->type & AHC_WIDE) {
+ /* Negotiate 16_BITS */
+ bus_width = BUS_16_BIT;
+ if(bootverbose)
+ printf("%s: target %d "
+ "using 16Bit "
+ "transfers\n",
+ ahc_name(ahc),
+ target);
+ scratch |= WIDEXFER;
+ } else
+ bus_width = BUS_8_BIT;
break;
default:
- phase = "unknown";
break;
+ }
+ ahc_construct_wdtr(ahc, /*start_byte*/0,
+ bus_width);
+ AHC_OUTB(ahc, RETURN_1, SEND_MSG);
}
- printf("parity error during %s phase.\n", phase);
+
+ ahc->needwdtr &= ~targ_mask;
+ ahc->wdtrpending &= ~targ_mask;
+ AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset, scratch);
+ AHC_OUTB(ahc, SCSIRATE, scratch);
+ break;
+ }
+ default:
+ /* Unknown extended message. Reject it. */
+ AHC_OUTB(ahc, RETURN_1, SEND_REJ);
+ }
+ }
+ case REJECT_MSG:
+ {
+ /*
+ * What we care about here is if we had an
+ * outstanding SDTR or WDTR message for this
+ * target. If we did, this is a signal that
+ * the target is refusing negotiation.
+ */
+
+ u_char targ_scratch;
+ targ_scratch = AHC_INB(ahc, TARG_SCRATCH
+ + scratch_offset);
+
+ if (ahc->wdtrpending & targ_mask){
+ /* note 8bit xfers and clear flag */
+ targ_scratch &= 0x7f;
+ ahc->needwdtr &= ~targ_mask;
+ ahc->wdtrpending &= ~targ_mask;
+ printf("%s:%c:%d: refuses WIDE negotiation. Using "
+ "8bit transfers\n", ahc_name(ahc),
+ channel, target);
+ } else if(ahc->sdtrpending & targ_mask){
+ /* note asynch xfers and clear flag */
+ targ_scratch &= 0xf0;
+ ahc->needsdtr &= ~targ_mask;
+ ahc->sdtrpending &= ~targ_mask;
+ printf("%s:%c:%d: refuses syncronous negotiation. "
+ "Using asyncronous transfers\n",
+ ahc_name(ahc),
+ channel, target);
+ } else {
/*
- * We've set the hardware to assert ATN if we
- * get a parity error on "in" phases, so all we
- * need to do is stuff the message buffer with
- * the appropriate message. "In" phases have set
- * mesg_out to something other than MSG_NOP.
+ * Otherwise, we ignore it.
*/
- if(mesg_out != MSG_NOP) {
- AHC_OUTB(ahc, MSG0, mesg_out);
- AHC_OUTB(ahc, MSG_LEN, 1);
- }
- else
- /*
- * Should we allow the target to make
- * this decision for us?
- */
- xs->error = XS_DRIVER_STUFFUP;
+#ifdef AHC_DEBUG
+ if(ahc_debug & AHC_SHOWMISC)
+ printf("%s:%c:%d: Message reject -- ignored\n",
+ ahc_name(ahc), channel, target);
+#endif
+ break;
}
- else if (status & SELTO) {
- u_char waiting;
- u_char flags;
+ AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset, targ_scratch);
+ AHC_OUTB(ahc, SCSIRATE, targ_scratch);
+ break;
+ }
+ case BAD_STATUS:
+ {
+ int scb_index;
+ struct scsi_xfer *xs;
+
+ /* The sequencer will notify us when a command
+ * has an error that would be of interest to
+ * the kernel. This allows us to leave the sequencer
+ * running in the common case of command completes
+ * without error.
+ */
- xs = scb->xs;
- xs->error = XS_SELTIMEOUT;
- /*
- * Clear any pending messages for the timed out
- * target, and mark the target as free
- */
- flags = AHC_INB(ahc, FLAGS);
- AHC_OUTB(ahc, MSG_LEN, 0);
- ahc_unbusy_target(ahc, xs->sc_link->target,
+ scb_index = AHC_INB(ahc, SCB_TAG);
+ scb = ahc->scbarray[scb_index];
+
+ /*
+ * Set the default return value to 0 (don't
+ * send sense). The sense code will change
+ * this if needed and this reduces code
+ * duplication.
+ */
+ AHC_OUTB(ahc, RETURN_1, 0);
+ if (!(scb && (scb->flags & SCB_ACTIVE))) {
+ printf("%s:%c:%d: ahc_intr - referenced scb "
+ "not valid during seqint 0x%x scb(%d)\n",
+ ahc_name(ahc),
+ channel, target, intstat,
+ scb_index);
+ goto clear;
+ }
+
+ xs = scb->xs;
+
+ scb->status = AHC_INB(ahc, SCB_TARGET_STATUS);
+
+#ifdef AHC_DEBUG
+ if((ahc_debug & AHC_SHOWSCBS)
+ && xs->sc_link->target == DEBUGTARGET)
+ ahc_print_scb(scb);
+#endif
+ xs->status = scb->status;
+ switch(scb->status){
+ case SCSI_OK:
+ printf("%s: Interrupted for staus of"
+ " 0???\n", ahc_name(ahc));
+ break;
+ case SCSI_CHECK:
+#ifdef AHC_DEBUG
+ if(ahc_debug & AHC_SHOWSENSE)
+ {
+ sc_print_addr(xs->sc_link);
+ printf("requests Check Status\n");
+ }
+#endif
+
+ if ((xs->error == XS_NOERROR)
+ && !(scb->flags & SCB_SENSE)) {
+ struct ahc_dma_seg *sg = scb->ahc_dma;
+ struct scsi_sense *sc = &(scb->sense_cmd);
+#ifdef AHC_DEBUG
+ if (ahc_debug & AHC_SHOWSENSE)
+ {
+ sc_print_addr(xs->sc_link);
+ printf("Sending Sense\n");
+ }
+#endif
#if defined(__FreeBSD__)
- ((long)xs->sc_link->fordriver & SELBUSB)
+ sc->op_code = REQUEST_SENSE;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- IS_SCSIBUS_B(ahc, xs->sc_link)
+ sc->opcode = REQUEST_SENSE;
#endif
- ? 'B' : 'A');
- /* Stop the selection */
- AHC_OUTB(ahc, SCSISEQ, 0);
-
- AHC_OUTB(ahc, SCB_CONTROL, 0);
+ sc->byte2 = xs->sc_link->lun << 5;
+ sc->length = sizeof(struct scsi_sense_data);
+ sc->control = 0;
- AHC_OUTB(ahc, CLRSINT1, CLRSELTIMEO);
+ sg->addr = KVTOPHYS(&xs->sense);
+ sg->len = sizeof(struct scsi_sense_data);
- AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
+ scb->control &= DISCENB;
+ scb->status = 0;
+ scb->SG_segment_count = 1;
+ scb->SG_list_pointer = KVTOPHYS(sg);
+ scb->data = sg->addr;
+ scb->datalen = sg->len;
+#ifdef AHC_BROKEN_CACHE
+ if (ahc_broken_cache)
+ INVALIDATE_CACHE();
+#endif
+ scb->cmdpointer = KVTOPHYS(sc);
+ scb->cmdlen = sizeof(*sc);
- /* Shift the waiting for selection queue forward */
- waiting = AHC_INB(ahc, WAITING_SCBH);
- AHC_OUTB(ahc, SCBPTR, waiting);
- waiting = AHC_INB(ahc, SCB_NEXT);
- AHC_OUTB(ahc, WAITING_SCBH, waiting);
+ scb->flags |= SCB_SENSE;
+ ahc_send_scb(ahc, scb);
+ /*
+ * Ensure that the target is "BUSY"
+ * so we don't get overlapping
+ * commands if we happen to be doing
+ * tagged I/O.
+ */
+ ahc_busy_target(ahc, target, channel);
- RESTART_SEQUENCER(ahc);
- }
- else if (!(status & BUSFREE)) {
- sc_print_addr(scb->xs->sc_link);
- printf("Unknown SCSIINT. Status = 0x%x\n", status);
- AHC_OUTB(ahc, CLRSINT1, status);
- UNPAUSE_SEQUENCER(ahc);
- AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
- scb = NULL;
- }
- if(scb != NULL) {
- /* We want to process the command */
- untimeout(ahc_timeout, (caddr_t)scb);
- ahc_done(ahc, scb);
+ /*
+ * Make us the next command to run
+ */
+ ahc_add_waiting_scb(ahc, scb);
+ AHC_OUTB(ahc, RETURN_1, SEND_SENSE);
+ break;
+ }
+ /*
+ * Clear the SCB_SENSE Flag and have
+ * the sequencer do a normal command
+ * complete with either a "DRIVER_STUFFUP"
+ * error or whatever other error condition
+ * we already had.
+ */
+ scb->flags &= ~SCB_SENSE;
+ if (xs->error == XS_NOERROR)
+ xs->error = XS_DRIVER_STUFFUP;
+ break;
+ case SCSI_BUSY:
+ xs->error = XS_BUSY;
+ sc_print_addr(xs->sc_link);
+ printf("Target Busy\n");
+ break;
+ case SCSI_QUEUE_FULL:
+ /*
+ * The upper level SCSI code will someday
+ * handle this properly.
+ */
+ sc_print_addr(xs->sc_link);
+ printf("Queue Full\n");
+ scb->flags |= SCB_ASSIGNEDQ;
+ STAILQ_INSERT_TAIL(&ahc->assigned_scbs,scb, links);
+ AHC_OUTB(ahc, RETURN_1, SEND_SENSE);
+ break;
+ default:
+ sc_print_addr(xs->sc_link);
+ printf("unexpected targ_status: %x\n", scb->status);
+ xs->error = XS_DRIVER_STUFFUP;
+ break;
}
+ break;
}
- if (intstat & CMDCMPLT) {
- int scb_index;
+ case RESIDUAL:
+ {
+ int scb_index;
+ struct scsi_xfer *xs;
- do {
- scb_index = AHC_INB(ahc, QOUTFIFO);
- scb = ahc->scbarray[scb_index];
- if (!scb || !(scb->flags & SCB_ACTIVE)) {
- printf("%s: WARNING "
- "no command for scb %d (cmdcmplt)\n"
- "QOUTCNT == %d\n",
- ahc_name(ahc), scb_index,
- AHC_INB(ahc, QOUTCNT));
- AHC_OUTB(ahc, CLRINT, CLRCMDINT);
- continue;
+ scb_index = AHC_INB(ahc, SCB_TAG);
+ scb = ahc->scbarray[scb_index];
+ xs = scb->xs;
+ /*
+ * Don't clobber valid resid info with
+ * a resid coming from a check sense
+ * operation.
+ */
+ if (!(scb->flags & SCB_SENSE)) {
+ int resid_sgs;
+
+ /*
+ * Remainder of the SG where the transfer
+ * stopped.
+ */
+ xs->resid = (AHC_INB(ahc, SCB_RESID_DCNT2)<<16) |
+ (AHC_INB(ahc, SCB_RESID_DCNT1)<<8) |
+ AHC_INB(ahc, SCB_RESID_DCNT0);
+
+ /*
+ * Add up the contents of all residual
+ * SG segments that are after the SG where
+ * the transfer stopped.
+ */
+ resid_sgs = AHC_INB(ahc, SCB_RESID_SGCNT) - 1;
+ while (resid_sgs > 0) {
+ int sg;
+
+ sg = scb->SG_segment_count - resid_sgs;
+ xs->resid += scb->ahc_dma[sg].len;
+ resid_sgs--;
}
- AHC_OUTB(ahc, CLRINT, CLRCMDINT);
- untimeout(ahc_timeout, (caddr_t)scb);
- ahc_done(ahc, scb);
- } while (AHC_INB(ahc, QOUTCNT) & ahc->qcntmask);
+#if defined(__FreeBSD__)
+ xs->flags |= SCSI_RESID_VALID;
+#elif defined(__NetBSD__) || defined(__OpenBSD__)
+ /* XXX - Update to do this right */
+#endif
+#ifdef AHC_DEBUG
+ if (ahc_debug & AHC_SHOWMISC) {
+ sc_print_addr(xs->sc_link);
+ printf("Handled Residual of %ld bytes\n"
+ ,xs->resid);
+ }
+#endif
+ }
+ break;
+ }
+ case ABORT_TAG:
+ {
+ int scb_index;
+ struct scsi_xfer *xs;
- ahc_run_waiting_queues(ahc);
+ scb_index = AHC_INB(ahc, SCB_TAG);
+ scb = ahc->scbarray[scb_index];
+ xs = scb->xs;
+ /*
+ * We didn't recieve a valid tag back from
+ * the target on a reconnect.
+ */
+ sc_print_addr(xs->sc_link);
+ printf("invalid tag recieved -- sending ABORT_TAG\n");
+ xs->error = XS_DRIVER_STUFFUP;
+ untimeout(ahc_timeout, (caddr_t)scb);
+ ahc_done(ahc, scb);
+ break;
}
-#if defined(__NetBSD__) || defined(__OpenBSD__)
- return 1;
+ case AWAITING_MSG:
+ {
+ int scb_index;
+ scb_index = AHC_INB(ahc, SCB_TAG);
+ scb = ahc->scbarray[scb_index];
+ /*
+ * This SCB had a zero length command, informing
+ * the sequencer that we wanted to send a special
+ * message to this target. We only do this for
+ * BUS_DEVICE_RESET messages currently.
+ */
+ if (scb->flags & SCB_DEVICE_RESET) {
+ AHC_OUTB(ahc, MSG0,
+ MSG_BUS_DEV_RESET);
+ AHC_OUTB(ahc, MSG_LEN, 1);
+ printf("Bus Device Reset Message Sent\n");
+ } else if (scb->flags & SCB_MSGOUT_WDTR) {
+ ahc_construct_wdtr(ahc, AHC_INB(ahc, MSG_LEN),
+ BUS_16_BIT);
+ } else if (scb->flags & SCB_MSGOUT_SDTR) {
+ u_int8_t target_scratch;
+ u_int8_t ultraenable;
+ int sxfr;
+ int i;
+
+ /* Pull the user defined setting */
+ target_scratch = AHC_INB(ahc, TARG_SCRATCH
+ + scratch_offset);
+
+ sxfr = target_scratch & SXFR;
+ if (scratch_offset < 8)
+ ultraenable = AHC_INB(ahc, ULTRA_ENB);
+ else
+ ultraenable = AHC_INB(ahc, ULTRA_ENB + 1);
+
+ if (ultraenable & targ_mask)
+ /* Want an ultra speed in the table */
+ sxfr |= 0x100;
+
+ for (i = 0; i < ahc_num_syncrates; i++)
+ if (sxfr == ahc_syncrates[i].sxfr)
+ break;
+
+ ahc_construct_sdtr(ahc, AHC_INB(ahc, MSG_LEN),
+ ahc_syncrates[i].period,
+ target_scratch & WIDEXFER ?
+ MAX_OFFSET_16BIT : MAX_OFFSET_8BIT);
+ } else
+ panic("ahc_intr: AWAITING_MSG for an SCB that "
+ "does not have a waiting message");
+ break;
+ }
+ case IMMEDDONE:
+ {
+ /*
+ * Take care of device reset messages
+ */
+ u_char scbindex = AHC_INB(ahc, SCB_TAG);
+ scb = ahc->scbarray[scbindex];
+ if (scb->flags & SCB_DEVICE_RESET) {
+ u_char targ_scratch;
+ int found;
+ /*
+ * Go back to async/narrow transfers and
+ * renegotiate.
+ */
+ ahc_unbusy_target(ahc, target, channel);
+ ahc->needsdtr |= ahc->needsdtr_orig & targ_mask;
+ ahc->needwdtr |= ahc->needwdtr_orig & targ_mask;
+ ahc->sdtrpending &= ~targ_mask;
+ ahc->wdtrpending &= ~targ_mask;
+ targ_scratch = AHC_INB(ahc, TARG_SCRATCH
+ + scratch_offset);
+ targ_scratch &= SXFR;
+ AHC_OUTB(ahc, TARG_SCRATCH + scratch_offset,
+ targ_scratch);
+ found = ahc_reset_device(ahc, target,
+ channel, SCB_LIST_NULL,
+ XS_NOERROR);
+ sc_print_addr(scb->xs->sc_link);
+ printf("Bus Device Reset delivered. "
+ "%d SCBs aborted\n", found);
+ ahc->in_timeout = FALSE;
+ ahc_run_done_queue(ahc);
+ } else
+ panic("ahc_intr: Immediate complete for "
+ "unknown operation.");
+ break;
+ }
+ case DATA_OVERRUN:
+ {
+ /*
+ * When the sequencer detects an overrun, it
+ * sets STCNT to 0x00ffffff and allows the
+ * target to complete its transfer in
+ * BITBUCKET mode.
+ */
+ u_char scbindex = AHC_INB(ahc, SCB_TAG);
+ u_int32_t overrun;
+ scb = ahc->scbarray[scbindex];
+ overrun = AHC_INB(ahc, STCNT0)
+ | (AHC_INB(ahc, STCNT1) << 8)
+ | (AHC_INB(ahc, STCNT2) << 16);
+ overrun = 0x00ffffff - overrun;
+ sc_print_addr(scb->xs->sc_link);
+ printf("data overrun of %d bytes detected."
+ " Forcing a retry.\n", overrun);
+ /*
+ * Set this and it will take affect when the
+ * target does a command complete.
+ */
+ scb->xs->error = XS_DRIVER_STUFFUP;
+ break;
+ }
+#if NOT_YET
+ /* XXX Fill these in later */
+ case MESG_BUFFER_BUSY:
+ break;
+ case MSGIN_PHASEMIS:
+ break;
#endif
+ default:
+ printf("ahc_intr: seqint, "
+ "intstat == 0x%x, scsisigi = 0x%x\n",
+ intstat, AHC_INB(ahc, SCSISIGI));
+ break;
+ }
+
+clear:
+ /*
+ * Clear the upper byte that holds SEQINT status
+ * codes and clear the SEQINT bit.
+ */
+ AHC_OUTB(ahc, CLRINT, CLRSEQINT);
+
+ /*
+ * The sequencer is paused immediately on
+ * a SEQINT, so we should restart it when
+ * we're done.
+ */
+ unpause_sequencer(ahc, /*unpause_always*/TRUE);
}
/*
}
#elif defined(__NetBSD__) || defined(__OpenBSD__)
/*
- * Since NetBSD doesn't have error ignoring operation mode
+ * Since NetBSD nor OpenBSD doesn't have error ignoring operation mode
* (SCSI_ERR_OK in FreeBSD), we don't have to care this case.
*/
#endif
ahc_init(ahc)
struct ahc_data *ahc;
{
- u_char scsi_conf, sblkctl, i;
- u_short ultraenable = 0;
- int max_targ = 15;
+ u_int8_t scsi_conf, sblkctl, i;
+ u_int16_t ultraenable = 0;
+ int max_targ = 15;
/*
* Assume we have a board at this stage and it has been reset.
*/
if(scsi_conf & RESET_SCSI) {
/* Reset the bus */
+#if (!defined(__NetBSD__) && !defined(__OpenBSD__)) || defined(DEBUG)
if(bootverbose)
printf("%s: Reseting Channel B\n",
ahc_name(ahc));
+#endif
AHC_OUTB(ahc, SCSISEQ, SCSIRSTO);
DELAY(1000);
AHC_OUTB(ahc, SCSISEQ, 0);
if(scsi_conf & RESET_SCSI) {
/* Reset the bus */
+#if (!defined(__NetBSD__) && !defined(__OpenBSD__)) || defined(DEBUG)
if(bootverbose)
printf("%s: Reseting Channel A\n", ahc_name(ahc));
+#endif
AHC_OUTB(ahc, SCSISEQ, SCSIRSTO);
DELAY(1000);
* Load the Sequencer program and Enable the adapter
* in "fast" mode.
*/
+#if (!defined(__NetBSD__) && !defined(__OpenBSD__)) || defined(DEBUG)
if(bootverbose)
printf("%s: Downloading Sequencer Program...",
ahc_name(ahc));
+#endif
ahc_loadseq(ahc);
+#if (!defined(__NetBSD__) && !defined(__OpenBSD__)) || defined(DEBUG)
if(bootverbose)
printf("Done\n");
+#endif
AHC_OUTB(ahc, SEQCTL, FASTMODE);
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/TRUE);
/*
* Note that we are going and return (to probe)
}
SC_DEBUG(xs->sc_link, SDEV_DB3, ("start scb(%p)\n", scb));
scb->xs = xs;
- if (flags & SCSI_RESET)
+ if (flags & SCSI_RESET) {
scb->flags |= SCB_DEVICE_RESET|SCB_IMMED;
+ scb->control |= MK_MESSAGE;
+ }
/*
* Put all the arguments for the xfer in the scb
*/
scb->control |= DISCENB;
if((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask))
{
- scb->control |= NEEDWDTR;
+ scb->control |= MK_MESSAGE;
+ scb->flags |= SCB_MSGOUT_WDTR;
ahc->wdtrpending |= mask;
}
else if((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask))
{
- scb->control |= NEEDSDTR;
+ scb->control |= MK_MESSAGE;
+ scb->flags |= SCB_MSGOUT_SDTR;
ahc->sdtrpending |= mask;
}
scb->tcl = ((xs->sc_link->target << 4) & 0xF0) |
/* We already have a valid slot */
u_char curscb;
- PAUSE_SEQUENCER(ahc);
+ pause_sequencer(ahc);
curscb = AHC_INB(ahc, SCBPTR);
AHC_OUTB(ahc, SCBPTR, scb->position);
ahc_send_scb(ahc, scb);
AHC_OUTB(ahc, SCBPTR, curscb);
AHC_OUTB(ahc, QINFIFO, scb->position);
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/FALSE);
scb->flags |= SCB_ACTIVE;
if (!(flags & SCSI_NOMASK)) {
timeout(ahc_timeout, (caddr_t)scb,
else if((wscb = ahc->waiting_scbs.stqh_first) != NULL) {
STAILQ_REMOVE_HEAD(&ahc->waiting_scbs, links);
wscb->position = scb->position;
- STAILQ_INSERT_HEAD(&ahc->assigned_scbs, wscb, links);
+ STAILQ_INSERT_TAIL(&ahc->assigned_scbs, wscb, links);
wscb->flags ^= SCB_WAITINGQ|SCB_ASSIGNEDQ;
/*
struct ahc_data *ahc;
{
static u_char seqprog[] = {
+#if defined(__FreeBSD__)
# include "aic7xxx_seq.h"
+#endif
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+# include <dev/microcode/aic7xxx/aic7xxx_seq.h>
+#endif
};
AHC_OUTB(ahc, SEQCTL, PERRORDIS|SEQRESET|LOADRAM);
* Ensure that the card doesn't do anything
* behind our back.
*/
- PAUSE_SEQUENCER(ahc);
+ pause_sequencer(ahc);
sc_print_addr(scb->xs->sc_link);
printf("timed out ");
scb->flags |= SCB_ABORTED|SCB_SENTORDEREDTAG;
ahc->orderedtag |= 0xFF;
timeout(ahc_timeout, (caddr_t)scb, (5 * hz));
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/FALSE);
printf("Ordered Tag queued\n");
goto done;
}
}
scb->flags |= SCB_DEVICE_RESET|SCB_ABORTED;
scb->control &= DISCENB;
+ scb->control |= MK_MESSAGE;
scb->cmdlen = 0;
scb->SG_segment_count = 0;
scb->SG_list_pointer = 0;
sc_print_addr(scb->xs->sc_link);
printf("BUS DEVICE RESET message queued.\n");
AHC_OUTB(ahc, SCBPTR, active_scb);
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/FALSE);
goto done;
}
/* Is the active SCB really active? */
else if((active_scbp->flags & SCB_ACTIVE) && bus_state){
AHC_OUTB(ahc, MSG_LEN, 1);
- AHC_OUTB(ahc, MSG0, MSG_BUS_DEVICE_RESET);
+ AHC_OUTB(ahc, MSG0, MSG_BUS_DEV_RESET);
AHC_OUTB(ahc, SCSISIGO, bus_state|ATNO);
sc_print_addr(active_scbp->xs->sc_link);
printf("asserted ATN - device reset in "
timeout(ahc_timeout, (caddr_t)active_scbp,
(2 * hz));
AHC_OUTB(ahc, SCBPTR, active_scb);
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/FALSE);
goto done;
}
}
AHC_OUTB(ahc, CLRSINT1, CLRSCSIRSTI|CLRSELTIMEO);
AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
AHC_OUTB(ahc, SBLKCTL, sblkctl);
- UNPAUSE_SEQUENCER(ahc);
+ unpause_sequencer(ahc, /*unpause_always*/TRUE);
}
/* Case 2: A command from this bus is active or we're idle */
else {
}
AHC_OUTB(ahc, CLRSINT1, CLRSCSIRSTI|CLRSELTIMEO);
AHC_OUTB(ahc, CLRINT, CLRSCSIINT);
- RESTART_SEQUENCER(ahc);
+ restart_sequencer(ahc);
}
ahc_run_done_queue(ahc);
return found;
else
return ((chan == channel) && (targ == target));
}
+
+
+static void
+ahc_construct_sdtr(ahc, start_byte, period, offset)
+ struct ahc_data *ahc;
+ int start_byte;
+ u_int8_t period;
+ u_int8_t offset;
+{
+ AHC_OUTB(ahc, MSG0 + start_byte, MSG_EXTENDED);
+ AHC_OUTB(ahc, MSG1 + start_byte, MSG_EXT_SDTR_LEN);
+ AHC_OUTB(ahc, MSG2 + start_byte, MSG_EXT_SDTR);
+ AHC_OUTB(ahc, MSG3 + start_byte, period);
+ AHC_OUTB(ahc, MSG4 + start_byte, offset);
+ AHC_OUTB(ahc, MSG_LEN, start_byte + 5);
+}
+
+static void
+ahc_construct_wdtr(ahc, start_byte, bus_width)
+ struct ahc_data *ahc;
+ int start_byte;
+ u_int8_t bus_width;
+{
+ AHC_OUTB(ahc, MSG0 + start_byte, MSG_EXTENDED);
+ AHC_OUTB(ahc, MSG1 + start_byte, MSG_EXT_WDTR_LEN);
+ AHC_OUTB(ahc, MSG2 + start_byte, MSG_EXT_WDTR);
+ AHC_OUTB(ahc, MSG3 + start_byte, bus_width);
+ AHC_OUTB(ahc, MSG_LEN, start_byte + 4);
+}
-/* $OpenBSD: aic7xxxreg.h,v 1.3 1996/10/31 01:01:25 niklas Exp $ */
+/* $OpenBSD: aic7xxxreg.h,v 1.4 1996/11/28 23:27:45 niklas Exp $ */
+/* $NetBSD: aic7xxxreg.h,v 1.4 1996/10/08 03:04:04 gibbs Exp $ */
/*
* Aic7xxx register and scratch ram definitions.
*
#define SEND_REJECT 0x11 /* sending a message reject */
#define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/
#define NO_MATCH 0x31 /* no cmd match for reconnect */
-#define SDTR_MSG 0x41 /* SDTR message received */
-#define WDTR_MSG 0x51 /* WDTR message received */
+#define EXTENDED_MSG 0x41 /* Extended message received */
#define REJECT_MSG 0x61 /* Reject message received */
#define BAD_STATUS 0x71 /* Bad status from target */
#define RESIDUAL 0x81 /* Residual byte count != 0 */
*/
#define SCBARRAY 0x0a0
#define SCB_CONTROL 0x0a0
-#define NEEDWDTR 0x80
+#define MK_MESSAGE 0x80
#define DISCENB 0x40
#define TAG_ENB 0x20
-#define NEEDSDTR 0x10
#define DISCONNECTED 0x04
#define SCB_TAG_TYPE 0x03
#define SCB_TCL 0x0a1
*/
#define LASTPHASE 0x03d
#define ARG_1 0x03e
-#define MAXOFFSET 0x01
#define RETURN_1 0x03f
-#define SEND_WDTR 0x80
-#define SEND_SDTR 0x60
+#define SEND_MSG 0x80
#define SEND_SENSE 0x40
#define SEND_REJ 0x20
#define SCB_PAGEDIN 0x10
#define ULTRA_ENB 0x052
#define ULTRA_ENB_B 0x053
+#define MSGIN_EXT_LEN 0x054
+#define MSGIN_EXT_OPCODE 0x055
+#define MSGIN_EXT_BYTE0 0x056
+#define MSGIN_EXT_BYTE1 0x057
+#define MSGIN_EXT_LASTBYTE 0x058 /*
+ * We don't use this location, but
+ * continue to store bytes until
+ * we reach this address (avoids
+ * a more complicated compare).
+ * So, we can store at most 2
+ * bytes for now.
+ */
+
#define SCSICONF 0x05a
#define RESET_SCSI 0x40
#define BIOSDISABLED 0x30
#define CHANNEL_B_PRIMARY 0x08
-/* Message codes */
-#define MSG_EXTENDED 0x01
-#define MSG_SDTR 0x01
-#define MSG_WDTR 0x03
-#define MSG_SDPTRS 0x02
-#define MSG_RDPTRS 0x03
-#define MSG_DISCONNECT 0x04
-#define MSG_INITIATOR_DET_ERROR 0x05
-#define MSG_ABORT 0x06
-#define MSG_REJECT 0x07
-#define MSG_NOP 0x08
-#define MSG_MSG_PARITY_ERROR 0x09
-#define MSG_BUS_DEVICE_RESET 0x0c
-#define MSG_ABORT_TAG 0x0d
-#define MSG_SIMPLE_TAG 0x20
-#define MSG_IDENTIFY 0x80
-
/* WDTR Message values */
#define BUS_8_BIT 0x00
#define BUS_16_BIT 0x01
-/* $OpenBSD: aic7xxxvar.h,v 1.8 1996/10/31 01:01:25 niklas Exp $ */
+/* $OpenBSD: aic7xxxvar.h,v 1.9 1996/11/28 23:27:45 niklas Exp $ */
+/* $NetBSD: aic7xxxvar.h,v 1.10 1996/10/21 22:34:09 thorpej Exp $ */
/*
* Interface to the generic driver for the aic7xxx based adaptec
* SCSI controllers. This is used to implement product specific
outsl((ahc)->baseport+(port), valp, size)
#elif defined(__NetBSD__) || defined(__OpenBSD__)
#define AHC_INB(ahc, port) \
- bus_io_read_1((ahc)->sc_bc, (ahc)->sc_ioh, port)
+ bus_space_read_1((ahc)->sc_iot, (ahc)->sc_ioh, port)
#define AHC_INSB(ahc, port, valp, size) \
- bus_io_read_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
+ bus_space_read_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, valp, size)
#define AHC_OUTB(ahc, port, val) \
- bus_io_write_1((ahc)->sc_bc, (ahc)->sc_ioh, port, val)
+ bus_space_write_1((ahc)->sc_iot, (ahc)->sc_ioh, port, val)
#define AHC_OUTSB(ahc, port, valp, size) \
- bus_io_write_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
+ bus_space_write_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, valp, size)
#define AHC_OUTSL(ahc, port, valp, size) \
- bus_io_write_multi_4((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
+ bus_space_write_multi_4((ahc)->sc_iot, (ahc)->sc_ioh, port, valp, size)
#endif
#define AHC_NSEG 256 /* number of dma segments supported */
*/
-typedef unsigned long int physaddr;
+typedef u_int32_t physaddr;
#if defined(__FreeBSD__)
extern u_long ahc_unit;
#endif
struct ahc_dma_seg {
- physaddr addr;
- long len;
+ physaddr addr;
+ u_int32_t len;
};
typedef enum {
AHC_AIC78X0 = 0x060, /* PCI Based Controller */
AHC_274 = 0x110, /* EISA Based Controller */
AHC_284 = 0x210, /* VL/ISA Based Controller */
+ AHC_294AU = 0x421, /* aic7860 based '2940' */
AHC_294 = 0x440, /* PCI Based Controller */
AHC_294U = 0x441, /* ULTRA PCI Based Controller */
AHC_394 = 0x840, /* Twin Channel PCI Controller */
}ahc_flag;
typedef enum {
- SCB_FREE = 0x000,
- SCB_ACTIVE = 0x001,
- SCB_ABORTED = 0x002,
- SCB_DEVICE_RESET = 0x004,
- SCB_IMMED = 0x008,
- SCB_SENSE = 0x010,
- SCB_TIMEDOUT = 0x020,
- SCB_QUEUED_FOR_DONE = 0x040,
- SCB_PAGED_OUT = 0x080,
- SCB_WAITINGQ = 0x100,
- SCB_ASSIGNEDQ = 0x200,
- SCB_SENTORDEREDTAG = 0x400
+ SCB_FREE = 0x0000,
+ SCB_ACTIVE = 0x0001,
+ SCB_ABORTED = 0x0002,
+ SCB_DEVICE_RESET = 0x0004,
+ SCB_IMMED = 0x0008,
+ SCB_SENSE = 0x0010,
+ SCB_TIMEDOUT = 0x0020,
+ SCB_QUEUED_FOR_DONE = 0x0040,
+ SCB_PAGED_OUT = 0x0080,
+ SCB_WAITINGQ = 0x0100,
+ SCB_ASSIGNEDQ = 0x0200,
+ SCB_SENTORDEREDTAG = 0x0400,
+ SCB_MSGOUT_SDTR = 0x0800,
+ SCB_MSGOUT_WDTR = 0x1000
}scb_flag;
/*
/*8*/ u_char residual_SG_segment_count;
/*9*/ u_char residual_data_count[3];
/*12*/ physaddr data;
-/*16*/ u_long datalen; /* Really only three bits, but its
+/*16*/ u_int32_t datalen; /* Really only three bits, but its
* faster to treat it as a long on
* a quad boundary.
*/
#elif defined(__NetBSD__) || defined(__OpenBSD__)
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
- bus_io_handle_t sc_ioh;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
#endif
ahc_type type;
ahc_flag flags;
#define ahc_name(ahc) (ahc)->sc_dev.dv_xname
-void ahc_reset __P((char *devname, bus_chipset_tag_t bc, bus_io_handle_t ioh));
-void ahc_construct __P((struct ahc_data *ahc, bus_chipset_tag_t bc, bus_io_handle_t ioh, ahc_type type, ahc_flag flags));
+void ahc_reset __P((char *devname, bus_space_tag_t iot,
+ bus_space_handle_t ioh));
+void ahc_construct __P((struct ahc_data *ahc, bus_space_tag_t iot,
+ bus_space_handle_t ioh, ahc_type type, ahc_flag flags));
#endif
-void ahc_free __P((struct ahc_data *));
-int ahc_init __P((struct ahc_data *));
-int ahc_attach __P((struct ahc_data *));
+void ahc_free __P((struct ahc_data *));
+int ahc_init __P((struct ahc_data *));
+int ahc_attach __P((struct ahc_data *));
#if defined(__FreeBSD__)
-void ahc_intr __P((void *arg));
+void ahc_intr __P((void *arg));
#elif defined(__NetBSD__) || defined(__OpenBSD__)
-int ahc_intr __P((void *arg));
+int ahc_intr __P((void *arg));
#endif
#endif /* _AIC7XXX_H_ */
-/* $OpenBSD: am7990.c,v 1.8 1996/05/10 12:41:10 deraadt Exp $ */
-/* $NetBSD: am7990.c,v 1.19 1996/05/07 01:38:35 thorpej Exp $ */
+/* $OpenBSD: am7990.c,v 1.9 1996/11/28 23:27:46 niklas Exp $ */
+/* $NetBSD: am7990.c,v 1.22 1996/10/13 01:37:19 christos Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
#ifdef LEDEBUG
if (sc->sc_debug)
printf("trans tmd: "
- "ladr %04x, hadr %02x, flags %02x, "
- "bcnt %04x, mcnt %04x\n",
- tmd.tmd0, tmd.tmd1_hadr, tmd.tmd1_bits,
- tmd.tmd2, tmd.tmd3);
+ "ladr %04x, hadr %02x, flags %02x, "
+ "bcnt %04x, mcnt %04x\n",
+ tmd.tmd0, tmd.tmd1_hadr, tmd.tmd1_bits,
+ tmd.tmd2, tmd.tmd3);
#endif
(*sc->sc_copyfromdesc)(sc, &tmd, LE_TMDADDR(sc, bix),
am7990_reset(sc);
return;
}
- if (tmd.tmd3 & LE_T3_LCAR)
- printf("%s: lost carrier\n",
- sc->sc_dev.dv_xname);
+ if (tmd.tmd3 & LE_T3_LCAR) {
+ if (sc->sc_nocarrier)
+ (*sc->sc_nocarrier)(sc);
+ else
+ printf("%s: lost carrier\n",
+ sc->sc_dev.dv_xname);
+ }
if (tmd.tmd3 & LE_T3_LCOL)
ifp->if_collisions++;
if (tmd.tmd3 & LE_T3_RTRY) {
-/* $OpenBSD: am7990var.h,v 1.5 1996/05/10 12:41:11 deraadt Exp $ */
-/* $NetBSD: am7990var.h,v 1.7 1996/05/07 01:38:37 thorpej Exp $ */
+/* $OpenBSD: am7990var.h,v 1.6 1996/11/28 23:27:47 niklas Exp $ */
+/* $NetBSD: am7990var.h,v 1.8 1996/07/05 23:57:01 abrown Exp $ */
/*
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
*
* read/write CSR
* hardware init hook - may be NULL
+ * no carrier hook - may be NULL
*/
u_int16_t (*sc_rdcsr)
__P((struct am7990_softc *, u_int16_t));
void (*sc_wrcsr)
__P((struct am7990_softc *, u_int16_t, u_int16_t));
void (*sc_hwinit) __P((struct am7990_softc *));
+ void (*sc_nocarrier) __P((struct am7990_softc *));
void *sc_sh; /* shutdownhook cookie */
-/* $OpenBSD: cd1400reg.h,v 1.2 1996/06/20 11:39:12 deraadt Exp $ */
+/* $OpenBSD: cd1400reg.h,v 1.3 1996/11/28 23:27:47 niklas Exp $ */
+/* $NetBSD: cd1400reg.h,v 1.3 1996/09/24 18:02:33 christos Exp $ */
/*-
* cyclades cyclom-y serial driver
-/* $OpenBSD: cy.c,v 1.4 1996/11/12 20:30:17 niklas Exp $ */
+/* $OpenBSD: cy.c,v 1.5 1996/11/28 23:27:48 niklas Exp $ */
/*
* cy.c
* Some debugging counters (number of receive/transmit interrupts etc.)
* can be enabled by defining CY_DEBUG1
*
- * This version uses the bus_mem/io_??() stuff
+ * This version uses the bus_space/io_??() stuff
*
* NOT TESTED !!!
*
#include <sys/malloc.h>
#include <sys/systm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#if NCY_ISA > 0
#define ISSET(t, f) ((t) & (f))
void cyattach __P((struct device *, struct device *, void *));
-int cy_probe_common __P((int, bus_chipset_tag_t, bus_mem_handle_t, int));
+int cy_probe_common __P((int, bus_space_tag_t, bus_space_handle_t, int));
int cyintr __P((void *));
int cyparam __P((struct tty *, struct termios *));
void cystart __P((struct tty *));
static int cy_nr_cd1400s[NCY];
static int cy_bus_types[NCY];
-static bus_mem_handle_t cy_card_memh[NCY];
+static bus_space_handle_t cy_card_memh[NCY];
static int cy_open = 0;
static int cy_events = 0;
* Common probe routine
*/
int
-cy_probe_common(card, bc, memh, bustype)
+cy_probe_common(card, memt, memh, bustype)
int card, bustype;
- bus_chipset_tag_t bc;
- bus_mem_handle_t memh;
+ bus_space_tag_t memt;
+ bus_space_handle_t memh;
{
int cy_chip, chip_offs;
u_char firmware_ver;
/* Cyclom card hardware reset */
- bus_mem_write_1(bc, memh, CY16_RESET<<bustype, 0);
+ bus_space_write_1(memt, memh, CY16_RESET<<bustype, 0);
DELAY(500); /* wait for reset to complete */
- bus_mem_write_1(bc, memh, CY_CLEAR_INTR<<bustype, 0);
+ bus_space_write_1(memt, memh, CY_CLEAR_INTR<<bustype, 0);
#ifdef CY_DEBUG
printf("cy: card reset done\n");
/* wait until the chip is ready for command */
DELAY(1000);
- if(bus_mem_read_1(bc, memh, chip_offs +
+ if(bus_space_read_1(memt, memh, chip_offs +
((CD1400_CCR<<1) << bustype)) != 0) {
#ifdef CY_DEBUG
printf("not ready for command\n");
}
/* clear the firmware version reg. */
- bus_mem_write_1(bc, memh, chip_offs +
+ bus_space_write_1(memt, memh, chip_offs +
((CD1400_GFRCR<<1) << bustype), 0);
/*
* cleared chip 0 GFRCR. In that case we have a 16 port card.
*/
if(cy_chip == 4 &&
- bus_mem_read_1(bc, memh, chip_offs +
+ bus_space_read_1(memt, memh, chip_offs +
((CD1400_GFRCR<<1) << bustype)) ==0)
break;
/* reset the chip */
- bus_mem_write_1(bc, memh, chip_offs +
+ bus_space_write_1(memt, memh, chip_offs +
((CD1400_CCR<<1) << bustype),
CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET);
for(i = 0; i < 200; i++) {
DELAY(50);
firmware_ver =
- bus_mem_read_1(bc, memh, chip_offs +
+ bus_space_read_1(memt, memh, chip_offs +
((CD1400_GFRCR<<1) << bustype));
if((firmware_ver & 0xf0) == 0x40) /* found a CD1400 */
break;
switch(sc->sc_bustype) {
#if NCY_ISA > 0
case CY_BUSTYPE_ISA:
- sc->sc_bc = ((struct isa_attach_args *)(aux))->ia_bc;
+ sc->sc_memt = ((struct isa_attach_args *)(aux))->ia_memt;
break;
#endif
#if NCY_PCI > 0
case CY_BUSTYPE_PCI:
- sc->sc_bc = ((struct pci_attach_args *)aux)->pa_bc;
+ sc->sc_memt = ((struct pci_attach_args *)aux)->pa_memt;
break;
#endif
}
for(cdu = 0; cdu < CD1400_NO_OF_CHANNELS; cdu++) {
sc->sc_ports[port].cy_port_num = port;
- sc->sc_ports[port].cy_bc = sc->sc_bc;
+ sc->sc_ports[port].cy_memt = sc->sc_memt;
sc->sc_ports[port].cy_memh = sc->sc_memh;
sc->sc_ports[port].cy_chip_offs = chip_offs;
sc->sc_ports[port].cy_bustype = sc->sc_bustype;
printf(" (%d ports)\n", port);
/* ensure an edge for the next interrupt */
- bus_mem_write_1(sc->sc_bc, sc->sc_memh,
+ bus_space_write_1(sc->sc_memt, sc->sc_memh,
CY_CLEAR_INTR<<sc->sc_bustype, 0);
switch(sc->sc_bustype) {
} /* for(...all CD1400s on a card) */
/* ensure an edge for next interrupt */
- bus_mem_write_1(sc->sc_bc, sc->sc_memh,
+ bus_space_write_1(sc->sc_memt, sc->sc_memh,
CY_CLEAR_INTR<<sc->sc_bustype, 0);
return int_serviced;
}
-/* $OpenBSD: cyreg.h,v 1.1 1996/07/27 07:20:03 deraadt Exp $ */
+/* $OpenBSD: cyreg.h,v 1.2 1996/11/28 23:27:49 niklas Exp $ */
/* $FreeBSD: cyreg.h,v 1.1 1995/07/05 12:15:51 bde Exp $ */
/*-
/*
* read/write cd1400 registers (when cy_port-structure is available)
*/
-#define cd_read_reg(cy,reg) bus_mem_read_1(cy->cy_bc, cy->cy_memh, \
+#define cd_read_reg(cy,reg) bus_space_read_1(cy->cy_memt, cy->cy_memh, \
cy->cy_chip_offs+(((reg<<1))<<cy->cy_bustype))
-#define cd_write_reg(cy,reg,val) bus_mem_write_1(cy->cy_bc, cy->cy_memh, \
+#define cd_write_reg(cy,reg,val) bus_space_write_1(cy->cy_memt, cy->cy_memh, \
cy->cy_chip_offs+(((reg<<1))<<cy->cy_bustype), \
(val))
/*
* read/write cd1400 registers (when sc_softc-structure is available)
*/
-#define cd_read_reg_sc(sc,chip,reg) bus_mem_read_1(sc->sc_bc, \
+#define cd_read_reg_sc(sc,chip,reg) bus_space_read_1(sc->sc_memt, \
sc->sc_memh, \
sc->sc_cd1400_offs[chip]+\
(((reg<<1))<<sc->sc_bustype))
-#define cd_write_reg_sc(sc,chip,reg,val) bus_mem_write_1(sc->sc_bc, \
+#define cd_write_reg_sc(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
sc->sc_memh, \
sc->sc_cd1400_offs[chip]+\
(((reg<<1))<<sc->sc_bustype), \
/* software state for one port */
struct cy_port {
int cy_port_num;
- bus_chipset_tag_t cy_bc;
- bus_mem_handle_t cy_memh;
+ bus_space_tag_t cy_memt;
+ bus_space_handle_t cy_memh;
int cy_chip_offs;
int cy_bustype;
struct tty *cy_tty;
struct cy_softc {
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
- bus_mem_handle_t sc_memh;
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_memh;
int sc_bustype;
int sc_nports; /* number of ports on this card */
int sc_cd1400_offs[CY_MAX_CD1400s];
-/* $OpenBSD: elink3.c,v 1.15 1996/11/12 20:30:18 niklas Exp $ */
-/* $NetBSD: elink3.c,v 1.7 1996/05/14 22:22:05 thorpej Exp $ */
+/* $OpenBSD: elink3.c,v 1.16 1996/11/28 23:27:49 niklas Exp $ */
+/* $NetBSD: elink3.c,v 1.11 1996/10/21 22:34:21 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/ic/elink3var.h>
u_int16_t conn;
{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
u_int16_t i;
sc->ep_connectors = 0;
u_int16_t x;
if (epbusyeeprom(sc))
return;
- bus_io_write_2(bc, ioh, EP_W0_EEPROM_COMMAND, READ_EEPROM | i);
+ bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND,
+ READ_EEPROM | i);
if (epbusyeeprom(sc))
return;
- x = bus_io_read_2(bc, ioh, EP_W0_EEPROM_DATA);
+ x = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA);
sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8;
sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x;
}
printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_TX_AVAIL_THRESH | 1800 );
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_AVAIL_THRESH | 1800 );
GO_WINDOW(5);
- i = bus_io_read_2(bc, ioh, EP_W5_TX_AVAIL_THRESH);
+ i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH);
GO_WINDOW(1);
if (i == 1800*4)
sc->txashift = 2;
register struct ep_softc *sc;
{
register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int i;
- while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
+ while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
if (sc->bustype != EP_BUS_PCI) {
GO_WINDOW(0);
- bus_io_write_2(bc, ioh, EP_W0_CONFIG_CTRL, 0);
- bus_io_write_2(bc, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
+ bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0);
+ bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
}
if (sc->bustype == EP_BUS_PCMCIA) {
#ifdef EP_COAX_DEFAULT
- bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG,3<<14);
+ bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,3<<14);
#else
- bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG,0<<14);
+ bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,0<<14);
#endif
- bus_io_write_2(bc, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
+ bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
}
GO_WINDOW(2);
for (i = 0; i < 6; i++) /* Reload the ether_addr. */
- bus_io_write_1(bc, ioh, EP_W2_ADDR_0 + i,
+ bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i,
sc->sc_arpcom.ac_enaddr[i]);
if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA)
/* Reset the station-address receive filter */
for (i = 0; i < 6; i++)
- bus_io_write_1(bc, ioh,EP_W2_RECVMASK_0 + i, 0);
+ bus_space_write_1(iot, ioh,EP_W2_RECVMASK_0 + i, 0);
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_RESET);
- bus_io_write_2(bc, ioh, EP_COMMAND, TX_RESET);
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_RESET);
+ bus_space_write_2(iot, ioh, EP_COMMAND, TX_RESET);
GO_WINDOW(1); /* Window 1 is operating window */
for (i = 0; i < 31; i++)
- bus_io_read_1(bc, ioh, EP_W1_TX_STATUS);
+ bus_space_read_1(iot, ioh, EP_W1_TX_STATUS);
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
- S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
- S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK |
+ S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK |
+ S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
/*
* Attempt to get rid of any stray interrupts that occured during
* already be queued. However, a single stray interrupt is
* unimportant.
*/
- bus_io_write_2(bc, ioh, EP_COMMAND, ACK_INTR | 0xff);
+ bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff);
epsetfilter(sc);
epsetlink(sc);
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_ENABLE);
- bus_io_write_2(bc, ioh, EP_COMMAND, TX_ENABLE);
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE);
+ bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE);
epmbuffill(sc);
register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
GO_WINDOW(1); /* Window 1 is operating window */
- bus_io_write_2(sc->sc_bc, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |
+ bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |
FIL_INDIVIDUAL | FIL_BRDCST |
((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) |
((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 ));
register struct ep_softc *sc;
{
register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
/*
* you can `ifconfig (link0|-link0) ep0' to get the following
* set too, then you get the UTP port.
*/
GO_WINDOW(4);
- bus_io_write_2(bc, ioh, EP_W4_MEDIA_TYPE, DISABLE_UTP);
+ bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, DISABLE_UTP);
if (!(ifp->if_flags & IFF_LINK0) && (sc->ep_connectors & BNC)) {
if (sc->bustype == EP_BUS_PCMCIA) {
GO_WINDOW(0);
- bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG,3<<14);
+ bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,3<<14);
GO_WINDOW(1);
}
- bus_io_write_2(bc, ioh, EP_COMMAND, START_TRANSCEIVER);
+ bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER);
delay(1000);
}
if (ifp->if_flags & IFF_LINK0) {
- bus_io_write_2(bc, ioh, EP_COMMAND, STOP_TRANSCEIVER);
+ bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER);
delay(1000);
if ((ifp->if_flags & IFF_LINK1) && (sc->ep_connectors & UTP)) {
if (sc->bustype == EP_BUS_PCMCIA) {
GO_WINDOW(0);
- bus_io_write_2(bc, ioh,
+ bus_space_write_2(iot, ioh,
EP_W0_ADDRESS_CFG,0<<14);
GO_WINDOW(4);
}
- bus_io_write_2(bc, ioh, EP_W4_MEDIA_TYPE, ENABLE_UTP);
+ bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,
+ ENABLE_UTP);
}
}
GO_WINDOW(1);
struct ifnet *ifp;
{
register struct ep_softc *sc = ifp->if_softc;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct mbuf *m, *m0;
int sh, len, pad;
goto readcheck;
}
- if (bus_io_read_2(bc, ioh, EP_W1_FREE_TX) < len + pad + 4) {
- bus_io_write_2(bc, ioh, EP_COMMAND,
+ if (bus_space_read_2(iot, ioh, EP_W1_FREE_TX) < len + pad + 4) {
+ bus_space_write_2(iot, ioh, EP_COMMAND,
SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift));
/* not enough room in FIFO */
ifp->if_flags |= IFF_OACTIVE;
return;
} else {
- bus_io_write_2(bc, ioh, EP_COMMAND,
+ bus_space_write_2(iot, ioh, EP_COMMAND,
SET_TX_AVAIL_THRESH | (2044 >> sc->txashift));
}
if (m0 == 0) /* not really needed */
return;
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_TX_START_THRESH |
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH |
(len / 4 + sc->tx_start_thresh));
#if NBPFILTER > 0
*/
sh = splhigh();
- bus_io_write_2(bc, ioh, EP_W1_TX_PIO_WR_1, len);
- bus_io_write_2(bc, ioh, EP_W1_TX_PIO_WR_1,
+ bus_space_write_2(iot, ioh, EP_W1_TX_PIO_WR_1, len);
+ bus_space_write_2(iot, ioh, EP_W1_TX_PIO_WR_1,
0xffff); /* Second dword meaningless */
if (EP_IS_BUS_32(sc->bustype)) {
for (m = m0; m; ) {
if (m->m_len > 3)
- bus_io_write_multi_4(bc, ioh,
+ bus_space_write_multi_4(iot, ioh,
EP_W1_TX_PIO_WR_1, mtod(m, u_int32_t *),
m->m_len / 4);
if (m->m_len & 3)
- bus_io_write_multi_1(bc, ioh,
+ bus_space_write_multi_1(iot, ioh,
EP_W1_TX_PIO_WR_1,
mtod(m, u_int8_t *) + (m->m_len & ~3),
m->m_len & 3);
} else {
for (m = m0; m; ) {
if (m->m_len > 1)
- bus_io_write_multi_2(bc, ioh,
+ bus_space_write_multi_2(iot, ioh,
EP_W1_TX_PIO_WR_1, mtod(m, u_int16_t *),
m->m_len / 2);
if (m->m_len & 1)
- bus_io_write_1(bc, ioh, EP_W1_TX_PIO_WR_1,
+ bus_space_write_1(iot, ioh, EP_W1_TX_PIO_WR_1,
*(mtod(m, u_int8_t *) + m->m_len - 1));
MFREE(m, m0);
m = m0;
}
}
while (pad--)
- bus_io_write_1(bc, ioh, EP_W1_TX_PIO_WR_1, 0);
+ bus_space_write_1(iot, ioh, EP_W1_TX_PIO_WR_1, 0);
splx(sh);
++ifp->if_opackets;
readcheck:
- if ((bus_io_read_2(bc, ioh, EP_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) {
+ if ((bus_space_read_2(iot, ioh, EP_W1_RX_STATUS) & ERR_INCOMPLETE) ==
+ 0) {
/* We received a complete packet. */
- u_int16_t status = bus_io_read_2(bc, ioh, EP_STATUS);
+ u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS);
if ((status & S_INTR_LATCH) == 0) {
/*
epread(sc);
}
else
- /* Got an interrupt, return so that it gets serviced. */
+ /* Got an interrupt, return to get it serviced. */
return;
}
else {
if (epstatus(sc)) {
if (ifp->if_flags & IFF_DEBUG)
printf("%s: adapter reset\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
epreset(sc);
}
}
epstatus(sc)
register struct ep_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
u_int16_t fifost;
/*
* Check the FIFO status and act accordingly
*/
GO_WINDOW(4);
- fifost = bus_io_read_2(bc, ioh, EP_W4_FIFO_DIAG);
+ fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG);
GO_WINDOW(1);
if (fifost & FIFOS_RX_UNDERRUN) {
eptxstat(sc)
register struct ep_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int i;
/*
* We need to read+write TX_STATUS until we get a 0 status
* in order to turn off the interrupt flag.
*/
- while ((i = bus_io_read_1(bc, ioh, EP_W1_TX_STATUS)) & TXS_COMPLETE) {
- bus_io_write_1(bc, ioh, EP_W1_TX_STATUS, 0x0);
+ while ((i = bus_space_read_1(iot, ioh, EP_W1_TX_STATUS)) &
+ TXS_COMPLETE) {
+ bus_space_write_1(iot, ioh, EP_W1_TX_STATUS, 0x0);
if (i & TXS_JABBER) {
++sc->sc_arpcom.ac_if.if_oerrors;
epreset(sc);
} else if (i & TXS_MAX_COLLISION) {
++sc->sc_arpcom.ac_if.if_collisions;
- bus_io_write_2(bc, ioh, EP_COMMAND, TX_ENABLE);
+ bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE);
sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
} else
sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
void *arg;
{
register struct ep_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
u_int16_t status;
int ret = 0;
for (;;) {
- bus_io_write_2(bc, ioh, EP_COMMAND, C_INTR_LATCH);
+ bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH);
- status = bus_io_read_2(bc, ioh, EP_STATUS);
+ status = bus_space_read_2(iot, ioh, EP_STATUS);
if ((status & (S_TX_COMPLETE | S_TX_AVAIL |
S_RX_COMPLETE | S_CARD_FAILURE)) == 0)
* Due to the i386 interrupt queueing, we may get spurious
* interrupts occasionally.
*/
- bus_io_write_2(bc, ioh, EP_COMMAND, ACK_INTR | status);
+ bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status);
if (status & S_RX_COMPLETE)
epread(sc);
}
if (status & S_CARD_FAILURE) {
printf("%s: adapter failure (%x)\n",
- sc->sc_dev.dv_xname, status);
+ sc->sc_dev.dv_xname, status);
epreset(sc);
return (1);
}
epread(sc)
register struct ep_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct mbuf *m;
struct ether_header *eh;
int len;
- len = bus_io_read_2(bc, ioh, EP_W1_RX_STATUS);
+ len = bus_space_read_2(iot, ioh, EP_W1_RX_STATUS);
again:
if (ifp->if_flags & IFF_DEBUG) {
* I'll modify epread() so that it can handle RX_EARLY interrupts.
*/
if (epstatus(sc)) {
- len = bus_io_read_2(bc, ioh, EP_W1_RX_STATUS);
+ len = bus_space_read_2(iot, ioh, EP_W1_RX_STATUS);
/* Check if we are stuck and reset [see XXX comment] */
if (len & ERR_INCOMPLETE) {
if (ifp->if_flags & IFF_DEBUG)
return;
abort:
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
- while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
+ while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
}
struct ep_softc *sc;
int totlen;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct mbuf *top, **mp, *m;
int len, pad;
if (EP_IS_BUS_32(sc->bustype)) {
if (len > 3) {
len &= ~3;
- bus_io_read_multi_4(bc, ioh,
+ bus_space_read_multi_4(iot, ioh,
EP_W1_RX_PIO_RD_1, mtod(m, u_int32_t *),
len / 4);
} else
- bus_io_read_multi_1(bc, ioh,
+ bus_space_read_multi_1(iot, ioh,
EP_W1_RX_PIO_RD_1, mtod(m, u_int8_t *),
len);
} else {
if (len > 1) {
len &= ~1;
- bus_io_read_multi_2(bc, ioh,
+ bus_space_read_multi_2(iot, ioh,
EP_W1_RX_PIO_RD_1, mtod(m, u_int16_t *),
len / 2);
} else
*(mtod(m, u_int8_t *)) =
- bus_io_read_1(bc, ioh, EP_W1_RX_PIO_RD_1);
+ bus_space_read_1(iot, ioh,
+ EP_W1_RX_PIO_RD_1);
}
m->m_len = len;
totlen -= len;
mp = &m->m_next;
}
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
- while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
+ while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
splx(sh);
epstop(sc)
register struct ep_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISABLE);
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
- while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE);
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
+ while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
- bus_io_write_2(bc, ioh, EP_COMMAND, TX_DISABLE);
- bus_io_write_2(bc, ioh, EP_COMMAND, STOP_TRANSCEIVER);
- bus_io_write_2(bc, ioh, EP_COMMAND, RX_RESET);
- bus_io_write_2(bc, ioh, EP_COMMAND, TX_RESET);
- bus_io_write_2(bc, ioh, EP_COMMAND, C_INTR_LATCH);
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_RD_0_MASK);
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_INTR_MASK);
- bus_io_write_2(bc, ioh, EP_COMMAND, SET_RX_FILTER);
+ bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE);
+ bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER);
+ bus_space_write_2(iot, ioh, EP_COMMAND, RX_RESET);
+ bus_space_write_2(iot, ioh, EP_COMMAND, TX_RESET);
+ bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH);
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK);
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK);
+ bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER);
epmbufempty(sc);
}
* each card compares the data on the bus; if there is a difference
* then that card goes into ID_WAIT state again). In the meantime;
* one bit of data is returned in the AX register which is conveniently
- * returned to us by bus_io_read_1(). Hence; we read 16 times getting one
+ * returned to us by bus_space_read_1(). Hence; we read 16 times getting one
* bit of data with each read.
*
* NOTE: the caller must provide an i/o handle for ELINK_ID_PORT!
*/
u_int16_t
-epreadeeprom(bc, ioh, offset)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+epreadeeprom(iot, ioh, offset)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int offset;
{
u_int16_t data = 0;
int i;
- bus_io_write_1(bc, ioh, 0, 0x80 + offset);
+ bus_space_write_1(iot, ioh, 0, 0x80 + offset);
delay(1000);
for (i = 0; i < 16; i++)
- data = (data << 1) | (bus_io_read_2(bc, ioh, 0) & 1);
+ data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1);
return (data);
}
epbusyeeprom(sc)
struct ep_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int i = 100, j;
while (i--) {
- j = bus_io_read_2(bc, ioh, EP_W0_EEPROM_COMMAND);
+ j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND);
if (j & EEPROM_BUSY)
delay(100);
else
-/* $OpenBSD: elink3reg.h,v 1.5 1996/10/31 01:01:29 niklas Exp $ */
-/* $NetBSD: elink3reg.h,v 1.3 1996/05/10 05:28:09 thorpej Exp $ */
+/* $OpenBSD: elink3reg.h,v 1.6 1996/11/28 23:27:50 niklas Exp $ */
+/* $NetBSD: elink3reg.h,v 1.5 1996/10/21 22:34:23 thorpej Exp $ */
/*
* Copyright (c) 1995 Herb Peyerl <hpeyerl@beer.org>
#define EP_W7_TX_STATUS 0x0b
#define EP_W7_MASTER_STATUS 0x0c
+/*
+ * Window 7 registers.
+ * Address and length for a single bus-master DMA transfer.
+ */
+#define EP_W7_MASTER_ADDDRES 0x00
+#define EP_W7_RX_ERROR 0x04
+#define EP_W7_MASTER_LEN 0x06
+#define EP_W7_RX_STATUS 0x08
+#define EP_W7_TIMER 0x0a
+#define EP_W7_TX_STATUS 0x0b
+#define EP_W7_MASTER_STATUS 0x0c
+
/*
* Register definitions.
*/
#define ENABLE_DRQ_IRQ 0x0001
#define MFG_ID 0x506d /* `TCM' */
#define PROD_ID 0x5090
-#define GO_WINDOW(x) bus_io_write_2(sc->sc_bc, \
+#define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \
sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x)
#define AUI 0x1
#define BNC 0x2
-/* $OpenBSD: elink3var.h,v 1.6 1996/10/31 01:01:29 niklas Exp $ */
-/* $NetBSD: elink3var.h,v 1.5 1996/05/14 22:22:06 thorpej Exp $ */
+/* $OpenBSD: elink3var.h,v 1.7 1996/11/28 23:27:51 niklas Exp $ */
+/* $NetBSD: elink3var.h,v 1.6 1996/10/21 22:34:25 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
void *sc_ih;
struct arpcom sc_arpcom; /* Ethernet common part */
- bus_chipset_tag_t sc_bc; /* bus cookie */
- bus_io_handle_t sc_ioh; /* bus i/o handle */
+ bus_space_tag_t sc_iot; /* bus cookie */
+ bus_space_handle_t sc_ioh; /* bus i/o handle */
#define MAX_MBS 8 /* # of mbufs we keep around */
struct mbuf *mb[MAX_MBS]; /* spare mbuf storage. */
int next_mb; /* Which mbuf to use next. */
#define EP_ABSENT 0x02
};
-u_int16_t epreadeeprom __P((bus_chipset_tag_t, bus_io_handle_t, int));
+u_int16_t epreadeeprom __P((bus_space_tag_t, bus_space_handle_t, int));
void epconfig __P((struct ep_softc *, u_int16_t));
int epintr __P((void *));
void epstop __P((struct ep_softc *));
-/* $OpenBSD: ncr5380sbc.c,v 1.6 1996/05/26 00:27:01 deraadt Exp $ */
-/* $NetBSD: ncr5380sbc.c,v 1.11 1996/05/13 14:10:21 christos Exp $ */
+/* $OpenBSD: ncr5380sbc.c,v 1.7 1996/11/28 23:27:51 niklas Exp $ */
+/* $NetBSD: ncr5380sbc.c,v 1.13 1996/10/13 01:37:25 christos Exp $ */
/*
* Copyright (c) 1995 David Jones, Gordon W. Ross
sc = sc_link->adapter_softc;
printf("%s: cmd timeout, targ=%d, lun=%d\n",
- sc->sc_dev.dv_xname,
- sr->sr_target, sr->sr_lun);
+ sc->sc_dev.dv_xname,
+ sr->sr_target, sr->sr_lun);
/*
* Mark the overdue job as failed, and arrange for
sr = sc->sc_current;
if (sr) {
printf("%s: polled request aborting %d/%d\n",
- sc->sc_dev.dv_xname,
- sr->sr_target, sr->sr_lun);
+ sc->sc_dev.dv_xname,
+ sr->sr_target, sr->sr_lun);
ncr5380_abort(sc);
}
if (sc->sc_state != NCR_IDLE) {
/* fallthrough */
default:
printf("%s: target %d, bad status=%d\n",
- sc->sc_dev.dv_xname, sr->sr_target, sr->sr_status);
+ sc->sc_dev.dv_xname, sr->sr_target, sr->sr_status);
xs->error = XS_DRIVER_STUFFUP;
break;
}
/* Work with the reselected job. */
if (sr->sr_flags & SR_IMMED) {
printf("%s: reselected while polling (abort)\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
/* Abort the reselected job. */
sc->sc_state |= NCR_ABORTING;
sc->sc_msgpriq |= SEND_ABORT;
case XS_BUSY:
/* XXX - Reset and try again. */
printf("%s: select found SCSI bus busy, resetting...\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
ncr5380_reset_scsibus(sc);
/* fallthrough */
case XS_SELTIMEOUT:
#ifdef NCR5380_DEBUG
if (ncr5380_debug & NCR_DBG_CMDS) {
printf("ncr5380_sched: begin, target=%d, LUN=%d\n",
- xs->sc_link->target, xs->sc_link->lun);
+ xs->sc_link->target, xs->sc_link->lun);
ncr5380_show_scsi_cmd(xs);
}
#endif
/* Probably never get here... */
if (--timo <= 0) {
printf("%s: reselect, BSY stuck, bus=0x%x\n",
- sc->sc_dev.dv_xname, bus);
+ sc->sc_dev.dv_xname, bus);
/* Not much we can do. Reset the bus. */
ncr5380_reset_scsibus(sc);
return;
*/
if ((bus & SCI_BUS_IO) == 0) {
printf("%s: selected as target, data=0x%x\n",
- sc->sc_dev.dv_xname, data);
+ sc->sc_dev.dv_xname, data);
/* Not much we can do. Reset the bus. */
/* XXX: send some sort of message? */
ncr5380_reset_scsibus(sc);
if ((data & 0x7F) != target_mask) {
/* No selecting ID? or >2 IDs on bus? */
printf("%s: bad reselect, data=0x%x\n",
- sc->sc_dev.dv_xname, data);
+ sc->sc_dev.dv_xname, data);
return;
}
break; /* success */
if (--timo <= 0) {
printf("%s: reselect, SEL stuck, bus=0x%x\n",
- sc->sc_dev.dv_xname, bus);
+ sc->sc_dev.dv_xname, bus);
NCR_BREAK();
/* assume connected (fail later if not) */
break;
/* Wait for REQ before reading bus phase. */
if (ncr5380_wait_req(sc)) {
printf("%s: reselect, no REQ\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
/* Try to send an ABORT message. */
goto abort;
}
phase = SCI_BUS_PHASE(*sc->sci_bus_csr);
if (phase != PHASE_MSG_IN) {
printf("%s: reselect, phase=%d\n",
- sc->sc_dev.dv_xname, phase);
+ sc->sc_dev.dv_xname, phase);
goto abort;
}
msg = *(sc->sci_data);
if ((msg & 0x80) == 0) {
printf("%s: reselect, not identify, msg=%d\n",
- sc->sc_dev.dv_xname, msg);
+ sc->sc_dev.dv_xname, msg);
goto abort;
}
lun = msg & 7;
}
printf("%s: phantom reselect: target=%d, LUN=%d\n",
- sc->sc_dev.dv_xname, target, lun);
+ sc->sc_dev.dv_xname, target, lun);
abort:
/*
* Try to send an ABORT message. This makes us
goto reject;
default:
printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
NCR_BREAK();
goto reject;
}
default:
NCR_TRACE("msg_in: eh? imsg=0x%x\n", sc->sc_imess[0]);
printf("%s: unrecognized MESSAGE; sending REJECT\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
NCR_BREAK();
/* fallthrough */
reject:
NCR_TRACE("msg_out: SEND_IDENTIFY\n", 0);
if (sr == NULL) {
printf("%s: SEND_IDENTIFY while not connected; sending NOOP\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
NCR_BREAK();
goto noop;
}
case 0:
printf("%s: unexpected MESSAGE OUT; sending NOOP\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
NCR_BREAK();
noop:
NCR_TRACE("msg_out: send NOOP\n", 0);
default:
printf("%s: weird MESSAGE OUT; sending NOOP\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
NCR_BREAK();
goto noop;
}
if (len != xs->cmdlen) {
#ifdef NCR5380_DEBUG
printf("ncr5380_command: short transfer: wanted %d got %d.\n",
- xs->cmdlen, len);
+ xs->cmdlen, len);
ncr5380_show_scsi_cmd(xs);
NCR_BREAK();
#endif
*/
if (sc->sc_state & NCR_ABORTING) {
printf("%s: aborting, but phase=%s (reset)\n",
- sc->sc_dev.dv_xname,
- phase_names[phase & 7]);
+ sc->sc_dev.dv_xname, phase_names[phase & 7]);
return ACT_RESET_BUS; /* XXX */
}
expected_phase = (xs->flags & SCSI_DATA_OUT) ?
PHASE_DATA_OUT : PHASE_DATA_IN;
if (phase != expected_phase) {
- printf("%s: data phase error\n",
- sc->sc_dev.dv_xname);
+ printf("%s: data phase error\n", sc->sc_dev.dv_xname);
goto abort;
}
/* Make sure we have some data to move. */
if (sc->sc_datalen <= 0) {
printf("%s: can not transfer more data\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
goto abort;
}
if (--timo <= 0) {
if (sc->sc_state & NCR_ABORTING) {
printf("%s: no REQ while aborting, reset\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
act_flags |= ACT_RESET_BUS;
goto do_actions;
}
printf("%s: no REQ for next phase, abort\n",
- sc->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
sc->sc_state |= NCR_ABORTING;
ncr_sched_msgout(sc, SEND_ABORT);
goto next_phase;
* XXX - better place to check?
*/
if (*(sc->sci_csr) & SCI_CSR_PERR) {
- printf("%s: parity error!\n",
- sc->sc_dev.dv_xname);
+ printf("%s: parity error!\n", sc->sc_dev.dv_xname);
/* XXX: sc->sc_state |= NCR_ABORTING; */
ncr_sched_msgout(sc, SEND_PARITY_ERROR);
}
*/
sc->sc_state |= NCR_ABORTING;
printf("%s: reset SCSI bus for TID=%d LUN=%d\n",
- sc->sc_dev.dv_xname,
- sr->sr_target, sr->sr_lun);
+ sc->sc_dev.dv_xname, sr->sr_target, sr->sr_lun);
ncr5380_reset_scsibus(sc);
}
/* XXX: from the aic6360 driver, but why? */
if (sc->sc_datalen < 0) {
printf("%s: %d extra bytes from %d:%d\n",
- sc->sc_dev.dv_xname, -sc->sc_datalen,
- sr->sr_target, sr->sr_lun);
+ sc->sc_dev.dv_xname, -sc->sc_datalen,
+ sr->sr_target, sr->sr_lun);
sc->sc_datalen = 0;
}
xs->resid = sc->sc_datalen;
}
/* Device is sitting on the bus! */
printf("%s: Target %d LUN %d stuck busy, resetting...\n",
- sc->sc_dev.dv_xname,
- sr->sr_target, sr->sr_lun);
+ sc->sc_dev.dv_xname, sr->sr_target, sr->sr_lun);
ncr5380_reset_scsibus(sc);
busfree:
NCR_TRACE("machine: discon, waited %d\n",
if ( ! ( xs->flags & SCSI_RESET ) ) {
printf("si(%d:%d:%d)-",
- xs->sc_link->scsibus,
- xs->sc_link->target,
- xs->sc_link->lun);
+ xs->sc_link->scsibus, xs->sc_link->target,
+ xs->sc_link->lun);
while (i < xs->cmdlen) {
if (i) printf(",");
printf("%x",b[i++]);
printf("-\n");
} else {
printf("si(%d:%d:%d)-RESET-\n",
- xs->sc_link->scsibus,
- xs->sc_link->target,
- xs->sc_link->lun);
+ xs->sc_link->scsibus, xs->sc_link->target,
+ xs->sc_link->lun);
}
}
-/* $OpenBSD: pdqvar.h,v 1.9 1996/11/12 20:30:22 niklas Exp $ */
-/* $NetBSD: pdqvar.h,v 1.8 1996/07/10 18:55:05 cgd Exp $ */
+/* $OpenBSD: pdqvar.h,v 1.10 1996/11/28 23:27:52 niklas Exp $ */
+/* $NetBSD: pdqvar.h,v 1.11 1996/10/25 21:33:37 cgd Exp $ */
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
#define PDQ_OS_USEC_DELAY(n) DELAY(n)
#define PDQ_OS_MEMZERO(p, n) bzero((caddr_t)(p), (n))
#if (defined(__NetBSD__) || defined(__OpenBSD__)) && defined(__alpha__)
-#define PDQ_OS_VA_TO_PA(pdq, p) (vtophys((vm_offset_t)p) | (pdq->pdq_type == PDQ_DEFTA ? 0 : 0x40000000))
+#define PDQ_OS_VA_TO_PA(pdq, p) (alpha_XXX_dmamap((vm_offset_t)p))
#else
#define PDQ_OS_VA_TO_PA(pdq, p) vtophys(p)
#endif
#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#define PDQ_OS_PTR_FMT "%p"
typedef void ifnet_ret_t;
typedef u_long ioctl_cmd_t;
-typedef bus_chipset_tag_t pdq_bus_t;
-typedef bus_io_handle_t pdq_bus_ioport_t;
-#if defined(PDQ_IOMAPPED)
-typedef bus_io_handle_t pdq_bus_memaddr_t;
-#else
-typedef bus_mem_handle_t pdq_bus_memaddr_t;
-#endif
+typedef bus_space_tag_t pdq_bus_t;
+typedef bus_space_handle_t pdq_bus_ioport_t;
+typedef bus_space_handle_t pdq_bus_memaddr_t;
typedef pdq_uint32_t pdq_bus_memoffset_t;
#define PDQ_OS_IOMEM
-#define PDQ_OS_IORD_32(t, base, offset) bus_io_read_4 (t, base, offset)
-#define PDQ_OS_IOWR_32(t, base, offset, data) bus_io_write_4 (t, base, offset, data)
-#define PDQ_OS_IORD_8(t, base, offset) bus_io_read_1 (t, base, offset)
-#define PDQ_OS_IOWR_8(t, base, offset, data) bus_io_write_1 (t, base, offset, data)
-#define PDQ_OS_MEMRD_32(t, base, offset) bus_mem_read_4(t, base, offset)
-#define PDQ_OS_MEMWR_32(t, base, offset, data) bus_mem_write_4(t, base, offset, data)
+#define PDQ_OS_IORD_32(t, base, offset) bus_space_read_4 (t, base, offset)
+#define PDQ_OS_IOWR_32(t, base, offset, data) bus_space_write_4 (t, base, offset, data)
+#define PDQ_OS_IORD_8(t, base, offset) bus_space_read_1 (t, base, offset)
+#define PDQ_OS_IOWR_8(t, base, offset, data) bus_space_write_1 (t, base, offset, data)
+#define PDQ_OS_MEMRD_32(t, base, offset) bus_space_read_4(t, base, offset)
+#define PDQ_OS_MEMWR_32(t, base, offset, data) bus_space_write_4(t, base, offset, data)
#define PDQ_CSR_OFFSET(base, offset) (0 + (offset)*sizeof(pdq_uint32_t))
#if defined(PDQ_IOMAPPED)
struct device sc_dev; /* base device */
void *sc_ih; /* interrupt vectoring */
void *sc_ats; /* shutdown hook */
+ bus_space_tag_t sc_csrtag; /* space tag for CSRs */
+ bus_space_handle_t sc_csrhandle; /* space handle for CSRs */
+#define sc_bc sc_csrtag
+#define sc_membase sc_csrhandle
+ bus_space_tag_t sc_iotag; /* i/o space tag */
+ bus_space_handle_t sc_iobase; /* i/o space handle */
#elif defined(__FreeBSD__)
struct kern_devconf *sc_kdc; /* freebsd cruft */
#endif
struct arpcom sc_ac;
#define sc_if sc_ac.ac_if
pdq_t *sc_pdq;
-#if defined(__alpha__) || defined(__i386__)
+#if !defined(__NetBSD__) && !defined(__OpenBSD__)
pdq_bus_ioport_t sc_iobase;
-#endif
#ifdef PDQ_IOMAPPED
#define sc_membase sc_iobase
#else
pdq_bus_memaddr_t sc_membase;
#endif
pdq_bus_t sc_bc;
+#endif /* ! __NetBSD__ && ! __OpenBSD__ */
#if !defined(__bsdi__) || _BSDI_VERSION >= 199401
#define sc_bpf sc_if.if_bpf
#else
-/* $OpenBSD: smc93cx6.c,v 1.5 1996/11/12 20:30:23 niklas Exp $ */
+/* $OpenBSD: smc93cx6.c,v 1.6 1996/11/28 23:27:53 niklas Exp $ */
+/* $NetBSD: smc93cx6.c,v 1.5 1996/10/21 22:34:38 thorpej Exp $ */
/*
* Interface for the 93C46/26/06 serial eeprom parts.
#include <machine/clock.h>
#include <i386/scsi/93cx6.h>
#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/ic/smc93cx6var.h>
#endif
u_int start_addr;
int count;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- bus_io_size_t start_addr;
- bus_io_size_t count;
+ bus_size_t start_addr;
+ bus_size_t count;
#endif
{
int i = 0, k = 0;
-/* $OpenBSD: smc93cx6var.h,v 1.4 1996/10/31 01:01:41 niklas Exp $ */
+/* $OpenBSD: smc93cx6var.h,v 1.5 1996/11/28 23:27:53 niklas Exp $ */
+/* $NetBSD: smc93cx6var.h,v 1.3 1996/10/21 22:34:41 thorpej Exp $ */
+
/*
* Interface to the 93C46 serial EEPROM that is used to store BIOS
* settings for the aic7xxx based adaptec SCSI controllers. It can
#if defined(__FreeBSD__)
u_long sd_iobase;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- bus_chipset_tag_t sd_bc;
- bus_io_handle_t sd_ioh;
- bus_io_size_t sd_offset;
+ bus_space_tag_t sd_iot;
+ bus_space_handle_t sd_ioh;
+ bus_size_t sd_offset;
#endif
u_int16_t sd_MS;
u_int16_t sd_RDY;
#define SEEPROM_OUTB(sd, value) outb(sd->sd_iobase, value)
#elif defined(__NetBSD__) || defined(__OpenBSD__)
#define SEEPROM_INB(sd) \
- bus_io_read_1(sd->sd_bc, sd->sd_ioh, sd->sd_offset)
+ bus_space_read_1(sd->sd_iot, sd->sd_ioh, sd->sd_offset)
#define SEEPROM_OUTB(sd, value) \
- bus_io_write_1(sd->sd_bc, sd->sd_ioh, sd->sd_offset, value)
+ bus_space_write_1(sd->sd_iot, sd->sd_ioh, sd->sd_offset, value)
#endif
#if defined(__FreeBSD__)
u_int16_t *buf, u_int start_addr, int count));
#elif defined(__NetBSD__) || defined(__OpenBSD__)
int read_seeprom __P((struct seeprom_descriptor *sd,
- u_int16_t *buf, bus_io_size_t start_addr, bus_io_size_t count));
+ u_int16_t *buf, bus_size_t start_addr, bus_size_t count));
#endif
--- /dev/null
+/* $OpenBSD: uha.c,v 1.1 1996/11/28 23:27:54 niklas Exp $ */
+/* $NetBSD: uha.c,v 1.3 1996/10/13 01:37:29 christos Exp $ */
+
+#undef UHADEBUG
+#ifdef DDB
+#define integrate
+#else
+#define integrate static inline
+#endif
+
+/*
+ * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu)
+ * Slight fixes to timeouts to run with the 34F
+ * Thanks to Julian Elischer for advice and help with this port.
+ *
+ * Originally written by Julian Elischer (julian@tfs.com)
+ * for TRW Financial Systems for use under the MACH(2.5) operating system.
+ *
+ * TRW Financial Systems, in accordance with their agreement with Carnegie
+ * Mellon University, makes this software available to CMU to distribute
+ * or use in any manner that they see fit as long as this message is kept with
+ * the software. For this reason TFS also grants any other persons or
+ * organisations permission to use or modify this software.
+ *
+ * TFS supplies this software to be publicly redistributed
+ * on the understanding that TFS is not responsible for the correct
+ * functioning of this software in any circumstances.
+ *
+ * commenced: Sun Sep 27 18:14:01 PDT 1992
+ * slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/buf.h>
+#include <sys/proc.h>
+#include <sys/user.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/ic/uhareg.h>
+#include <dev/ic/uhavar.h>
+
+#ifndef DDB
+#define Debugger() panic("should call debugger here (ultra14f.c)")
+#endif /* ! DDB */
+
+#define KVTOPHYS(x) vtophys(x)
+
+void uha_reset_mscp __P((struct uha_softc *, struct uha_mscp *));
+void uha_free_mscp __P((struct uha_softc *, struct uha_mscp *));
+void uha_init_mscp __P((struct uha_softc *, struct uha_mscp *));
+struct uha_mscp *uha_get_mscp __P((struct uha_softc *, int));
+void uhaminphys __P((struct buf *));
+int uha_scsi_cmd __P((struct scsi_xfer *));
+
+struct scsi_adapter uha_switch = {
+ uha_scsi_cmd,
+ uhaminphys,
+ 0,
+ 0,
+};
+
+/* the below structure is so we have a default dev struct for out link struct */
+struct scsi_device uha_dev = {
+ NULL, /* Use default error handler */
+ NULL, /* have a queue, served by this */
+ NULL, /* have no async handler */
+ NULL, /* Use default 'done' routine */
+};
+
+struct cfdriver uha_cd = {
+ NULL, "uha", DV_DULL
+};
+
+#define UHA_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
+
+#ifdef __OpenBSD__
+int uhaprint __P((void *, const char *));
+
+int
+uhaprint(aux, name)
+ void *aux;
+ const char *name;
+{
+
+ if (name != NULL)
+ printf("%s: scsibus ", name);
+ return UNCONF;
+}
+#endif
+
+/*
+ * Attach all the sub-devices we can find
+ */
+void
+uha_attach(sc)
+ struct uha_softc *sc;
+{
+
+ (sc->init)(sc);
+ TAILQ_INIT(&sc->sc_free_mscp);
+
+ /*
+ * fill in the prototype scsi_link.
+ */
+#ifndef __OpenBSD__
+ sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE;
+#endif
+ sc->sc_link.adapter_softc = sc;
+ sc->sc_link.adapter_target = sc->sc_scsi_dev;
+ sc->sc_link.adapter = &uha_switch;
+ sc->sc_link.device = &uha_dev;
+ sc->sc_link.openings = 2;
+
+ /*
+ * ask the adapter what subunits are present
+ */
+#ifdef __OpenBSD__
+ config_found(&sc->sc_dev, &sc->sc_link, uhaprint);
+#else
+ config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
+#endif
+}
+
+integrate void
+uha_reset_mscp(sc, mscp)
+ struct uha_softc *sc;
+ struct uha_mscp *mscp;
+{
+
+ mscp->flags = 0;
+}
+
+/*
+ * A mscp (and hence a mbx-out) is put onto the free list.
+ */
+void
+uha_free_mscp(sc, mscp)
+ struct uha_softc *sc;
+ struct uha_mscp *mscp;
+{
+ int s;
+
+ s = splbio();
+
+ uha_reset_mscp(sc, mscp);
+ TAILQ_INSERT_HEAD(&sc->sc_free_mscp, mscp, chain);
+
+ /*
+ * If there were none, wake anybody waiting for one to come free,
+ * starting with queued entries.
+ */
+ if (mscp->chain.tqe_next == 0)
+ wakeup(&sc->sc_free_mscp);
+
+ splx(s);
+}
+
+integrate void
+uha_init_mscp(sc, mscp)
+ struct uha_softc *sc;
+ struct uha_mscp *mscp;
+{
+ int hashnum;
+
+ bzero(mscp, sizeof(struct uha_mscp));
+ /*
+ * put in the phystokv hash table
+ * Never gets taken out.
+ */
+ mscp->hashkey = KVTOPHYS(mscp);
+ hashnum = MSCP_HASH(mscp->hashkey);
+ mscp->nexthash = sc->sc_mscphash[hashnum];
+ sc->sc_mscphash[hashnum] = mscp;
+ uha_reset_mscp(sc, mscp);
+}
+
+/*
+ * Get a free mscp
+ *
+ * If there are none, see if we can allocate a new one. If so, put it in the
+ * hash table too otherwise either return an error or sleep.
+ */
+struct uha_mscp *
+uha_get_mscp(sc, flags)
+ struct uha_softc *sc;
+ int flags;
+{
+ struct uha_mscp *mscp;
+ int s;
+
+ s = splbio();
+
+ /*
+ * If we can and have to, sleep waiting for one to come free
+ * but only if we can't allocate a new one
+ */
+ for (;;) {
+ mscp = sc->sc_free_mscp.tqh_first;
+ if (mscp) {
+ TAILQ_REMOVE(&sc->sc_free_mscp, mscp, chain);
+ break;
+ }
+ if (sc->sc_nummscps < UHA_MSCP_MAX) {
+ mscp = (struct uha_mscp *) malloc(sizeof(struct uha_mscp),
+ M_TEMP, M_NOWAIT);
+ if (!mscp) {
+ printf("%s: can't malloc mscp\n",
+ sc->sc_dev.dv_xname);
+ goto out;
+ }
+ uha_init_mscp(sc, mscp);
+ sc->sc_nummscps++;
+ break;
+ }
+ if ((flags & SCSI_NOSLEEP) != 0)
+ goto out;
+ tsleep(&sc->sc_free_mscp, PRIBIO, "uhamsc", 0);
+ }
+
+ mscp->flags |= MSCP_ALLOC;
+
+out:
+ splx(s);
+ return (mscp);
+}
+
+/*
+ * given a physical address, find the mscp that it corresponds to.
+ */
+struct uha_mscp *
+uha_mscp_phys_kv(sc, mscp_phys)
+ struct uha_softc *sc;
+ u_long mscp_phys;
+{
+ int hashnum = MSCP_HASH(mscp_phys);
+ struct uha_mscp *mscp = sc->sc_mscphash[hashnum];
+
+ while (mscp) {
+ if (mscp->hashkey == mscp_phys)
+ break;
+ mscp = mscp->nexthash;
+ }
+ return (mscp);
+}
+
+/*
+ * We have a mscp which has been processed by the adaptor, now we look to see
+ * how the operation went.
+ */
+void
+uha_done(sc, mscp)
+ struct uha_softc *sc;
+ struct uha_mscp *mscp;
+{
+ struct scsi_sense_data *s1, *s2;
+ struct scsi_xfer *xs = mscp->xs;
+
+ SC_DEBUG(xs->sc_link, SDEV_DB2, ("uha_done\n"));
+ /*
+ * Otherwise, put the results of the operation
+ * into the xfer and call whoever started it
+ */
+ if ((mscp->flags & MSCP_ALLOC) == 0) {
+ printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
+ Debugger();
+ return;
+ }
+ if (xs->error == XS_NOERROR) {
+ if (mscp->host_stat != UHA_NO_ERR) {
+ switch (mscp->host_stat) {
+ case UHA_SBUS_TIMEOUT: /* No response */
+ xs->error = XS_SELTIMEOUT;
+ break;
+ default: /* Other scsi protocol messes */
+ printf("%s: host_stat %x\n",
+ sc->sc_dev.dv_xname, mscp->host_stat);
+ xs->error = XS_DRIVER_STUFFUP;
+ }
+ } else if (mscp->target_stat != SCSI_OK) {
+ switch (mscp->target_stat) {
+ case SCSI_CHECK:
+ s1 = &mscp->mscp_sense;
+ s2 = &xs->sense;
+ *s2 = *s1;
+ xs->error = XS_SENSE;
+ break;
+ case SCSI_BUSY:
+ xs->error = XS_BUSY;
+ break;
+ default:
+ printf("%s: target_stat %x\n",
+ sc->sc_dev.dv_xname, mscp->target_stat);
+ xs->error = XS_DRIVER_STUFFUP;
+ }
+ } else
+ xs->resid = 0;
+ }
+ uha_free_mscp(sc, mscp);
+ xs->flags |= ITSDONE;
+ scsi_done(xs);
+}
+
+void
+uhaminphys(bp)
+ struct buf *bp;
+{
+
+ if (bp->b_bcount > ((UHA_NSEG - 1) << PGSHIFT))
+ bp->b_bcount = ((UHA_NSEG - 1) << PGSHIFT);
+ minphys(bp);
+}
+
+/*
+ * start a scsi operation given the command and the data address. Also
+ * needs the unit, target and lu.
+ */
+int
+uha_scsi_cmd(xs)
+ struct scsi_xfer *xs;
+{
+ struct scsi_link *sc_link = xs->sc_link;
+ struct uha_softc *sc = sc_link->adapter_softc;
+ struct uha_mscp *mscp;
+ struct uha_dma_seg *sg;
+ int seg; /* scatter gather seg being worked on */
+ u_long thiskv, thisphys, nextphys;
+ int bytes_this_seg, bytes_this_page, datalen, flags;
+ int s;
+
+ SC_DEBUG(sc_link, SDEV_DB2, ("uha_scsi_cmd\n"));
+ /*
+ * get a mscp (mbox-out) to use. If the transfer
+ * is from a buf (possibly from interrupt time)
+ * then we can't allow it to sleep
+ */
+ flags = xs->flags;
+ if ((mscp = uha_get_mscp(sc, flags)) == NULL) {
+ xs->error = XS_DRIVER_STUFFUP;
+ return (TRY_AGAIN_LATER);
+ }
+ mscp->xs = xs;
+ mscp->timeout = xs->timeout;
+
+ /*
+ * Put all the arguments for the xfer in the mscp
+ */
+ if (flags & SCSI_RESET) {
+ mscp->opcode = UHA_SDR;
+ mscp->ca = 0x01;
+ } else {
+ mscp->opcode = UHA_TSP;
+ /* XXX Not for tapes. */
+ mscp->ca = 0x01;
+ bcopy(xs->cmd, &mscp->scsi_cmd, mscp->scsi_cmd_length);
+ }
+ mscp->xdir = UHA_SDET;
+ mscp->dcn = 0x00;
+ mscp->chan = 0x00;
+ mscp->target = sc_link->target;
+ mscp->lun = sc_link->lun;
+ mscp->scsi_cmd_length = xs->cmdlen;
+ mscp->sense_ptr = KVTOPHYS(&mscp->mscp_sense);
+ mscp->req_sense_length = sizeof(mscp->mscp_sense);
+ mscp->host_stat = 0x00;
+ mscp->target_stat = 0x00;
+
+ if (xs->datalen) {
+ sg = mscp->uha_dma;
+ seg = 0;
+#ifdef TFS
+ if (flags & SCSI_DATA_UIO) {
+ struct iovec *iovp;
+ iovp = ((struct uio *) xs->data)->uio_iov;
+ datalen = ((struct uio *) xs->data)->uio_iovcnt;
+ xs->datalen = 0;
+ while (datalen && seg < UHA_NSEG) {
+ sg->seg_addr = (physaddr)iovp->iov_base;
+ sg->seg_len = iovp->iov_len;
+ xs->datalen += iovp->iov_len;
+ SC_DEBUGN(sc_link, SDEV_DB4, ("(0x%x@0x%x)",
+ iovp->iov_len, iovp->iov_base));
+ sg++;
+ iovp++;
+ seg++;
+ datalen--;
+ }
+ } else
+#endif /*TFS */
+ {
+ /*
+ * Set up the scatter gather block
+ */
+ SC_DEBUG(sc_link, SDEV_DB4,
+ ("%d @0x%x:- ", xs->datalen, xs->data));
+ datalen = xs->datalen;
+ thiskv = (int) xs->data;
+ thisphys = KVTOPHYS(thiskv);
+
+ while (datalen && seg < UHA_NSEG) {
+ bytes_this_seg = 0;
+
+ /* put in the base address */
+ sg->seg_addr = thisphys;
+
+ SC_DEBUGN(sc_link, SDEV_DB4, ("0x%x", thisphys));
+
+ /* do it at least once */
+ nextphys = thisphys;
+ while (datalen && thisphys == nextphys) {
+ /*
+ * This page is contiguous (physically)
+ * with the the last, just extend the
+ * length
+ */
+ /* how far to the end of the page */
+ nextphys = (thisphys & ~PGOFSET) + NBPG;
+ bytes_this_page = nextphys - thisphys;
+ /**** or the data ****/
+ bytes_this_page = min(bytes_this_page,
+ datalen);
+ bytes_this_seg += bytes_this_page;
+ datalen -= bytes_this_page;
+
+ /* get more ready for the next page */
+ thiskv = (thiskv & ~PGOFSET) + NBPG;
+ if (datalen)
+ thisphys = KVTOPHYS(thiskv);
+ }
+ /*
+ * next page isn't contiguous, finish the seg
+ */
+ SC_DEBUGN(sc_link, SDEV_DB4,
+ ("(0x%x)", bytes_this_seg));
+ sg->seg_len = bytes_this_seg;
+ sg++;
+ seg++;
+ }
+ }
+ /* end of iov/kv decision */
+ SC_DEBUGN(sc_link, SDEV_DB4, ("\n"));
+ if (datalen) {
+ /*
+ * there's still data, must have run out of segs!
+ */
+ printf("%s: uha_scsi_cmd, more than %d dma segs\n",
+ sc->sc_dev.dv_xname, UHA_NSEG);
+ goto bad;
+ }
+ mscp->data_addr = KVTOPHYS(mscp->uha_dma);
+ mscp->data_length = xs->datalen;
+ mscp->sgth = 0x01;
+ mscp->sg_num = seg;
+ } else { /* No data xfer, use non S/G values */
+ mscp->data_addr = (physaddr)0;
+ mscp->data_length = 0;
+ mscp->sgth = 0x00;
+ mscp->sg_num = 0;
+ }
+ mscp->link_id = 0;
+ mscp->link_addr = (physaddr)0;
+
+ s = splbio();
+ (sc->start_mbox)(sc, mscp);
+ splx(s);
+
+ /*
+ * Usually return SUCCESSFULLY QUEUED
+ */
+ if ((flags & SCSI_POLL) == 0)
+ return (SUCCESSFULLY_QUEUED);
+
+ /*
+ * If we can't use interrupts, poll on completion
+ */
+ if ((sc->poll)(sc, xs, mscp->timeout)) {
+ uha_timeout(mscp);
+ if ((sc->poll)(sc, xs, mscp->timeout))
+ uha_timeout(mscp);
+ }
+ return (COMPLETE);
+
+bad:
+ xs->error = XS_DRIVER_STUFFUP;
+ uha_free_mscp(sc, mscp);
+ return (COMPLETE);
+}
+
+void
+uha_timeout(arg)
+ void *arg;
+{
+ struct uha_mscp *mscp = arg;
+ struct scsi_xfer *xs = mscp->xs;
+ struct scsi_link *sc_link = xs->sc_link;
+ struct uha_softc *sc = sc_link->adapter_softc;
+ int s;
+
+ sc_print_addr(sc_link);
+ printf("timed out");
+
+ s = splbio();
+
+ if (mscp->flags & MSCP_ABORT) {
+ /* abort timed out */
+ printf(" AGAIN\n");
+ /* XXX Must reset! */
+ } else {
+ /* abort the operation that has timed out */
+ printf("\n");
+ mscp->xs->error = XS_TIMEOUT;
+ mscp->timeout = UHA_ABORT_TIMEOUT;
+ mscp->flags |= MSCP_ABORT;
+ (sc->start_mbox)(sc, mscp);
+ }
+
+ splx(s);
+}
--- /dev/null
+/* $OpenBSD: uhareg.h,v 1.1 1996/11/28 23:27:54 niklas Exp $ */
+/* $NetBSD: uhareg.h,v 1.2 1996/09/01 00:54:41 mycroft Exp $ */
+
+/*
+ * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu)
+ * Slight fixes to timeouts to run with the 34F
+ * Thanks to Julian Elischer for advice and help with this port.
+ *
+ * Originally written by Julian Elischer (julian@tfs.com)
+ * for TRW Financial Systems for use under the MACH(2.5) operating system.
+ *
+ * TRW Financial Systems, in accordance with their agreement with Carnegie
+ * Mellon University, makes this software available to CMU to distribute
+ * or use in any manner that they see fit as long as this message is kept with
+ * the software. For this reason TFS also grants any other persons or
+ * organisations permission to use or modify this software.
+ *
+ * TFS supplies this software to be publicly redistributed
+ * on the understanding that TFS is not responsible for the correct
+ * functioning of this software in any circumstances.
+ *
+ * commenced: Sun Sep 27 18:14:01 PDT 1992
+ * slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993
+ */
+
+typedef u_long physaddr;
+typedef u_long physlen;
+
+/************************** board definitions *******************************/
+/*
+ * I/O Port Interface
+ */
+#define U14_LMASK 0x0000 /* local doorbell mask reg */
+#define U14_LINT 0x0001 /* local doorbell int/stat reg */
+#define U14_SMASK 0x0002 /* system doorbell mask reg */
+#define U14_SINT 0x0003 /* system doorbell int/stat reg */
+#define U14_ID 0x0004 /* product id reg (2 ports) */
+#define U14_CONFIG 0x0006 /* config reg (2 ports) */
+#define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */
+#define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */
+
+#define U24_CONFIG 0x0005 /* config reg (3 ports) */
+#define U24_LMASK 0x000c /* local doorbell mask reg */
+#define U24_LINT 0x000d /* local doorbell int/stat reg */
+#define U24_SMASK 0x000e /* system doorbell mask reg */
+#define U24_SINT 0x000f /* system doorbell int/stat reg */
+#define U24_OGMCMD 0x0016 /* outgoing commands */
+#define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */
+#define U24_ICMCMD 0x001b /* incoming commands */
+#define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */
+
+/*
+ * UHA_LMASK bits (read only)
+ */
+#define UHA_LDIE 0x80 /* local doorbell int enabled */
+#define UHA_SRSTE 0x40 /* soft reset enabled */
+#define UHA_ABORTEN 0x10 /* abort MSCP enabled */
+#define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */
+
+/*
+ * UHA_LINT bits (read only)
+ */
+#define U14_LDIP 0x80 /* local doorbell int pending */
+#define U24_LDIP 0x02 /* local doorbell int pending */
+
+/*
+ * UHA_LINT bits (write only)
+ */
+#define U14_OGMFULL 0x01 /* outgoing mailbox is full */
+#define U14_ABORT 0x10 /* abort MSCP */
+
+#define U24_OGMFULL 0x02 /* outgoing mailbox is full */
+
+#define UHA_SBRST 0x40 /* scsi bus reset */
+#define UHA_ADRST 0x80 /* adapter soft reset */
+#define UHA_ASRST 0xc0 /* adapter and scsi reset */
+
+/*
+ * UHA_SMASK bits (read/write)
+ */
+#define UHA_ENSINT 0x80 /* enable system doorbell interrupt */
+#define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */
+#define UHA_ENICM 0x01 /* enable ICM interrupt */
+
+/*
+ * UHA_SINT bits (read)
+ */
+#define U14_SDIP 0x80 /* system doorbell int pending */
+#define U24_SDIP 0x02 /* system doorbell int pending */
+
+#define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */
+#define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */
+
+/*
+ * UHA_SINT bits (write)
+ */
+#define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */
+#define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */
+
+#define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */
+
+/*
+ * U14_CONFIG bits (read only)
+ */
+#define U14_DMA_CH5 0x0000 /* DMA channel 5 */
+#define U14_DMA_CH6 0x4000 /* 6 */
+#define U14_DMA_CH7 0x8000 /* 7 */
+#define U14_DMA_MASK 0xc000
+#define U14_IRQ15 0x0000 /* IRQ 15 */
+#define U14_IRQ14 0x1000 /* 14 */
+#define U14_IRQ11 0x2000 /* 11 */
+#define U14_IRQ10 0x3000 /* 10 */
+#define U14_IRQ_MASK 0x3000
+#define U14_HOSTID_MASK 0x0007
+
+/*
+ * U24_CONFIG bits (read only)
+ */
+#define U24_MAGIC1 0x08
+#define U24_IRQ15 0x10
+#define U24_IRQ14 0x20
+#define U24_IRQ11 0x40
+#define U24_IRQ10 0x80
+#define U24_IRQ_MASK 0xf0
+
+#define U24_MAGIC2 0x04
+
+#define U24_HOSTID_MASK 0x07
+
+/*
+ * EISA registers (offset from slot base)
+ */
+#define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */
+#define EISA_MODEL 0x0c82 /* model number (2 ports) */
+#define EISA_CONTROL 0x0c84
+#define EISA_RESET 0x04
+#define EISA_ERROR 0x02
+#define EISA_ENABLE 0x01
+
+/*
+ * host_stat error codes
+ */
+#define UHA_NO_ERR 0x00 /* No error supposedly */
+#define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */
+#define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */
+#define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */
+#define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */
+#define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */
+#define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */
+#define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */
+
+#define UHA_NSEG 33 /* number of dma segments supported */
+
+struct uha_dma_seg {
+ physaddr seg_addr;
+ physlen seg_len;
+};
+
+#pragma pack(1)
+struct uha_mscp {
+ u_char opcode:3;
+#define UHA_HAC 0x01 /* host adapter command */
+#define UHA_TSP 0x02 /* target scsi pass through command */
+#define UHA_SDR 0x04 /* scsi device reset */
+ u_char xdir:2; /* xfer direction */
+#define UHA_SDET 0x00 /* determined by scsi command */
+#define UHA_SDIN 0x01 /* scsi data in */
+#define UHA_SDOUT 0x02 /* scsi data out */
+#define UHA_NODATA 0x03 /* no data xfer */
+ u_char dcn:1; /* disable disconnect for this command */
+ u_char ca:1; /* cache control */
+ u_char sgth:1; /* scatter gather flag */
+ u_char target:3;
+ u_char chan:2; /* scsi channel (always 0 for 14f) */
+ u_char lun:3;
+ physaddr data_addr;
+ physlen data_length;
+ physaddr link_addr;
+ u_char link_id;
+ u_char sg_num; /* number of scat gath segs */
+ /*in s-g list if sg flag is */
+ /*set. starts at 1, 8bytes per */
+ u_char req_sense_length;
+ u_char scsi_cmd_length;
+ struct scsi_generic scsi_cmd;
+ u_char host_stat;
+ u_char target_stat;
+ physaddr sense_ptr; /* if 0 no auto sense */
+
+ struct uha_dma_seg uha_dma[UHA_NSEG];
+ struct scsi_sense_data mscp_sense;
+ /*-----------------end of hardware supported fields----------------*/
+ TAILQ_ENTRY(uha_mscp) chain;
+ struct uha_mscp *nexthash;
+ long hashkey;
+ struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
+ int flags;
+#define MSCP_ALLOC 0x01
+#define MSCP_ABORT 0x02
+ int timeout;
+};
+#pragma pack(4)
+
--- /dev/null
+/* $OpenBSD: uhavar.h,v 1.1 1996/11/28 23:27:55 niklas Exp $ */
+/* $NetBSD: uhavar.h,v 1.3 1996/10/21 22:34:43 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define UHA_MSCP_MAX 32 /* store up to 32 MSCPs at one time */
+#define MSCP_HASH_SIZE 32 /* hash table size for phystokv */
+#define MSCP_HASH_SHIFT 9
+#define MSCP_HASH(x) ((((long)(x))>>MSCP_HASH_SHIFT) & (MSCP_HASH_SIZE - 1))
+
+struct uha_softc {
+ struct device sc_dev;
+
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+ int sc_irq, sc_drq;
+ void *sc_ih;
+
+ void (*start_mbox) __P((struct uha_softc *, struct uha_mscp *));
+ int (*poll) __P((struct uha_softc *, struct scsi_xfer *, int));
+ void (*init) __P((struct uha_softc *));
+
+ struct uha_mscp *sc_mscphash[MSCP_HASH_SIZE];
+ TAILQ_HEAD(, uha_mscp) sc_free_mscp;
+ int sc_nummscps;
+ int sc_scsi_dev; /* our scsi id */
+ struct scsi_link sc_link;
+};
+
+void uha_attach __P((struct uha_softc *));
+void uha_timeout __P((void *arg));
+struct uha_mscp *uha_mscp_phys_kv __P((struct uha_softc *, u_long));
+void uha_done __P((struct uha_softc *, struct uha_mscp *));
-/* $OpenBSD: z8530reg.h,v 1.3 1996/10/31 01:01:42 niklas Exp $ */
-/* $NetBSD: z8530reg.h,v 1.5 1996/01/24 19:21:40 gwr Exp $ */
+/* $OpenBSD: z8530reg.h,v 1.4 1996/11/28 23:27:56 niklas Exp $ */
+/* $NetBSD: z8530reg.h,v 1.7 1996/10/23 00:32:31 gwr Exp $ */
/*
* Copyright (c) 1992, 1993
* registers 2 and 9 across both channels, and reads registers 2 and 3
* differently for the two channels. We can, however, ignore this much
* of the time.
- */
-#if 0 /* Example only! */
-/*
- * The layout of this structure is hardware-dependent!
- * Define these in some machine-dependent place.
- */
-struct zschan {
- volatile u_char zc_csr; /* ctrl, status, or reg. number */
- volatile u_char zc_data; /* data or numbered register */
-};
-struct zsdevice {
- struct zschan zs_chan[2];
-};
-#endif /* Example only! */
-
-/*
+ *
+ * This file also includes flags for the Z85C30 and Z85230 enhanced scc.
+ * The CMOS 8530 includes extra SDLC functionality, and is used in a
+ * number of Macs (often in the Z85C80, an 85C30 combined w/ a SCSI
+ * controller). -wrs
+ *
* Some of the names in this files were chosen to make the hsis driver
* work unchanged (which means that they will match some in SunOS).
*
* framing error (missing stop bit, etc)
* end of frame (in synchronous modes)
* parity error (when `parity error is S.C.' is set)
- */
-
-/*
+ *
* Registers with only a single `numeric value' get a name.
* Other registers hold bits and are only numbered; the bit
* definitions imply the register number (see below).
*/
#define ZSRR_IVEC 2 /* interrupt vector (channel 0) */
#define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */
+#define ZSRR_TXSYNC 6 /* sync transmit char (monosync mode) */
+#define ZSRR_RXSYNC 7 /* sync receive char (monosync mode) */
+#define ZSRR_SYNCLO 6 /* sync low byte (bisync mode) */
+#define ZSRR_SYNCHI 7 /* sync high byte (bisync mode) */
+#define ZSRR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */
+#define ZSRR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */
#define ZSRR_BAUDLO 12 /* baud rate generator (low half) */
#define ZSRR_BAUDHI 13 /* baud rate generator (high half) */
+#define ZSRR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/
#define ZSWR_IVEC 2 /* interrupt vector (shared) */
#define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */
#define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */
#define ZSWR_BAUDLO 12 /* baud rate generator (low half) */
#define ZSWR_BAUDHI 13 /* baud rate generator (high half) */
+#define ZSWR_ENHANCED 7 /* write address of WR7' */
/*
* Registers 0 through 7 may be written with any one of the 8 command
#define ZSWR3_RX_7 0x40 /* receive 7 bits per char */
#define ZSWR3_RX_6 0x80 /* receive 6 bits per char */
#define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */
+#define ZSWR3_RXSIZE 0xc0 /* receive char size mask */
#define ZSWR3_HFC 0x20 /* hardware flow control */
#define ZSWR3_HUNT 0x10 /* enter hunt mode */
#define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */
#define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */
#define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */
+#define ZSWR4_CLK_MASK 0xc0 /* clock divisor mask */
#define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */
#define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */
-#define ZSWR4_SDLC 0x20 /* SDLC mode */
+#define ZSWR4_SDLC 0x20 /* SDLC mode */
#define ZSWR4_EXTSYNC 0x30 /* external sync mode */
+#define ZSWR4_SYNC_MASK 0x30 /* sync mode bit mask */
-#define ZSWR4_SYNCMODE 0x00 /* one of the above sync modes */
-#define ZSWR4_ONESB 0x04 /* 1 stop bit */
-#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */
-#define ZSWR4_TWOSB 0x0c /* 2 stop bits */
+#define ZSWR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */
+#define ZSWR4_ONESB 0x04 /* 1 stop bit */
+#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */
+#define ZSWR4_TWOSB 0x0c /* 2 stop bits */
+#define ZSWR4_SBMASK 0x0c /* mask of all stop bits */
-#define ZSWR4_EVENP 0x02 /* check for even parity */
+#define ZSWR4_EVENP 0x02 /* check for even parity */
#define ZSWR4_PARENB 0x01 /* enable parity checking */
+#define ZSWR4_PARMASK 0x03 /* mask of all parity bits */
/*
* Bits in Write Register 5 (`Transmit Parameter and Controls').
#define ZSWR5_TX_7 0x20 /* transmit 7 bits */
#define ZSWR5_TX_6 0x40 /* transmit 6 bits */
#define ZSWR5_TX_8 0x60 /* transmit 8 bits */
+#define ZSWR5_TXSIZE 0x60 /* transmit char size mask */
#define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */
#define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */
#define ZSWR7_SDLCFLAG 0x7e /* this value makes SDLC mode work */
#endif
+/*
+ * Bits in Write Register 7' (ZSWR_ENHANCED above). This register is
+ * only available on the 85230. Dispite the fact it contains flags
+ * and not a single value, the register was named as it is read
+ * via RR14. Weird.
+ */
+ /* 0x80 unused */
+#define ZSWR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */
+#define ZSWR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */
+#define ZSWR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */
+#define ZSWR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */
+#define ZSWR7P_RTS_DEACT 0x04 /* automatically deassert RTS */
+#define ZSWR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */
+#define ZSWR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */
+
/*
* Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6
* are taken as a unit and indicate the type of reset; 00 means no reset
#define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */
#define ZSWR9_A_RESET 0x80 /* reset channel A (0) */
#define ZSWR9_B_RESET 0x40 /* reset channel B (1) */
- /* 0x20 unused */
+#define ZSWR9_SOFT_INTAC 0x20 /* Not in NMOS version */
#define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */
#define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */
*/
#define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */
/* (else have TTL oscil. on RTxC*) */
-#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from TRxC* pin */
+#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */
#define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */
#define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */
#define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */
-#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from TRxC* pin */
-#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from RTxC* pin */
+#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */
+#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */
#define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */
#define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */
* Bits in Write Register 15 (`External/Status Interrupt Control').
* Most of these cause status interrupts whenever the corresponding
* bit or pin changes state (i.e., any rising or falling edge).
+ *
+ * NOTE: ZSWR15_SDLC_FIFO & ZSWR15_ENABLE_ENHANCED should not be
+ * set on an NMOS 8530. Also, ZSWR15_ENABLE_ENHANCED is only
+ * available on the 85230.
*/
#define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */
#define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */
#define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */
#define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */
#define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */
- /* 0x04 unused, must be zero */
+#define ZSWR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */
#define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */
- /* 0x01 unused, must be zero */
+#define ZSWR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */
/*
* Bits in Read Register 0 (`Transmit/Receive Buffer Status and External
-/* $OpenBSD: z8530sc.h,v 1.4 1996/10/31 01:01:42 niklas Exp $ */
-/* $NetBSD: z8530sc.h,v 1.3 1996/05/17 19:29:37 gwr Exp $ */
+/* $OpenBSD: z8530sc.h,v 1.5 1996/11/28 23:27:56 niklas Exp $ */
+/* $NetBSD: z8530sc.h,v 1.4 1996/10/16 20:34:54 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
u_char cs_heldchange; /* change pending (creg != preg) */
u_char cs_rr0; /* last rr0 processed */
- u_char cs_rr0_new; /* rr0 saved in status interrupt. */
+ u_char cs_rr0_delta; /* rr0 changes at status intr. */
char cs_softreq; /* need soft interrupt call */
};
-/* $OpenBSD: z8530tty.c,v 1.6 1996/06/18 10:23:03 deraadt Exp $ */
-/* $NetBSD: z8530tty.c,v 1.8.4.2 1996/06/13 23:11:56 gwr Exp $ */
+/* $OpenBSD: z8530tty.c,v 1.7 1996/11/28 23:27:57 niklas Exp $ */
+/* $NetBSD: z8530tty.c,v 1.13 1996/10/16 20:42:14 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
/*
* Stop output, e.g., for ^S or output flush.
*/
-int
+void
zsstop(tp, flag)
struct tty *tp;
int flag;
tp->t_state |= TS_FLUSH;
}
splx(s);
- return (0);
}
/*
zst->zst_tx_stopped = 1;
}
- cs->cs_rr0_new = rr0;
+ /*
+ * We have to accumulate status line changes here.
+ * Otherwise, if we get multiple status interrupts
+ * before the softint runs, we could fail to notice
+ * some status line changes in the softint routine.
+ * Fix from Bill Studenmund, October 1996.
+ */
+ cs->cs_rr0_delta |= (cs->cs_rr0 ^ rr0);
+ cs->cs_rr0 = rr0;
zst->zst_st_check = 1;
/* Ask for softint() call. */
if (zst->zst_st_check) {
zst->zst_st_check = 0;
- rr0 = cs->cs_rr0_new;
- delta = rr0 ^ cs->cs_rr0;
- cs->cs_rr0 = rr0;
+ rr0 = cs->cs_rr0;
+ delta = cs->cs_rr0_delta;
+ cs->cs_rr0_delta = 0;
if (delta & ZSRR0_DCD) {
c = ((rr0 & ZSRR0_DCD) != 0);
if (line->l_modem(tp, c) == 0)
+# $OpenBSD: Makefile.inc,v 1.5 1996/11/28 23:27:58 niklas Exp $
# $NetBSD: Makefile.inc,v 1.4 1996/05/20 00:48:43 thorpej Exp $
.if target(aic7xxx.o)
+/* $OpenBSD: aic7xxx.seq,v 1.5 1996/11/28 23:27:59 niklas Exp $ */
+/* $NetBSD: aic7xxx.seq,v 1.6 1996/10/08 03:04:06 gibbs Exp $ */
+
/*+M***********************************************************************
*Adaptec 274x/284x/294x device driver for Linux and FreeBSD.
*
*OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
*SUCH DAMAGE.
*
+ * from Id: aic7xxx.seq,v 1.42 1996/06/09 17:29:11 gibbs Exp
+ *
*-M************************************************************************/
-VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.4 1996/06/27 21:15:52 shawn Exp $"
+VERSION AIC7XXX_SEQ_VER "$NetBSD: aic7xxx.seq,v 1.6 1996/10/08 03:04:06 gibbs Exp $"
#if defined(__NetBSD__)
-#include "../../../../dev/ic/aic7xxxreg.h"
+#include "../../ic/aic7xxxreg.h"
+#include "../../../scsi/scsi_message.h"
#elif defined(__FreeBSD__)
#include "../../dev/aic7xxx/aic7xxx_reg.h"
+#include "../../scsi/scsi_message.h"
#endif
/*
* Messages are stored in scratch RAM starting with a length byte
* followed by the message itself.
*/
- test SCB_CMDLEN,0xff jnz mk_identify /* 0 Length Command? */
-
-/*
- * The kernel has sent us an SCB with no command attached. This implies
- * that the kernel wants to send a message of some sort to this target,
- * so we interrupt the driver, allow it to fill the message buffer, and
- * then go back into the arbitration loop
- */
- mvi INTSTAT,AWAITING_MSG
- jmp wait_for_selection
mk_identify:
and A,DISCENB,SCB_CONTROL /* mask off disconnect privledge */
and MSG0,0x7,SCB_TCL /* lun */
or MSG0,A /* or in disconnect privledge */
- or MSG0,MSG_IDENTIFY
+ or MSG0,MSG_IDENTIFYFLAG
mvi MSG_LEN, 1
- test SCB_CONTROL,0xb0 jz !message /* WDTR, SDTR or TAG?? */
/*
* Send a tag message if TAG_ENB is set in the SCB control block.
* Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
*/
-
mk_tag:
+ test SCB_CONTROL,TAG_ENB jz mk_message
mvi DINDEX, MSG1
- test SCB_CONTROL,TAG_ENB jz mk_tag_done
and DINDIR,0x23,SCB_CONTROL
mov DINDIR,SCB_TAG
add MSG_LEN,COMP_MSG0,DINDEX /* update message length */
-mk_tag_done:
+/*
+ * Interrupt the driver, and allow it to tweak the message buffer
+ * if it asks.
+ */
+mk_message:
+ test SCB_CONTROL,MK_MESSAGE jz wait_for_selection
- test SCB_CONTROL,0x90 jz !message /* NEEDWDTR|NEEDSDTR */
- mov DINDEX call mk_dtr /* build DTR message if needed */
+ mvi INTSTAT,AWAITING_MSG
-!message:
wait_for_selection:
test SSTAT0,SELDO jnz select
test SSTAT0,SELDI jz wait_for_selection
*/
p_mesgout:
test MSG_LEN, 0xff jnz p_mesgout_start
- mvi MSG_NOP call mk_mesg /* build NOP message */
+ mvi MSG_NOOP call mk_mesg /* build NOP message */
p_mesgout_start:
/*
mvi A call inb_first /* read the 1st message byte */
mov REJBYTE,A /* save it for the driver */
- test A,MSG_IDENTIFY jnz mesgin_identify
+ test A,MSG_IDENTIFYFLAG jnz mesgin_identify
cmp A,MSG_DISCONNECT je mesgin_disconnect
- cmp A,MSG_SDPTRS je mesgin_sdptrs
+ cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs
cmp ALLZEROS,A je mesgin_complete
- cmp A,MSG_RDPTRS je mesgin_rdptrs
+ cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs
cmp A,MSG_EXTENDED je mesgin_extended
- cmp A,MSG_REJECT je mesgin_reject
+ cmp A,MSG_MESSAGE_REJECT je mesgin_reject
rej_mesgin:
/*
or SCSISIGO,ATNO /* turn on ATNO */
mvi INTSTAT,SEND_REJECT /* let driver know */
- mvi MSG_REJECT call mk_mesg
+ mvi MSG_MESSAGE_REJECT call mk_mesg
mesgin_done:
call inb_last /*ack & turn auto PIO back on*/
/*
- * Is it an extended message? We only support the synchronous and wide data
- * transfer request messages, which will probably be in response to
- * WDTR or SDTR message outs from us. If it's not SDTR or WDTR, reject it -
- * apparently this can be done after any message in byte, according
- * to the SCSI-2 spec.
+ * Is it an extended message? Copy the message to our message buffer and
+ * notify the host. The host will tell us whether to reject this message,
+ * respond to it with the message that the host placed in our message buffer,
+ * or simply to do nothing.
*/
mesgin_extended:
- mvi ARG_1 call inb_next /* extended message length */
- mvi REJBYTE_EXT call inb_next /* extended message code */
-
- cmp REJBYTE_EXT,MSG_SDTR je p_mesginSDTR
- cmp REJBYTE_EXT,MSG_WDTR je p_mesginWDTR
- jmp rej_mesgin
-
-p_mesginWDTR:
- cmp ARG_1,2 jne rej_mesgin /* extended mesg length=2 */
- mvi ARG_1 call inb_next /* Width of bus */
- mvi INTSTAT,WDTR_MSG /* let driver know */
- test RETURN_1,0xff jz mesgin_done /* Do we need to send WDTR? */
- cmp RETURN_1,SEND_REJ je rej_mesgin /*
- * Bus width was too large
- * Reject it.
- */
-
-/* We didn't initiate the wide negotiation, so we must respond to the request */
- and RETURN_1,0x7f /* Clear the SEND_WDTR Flag */
- mvi DINDEX,MSG0
- mvi MSG0 call mk_wdtr /* build WDTR message */
- or SCSISIGO,ATNO /* turn on ATNO */
- jmp mesgin_done
-
-p_mesginSDTR:
- cmp ARG_1,3 jne rej_mesgin /* extended mesg length=3 */
- mvi ARG_1 call inb_next /* xfer period */
- mvi A call inb_next /* REQ/ACK offset */
- mvi INTSTAT,SDTR_MSG /* call driver to convert */
-
- test RETURN_1,0xff jz mesgin_done /* Do we need to mk_sdtr/rej */
- cmp RETURN_1,SEND_REJ je rej_mesgin /*
- * Requested SDTR too small
- * Reject it.
- */
- clr ARG_1 /* Use the scratch ram rate */
- mvi DINDEX, MSG0
- mvi MSG0 call mk_sdtr
+ mvi MSGIN_EXT_LEN call inb_next
+ mvi MSGIN_EXT_OPCODE call inb_next
+ mov A, MSGIN_EXT_LEN
+ dec A /* Length counts the op code */
+ mvi SINDEX, MSGIN_EXT_BYTE0
+mesgin_extended_loop:
+ test A, 0xFF jz mesgin_extended_intr
+ cmp SINDEX, MSGIN_EXT_LASTBYTE je mesgin_extended_dump
+ call inb_next
+ dec A
+/*
+ * We pass the arg to inb in SINDEX, but DINDEX is the one incremented
+ * so update SINDEX with DINDEX's value before looping again.
+ */
+ mov DINDEX jmp mesgin_extended_loop
+mesgin_extended_dump:
+/* We have no more storage space, so dump the rest */
+ test A, 0xFF jz mesgin_extended_intr
+ mvi NONE call inb_next
+ dec A
+ jmp mesgin_extended_dump
+mesgin_extended_intr:
+ mvi INTSTAT,EXTENDED_MSG /* let driver know */
+ cmp RETURN_1,SEND_REJ je rej_mesgin
+ cmp RETURN_1,SEND_MSG jne mesgin_done
+/* The kernel has setup a message to be sent */
or SCSISIGO,ATNO /* turn on ATNO */
jmp mesgin_done
*/
mvi ARG_1,SCB_LIST_NULL /* Default to no-tag */
snoop_tag_loop:
- test SSTAT1,BUSFREE jnz use_findSCB
- test SSTAT1,REQINIT jz snoop_tag_loop
- test SSTAT1,PHASEMIS jnz use_findSCB
- mvi A call inb_first
- cmp A,MSG_SIMPLE_TAG jne use_findSCB
+ test SSTAT1,BUSFREE jnz use_findSCB
+ test SSTAT1,REQINIT jz snoop_tag_loop
+ test SSTAT1,PHASEMIS jnz use_findSCB
+ mvi A call inb_first
+ cmp A,MSG_SIMPLE_Q_TAG jne use_findSCB
get_tag:
mvi ARG_1 call inb_next /* tag value */
/*
and DFCNTRL,WIDEODD
dma6:
test DFCNTRL,0x38 jnz dma6 /* SCSIENACK|SDMAENACK|HDMAENACK */
-
+return:
ret
/*
or A,0x08 /* Channel B entries add 8 */
ndx_dtr_2:
add SINDEX,TARG_SCRATCH,A ret
-
-/*
- * If we need to negotiate transfer parameters, build the WDTR or SDTR message
- * starting at the address passed in SINDEX. DINDEX is modified on return.
- * The SCSI-II spec requires that Wide negotiation occur first and you can
- * only negotiat one or the other at a time otherwise in the event of a message
- * reject, you wouldn't be able to tell which message was the culpret.
- */
-mk_dtr:
- test SCB_CONTROL,NEEDWDTR jnz mk_wdtr_16bit
- mvi ARG_1, MAXOFFSET /* Force an offset of 15 or 8 if WIDE */
-
-mk_sdtr:
- mvi DINDIR,1 /* extended message */
- mvi DINDIR,3 /* extended message length = 3 */
- mvi DINDIR,1 /* SDTR code */
- call sdtr_to_rate
- mov DINDIR,RETURN_1 /* REQ/ACK transfer period */
- cmp ARG_1, MAXOFFSET je mk_sdtr_max_offset
- and DINDIR,0x0f,SINDIR /* Sync Offset */
-
-mk_sdtr_done:
- add MSG_LEN,COMP_MSG0,DINDEX ret /* update message length */
-
-mk_sdtr_max_offset:
-/*
- * We're initiating sync negotiation, so request the max offset we can (15 or 8)
- */
- /* Talking to a WIDE device? */
- test SCSIRATE, WIDEXFER jnz wmax_offset
- mvi DINDIR, MAX_OFFSET_8BIT
- jmp mk_sdtr_done
-
-wmax_offset:
- mvi DINDIR, MAX_OFFSET_16BIT
- jmp mk_sdtr_done
-
-mk_wdtr_16bit:
- mvi ARG_1,BUS_16_BIT
-mk_wdtr:
- mvi DINDIR,1 /* extended message */
- mvi DINDIR,2 /* extended message length = 2 */
- mvi DINDIR,3 /* WDTR code */
- mov DINDIR,ARG_1 /* bus width */
-
- add MSG_LEN,COMP_MSG0,DINDEX ret /* update message length */
-
-sdtr_to_rate:
- call ndx_dtr /* index scratch space for target */
- shr A,SINDIR,0x4
- dec SINDEX /* Preserve SINDEX */
- and A,0x7
- clr RETURN_1
-sdtr_to_rate_loop:
- test A,0x0f jz sdtr_to_rate_done
- add RETURN_1,0x19
- dec A
- jmp sdtr_to_rate_loop
-sdtr_to_rate_done:
- shr RETURN_1,0x2
- add RETURN_1,0x19
- test SXFRCTL0,ULTRAEN jz return
- shr RETURN_1,0x1
-return:
- ret
+.\" $OpenBSD: aic7xxx_asm.1,v 1.4 1996/11/28 23:27:59 niklas Exp $
+.\"
.\" Copyright (c) 1994, 1995
.\" Justin T. Gibbs. All rights reserved.
.\"
+/* $OpenBSD: aic7xxx_asm.c,v 1.6 1996/11/28 23:28:00 niklas Exp $ */
+
/*+M*************************************************************************
* Adaptec AIC7770/AIC7870 sequencer code assembler.
*
* are token separators.
*
*-M*************************************************************************/
-static char id[] = "$Id: aic7xxx_asm.c,v 1.5 1996/06/27 21:15:54 shawn Exp $";
+static char id[] = "$Id: aic7xxx_asm.c,v 1.6 1996/11/28 23:28:00 niklas Exp $";
#include <ctype.h>
#include <stdio.h>
#include <string.h>
--- /dev/null
+#define AIC7XXX_SEQ_VER "$OpenBSD: aic7xxx_seq.h,v 1.1 1996/11/28 23:28:00 niklas Exp $"
+#if 0
+#define AIC7XXX_SEQ_VER "$NetBSD: aic7xxx_seq.h,v 1.2 1996/10/08 03:04:07 gibbs Exp $"
+#endif
+ 0xff, 0x6a, 0x93, 0x02,
+ 0xff, 0x6a, 0x03, 0x02,
+ 0x0f, 0x4a, 0x4a, 0x02,
+ 0x10, 0x6a, 0x00, 0x00,
+ 0xff, 0x6a, 0x04, 0x02,
+ 0x01, 0x4a, 0x09, 0x1e,
+ 0x08, 0x1f, 0x1f, 0x04,
+ 0x20, 0x0b, 0x32, 0x1a,
+ 0x08, 0x1f, 0x1f, 0x04,
+ 0x20, 0x0b, 0x32, 0x1a,
+ 0xff, 0x4e, 0x17, 0x18,
+ 0xff, 0x49, 0x64, 0x02,
+ 0x00, 0x9c, 0x05, 0x1e,
+ 0xff, 0x9b, 0x90, 0x02,
+ 0xff, 0xa1, 0x6e, 0x02,
+ 0xff, 0x6e, 0x64, 0x02,
+ 0x88, 0xa1, 0x19, 0x1e,
+ 0x00, 0x4d, 0x15, 0x1a,
+ 0x20, 0xa0, 0x1c, 0x1a,
+ 0x00, 0x4d, 0x4d, 0x00,
+ 0x00, 0x65, 0x1c, 0x10,
+ 0xff, 0x90, 0x9b, 0x02,
+ 0x00, 0x65, 0x05, 0x10,
+ 0xff, 0x4e, 0x90, 0x02,
+ 0x00, 0x65, 0x1e, 0x10,
+ 0x00, 0x4c, 0x15, 0x1a,
+ 0x20, 0xa0, 0x1c, 0x1a,
+ 0x00, 0x4c, 0x4c, 0x00,
+ 0xff, 0x4e, 0xba, 0x02,
+ 0xff, 0x90, 0x4e, 0x02,
+ 0xf7, 0x1f, 0x65, 0x02,
+ 0x08, 0xa1, 0x64, 0x02,
+ 0x00, 0x65, 0x65, 0x00,
+ 0xff, 0x65, 0x1f, 0x02,
+ 0x00, 0xa1, 0x35, 0x17,
+ 0x58, 0x6a, 0x00, 0x00,
+ 0x40, 0xa0, 0x64, 0x02,
+ 0x07, 0xa1, 0x35, 0x02,
+ 0x00, 0x35, 0x35, 0x00,
+ 0x80, 0x35, 0x35, 0x00,
+ 0x01, 0x6a, 0x34, 0x00,
+ 0x20, 0xa0, 0x2e, 0x1e,
+ 0x36, 0x6a, 0x66, 0x00,
+ 0x23, 0xa0, 0x6d, 0x02,
+ 0xff, 0xb9, 0x6d, 0x02,
+ 0xcb, 0x66, 0x34, 0x06,
+ 0x80, 0xa0, 0x30, 0x1e,
+ 0xa1, 0x6a, 0x91, 0x00,
+ 0x40, 0x0b, 0x36, 0x1a,
+ 0x20, 0x0b, 0x30, 0x1e,
+ 0xff, 0x6a, 0x34, 0x02,
+ 0x00, 0x19, 0x35, 0x17,
+ 0x80, 0x4a, 0x4a, 0x00,
+ 0x00, 0x65, 0x38, 0x10,
+ 0xff, 0xba, 0x4e, 0x02,
+ 0x20, 0x4a, 0x4a, 0x00,
+ 0x02, 0x01, 0x01, 0x00,
+ 0x00, 0x65, 0x7c, 0x17,
+ 0xff, 0x6c, 0x04, 0x02,
+ 0xff, 0x05, 0x6e, 0x02,
+ 0xff, 0x6e, 0x64, 0x02,
+ 0xdf, 0x01, 0x65, 0x02,
+ 0x80, 0x05, 0x42, 0x1a,
+ 0x08, 0x1f, 0x42, 0x1a,
+ 0x00, 0x52, 0x44, 0x1e,
+ 0x20, 0x65, 0x44, 0x10,
+ 0x00, 0x53, 0x44, 0x1e,
+ 0x20, 0x65, 0x65, 0x00,
+ 0xff, 0x65, 0x01, 0x02,
+ 0x02, 0x6a, 0x00, 0x00,
+ 0x08, 0x6a, 0x0c, 0x00,
+ 0x60, 0x6a, 0x0b, 0x00,
+ 0x08, 0x0c, 0x18, 0x1b,
+ 0x01, 0x0c, 0x48, 0x1e,
+ 0xe0, 0x03, 0x64, 0x02,
+ 0xff, 0x64, 0x3d, 0x02,
+ 0xff, 0x64, 0x03, 0x02,
+ 0x00, 0x6a, 0x55, 0x1c,
+ 0x40, 0x64, 0x5b, 0x1c,
+ 0x80, 0x64, 0x8d, 0x1c,
+ 0xa0, 0x64, 0x9c, 0x1c,
+ 0xc0, 0x64, 0x9a, 0x1c,
+ 0xe0, 0x64, 0xb1, 0x1c,
+ 0x01, 0x6a, 0x91, 0x00,
+ 0x00, 0x65, 0x48, 0x10,
+ 0x7d, 0x6a, 0x41, 0x00,
+ 0x00, 0x65, 0x5c, 0x10,
+ 0xff, 0xa9, 0x08, 0x02,
+ 0xff, 0xaa, 0x09, 0x02,
+ 0xff, 0xab, 0x0a, 0x02,
+ 0x00, 0x65, 0x60, 0x10,
+ 0x79, 0x6a, 0x41, 0x00,
+ 0x00, 0x65, 0x39, 0x17,
+ 0x10, 0x4a, 0x57, 0x1a,
+ 0x00, 0x65, 0x60, 0x17,
+ 0x10, 0x4a, 0x4a, 0x00,
+ 0xff, 0x42, 0x65, 0x1a,
+ 0x80, 0x02, 0x02, 0x00,
+ 0xff, 0x6a, 0x08, 0x00,
+ 0xff, 0x6a, 0x09, 0x00,
+ 0xff, 0x6a, 0x0a, 0x00,
+ 0x01, 0x42, 0x67, 0x18,
+ 0xbf, 0x41, 0x41, 0x02,
+ 0x00, 0x41, 0x2d, 0x17,
+ 0x80, 0x02, 0x8a, 0x1a,
+ 0x04, 0x0b, 0x85, 0x1e,
+ 0xff, 0x42, 0x42, 0x06,
+ 0xff, 0x42, 0x85, 0x1e,
+ 0xff, 0x6a, 0x64, 0x02,
+ 0x08, 0x43, 0x43, 0x06,
+ 0x00, 0x44, 0x44, 0x08,
+ 0xff, 0x6a, 0x8e, 0x02,
+ 0xff, 0x6a, 0x8d, 0x02,
+ 0x08, 0x6a, 0x8c, 0x00,
+ 0xff, 0x43, 0x88, 0x02,
+ 0xff, 0x44, 0x89, 0x02,
+ 0xff, 0x45, 0x8a, 0x02,
+ 0xff, 0x46, 0x8b, 0x02,
+ 0x0d, 0x93, 0x93, 0x00,
+ 0x08, 0x94, 0x77, 0x1e,
+ 0x40, 0x93, 0x93, 0x02,
+ 0x08, 0x93, 0x79, 0x1a,
+ 0xff, 0x99, 0x88, 0x02,
+ 0xff, 0x99, 0x89, 0x02,
+ 0xff, 0x99, 0x8a, 0x02,
+ 0xff, 0x99, 0x8b, 0x02,
+ 0xff, 0x99, 0x8c, 0x02,
+ 0xff, 0x99, 0x8d, 0x02,
+ 0xff, 0x99, 0x8e, 0x02,
+ 0xff, 0x8c, 0x08, 0x02,
+ 0xff, 0x8d, 0x09, 0x02,
+ 0xff, 0x8e, 0x0a, 0x02,
+ 0x10, 0x0c, 0x60, 0x1e,
+ 0xff, 0x08, 0xa9, 0x02,
+ 0xff, 0x09, 0xaa, 0x02,
+ 0xff, 0x0a, 0xab, 0x02,
+ 0xff, 0x42, 0xa8, 0x02,
+ 0x00, 0x65, 0x48, 0x10,
+ 0x7f, 0x02, 0x02, 0x02,
+ 0xe1, 0x6a, 0x91, 0x00,
+ 0x00, 0x65, 0x48, 0x10,
+ 0x00, 0x65, 0x39, 0x17,
+ 0xff, 0xb4, 0x88, 0x02,
+ 0xff, 0xb5, 0x89, 0x02,
+ 0xff, 0xb6, 0x8a, 0x02,
+ 0xff, 0xb7, 0x8b, 0x02,
+ 0xff, 0xb8, 0x8c, 0x02,
+ 0xff, 0x6a, 0x8d, 0x02,
+ 0xff, 0x6a, 0x8e, 0x02,
+ 0xff, 0x8c, 0x08, 0x02,
+ 0xff, 0x8d, 0x09, 0x02,
+ 0xff, 0x8e, 0x0a, 0x02,
+ 0x3d, 0x6a, 0x2d, 0x17,
+ 0x00, 0x65, 0x48, 0x10,
+ 0xa2, 0x6a, 0x27, 0x17,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0xff, 0x34, 0x9e, 0x1a,
+ 0x08, 0x6a, 0x1c, 0x17,
+ 0x35, 0x6a, 0x65, 0x00,
+ 0xff, 0x34, 0x66, 0x02,
+ 0x10, 0x0c, 0xae, 0x1a,
+ 0x02, 0x0b, 0xa0, 0x1e,
+ 0x10, 0x0c, 0xae, 0x1a,
+ 0x01, 0x66, 0xa5, 0x18,
+ 0x40, 0x6a, 0x0c, 0x00,
+ 0xff, 0x66, 0x66, 0x06,
+ 0x02, 0x0b, 0x0b, 0x00,
+ 0xff, 0x6c, 0x06, 0x02,
+ 0xff, 0x66, 0xa0, 0x1a,
+ 0x08, 0x0c, 0xaf, 0x1a,
+ 0x01, 0x0c, 0xa9, 0x1e,
+ 0x10, 0x0c, 0xaf, 0x1a,
+ 0x10, 0x03, 0x03, 0x00,
+ 0x00, 0x65, 0x48, 0x10,
+ 0x40, 0x6a, 0x0c, 0x00,
+ 0xff, 0x6a, 0x34, 0x02,
+ 0x00, 0x65, 0x48, 0x10,
+ 0x64, 0x6a, 0x27, 0x17,
+ 0xff, 0x64, 0x30, 0x02,
+ 0x80, 0x64, 0xf5, 0x1a,
+ 0x04, 0x64, 0xe5, 0x1c,
+ 0x02, 0x64, 0xf1, 0x1c,
+ 0x00, 0x6a, 0xbf, 0x1c,
+ 0x03, 0x64, 0xf3, 0x1c,
+ 0x01, 0x64, 0xd2, 0x1c,
+ 0x07, 0x64, 0x16, 0x1d,
+ 0x10, 0x03, 0x03, 0x00,
+ 0x11, 0x6a, 0x91, 0x00,
+ 0x07, 0x6a, 0x1c, 0x17,
+ 0x00, 0x65, 0x2a, 0x17,
+ 0x00, 0x65, 0x48, 0x10,
+ 0xff, 0xa8, 0xc1, 0x1e,
+ 0x81, 0x6a, 0x91, 0x00,
+ 0xff, 0xa2, 0xc5, 0x1e,
+ 0x71, 0x6a, 0x91, 0x00,
+ 0x40, 0x3f, 0xc5, 0x18,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x20, 0xa0, 0xcc, 0x1a,
+ 0xff, 0xa1, 0x6e, 0x02,
+ 0xff, 0x6e, 0x64, 0x02,
+ 0x88, 0xa1, 0xcb, 0x1e,
+ 0x00, 0x4d, 0x4d, 0x04,
+ 0x00, 0x65, 0xcc, 0x10,
+ 0x00, 0x4c, 0x4c, 0x04,
+ 0xff, 0xb8, 0xcf, 0x1a,
+ 0xb1, 0x6a, 0x91, 0x00,
+ 0x00, 0x65, 0x02, 0x10,
+ 0xff, 0xb9, 0x9d, 0x02,
+ 0x02, 0x6a, 0x91, 0x00,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x54, 0x6a, 0x23, 0x17,
+ 0x55, 0x6a, 0x23, 0x17,
+ 0xff, 0x54, 0x64, 0x02,
+ 0xff, 0x64, 0x64, 0x06,
+ 0x56, 0x6a, 0x65, 0x00,
+ 0xff, 0x64, 0xe0, 0x1e,
+ 0x58, 0x65, 0xdc, 0x1c,
+ 0x00, 0x65, 0x23, 0x17,
+ 0xff, 0x64, 0x64, 0x06,
+ 0x00, 0x66, 0xd7, 0x10,
+ 0xff, 0x64, 0xe0, 0x1e,
+ 0x6a, 0x6a, 0x23, 0x17,
+ 0xff, 0x64, 0x64, 0x06,
+ 0x00, 0x65, 0xdc, 0x10,
+ 0x41, 0x6a, 0x91, 0x00,
+ 0x20, 0x3f, 0xba, 0x1c,
+ 0x80, 0x3f, 0xbd, 0x18,
+ 0x10, 0x03, 0x03, 0x00,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x04, 0xa0, 0xa0, 0x00,
+ 0x04, 0x4a, 0xbd, 0x1e,
+ 0xff, 0x6a, 0xbb, 0x00,
+ 0x50, 0x6a, 0x60, 0x00,
+ 0xff, 0x4f, 0xba, 0x02,
+ 0xff, 0x90, 0x4f, 0x02,
+ 0xff, 0xba, 0xef, 0x1c,
+ 0xff, 0xba, 0x90, 0x02,
+ 0xff, 0x4f, 0xbb, 0x02,
+ 0xff, 0x4f, 0x90, 0x02,
+ 0x10, 0x6a, 0x60, 0x00,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x00, 0x65, 0x6f, 0x17,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0xef, 0x4a, 0x4a, 0x02,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x78, 0x64, 0xba, 0x1a,
+ 0x07, 0x64, 0x64, 0x02,
+ 0x00, 0x19, 0x4b, 0x00,
+ 0xf7, 0x4b, 0x4b, 0x02,
+ 0x08, 0x1f, 0x64, 0x02,
+ 0x00, 0x4b, 0x4b, 0x00,
+ 0x00, 0x65, 0x2a, 0x17,
+ 0xff, 0x6a, 0x3e, 0x00,
+ 0x08, 0x0c, 0x08, 0x1b,
+ 0x01, 0x0c, 0xfd, 0x1e,
+ 0x10, 0x0c, 0x08, 0x1b,
+ 0x64, 0x6a, 0x27, 0x17,
+ 0x20, 0x64, 0x08, 0x19,
+ 0x3e, 0x6a, 0x23, 0x17,
+ 0xff, 0x48, 0x64, 0x02,
+ 0x00, 0x3e, 0x65, 0x06,
+ 0x00, 0x65, 0x12, 0x13,
+ 0x04, 0x4a, 0x0c, 0x1f,
+ 0x00, 0x65, 0x2a, 0x17,
+ 0x00, 0x6a, 0x3c, 0x17,
+ 0xfb, 0xa0, 0xa0, 0x02,
+ 0x40, 0x4a, 0x4a, 0x00,
+ 0x00, 0x65, 0x48, 0x10,
+ 0xff, 0x3e, 0x90, 0x02,
+ 0xff, 0x4b, 0x64, 0x02,
+ 0x00, 0xa1, 0x12, 0x19,
+ 0x20, 0xa0, 0x12, 0x1f,
+ 0x00, 0x65, 0x2a, 0x17,
+ 0x00, 0x65, 0x09, 0x11,
+ 0x10, 0x03, 0x03, 0x00,
+ 0x91, 0x6a, 0x91, 0x00,
+ 0x0d, 0x6a, 0x1c, 0x17,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x61, 0x6a, 0x91, 0x00,
+ 0x00, 0x65, 0xbd, 0x10,
+ 0x40, 0x6a, 0x0c, 0x00,
+ 0xff, 0x6a, 0x3d, 0x02,
+ 0xff, 0xb8, 0xc5, 0x1e,
+ 0x00, 0x65, 0x02, 0x10,
+ 0x50, 0x6a, 0x60, 0x00,
+ 0xff, 0x34, 0x20, 0x1f,
+ 0x10, 0x6a, 0x60, 0x00,
+ 0xc1, 0x6a, 0x91, 0x00,
+ 0x01, 0x6a, 0x34, 0x00,
+ 0xff, 0x65, 0x35, 0x02,
+ 0x10, 0x6a, 0x60, 0x01,
+ 0x02, 0x0b, 0x0b, 0x00,
+ 0xff, 0x06, 0x6a, 0x02,
+ 0x10, 0x0c, 0x2b, 0x1b,
+ 0x02, 0x0b, 0x25, 0x1f,
+ 0xff, 0x65, 0x66, 0x02,
+ 0x10, 0x0c, 0x2b, 0x1b,
+ 0xff, 0x12, 0x6d, 0x03,
+ 0xff, 0x06, 0x6a, 0x03,
+ 0xd1, 0x6a, 0x91, 0x00,
+ 0x00, 0x65, 0x48, 0x10,
+ 0xff, 0x65, 0x93, 0x02,
+ 0x01, 0x0b, 0x30, 0x1b,
+ 0x10, 0x0c, 0x2e, 0x1f,
+ 0x04, 0x65, 0x32, 0x1b,
+ 0x01, 0x94, 0x31, 0x1f,
+ 0x40, 0x93, 0x93, 0x02,
+ 0x38, 0x93, 0x33, 0x1b,
+ 0xff, 0x6a, 0x6a, 0x03,
+ 0xf0, 0x65, 0x65, 0x02,
+ 0x0f, 0x05, 0x64, 0x02,
+ 0x00, 0x65, 0x65, 0x00,
+ 0xff, 0x65, 0x05, 0x03,
+ 0x80, 0x4a, 0x34, 0x1f,
+ 0x40, 0x4a, 0x34, 0x1b,
+ 0x21, 0x6a, 0x91, 0x01,
+ 0xff, 0x4b, 0x64, 0x02,
+ 0xff, 0x65, 0x90, 0x02,
+ 0x50, 0x6a, 0x60, 0x00,
+ 0x00, 0xa1, 0x54, 0x19,
+ 0x04, 0xa0, 0x54, 0x1f,
+ 0x20, 0xa0, 0x44, 0x1b,
+ 0xff, 0x3e, 0x46, 0x1d,
+ 0x00, 0x65, 0x54, 0x11,
+ 0xff, 0x3e, 0x64, 0x02,
+ 0x00, 0xb9, 0x54, 0x19,
+ 0x04, 0x4a, 0x53, 0x1f,
+ 0xff, 0xba, 0x4c, 0x1d,
+ 0xff, 0xbb, 0x50, 0x02,
+ 0xff, 0xba, 0x90, 0x02,
+ 0xff, 0x50, 0xbb, 0x02,
+ 0xff, 0x65, 0x90, 0x02,
+ 0xff, 0xbb, 0x52, 0x1d,
+ 0xff, 0xba, 0x50, 0x02,
+ 0xff, 0xbb, 0x90, 0x02,
+ 0xff, 0x50, 0xba, 0x02,
+ 0xff, 0x65, 0x90, 0x02,
+ 0x10, 0x6a, 0x60, 0x01,
+ 0xff, 0xba, 0x4f, 0x02,
+ 0x10, 0x6a, 0x60, 0x01,
+ 0x10, 0x6a, 0x60, 0x00,
+ 0x01, 0x65, 0x65, 0x06,
+ 0xff, 0x47, 0x64, 0x02,
+ 0x00, 0x65, 0x3c, 0x19,
+ 0x31, 0x6a, 0x91, 0x00,
+ 0x10, 0x3f, 0x34, 0x1d,
+ 0x10, 0x03, 0x03, 0x00,
+ 0xff, 0x3e, 0x5e, 0x19,
+ 0x06, 0x6a, 0x1c, 0x17,
+ 0x00, 0x65, 0x48, 0x10,
+ 0x0d, 0x6a, 0x1c, 0x17,
+ 0x00, 0x65, 0x48, 0x10,
+ 0xff, 0xac, 0x88, 0x02,
+ 0xff, 0xad, 0x89, 0x02,
+ 0xff, 0xae, 0x8a, 0x02,
+ 0xff, 0xaf, 0x8b, 0x02,
+ 0xff, 0xb0, 0x8c, 0x02,
+ 0xff, 0xb1, 0x8d, 0x02,
+ 0xff, 0xb2, 0x8e, 0x02,
+ 0xff, 0x8c, 0x08, 0x02,
+ 0xff, 0x8d, 0x09, 0x02,
+ 0xff, 0x8e, 0x0a, 0x02,
+ 0xff, 0xa3, 0x42, 0x02,
+ 0xff, 0xa4, 0x43, 0x02,
+ 0xff, 0xa5, 0x44, 0x02,
+ 0xff, 0xa6, 0x45, 0x02,
+ 0xff, 0xa7, 0x46, 0x03,
+ 0x10, 0x4a, 0x34, 0x1f,
+ 0xff, 0x42, 0xa3, 0x02,
+ 0xff, 0x43, 0xa4, 0x02,
+ 0xff, 0x44, 0xa5, 0x02,
+ 0xff, 0x45, 0xa6, 0x02,
+ 0xff, 0x46, 0xa7, 0x02,
+ 0xff, 0x14, 0xac, 0x02,
+ 0xff, 0x15, 0xad, 0x02,
+ 0xff, 0x16, 0xae, 0x02,
+ 0xff, 0x17, 0xaf, 0x02,
+ 0xff, 0xa9, 0xb0, 0x02,
+ 0xff, 0xaa, 0xb1, 0x02,
+ 0xff, 0xab, 0xb2, 0x03,
+ 0x4c, 0x05, 0x64, 0x0a,
+ 0x08, 0x1f, 0x7f, 0x1f,
+ 0x08, 0x64, 0x64, 0x00,
+ 0x20, 0x64, 0x65, 0x07,
+/* $OpenBSD: ahc_pci.c,v 1.6 1996/11/28 23:28:01 niklas Exp $ */
+/* $NetBSD: ahc_pci.c,v 1.9 1996/10/21 22:56:24 thorpej Exp $ */
+
/*
* Product specific probe and attach routines for:
* 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
- *
- * $Id: ahc_pci.c,v 1.5 1996/11/12 20:30:48 niklas Exp $
*/
#if defined(__FreeBSD__)
#include <sys/queue.h>
#if defined(__NetBSD__) || defined(__OpenBSD__)
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#endif /* defined(__NetBSD__) */
#include <dev/ic/aic7xxxvar.h>
#include <dev/ic/smc93cx6var.h>
+/*
+ * Under normal circumstances, these messages are unnecessary
+ * and not terribly cosmetic.
+ */
+#ifdef DEBUG
#define bootverbose 1
+#else
+#define bootverbose 0
+#endif
+
#define PCI_BASEADR0 PCI_MAPREG_START
#endif /* defined(__NetBSD__) */
#define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul
#define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul
#define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul
+#define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul
#define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul
#define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul
#define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul
case PCI_DEVICE_ID_ADAPTEC_2940:
return ("Adaptec 2940 SCSI host adapter");
break;
+ case PCI_DEVICE_ID_ADAPTEC_2940AU:
+ return ("Adaptec 2940A Ultra SCSI host adapter");
+ break;
case PCI_DEVICE_ID_ADAPTEC_AIC7880:
return ("Adaptec aic7880 Ultra SCSI host adapter");
break;
case PCI_DEVICE_ID_ADAPTEC_3940U:
case PCI_DEVICE_ID_ADAPTEC_2944U:
case PCI_DEVICE_ID_ADAPTEC_2940U:
+ case PCI_DEVICE_ID_ADAPTEC_2940AU:
case PCI_DEVICE_ID_ADAPTEC_3940:
case PCI_DEVICE_ID_ADAPTEC_2944:
case PCI_DEVICE_ID_ADAPTEC_2940:
{
#if defined(__FreeBSD__)
u_long io_port;
+ int unit = ahc->sc_dev.dv_unit;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
struct pci_attach_args *pa = aux;
struct ahc_data *ahc = (void *)self;
- bus_io_addr_t iobase;
- bus_io_size_t iosize;
- bus_io_handle_t ioh;
+ bus_addr_t iobase;
+ bus_size_t iosize;
+ bus_space_handle_t ioh;
pci_intr_handle_t ih;
const char *intrstr;
#endif
#elif defined(__NetBSD__) || defined(__OpenBSD__)
if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize))
return;
- if (bus_io_map(pa->pa_bc, iobase, iosize, &ioh))
+ if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &ioh))
return;
#endif
case PCI_DEVICE_ID_ADAPTEC_2940:
ahc_t = AHC_294;
break;
+ case PCI_DEVICE_ID_ADAPTEC_2940AU:
+ ahc_t = AHC_294AU;
+ break;
case PCI_DEVICE_ID_ADAPTEC_AIC7880:
ahc_t = AHC_AIC7880;
break;
if(ahc_t & AHC_ULTRA)
ultra_enb = inb(SXFRCTL0 + io_port) & ULTRAEN;
#else
- our_id = bus_io_read_1(pa->pa_bc, ioh, SCSIID) & OID;
+ our_id = bus_space_read_1(pa->pa_iot, ioh, SCSIID) & OID;
if(ahc_t & AHC_ULTRA)
- ultra_enb = bus_io_read_1(pa->pa_bc, ioh, SXFRCTL0) & ULTRAEN;
+ ultra_enb = bus_space_read_1(pa->pa_iot, ioh, SXFRCTL0) &
+ ULTRAEN;
#endif
#if defined(__FreeBSD__)
ahc_reset(io_port);
#elif defined(__NetBSD__) || defined(__OpenBSD__)
printf("\n");
- ahc_reset(ahc->sc_dev.dv_xname, pa->pa_bc, ioh);
+ ahc_reset(ahc->sc_dev.dv_xname, pa->pa_iot, ioh);
#endif
if(ahc_t & AHC_AIC7870){
return;
}
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- ahc_construct(ahc, pa->pa_bc, ioh, ahc_t, ahc_f);
+ ahc_construct(ahc, pa->pa_iot, ioh, ahc_t, ahc_f);
if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
pa->pa_intrline, &ih)) {
load_seeprom(ahc);
break;
}
+ case AHC_294AU:
case AHC_AIC7860:
{
id_string = "aic7860 ";
- /*
- * Use defaults, if the chip wasn't initialized by
- * a BIOS.
- */
- ahc->flags |= AHC_USEDEFAULTS;
+ load_seeprom(ahc);
break;
}
case AHC_AIC7850:
#if defined(__FreeBSD__)
sd.sd_iobase = ahc->baseport + SEECTL;
#elif defined(__NetBSD__) || defined(__OpenBSD__)
- sd.sd_bc = ahc->sc_bc;
+ sd.sd_iot = ahc->sc_iot;
sd.sd_ioh = ahc->sc_ioh;
sd.sd_offset = SEECTL;
#endif
-/* $OpenBSD: cy_pci.c,v 1.2 1996/11/12 20:30:49 niklas Exp $ */
+/* $OpenBSD: cy_pci.c,v 1.3 1996/11/28 23:28:02 niklas Exp $ */
/*
* cy.c
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/systm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
#define ISSET(t, f) ((t) & (f))
int cy_probe_pci __P((struct device *, void *, void *));
-int cy_probe_common __P((int card, bus_chipset_tag_t,
- bus_mem_handle_t, int bustype));
+int cy_probe_common __P((int card, bus_space_tag_t,
+ bus_space_handle_t, int bustype));
void cyattach __P((struct device *, struct device *, void *));
vm_offset_t v_addr, p_addr;
int card = ((struct device *)match)->dv_unit;
struct pci_attach_args *pa = aux;
- bus_chipset_tag_t bc;
- bus_mem_handle_t memh;
- bus_mem_addr_t memaddr;
- bus_mem_size_t memsize;
- bus_io_handle_t ioh;
- bus_io_addr_t iobase;
- bus_io_size_t iosize;
+ bus_space_tag_t memt;
+ bus_space_handle_t memh;
+ bus_addr_t memaddr;
+ bus_size_t memsize;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+ bus_addr_t iobase;
+ bus_size_t iosize;
int cacheable;
if(!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES &&
printf("cy: Found Cyclades PCI device, id = 0x%x\n", pa->pa_id);
#endif
- bc = pa->pa_bc;
+ memt = pa->pa_memt;
+ iot = pa->pa_iot;
if(pci_mem_find(pa->pa_pc, pa->pa_tag, 0x18,
&memaddr, &memsize, &cacheable) != 0) {
}
/* map the memory (non-cacheable) */
- if(bus_mem_map(bc, memaddr, memsize, 0, &memh) != 0) {
+ if(bus_space_map(memt, memaddr, memsize, 0, &memh) != 0) {
printf("cy%d: couldn't map PCI memory region\n", card);
return 0;
}
/* the PCI Cyclom IO space is only used for enabling interrupts */
if(pci_io_find(pa->pa_pc, pa->pa_tag, 0x14, &iobase, &iosize) != 0) {
- bus_mem_unmap(bc, memh, memsize);
+ bus_space_unmap(memt, memh, memsize);
printf("cy%d: couldn't find PCI io region\n", card);
return 0;
}
- if(bus_io_map(bc, iobase, iosize, &ioh) != 0) {
- bus_mem_unmap(bc, memh, memsize);
+ if(bus_space_map(iot, iobase, iosize, &ioh) != 0) {
+ bus_space_unmap(memt, memh, memsize);
printf("cy%d: couldn't map PCI io region\n", card);
return 0;
}
card, memaddr, memsize, iobase, iosize);
#endif
- if(cy_probe_common(card, bc, memh, CY_BUSTYPE_PCI) == 0) {
- bus_mem_unmap(bc, memh, memsize);
- bus_io_unmap(bc, ioh, iosize);
+ if(cy_probe_common(card, memt, memh, CY_BUSTYPE_PCI) == 0) {
+ bus_space_unmap(memt, memh, memsize);
+ bus_space_unmap(iot, ioh, iosize);
printf("cy%d: PCI Cyclom card with no CD1400s!?\n", card);
return 0;
}
/* Enable PCI card interrupts */
- bus_io_write_2(bc, ioh, CY_PCI_INTENA,
- bus_io_read_2(bc, ioh, CY_PCI_INTENA) | 0x900);
+ bus_space_write_2(iot, ioh, CY_PCI_INTENA,
+ bus_space_read_2(iot, ioh, CY_PCI_INTENA) | 0x900);
return 1;
}
-# $OpenBSD: files.pci,v 1.9 1996/07/27 07:20:07 deraadt Exp $
-# $NetBSD: files.pci,v 1.16 1996/05/16 03:44:16 mycroft Exp $
+# $OpenBSD: files.pci,v 1.10 1996/11/28 23:28:03 niklas Exp $
+# $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
#
# Config.new file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
file dev/pci/ahc_pci.c ahc_pci
file dev/ic/smc93cx6.c ahc_pci
+# BusLogic BT-9xx PCI family
+# device declaration in sys/dev/isa/files.isa
+attach bha at pci with bha_pci
+file dev/pci/bha_pci.c bha_pci
+
# Ethernet driver for DC21040-based boards
device de: ether, ifnet
attach de at pci
file dev/pci/if_de.c de
+# ENI ATM driver
+device en: atm, ifnet
+attach en at pci with en_pci
+file dev/pci/if_en_pci.c en
+file dev/ic/midway.c en
+
+# 3Com 3c590 and 3c595 Ethernet controllers
+# device declaration in sys/conf/files
+attach ep at pci with ep_pci
+file dev/pci/if_ep_pci.c ep_pci
+
# Digital DEFPA PCI FDDI Controller
device fpa: pdq, fddi, ifnet
attach fpa at pci
file dev/pci/if_fpa.c fpa
+# AMD am7990 (LANCE) -based Ethernet controllers
+# device declaration in sys/conf/files
+attach le at pci with le_pci
+file dev/pci/if_le_pci.c le_pci
+
# NCR 53c8xx SCSI chips
device ncr: scsi
attach ncr at pci
attach ppb at pci
file dev/pci/ppb.c ppb
-# 3Com 3c590 and 3c595 Ethernet controllers
-# device declaration in sys/conf/files
-attach ep at pci with ep_pci
-file dev/pci/if_ep_pci.c ep_pci
-
-# AMD am7990 (LANCE) -based Ethernet controllers
-# device declaration in sys/conf/files
-attach le at pci with le_pci
-file dev/pci/if_le_pci.c le_pci
-
-# ENI ATM driver
-device en: atm, ifnet
-attach en at pci with en_pci
-file dev/pci/if_en_pci.c en
-file dev/ic/midway.c en
-
-# Cyclades Cyclom multiport serial cards
+# Cyclades Cyclom-8/16/32
attach cy at pci with cy_pci
file dev/pci/cy_pci.c cy_pci
-/* $OpenBSD: if_de.c,v 1.14 1996/11/12 20:30:51 niklas Exp $ */
-/* $NetBSD: if_de.c,v 1.22.4.1 1996/06/03 20:32:07 cgd Exp $ */
+/* $OpenBSD: if_de.c,v 1.15 1996/11/28 23:28:04 niklas Exp $ */
+/* $NetBSD: if_de.c,v 1.29 1996/10/25 21:33:30 cgd Exp $ */
/*-
* Copyright (c) 1994, 1995 Matt Thomas (matt@lkg.dec.com)
#endif /* __bsdi__ */
#if defined(__NetBSD__) || defined(__OpenBSD__)
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/pci/pcireg.h>
int ri_free;
} tulip_ringinfo_t;
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+/*
+ * These macros are the same for NetBSD regardless of TULIP_IOMAPPED.
+ */
+typedef bus_size_t tulip_csrptr_t;
+
+#define TULIP_READ_CSR(sc, csr) \
+ bus_space_read_4((sc)->tulip_bst, (sc)->tulip_bsh, (sc)->tulip_csrs.csr)
+#define TULIP_WRITE_CSR(sc, csr, val) \
+ bus_space_write_4((sc)->tulip_bst, (sc)->tulip_bsh, (sc)->tulip_csrs.csr, \
+ (val))
+
+#define TULIP_READ_CSRBYTE(sc, csr) \
+ bus_space_read_1((sc)->tulip_bst, (sc)->tulip_bsh, (sc)->tulip_csrs.csr)
+#define TULIP_WRITE_CSRBYTE(sc, csr, val) \
+ bus_space_write_1((sc)->tulip_bst, (sc)->tulip_bsh, (sc)->tulip_csrs.csr, \
+ (val))
+#endif /* __NetBSD__ */
+
#ifdef TULIP_IOMAPPED
#define TULIP_EISA_CSRSIZE 16
#define TULIP_READ_CSRBYTE(sc, csr) (inb((sc)->tulip_csrs.csr))
#define TULIP_WRITE_CSRBYTE(sc, csr, val) outb((sc)->tulip_csrs.csr, val)
-#else
-typedef bus_io_size_t tulip_csrptr_t;
-
-#define TULIP_READ_CSR(sc, csr) \
- bus_io_read_4((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr)
-#define TULIP_WRITE_CSR(sc, csr, val) \
- bus_io_write_4((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr, (val))
-
-#define TULIP_READ_CSRBYTE(sc, csr) \
- bus_io_read_1((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr)
-#define TULIP_WRITE_CSRBYTE(sc, csr, val) \
- bus_io_write_1((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr, (val))
-#endif
+#endif /* ! __NetBSD__ */
#else /* TULIP_IOMAPPED */
#define TULIP_READ_CSR(sc, csr) (0 + *(sc)->tulip_csrs.csr)
#define TULIP_WRITE_CSR(sc, csr, val) \
((void)(*(sc)->tulip_csrs.csr = (val)))
-#else
-typedef bus_mem_size_t tulip_csrptr_t;
+#endif /* ! __NetBSD__ */
-#define TULIP_READ_CSR(sc, csr) \
- bus_mem_read_4((sc)->tulip_bc, (sc)->tulip_memh, (sc)->tulip_csrs.csr)
-#define TULIP_WRITE_CSR(sc, csr, val) \
- bus_mem_write_4((sc)->tulip_bc, (sc)->tulip_memh, (sc)->tulip_csrs.csr, \
- (val))
-#endif
#endif /* TULIP_IOMAPPED */
typedef struct {
struct device tulip_dev; /* base device */
void *tulip_ih; /* intrrupt vectoring */
void *tulip_ats; /* shutdown hook */
- bus_chipset_tag_t tulip_bc;
- pci_chipset_tag_t tulip_pc;
-#ifdef TULIP_IOMAPPED
- bus_io_handle_t tulip_ioh; /* I/O region handle */
-#else
- bus_io_handle_t tulip_memh; /* memory region handle */
-#endif
+ pci_chipset_tag_t tulip_pc; /* PCI chipset cookie */
+ bus_space_tag_t tulip_bst; /* bus space tag */
+ bus_space_handle_t tulip_bsh; /* bus space handle */
#endif
char tulip_xname[IFNAMSIZ]; /* name + unit number */
struct arpcom tulip_ac;
#if (defined(__NetBSD__) || defined(__OpenBSD__)) && defined(__alpha__)
/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
-#define vtophys(va) __alpha_bus_XXX_dmamap(sc->tulip_bc, (void *)(va))
-
+#undef vtophys
+#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
#endif
+
\f
static int
tulip_dc21040_media_probe(
#if defined(__NetBSD__) || defined(__OpenBSD__)
tulip_softc_t * const sc = (tulip_softc_t *) self;
struct pci_attach_args * const pa = (struct pci_attach_args *) aux;
- bus_chipset_tag_t bc = pa->pa_bc;
pci_chipset_tag_t pc = pa->pa_pc;
-#if defined(TULIP_IOMAPPED)
- bus_io_addr_t iobase;
- bus_io_size_t iosize;
-#else
- bus_mem_addr_t membase;
- bus_mem_size_t memsize;
-#endif
+ bus_addr_t tulipbase;
+ bus_size_t tulipsize;
#if defined(__FreeBSD__)
int unit = sc->tulip_dev.dv_unit;
#endif
#endif /* __bsdi__ */
#if defined(__NetBSD__) || defined(__OpenBSD__)
- sc->tulip_bc = bc;
sc->tulip_pc = pc;
#if defined(TULIP_IOMAPPED)
- retval = pci_io_find(pc, pa->pa_tag, PCI_CBIO, &iobase, &iosize);
+ sc->tulip_bst = pa->pa_iot;
+ retval = pci_io_find(pc, pa->pa_tag, PCI_CBIO, &tulipbase, &tulipsize);
if (!retval)
- retval = bus_io_map(bc, iobase, iosize, &sc->tulip_ioh);
+ retval = bus_space_map(pa->pa_iot, tulipbase, tulipsize, 0,
+ &sc->tulip_bsh);
#else
- retval = pci_mem_find(pc, pa->pa_tag, PCI_CBMA, &membase, &memsize,
+ sc->tulip_bst = pa->pa_memt;
+ retval = pci_mem_find(pc, pa->pa_tag, PCI_CBMA, &tulipbase, &tulipsize,
NULL);
if (!retval)
- retval = bus_mem_map(bc, membase, memsize, 0, &sc->tulip_memh);
+ retval = bus_space_map(pa->pa_memt, tulipbase, tulipsize, 0,
+ &sc->tulip_bsh);
#endif
csr_base = 0;
if (retval) {
-/* $NetBSD: if_ep_pci.c,v 1.7 1996/05/13 00:03:15 mycroft Exp $ */
+/* $NetBSD: if_ep_pci.c,v 1.13 1996/10/21 22:56:38 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/ic/elink3var.h>
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_3COM_3C590:
- case PCI_PRODUCT_3COM_3C595:
- case PCI_PRODUCT_3COM_3C595T:
- case PCI_PRODUCT_3COM_3C595TM:
- case PCI_PRODUCT_3COM_3C900:
- case PCI_PRODUCT_3COM_3C900T:
- case PCI_PRODUCT_3COM_3C905:
- case PCI_PRODUCT_3COM_3C905T:
+ case PCI_PRODUCT_3COM_3C595MII:
+ case PCI_PRODUCT_3COM_3C595T4:
+ case PCI_PRODUCT_3COM_3C595TX:
+ case PCI_PRODUCT_3COM_3C900COMBO:
+ case PCI_PRODUCT_3COM_3C900TPO:
+ case PCI_PRODUCT_3COM_3C905T4:
+ case PCI_PRODUCT_3COM_3C905TX:
break;
default:
return 0;
struct ep_softc *sc = (void *)self;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
- bus_chipset_tag_t bc = pa->pa_bc;
- bus_io_addr_t iobase;
- bus_io_size_t iosize;
+ bus_space_tag_t iot = pa->pa_iot;
+ bus_addr_t iobase;
+ bus_size_t iosize;
pci_intr_handle_t ih;
u_short conn = 0;
pcireg_t i;
return;
}
- if (bus_io_map(bc, iobase, iosize, &sc->sc_ioh)) {
+ if (bus_space_map(iot, iobase, iosize, 0, &sc->sc_ioh)) {
printf(": can't map i/o space\n");
return;
}
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->bustype = EP_BUS_PCI;
i = pci_conf_read(pc, pa->pa_tag, PCI_CONN);
case PCI_PRODUCT_3COM_3C590:
model = "3Com 3C590 Ethernet";
break;
- case PCI_PRODUCT_3COM_3C595:
- case PCI_PRODUCT_3COM_3C595T:
- case PCI_PRODUCT_3COM_3C595TM:
+ case PCI_PRODUCT_3COM_3C595MII:
+ case PCI_PRODUCT_3COM_3C595T4:
+ case PCI_PRODUCT_3COM_3C595TX:
model = "3Com 3C595 Ethernet";
break;
- case PCI_PRODUCT_3COM_3C900:
- case PCI_PRODUCT_3COM_3C900T:
+ case PCI_PRODUCT_3COM_3C900COMBO:
+ case PCI_PRODUCT_3COM_3C900TPO:
model = "3Com 3C900 Ethernet";
break;
- case PCI_PRODUCT_3COM_3C905:
- case PCI_PRODUCT_3COM_3C905T:
+ case PCI_PRODUCT_3COM_3C905T4:
+ case PCI_PRODUCT_3COM_3C905TX:
model = "3Com 3C905 Ethernet";
break;
default:
model = "unknown model!";
+ break;
}
printf(": <%s> ", model);
return;
}
printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
-
- epstop(sc);
}
-/* $NetBSD: if_fpa.c,v 1.11 1996/05/20 15:53:02 thorpej Exp $ */
+/* $OpenBSD: if_fpa.c,v 1.10 1996/11/28 23:28:06 niklas Exp $ */
+/* $NetBSD: if_fpa.c,v 1.15 1996/10/21 22:56:40 thorpej Exp $ */
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
pdq_uint32_t data;
pci_intr_handle_t intrhandle;
const char *intrstr;
-#ifdef PDQ_IOMAPPED
- bus_io_addr_t iobase;
- bus_io_size_t iosize;
-#else
- bus_mem_addr_t membase;
- bus_mem_size_t memsize;
-#endif
+ bus_addr_t csrbase;
+ bus_size_t csrsize;
+ int cacheable = 0;
data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CFLT);
if ((data & 0xFF00) < (DEFPA_LATENCY << 8)) {
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_CFLT, data);
}
- sc->sc_bc = pa->pa_bc;
bcopy(sc->sc_dev.dv_xname, sc->sc_if.if_xname, IFNAMSIZ);
sc->sc_if.if_flags = 0;
sc->sc_if.if_softc = sc;
+ /*
+ * NOTE: sc_bc is an alias for sc_csrtag and sc_membase is an
+ * alias for sc_csrhandle. sc_iobase is not used in this front-end.
+ */
#ifdef PDQ_IOMAPPED
- if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_CBIO, &iobase, &iosize)
- || bus_io_map(pa->pa_bc, iobase, iosize, &sc->sc_iobase)){
- printf("\n%s: can't map I/O space!\n", sc->sc_dev.dv_xname);
+ sc->sc_csrtag = pa->pa_iot;
+ if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_CBIO, &csrbase, &csrsize)) {
+ printf("\n%s: can't find I/O space!\n", sc->sc_dev.dv_xname);
return;
}
#else
- if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_CBMA, &membase, &memsize, NULL)
- || bus_mem_map(pa->pa_bc, membase, memsize, 0, &sc->sc_membase)) {
- printf("\n%s: can't map memory space!\n", sc->sc_dev.dv_xname);
+ sc->sc_csrtag = pa->pa_memt;
+ if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_CBMA, &csrbase, &csrsize,
+ &cacheable)) {
+ printf("\n%s: can't find memory space!\n", sc->sc_dev.dv_xname);
return;
}
#endif
- sc->sc_pdq = pdq_initialize(sc->sc_bc, sc->sc_membase,
+ if (bus_space_map(sc->sc_csrtag, csrbase, csrsize, cacheable,
+ &sc->sc_csrhandle)) {
+ printf("\n%s: can't map CSRs!\n", sc->sc_dev.dv_xname);
+ return;
+ }
+
+ sc->sc_pdq = pdq_initialize(sc->sc_csrtag, sc->sc_csrhandle,
sc->sc_if.if_xname, 0,
(void *) sc, PDQ_DEFPA);
if (sc->sc_pdq == NULL) {
-/* $NetBSD: if_le_pci.c,v 1.6.4.1 1996/06/03 20:32:13 cgd Exp $ */
+/* $NetBSD: if_le_pci.c,v 1.13 1996/10/25 21:33:32 cgd Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
#include <vm/vm.h>
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/pci/pcireg.h>
#ifdef __alpha__ /* XXX */
/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
-#define vtophys(va) __alpha_bus_XXX_dmamap(lesc->sc_bc, (void *)(va))
+#undef vtophys
+#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
#endif
int le_pci_match __P((struct device *, void *, void *));
u_int16_t port, val;
{
struct le_softc *lesc = (struct le_softc *)sc;
- bus_chipset_tag_t bc = lesc->sc_bc;
- bus_io_handle_t ioh = lesc->sc_ioh;
+ bus_space_tag_t iot = lesc->sc_iot;
+ bus_space_handle_t ioh = lesc->sc_ioh;
- bus_io_write_2(bc, ioh, lesc->sc_rap, port);
- bus_io_write_2(bc, ioh, lesc->sc_rdp, val);
+ bus_space_write_2(iot, ioh, lesc->sc_rap, port);
+ bus_space_write_2(iot, ioh, lesc->sc_rdp, val);
}
hide u_int16_t
u_int16_t port;
{
struct le_softc *lesc = (struct le_softc *)sc;
- bus_chipset_tag_t bc = lesc->sc_bc;
- bus_io_handle_t ioh = lesc->sc_ioh;
+ bus_space_tag_t iot = lesc->sc_iot;
+ bus_space_handle_t ioh = lesc->sc_ioh;
u_int16_t val;
- bus_io_write_2(bc, ioh, lesc->sc_rap, port);
- val = bus_io_read_2(bc, ioh, lesc->sc_rdp);
+ bus_space_write_2(iot, ioh, lesc->sc_rap, port);
+ val = bus_space_read_2(iot, ioh, lesc->sc_rdp);
return (val);
}
struct am7990_softc *sc = &lesc->sc_am7990;
struct pci_attach_args *pa = aux;
pci_intr_handle_t ih;
- bus_io_addr_t iobase;
- bus_io_size_t iosize;
- bus_io_handle_t ioh;
- bus_chipset_tag_t bc = pa->pa_bc;
+ bus_addr_t iobase;
+ bus_size_t iosize;
+ bus_space_handle_t ioh;
+ bus_space_tag_t iot = pa->pa_iot;
pci_chipset_tag_t pc = pa->pa_pc;
pcireg_t csr;
int i;
printf("%s: can't find I/O base\n", sc->sc_dev.dv_xname);
return;
}
- if (bus_io_map(bc, iobase, iosize, &ioh)) {
+ if (bus_space_map(iot, iobase, iosize, 0, &ioh)) {
printf("%s: can't map I/O space\n", sc->sc_dev.dv_xname);
return;
}
* Extract the physical MAC address from the ROM.
*/
for (i = 0; i < sizeof(sc->sc_arpcom.ac_enaddr); i++)
- sc->sc_arpcom.ac_enaddr[i] = bus_io_read_1(bc, ioh, i);
+ sc->sc_arpcom.ac_enaddr[i] = bus_space_read_1(iot, ioh, i);
sc->sc_mem = malloc(16384, M_DEVBUF, M_NOWAIT);
if (sc->sc_mem == 0) {
return;
}
- lesc->sc_bc = bc;
+ lesc->sc_iot = iot;
lesc->sc_ioh = ioh;
sc->sc_conf3 = 0;
-/* $NetBSD: if_levar.h,v 1.2 1996/05/12 02:30:05 thorpej Exp $ */
+/* $NetBSD: if_levar.h,v 1.3 1996/10/21 22:56:46 thorpej Exp $ */
/*
* LANCE Ethernet driver header file
struct am7990_softc sc_am7990; /* glue to MI code */
void *sc_ih;
- bus_chipset_tag_t sc_bc; /* chipset cookie */
- bus_io_handle_t sc_ioh; /* bus i/o handle */
+ bus_space_tag_t sc_iot; /* space cookie */
+ bus_space_handle_t sc_ioh; /* bus space handle */
int sc_rap, sc_rdp; /* offsets to LANCE registers */
};
-/* $OpenBSD: ncr.c,v 1.19 1996/11/23 21:47:04 kstailey Exp $ */
-/* $NetBSD: ncr.c,v 1.35.4.1 1996/06/03 20:32:17 cgd Exp $ */
+/* $OpenBSD: ncr.c,v 1.20 1996/11/28 23:28:08 niklas Exp $ */
+/* $NetBSD: ncr.c,v 1.48 1996/10/25 21:33:33 cgd Exp $ */
/**************************************************************************
**
#if defined(__NetBSD__) || defined(__OpenBSD__)
#ifdef _KERNEL
#define KERNEL
-
-/*
- * Normally found in the userland header stddef.h, which isn't available.
- */
-#define offsetof(type, member) ((size_t)(&((type *)0)->member))
#endif
-#else
-#include <stddef.h>
#endif
+#define offsetof(type, member) ((size_t)(&((type *)0)->member))
+
#include <sys/types.h>
#include <sys/param.h>
#include <sys/time.h>
#include <pci/ncrreg.h>
#else
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/pci/ncr_reg.h>
#include <dev/pci/pcireg.h>
#if (defined(__NetBSD__) || defined(__OpenBSD__)) && defined(__alpha__)
/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
-#define vtophys(va) __alpha_bus_XXX_dmamap(np->sc_bc, (void *)(va))
+#undef vtophys
+#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
#endif
/*==========================================================
**----------------------------------------------------------
*/
+#undef assert
#define assert(expression) { \
if (!(expression)) { \
(void)printf(\
#define INB(r) \
INB_OFF(offsetof(struct ncr_reg, r))
#define INB_OFF(o) \
- bus_io_read_1 (np->sc_bc, np->sc_ioh, (o))
+ bus_space_read_1 (np->sc_memt, np->sc_bah, (o))
#define INW(r) \
- bus_io_read_2 (np->sc_bc, np->sc_ioh, offsetof(struct ncr_reg, r))
+ bus_space_read_2 (np->sc_memt, np->sc_bah, offsetof(struct ncr_reg, r))
#define INL(r) \
INL_OFF(offsetof(struct ncr_reg, r))
#define INL_OFF(o) \
- bus_io_read_4 (np->sc_bc, np->sc_ioh, (o))
+ bus_space_read_4 (np->sc_memt, np->sc_bah, (o))
#define OUTB(r, val) \
- bus_io_write_1 (np->sc_bc, np->sc_ioh, offsetof(struct ncr_reg, r), (val))
+ bus_space_write_1 (np->sc_memt, np->sc_bah, offsetof(struct ncr_reg, r), (val))
#define OUTW(r, val) \
- bus_io_write_2 (np->sc_bc, np->sc_ioh, offsetof(struct ncr_reg, r), (val))
+ bus_space_write_2 (np->sc_memt, np->sc_bah, offsetof(struct ncr_reg, r), (val))
#define OUTL(r, val) \
OUTL_OFF(offsetof(struct ncr_reg, r), (val))
#define OUTL_OFF(o, val) \
- bus_io_write_4 (np->sc_bc, np->sc_ioh, (o), (val))
+ bus_space_write_4 (np->sc_memt, np->sc_bah, (o), (val))
#else
#define INB(r) \
INB_OFF(offsetof(struct ncr_reg, r))
#define INB_OFF(o) \
- bus_mem_read_1 (np->sc_bc, np->sc_memh, (o))
+ bus_space_read_1 (np->sc_memt, np->sc_bah, (o))
#define INW(r) \
- bus_mem_read_2 (np->sc_bc, np->sc_memh, offsetof(struct ncr_reg, r))
+ bus_space_read_2 (np->sc_memt, np->sc_bah, offsetof(struct ncr_reg, r))
#define INL(r) \
INL_OFF(offsetof(struct ncr_reg, r))
#define INL_OFF(o) \
- bus_mem_read_4 (np->sc_bc, np->sc_memh, (o))
+ bus_space_read_4 (np->sc_memt, np->sc_bah, (o))
#define OUTB(r, val) \
- bus_mem_write_1 (np->sc_bc, np->sc_memh, offsetof(struct ncr_reg, r), (val))
+ bus_space_write_1 (np->sc_memt, np->sc_bah, offsetof(struct ncr_reg, r), (val))
#define OUTW(r, val) \
- bus_mem_write_2 (np->sc_bc, np->sc_memh, offsetof(struct ncr_reg, r), (val))
+ bus_space_write_2 (np->sc_memt, np->sc_bah, offsetof(struct ncr_reg, r), (val))
#define OUTL(r, val) \
OUTL_OFF(offsetof(struct ncr_reg, r), (val))
#define OUTL_OFF(o, val) \
- bus_mem_write_4 (np->sc_bc, np->sc_memh, (o), (val))
+ bus_space_write_4 (np->sc_memt, np->sc_bah, (o), (val))
#endif
#if defined(__NetBSD__) || defined(__OpenBSD__)
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_memt;
pci_chipset_tag_t sc_pc;
-#ifdef NCR_IOMAPPED
- bus_io_handle_t sc_ioh;
-#else /* !NCR_IOMAPPED */
- bus_mem_handle_t sc_memh;
-#endif /* NCR_IOMAPPED */
+ bus_space_handle_t sc_bah;
#else /* !__NetBSD__ */
int unit;
#endif /* __NetBSD__ */
vm_offset_t vaddr;
vm_offset_t paddr;
#else
- bus_mem_addr_t paddr;
+ bus_addr_t paddr;
#endif
#if !(defined(__NetBSD__) || defined(__OpenBSD__))
#if 0
static char ident[] =
- "\n$NetBSD: ncr.c,v 1.35.4.1 1996/06/03 20:32:17 cgd Exp $\n";
+ "\n$NetBSD: ncr.c,v 1.48 1996/10/25 21:33:33 cgd Exp $\n";
#endif
static const u_long ncr_version = NCR_VERSION * 11
* Kernel variables referenced in the scripts.
* THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY.
*/
-static void *script_kvars[] =
- { (void *)&mono_time.tv_sec, (void *)&mono_time, (void *)&ncr_cache };
+static unsigned long script_kvars[] = {
+ (unsigned long)&mono_time.tv_sec,
+ (unsigned long)&mono_time,
+ (unsigned long)&ncr_cache,
+};
static struct script script0 = {
/*--------------------------< START >-----------------------*/ {
((old & ~RELOC_MASK) >
SCRIPT_KVAR_LAST))
panic("ncr KVAR out of range");
- new = vtophys(script_kvars[old &
+ new = vtophys((void *)script_kvars[old &
~RELOC_MASK]);
break;
case 0:
#define MIN_ASYNC_PD 40
#define MIN_SYNC_PD 20
-#if defined(__NetBSD__) || defined(__OpenBSD__)
+#if defined(__OpenBSD__)
int ncr_print __P((void *, const char *));
return UNCONF;
}
+#endif
+#if defined(__NetBSD__) || defined(__OpenBSD__)
+
void
ncr_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct pci_attach_args *pa = aux;
- bus_chipset_tag_t bc = pa->pa_bc;
+ bus_space_tag_t memt = pa->pa_memt;
pci_chipset_tag_t pc = pa->pa_pc;
- bus_mem_size_t memsize;
+ bus_size_t memsize;
int retval, cacheable;
pci_intr_handle_t intrhandle;
const char *intrstr;
ncb_p np = (void *)self;
+ int wide = 0;
printf(": NCR ");
switch (pa->pa_id) {
break;
case NCR_825_ID:
printf("53c825 Wide");
+ wide = 1;
break;
case NCR_860_ID:
printf("53c860");
break;
case NCR_875_ID:
printf("53c875 Wide");
+ wide = 1;
break;
}
printf(" SCSI\n");
- np->sc_bc = bc;
+ np->sc_memt = memt;
np->sc_pc = pc;
/*
}
/* Map the memory. Note that we never want it to be cacheable. */
- retval = bus_mem_map(pa->pa_bc, np->paddr, memsize, 0, &np->sc_memh);
+ retval = bus_space_map(pa->pa_memt, np->paddr, memsize, 0,
+ &np->sc_bah);
if (retval) {
printf("%s: couldn't map memory region\n", self->dv_xname);
return;
np->sc_link.adapter_softc = np;
np->sc_link.adapter_target = np->myaddr;
np->sc_link.openings = 1;
+#ifndef __OpenBSD__
+ np->sc_link.channel = SCSI_CHANNEL_ONLY_ONE;
+#endif
#else /* !__NetBSD__ */
np->sc_link.adapter_unit = unit;
np->sc_link.adapter_softc = np;
np->sc_link.device = &ncr_dev;
np->sc_link.flags = 0;
-#if defined(__NetBSD__) || defined(__OpenBSD__)
+#if defined(__NetBSD__)
+ config_found(self, &np->sc_link, scsiprint);
+#elif defined(__OpenBSD__)
config_found(self, &np->sc_link, ncr_print);
#else /* !__NetBSD__ */
#if (__FreeBSD__ >= 2)
-/* $OpenBSD: pci.c,v 1.4 1996/11/23 21:47:05 kstailey Exp $ */
-/* $NetBSD: pci.c,v 1.19 1996/05/03 17:33:49 christos Exp $ */
+/* $OpenBSD: pci.c,v 1.5 1996/11/28 23:28:09 niklas Exp $ */
+/* $NetBSD: pci.c,v 1.24 1996/10/21 22:56:55 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
void *aux;
{
struct pcibus_attach_args *pba = aux;
- bus_chipset_tag_t bc;
+ bus_space_tag_t iot, memt;
pci_chipset_tag_t pc;
int bus, device, maxndevs, function, nfunctions;
pci_attach_hook(parent, self, pba);
printf("\n");
- bc = pba->pba_bc;
+ iot = pba->pba_iot;
+ memt = pba->pba_memt;
pc = pba->pba_pc;
bus = pba->pba_bus;
maxndevs = pci_bus_maxdevs(pc, bus);
class = pci_conf_read(pc, tag, PCI_CLASS_REG);
intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
- pa.pa_bc = bc;
+ pa.pa_iot = iot;
+ pa.pa_memt = memt;
pa.pa_pc = pc;
pa.pa_device = device;
pa.pa_function = function;
pci_chipset_tag_t pc;
pcitag_t pcitag;
int reg;
- bus_io_addr_t *iobasep;
- bus_io_size_t *iosizep;
+ bus_addr_t *iobasep;
+ bus_size_t *iosizep;
{
pcireg_t addrdata, sizedata;
int s;
if (iobasep != NULL)
*iobasep = PCI_MAPREG_IO_ADDR(addrdata);
if (iosizep != NULL)
- *iosizep = ~PCI_MAPREG_IO_ADDR(sizedata) + 1;
+ *iosizep = PCI_MAPREG_IO_SIZE(sizedata);
return (0);
}
pci_chipset_tag_t pc;
pcitag_t pcitag;
int reg;
- bus_mem_addr_t *membasep;
- bus_mem_size_t *memsizep;
+ bus_addr_t *membasep;
+ bus_size_t *memsizep;
int *cacheablep;
{
pcireg_t addrdata, sizedata;
if (membasep != NULL)
*membasep = PCI_MAPREG_MEM_ADDR(addrdata); /* PCI addr */
if (memsizep != NULL)
- *memsizep = ~PCI_MAPREG_MEM_ADDR(sizedata) + 1;
+ *memsizep = PCI_MAPREG_MEM_SIZE(sizedata);
if (cacheablep != NULL)
*cacheablep = PCI_MAPREG_MEM_CACHEABLE(addrdata);
-/* $OpenBSD: pci_subr.c,v 1.3 1996/10/31 03:29:11 millert Exp $ */
-/* $NetBSD: pci_subr.c,v 1.17 1996/03/02 02:28:48 cgd Exp $ */
+/* $OpenBSD: pci_subr.c,v 1.4 1996/11/28 23:28:10 niklas Exp $ */
+/* $NetBSD: pci_subr.c,v 1.19 1996/10/13 01:38:29 christos Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
-$OpenBSD: pcidevs,v 1.13 1996/10/14 10:22:22 deraadt Exp $
-/* $NetBSD: pcidevs,v 1.8 1996/05/07 01:59:45 thorpej Exp $ */
+$OpenBSD: pcidevs,v 1.14 1996/11/28 23:28:11 niklas Exp $
+/* $NetBSD: pcidevs,v 1.20 1996/10/19 13:01:49 jonathan Exp $ */
/*
vendor ACC 0x10aa ACC Microelectronics
vendor DIGICOM 0x10ab Digicom
vendor HONEYWELL 0x10ac Honeywell IASD
-vendor SYMPHONY 0x10ad Symphony Labs (or Winbond?)
vendor CORNERSTONE 0x10ae Cornerstone Technology
vendor MICROCOMPSON 0x10af Micro Computer Sysytems (M) SON
vendor CARDEXPER 0x10b0 CardExpert Technology
vendor NVIDIA 0x10de Nvidia Corporation
vendor EMULEX 0x10df Emulex
vendor IMS 0x10e0 Integrated Micro Solutions
-vendor TEKRAM 0x10e1 Tekram Technology
vendor APTIX 0x10e2 Aptix Corporation
vendor NEWBRIDGE 0x10e3 Newbridge Microsystems
vendor TANDEM 0x10e4 Tandem Computers
vendor TRIONES 0x1103 Triones Technologies
vendor RASTEROPS 0x1104 RasterOps
vendor SIGMA 0x1105 Sigma Designs
-vendor VIATECH 0x1106 Via Technologies
+vendor VIATECH 0x1106 VIA Technologies
vendor STRATIS 0x1107 Stratus Computer
vendor PROTEON 0x1108 Proteon
vendor COGENT 0x1109 Cogent Data Technologies
vendor ZEITNET 0x1193 ZeitNet
vendor SPECIALIX 0x11cb Specialix
vendor CYCLADES 0x120e Cyclades
-vendor SYMPHONY2 0x1c1c Symphony (duplicate? see 0x10ad)
-vendor TEKRAM2 0x1de1 Tekram (mistyped? see 0x10e1)
+vendor ZEINET 0x1193 Zeinet
+vendor SYMPHONY 0x1c1c Symphony Labs
+vendor TEKRAM 0x1de1 Tekram Technology
vendor AVANCE2 0x4005 Avance Logic (mistyped? see 0x1005)
vendor S3 0x5333 S3
vendor INTEL 0x8086 Intel
*/
/* 3COM Products */
-product 3COM 3C590 0x5900 3c590 10Mbps
-product 3COM 3C595 0x5950 3c595 100Base-TX
-product 3COM 3C595T 0x5951 3c595 100Base-T4
-product 3COM 3C595TM 0x5952 3c595 100Base-T/MII
-product 3COM 3C900 0x9000 3c900 10Base-T
-product 3COM 3C900T 0x9001 3c900 10Mbps-Combo
-product 3COM 3C905 0x9050 3c905 100Base-TX
-product 3COM 3C905T 0x9051 3c905 100Base-T4
-
-/* Acer products */
-product ACER M1435 0x1435 M1435
+product 3COM 3C590 0x5900 3c590 10Mbps
+product 3COM 3C595TX 0x5950 3c595 100Base-TX
+product 3COM 3C595T4 0x5951 3c595 100Base-T4
+product 3COM 3C595MII 0x5952 3c595 10Mbps-MII
+product 3COM 3C900TPO 0x9000 3c900 10Base-T
+product 3COM 3C900COMBO 0x9001 3c900 10Mbps-Combo
+product 3COM 3C905TX 0x9050 3c905 100Base-TX
+product 3COM 3C905T4 0x9051 3c905 100Base-T4
+
+/* Acer Labs products */
+product ALI M1445 0x1445 M1445
+product ALI M1449 0x1449 M1449
+product ALI M1451 0x1451 M1451
+product ALI M4803 0x5215 M4803
/* Adaptec products */
-product ADP 3940U 0x8278 AHA-3940 Ultra
-product ADP 2944U 0x8478 AHA-2944 Ultra
-product ADP 2940U 0x8178 AHA-2940 Ultra
-product ADP 3940 0x7278 AHA-3940
-product ADP 2944 0x7478 AHA-2944
-product ADP 2940 0x7178 AHA-2940
-product ADP AIC7880 0x8078 AIC-7880 Ultra
-product ADP AIC7870 0x7078 AIC-7870
-product ADP AIC7850 0x5078 AIC-7850
+product ADP AIC7850 0x5078 AIC-7850
+product ADP AIC7855 0x5578 AIC-7855
+product ADP AIC7860 0x6078 AIC-7860
+product ADP 2940AU 0x6178 AHA-2940A Ultra
+product ADP AIC7870 0x7078 AIC-7870
+product ADP 2940 0x7178 AHA-2940
+product ADP 3940 0x7278 AHA-3940
+product ADP 2944 0x7478 AHA-2944
+product ADP AIC7880 0x8078 AIC-7880 Ultra
+product ADP 2940U 0x8178 AHA-2940 Ultra
+product ADP 3940U 0x8278 AHA-3940 Ultra
+product ADP 2944U 0x8478 AHA-2944 Ultra
/* AMD products */
-product AMD PCNET_PCI 0x2000 PCnet-PCI Ethernet
+product AMD PCNET_PCI 0x2000 79c970 PCnet-PCI LANCE Ethernet
+product AMD PCSCSI_PCI 0x2020 53c974 PCscsi-PCI SCSI
+
+/* ARK Logic products */
+product ARK 1000PV 0xa091 1000PV
+product ARK 2000PV 0xa099 2000PV
/* ATI products */
product ATI MACH32 0x4158 Mach32
-product ATI MACH64_CX 0x4358 Mach64-CX
-product ATI MACH64_GX 0x4758 Mach64-GX
+product ATI MACH64_CT 0x4354 Mach64 CT
+product ATI MACH64_CX 0x4358 Mach64 CX
+product ATI MACH64_ET 0x4554 Mach64 ET
+product ATI MACH64_VT 0x4654 Mach64 VT
+product ATI MACH64_GT 0x4754 Mach64 GT
+product ATI MACH64_GX 0x4758 Mach64 GX
+
+/* Atronics products */
+product ATRONICS IDE_2015PL 0x2015 IDE-2015PL
+
+/* Avance Logic products */
+product AVANCE ALG2301 0x2301 ALG2301
/* BusLogic products */
-product BUSLOGIC OLD946C 0x0140 946C
-product BUSLOGIC 946C 0x1040 946C
+product BUSLOGIC OLD946C 0x0140 946C 01
+product BUSLOGIC 946C 0x1040 946C 10
+
+/* Chips and Technologies products */
+product CHIPS 65545 0x00d8 65545
/* Cirrus Logic products */
-/* product CIRRUS UNK 0x00a4 unknown */
-product CIRRUS 5434 0x00a8 5434
+product CIRRUS GD_5430 0x00a0 GD 5430
+product CIRRUS GD_5434_4 0x00a4 GD 5434-4
+product CIRRUS GD_5434_8 0x00a8 GD 5434-8
+product CIRRUS GD_5436 0x00ac GD 5436
+product CIRRUS CL_6729 0x1100 CL 6729
+product CIRRUS CL_7542 0x1200 CL 7542
+
+/* CMD Technology products */
+product CMDTECH 640A 0x0640 640A
+
+/* Contaq Microsystems products */
+product CONTAQ 82C599 0x0600 82C599
/* DEC products */
product DEC 21050 0x0001 DECchip 21050 PCI-PCI Bridge
product DEC NVRAM 0x0007 Zephyr NV-RAM
product DEC KZPSA 0x0008 KZPSA
product DEC 21140 0x0009 DECchip 21140 (\"FasterNet\")
+product DEC PBXGB 0x000d TGA2
product DEC DEFPA 0x000f DEFPA
/* product DEC ??? 0x0010 ??? VME Interface */
product DEC 21041 0x0014 DECchip 21041 (\"Tulip Pass 3\")
+product DEC DGLPB 0x0016 DGLPB (\"OPPO\")
/* Diamond products */
product DIAMOND vIPER 0x9001 Viper/PCI
-/* CMD Technologies Products */
-product CMDTECH PCI0640 0x0640 UNSUPP PCI to IDE Controller
+/* Distributed Processing Technology products */
+product DPT SC_RAID 0xa400 SmartCache/Raid
/* FORE products */
product FORE PCA200 0x0210 ATM PCA-200
+product FORE PCA200E 0x0300 ATM PCA-200e
+
+/* Future Domain products */
+product FUTUREDOMAIN TMC_18C30 0x0000 TMC-18C30 (36C70)
-/* ENI products */
-product EFFICIENTNETS ENI155P 0x0002 ENI-155P ATM
+/* Efficient Networks products */
+product EFFICIENTNETS ENI155P 0x0002 155P-MF1 ATM
+
+/* Hewlett-Packard products */
+product HP J2585A 0x1030 J2585A
+
+/* IBM products */
+product IBM 82351 0x0022 82351 PCI-PCI Bridge
+
+/* Integrated Micro Solutions products */
+product IMS 8849 0x8849 8849
/* Intel products */
product INTEL PCEB 0x0482 82375EB PCI-EISA Bridge
product INTEL SIO 0x0484 82378IB PCI-ISA Bridge (System I/O)
product INTEL PCIB 0x0486 82426EX PCI-ISA Bridge
product INTEL PCMC 0x04a3 82434LX PCI, Cache, and Memory Controller
+product INTEL SAA7116 0x1223 SAA7116
+product INTEL 82437 0x122d 82437 Triton
+product INTEL 82471 0x122e 82471 Triton
+product INTEL 82438 0x1230 82438
+
+/* I. T. T. products */
+product ITT AGX016 0x0001 AGX016
+
+/* LeadTek Research */
+product LEADTEK S3_805 0x0000 S3 805
+
+/* Matrox products */
+product MATROX ATLAS 0x0518 MGA-2 Atlas PX2085
+product MATROX IMPRESSION 0x0d10 MGA Impression
/* Mylex products */
product MYLEX 960P 0x0001 RAID controller
+/* Mutech products */
+product MUTECH MV1000 0x0001 MV1000
+
+/* National Semiconductor products */
+product NS 87410 0xd001 87410
+
/* NCR/Symbios Logic products */
product OLDNCR 810 0x0001 53c810
product OLDNCR 820 0x0002 53c820
product NUMBER9 IMAG128 0x2309 Imagine-128
/* Opti products */
+product OPTI 82C557 0xc557 82C557
+product OPTI 82C558 0xc558 82C558
+product OPTI 82C621 0xc621 82C621
product OPTI 82C822 0xc822 82C822
-product OPTI 82C621 0xc821 82C621
+
+/* Promise products */
+product PROMISE DC5030 0x5300 DC5030
/* QLogic products */
product QLOGIC ISP1020 0x1020 ISP1020
+product QLOGIC ISP1022 0x1022 ISP1022
+
+/* Quantum Designs products */
+product QUANTUMDESIGNS 8500 0x0001 8500
+product QUANTUMDESIGNS 8580 0x0002 8580
+
+/* Realtek (Creative Labs?) products */
+product REALTEK RT8029 0x8029 Ethernet
/* S3 products */
-/* Names??? */
-product S3 TRIO64 0x8811 Trio32/64/64V+
+product S3 TRIO64 0x8811 Trio32/64
product S3 868 0x8880 868
product S3 928 0x88b0 928
-product S3 864_0 0x88c0 Vision 864-0
-product S3 864_1 0x88c1 Vision 864-1
-product S3 964 0x88d0 964
+product S3 864_0 0x88c0 864-0
+product S3 864_1 0x88c1 864-1
+product S3 964_0 0x88d0 964-0
+product S3 964_1 0x88d1 964-1
product S3 968 0x88f0 968
+/* Silicon Integrated System products */
+product SIS 86C201 0x0001 86C201
+product SIS 86C202 0x0002 86C202
+product SIS 86C205 0x0005 86C205
+product SIS 85C503 0x0008 85C503
+product SIS 85C501 0x0406 85C501
+product SIS 85C496 0x0496 85C496
+product SIS 85C601 0x0601 85C601
+
/* SMC products */
-product SMC 37C665 0x1000 37C665
+product SMC 37C665 0x1000 FDC 37C665
+
+/* Symphony Labs products */
+product SYMPHONY 82C101 0x0001 82C101
+
+/* Tekram Technology products */
+product TEKRAM DC290 0xdc29 DC290
+
+/* Trident products */
+product TRIDENT TGUI_9320 0x9320 TGUI 9320
+product TRIDENT TGUI_9420 0x9420 TGUI 9420
+product TRIDENT TGUI_9440 0x9440 TGUI 9440
+product TRIDENT TGUI_9660 0x9660 TGUI 9660
+product TRIDENT TGUI_9680 0x9680 TGUI 9680
+product TRIDENT TGUI_9682 0x9682 TGUI 9682
/* Tseng Labs products */
-product TSENG W32P_A 0x3202 ET4000w32p rev A
-product TSENG W32P_D 0x3207 ET4000w32p rev D
+product TSENG ET4000_W32P_A 0x3202 ET4000w32p rev A
+product TSENG ET4000_W32P_B 0x3205 ET4000w32p rev B
+product TSENG ET4000_W32P_C 0x3206 ET4000w32p rev C
+product TSENG ET4000_W32P_D 0x3207 ET4000w32p rev D
+product TSENG ET6000 0x3208 ET6000
/* UMC products */
product UMC UM8673F 0x0101 UM8673F
product UMC UM8881F 0x8881 UM8881F PCI-Host bridge
product UMC UM8886F 0x8886 UM8886F PCI-ISA bridge
+product UMC UM8886A 0x888a UM8886A
+product UMC UM8891A 0x8891 UM8891A
+
+/* VIA Technologies products */
+product VIATECH 82C505 0x0505 82C505
+product VIATECH ALT_82C505 0x0561 82C505
+product VIATECH 82C576 0x0505 82C576 3V
+
+/* Vortex Computer Systems products */
+product VORTEX GDT_6000B 0x0001 GDT 6000b
+
+/* VLSI products */
+product VLSI 82C592_FC1 0x0005 82C592-FC1
+product VLSI 82C593_FC1 0x0006 82C593-FC1
+
+/* Weitek products */
+product WEITEK P9000 0x9001 P9000
+product WEITEK P9100 0x9100 P9100
+
+/* Winbond Electronics products */
+product WINBOND W83769F 0x0001 W83769F
+
+/* Zeinet products */
+product ZEINET 1221 0x0001 1221
+
+/* Cyclades products */
+product CYCLADES CYCLOMY_1 0x0100 Cyclom-Y below 1M
+product CYCLADES CYCLOMY_2 0x0101 Cyclom-Y above 1M
/* Cyclades products */
product CYCLADES CYCLOMY_1 0x0100 Cyclom-Y below 1M
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * OpenBSD: pcidevs,v 1.12 1996/10/14 09:00:53 deraadt Exp
+ * OpenBSD: pcidevs,v 1.13 1996/10/14 10:22:22 deraadt Exp
*/
-/* $NetBSD: pcidevs,v 1.8 1996/05/07 01:59:45 thorpej Exp $ */
+/* $NetBSD: pcidevs,v 1.20 1996/10/19 13:01:49 jonathan Exp $ */
/*
#define PCI_VENDOR_ACC 0x10aa /* ACC Microelectronics */
#define PCI_VENDOR_DIGICOM 0x10ab /* Digicom */
#define PCI_VENDOR_HONEYWELL 0x10ac /* Honeywell IASD */
-#define PCI_VENDOR_SYMPHONY 0x10ad /* Symphony Labs (or Winbond?) */
#define PCI_VENDOR_CORNERSTONE 0x10ae /* Cornerstone Technology */
#define PCI_VENDOR_MICROCOMPSON 0x10af /* Micro Computer Sysytems (M) SON */
#define PCI_VENDOR_CARDEXPER 0x10b0 /* CardExpert Technology */
#define PCI_VENDOR_NVIDIA 0x10de /* Nvidia Corporation */
#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
#define PCI_VENDOR_IMS 0x10e0 /* Integrated Micro Solutions */
-#define PCI_VENDOR_TEKRAM 0x10e1 /* Tekram Technology */
#define PCI_VENDOR_APTIX 0x10e2 /* Aptix Corporation */
#define PCI_VENDOR_NEWBRIDGE 0x10e3 /* Newbridge Microsystems */
#define PCI_VENDOR_TANDEM 0x10e4 /* Tandem Computers */
#define PCI_VENDOR_TRIONES 0x1103 /* Triones Technologies */
#define PCI_VENDOR_RASTEROPS 0x1104 /* RasterOps */
#define PCI_VENDOR_SIGMA 0x1105 /* Sigma Designs */
-#define PCI_VENDOR_VIATECH 0x1106 /* Via Technologies */
+#define PCI_VENDOR_VIATECH 0x1106 /* VIA Technologies */
#define PCI_VENDOR_STRATIS 0x1107 /* Stratus Computer */
#define PCI_VENDOR_PROTEON 0x1108 /* Proteon */
#define PCI_VENDOR_COGENT 0x1109 /* Cogent Data Technologies */
#define PCI_VENDOR_ZEITNET 0x1193 /* ZeitNet */
#define PCI_VENDOR_SPECIALIX 0x11cb /* Specialix */
#define PCI_VENDOR_CYCLADES 0x120e /* Cyclades */
-#define PCI_VENDOR_SYMPHONY2 0x1c1c /* Symphony (duplicate? see 0x10ad) */
-#define PCI_VENDOR_TEKRAM2 0x1de1 /* Tekram (mistyped? see 0x10e1) */
+#define PCI_VENDOR_ZEINET 0x1193 /* Zeinet */
+#define PCI_VENDOR_SYMPHONY 0x1c1c /* Symphony Labs */
+#define PCI_VENDOR_TEKRAM 0x1de1 /* Tekram Technology */
#define PCI_VENDOR_AVANCE2 0x4005 /* Avance Logic (mistyped? see 0x1005) */
#define PCI_VENDOR_S3 0x5333 /* S3 */
#define PCI_VENDOR_INTEL 0x8086 /* Intel */
/* 3COM Products */
#define PCI_PRODUCT_3COM_3C590 0x5900 /* 3c590 10Mbps */
-#define PCI_PRODUCT_3COM_3C595 0x5950 /* 3c595 100Base-TX */
-#define PCI_PRODUCT_3COM_3C595T 0x5951 /* 3c595 100Base-T4 */
-#define PCI_PRODUCT_3COM_3C595TM 0x5952 /* 3c595 100Base-T/MII */
-#define PCI_PRODUCT_3COM_3C900 0x9000 /* 3c900 10Base-T */
-#define PCI_PRODUCT_3COM_3C900T 0x9001 /* 3c900 10Mbps-Combo */
-#define PCI_PRODUCT_3COM_3C905 0x9050 /* 3c905 100Base-TX */
-#define PCI_PRODUCT_3COM_3C905T 0x9051 /* 3c905 100Base-T4 */
+#define PCI_PRODUCT_3COM_3C595TX 0x5950 /* 3c595 100Base-TX */
+#define PCI_PRODUCT_3COM_3C595T4 0x5951 /* 3c595 100Base-T4 */
+#define PCI_PRODUCT_3COM_3C595MII 0x5952 /* 3c595 10Mbps-MII */
+#define PCI_PRODUCT_3COM_3C900TPO 0x9000 /* 3c900 10Base-T */
+#define PCI_PRODUCT_3COM_3C900COMBO 0x9001 /* 3c900 10Mbps-Combo */
+#define PCI_PRODUCT_3COM_3C905TX 0x9050 /* 3c905 100Base-TX */
+#define PCI_PRODUCT_3COM_3C905T4 0x9051 /* 3c905 100Base-T4 */
-/* Acer products */
-#define PCI_PRODUCT_ACER_M1435 0x1435 /* M1435 */
+/* Acer Labs products */
+#define PCI_PRODUCT_ALI_M1445 0x1445 /* M1445 */
+#define PCI_PRODUCT_ALI_M1449 0x1449 /* M1449 */
+#define PCI_PRODUCT_ALI_M1451 0x1451 /* M1451 */
+#define PCI_PRODUCT_ALI_M4803 0x5215 /* M4803 */
/* Adaptec products */
-#define PCI_PRODUCT_ADP_3940U 0x8278 /* AHA-3940 Ultra */
-#define PCI_PRODUCT_ADP_2944U 0x8478 /* AHA-2944 Ultra */
-#define PCI_PRODUCT_ADP_2940U 0x8178 /* AHA-2940 Ultra */
+#define PCI_PRODUCT_ADP_AIC7850 0x5078 /* AIC-7850 */
+#define PCI_PRODUCT_ADP_AIC7855 0x5578 /* AIC-7855 */
+#define PCI_PRODUCT_ADP_AIC7860 0x6078 /* AIC-7860 */
+#define PCI_PRODUCT_ADP_2940AU 0x6178 /* AHA-2940A Ultra */
+#define PCI_PRODUCT_ADP_AIC7870 0x7078 /* AIC-7870 */
+#define PCI_PRODUCT_ADP_2940 0x7178 /* AHA-2940 */
#define PCI_PRODUCT_ADP_3940 0x7278 /* AHA-3940 */
#define PCI_PRODUCT_ADP_2944 0x7478 /* AHA-2944 */
-#define PCI_PRODUCT_ADP_2940 0x7178 /* AHA-2940 */
#define PCI_PRODUCT_ADP_AIC7880 0x8078 /* AIC-7880 Ultra */
-#define PCI_PRODUCT_ADP_AIC7870 0x7078 /* AIC-7870 */
-#define PCI_PRODUCT_ADP_AIC7850 0x5078 /* AIC-7850 */
+#define PCI_PRODUCT_ADP_2940U 0x8178 /* AHA-2940 Ultra */
+#define PCI_PRODUCT_ADP_3940U 0x8278 /* AHA-3940 Ultra */
+#define PCI_PRODUCT_ADP_2944U 0x8478 /* AHA-2944 Ultra */
/* AMD products */
-#define PCI_PRODUCT_AMD_PCNET_PCI 0x2000 /* PCnet-PCI Ethernet */
+#define PCI_PRODUCT_AMD_PCNET_PCI 0x2000 /* 79c970 PCnet-PCI LANCE Ethernet */
+#define PCI_PRODUCT_AMD_PCSCSI_PCI 0x2020 /* 53c974 PCscsi-PCI SCSI */
+
+/* ARK Logic products */
+#define PCI_PRODUCT_ARK_1000PV 0xa091 /* 1000PV */
+#define PCI_PRODUCT_ARK_2000PV 0xa099 /* 2000PV */
/* ATI products */
#define PCI_PRODUCT_ATI_MACH32 0x4158 /* Mach32 */
-#define PCI_PRODUCT_ATI_MACH64_CX 0x4358 /* Mach64-CX */
-#define PCI_PRODUCT_ATI_MACH64_GX 0x4758 /* Mach64-GX */
+#define PCI_PRODUCT_ATI_MACH64_CT 0x4354 /* Mach64 CT */
+#define PCI_PRODUCT_ATI_MACH64_CX 0x4358 /* Mach64 CX */
+#define PCI_PRODUCT_ATI_MACH64_ET 0x4554 /* Mach64 ET */
+#define PCI_PRODUCT_ATI_MACH64_VT 0x4654 /* Mach64 VT */
+#define PCI_PRODUCT_ATI_MACH64_GT 0x4754 /* Mach64 GT */
+#define PCI_PRODUCT_ATI_MACH64_GX 0x4758 /* Mach64 GX */
+
+/* Atronics products */
+#define PCI_PRODUCT_ATRONICS_IDE_2015PL 0x2015 /* IDE-2015PL */
+
+/* Avance Logic products */
+#define PCI_PRODUCT_AVANCE_ALG2301 0x2301 /* ALG2301 */
/* BusLogic products */
-#define PCI_PRODUCT_BUSLOGIC_OLD946C 0x0140 /* 946C */
-#define PCI_PRODUCT_BUSLOGIC_946C 0x1040 /* 946C */
+#define PCI_PRODUCT_BUSLOGIC_OLD946C 0x0140 /* 946C 01 */
+#define PCI_PRODUCT_BUSLOGIC_946C 0x1040 /* 946C 10 */
+
+/* Chips and Technologies products */
+#define PCI_PRODUCT_CHIPS_65545 0x00d8 /* 65545 */
/* Cirrus Logic products */
-/* product CIRRUS UNK 0x00a4 unknown */
-#define PCI_PRODUCT_CIRRUS_5434 0x00a8 /* 5434 */
+#define PCI_PRODUCT_CIRRUS_GD_5430 0x00a0 /* GD 5430 */
+#define PCI_PRODUCT_CIRRUS_GD_5434_4 0x00a4 /* GD 5434-4 */
+#define PCI_PRODUCT_CIRRUS_GD_5434_8 0x00a8 /* GD 5434-8 */
+#define PCI_PRODUCT_CIRRUS_GD_5436 0x00ac /* GD 5436 */
+#define PCI_PRODUCT_CIRRUS_CL_6729 0x1100 /* CL 6729 */
+#define PCI_PRODUCT_CIRRUS_CL_7542 0x1200 /* CL 7542 */
+
+/* CMD Technology products */
+#define PCI_PRODUCT_CMDTECH_640A 0x0640 /* 640A */
+
+/* Contaq Microsystems products */
+#define PCI_PRODUCT_CONTAQ_82C599 0x0600 /* 82C599 */
/* DEC products */
#define PCI_PRODUCT_DEC_21050 0x0001 /* DECchip 21050 PCI-PCI Bridge */
#define PCI_PRODUCT_DEC_NVRAM 0x0007 /* Zephyr NV-RAM */
#define PCI_PRODUCT_DEC_KZPSA 0x0008 /* KZPSA */
#define PCI_PRODUCT_DEC_21140 0x0009 /* DECchip 21140 (\"FasterNet\") */
+#define PCI_PRODUCT_DEC_PBXGB 0x000d /* TGA2 */
#define PCI_PRODUCT_DEC_DEFPA 0x000f /* DEFPA */
/* product DEC ??? 0x0010 ??? VME Interface */
#define PCI_PRODUCT_DEC_21041 0x0014 /* DECchip 21041 (\"Tulip Pass 3\") */
+#define PCI_PRODUCT_DEC_DGLPB 0x0016 /* DGLPB (\"OPPO\") */
/* Diamond products */
#define PCI_PRODUCT_DIAMOND_vIPER 0x9001 /* Viper/PCI */
-/* CMD Technologies Products */
-#define PCI_PRODUCT_CMDTECH_PCI0640 0x0640 /* UNSUPP PCI to IDE Controller */
+/* Distributed Processing Technology products */
+#define PCI_PRODUCT_DPT_SC_RAID 0xa400 /* SmartCache/Raid */
/* FORE products */
#define PCI_PRODUCT_FORE_PCA200 0x0210 /* ATM PCA-200 */
+#define PCI_PRODUCT_FORE_PCA200E 0x0300 /* ATM PCA-200e */
+
+/* Future Domain products */
+#define PCI_PRODUCT_FUTUREDOMAIN_TMC_18C30 0x0000 /* TMC-18C30 (36C70) */
+
+/* Efficient Networks products */
+#define PCI_PRODUCT_EFFICIENTNETS_ENI155P 0x0002 /* 155P-MF1 ATM */
+
+/* Hewlett-Packard products */
+#define PCI_PRODUCT_HP_J2585A 0x1030 /* J2585A */
+
+/* IBM products */
+#define PCI_PRODUCT_IBM_82351 0x0022 /* 82351 PCI-PCI Bridge */
-/* ENI products */
-#define PCI_PRODUCT_EFFICIENTNETS_ENI155P 0x0002 /* ENI-155P ATM */
+/* Integrated Micro Solutions products */
+#define PCI_PRODUCT_IMS_8849 0x8849 /* 8849 */
/* Intel products */
#define PCI_PRODUCT_INTEL_PCEB 0x0482 /* 82375EB PCI-EISA Bridge */
#define PCI_PRODUCT_INTEL_SIO 0x0484 /* 82378IB PCI-ISA Bridge (System I/O) */
#define PCI_PRODUCT_INTEL_PCIB 0x0486 /* 82426EX PCI-ISA Bridge */
#define PCI_PRODUCT_INTEL_PCMC 0x04a3 /* 82434LX PCI, Cache, and Memory Controller */
+#define PCI_PRODUCT_INTEL_SAA7116 0x1223 /* SAA7116 */
+#define PCI_PRODUCT_INTEL_82437 0x122d /* 82437 Triton */
+#define PCI_PRODUCT_INTEL_82471 0x122e /* 82471 Triton */
+#define PCI_PRODUCT_INTEL_82438 0x1230 /* 82438 */
+
+/* I. T. T. products */
+#define PCI_PRODUCT_ITT_AGX016 0x0001 /* AGX016 */
+
+/* LeadTek Research */
+#define PCI_PRODUCT_LEADTEK_S3_805 0x0000 /* S3 805 */
+
+/* Matrox products */
+#define PCI_PRODUCT_MATROX_ATLAS 0x0518 /* MGA-2 Atlas PX2085 */
+#define PCI_PRODUCT_MATROX_IMPRESSION 0x0d10 /* MGA Impression */
/* Mylex products */
#define PCI_PRODUCT_MYLEX_960P 0x0001 /* RAID controller */
+/* Mutech products */
+#define PCI_PRODUCT_MUTECH_MV1000 0x0001 /* MV1000 */
+
+/* National Semiconductor products */
+#define PCI_PRODUCT_NS_87410 0xd001 /* 87410 */
+
/* NCR/Symbios Logic products */
#define PCI_PRODUCT_OLDNCR_810 0x0001 /* 53c810 */
#define PCI_PRODUCT_OLDNCR_820 0x0002 /* 53c820 */
#define PCI_PRODUCT_NUMBER9_IMAG128 0x2309 /* Imagine-128 */
/* Opti products */
+#define PCI_PRODUCT_OPTI_82C557 0xc557 /* 82C557 */
+#define PCI_PRODUCT_OPTI_82C558 0xc558 /* 82C558 */
+#define PCI_PRODUCT_OPTI_82C621 0xc621 /* 82C621 */
#define PCI_PRODUCT_OPTI_82C822 0xc822 /* 82C822 */
-#define PCI_PRODUCT_OPTI_82C621 0xc821 /* 82C621 */
+
+/* Promise products */
+#define PCI_PRODUCT_PROMISE_DC5030 0x5300 /* DC5030 */
/* QLogic products */
#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 /* ISP1020 */
+#define PCI_PRODUCT_QLOGIC_ISP1022 0x1022 /* ISP1022 */
+
+/* Quantum Designs products */
+#define PCI_PRODUCT_QUANTUMDESIGNS_8500 0x0001 /* 8500 */
+#define PCI_PRODUCT_QUANTUMDESIGNS_8580 0x0002 /* 8580 */
+
+/* Realtek (Creative Labs?) products */
+#define PCI_PRODUCT_REALTEK_RT8029 0x8029 /* Ethernet */
/* S3 products */
-/* Names??? */
-#define PCI_PRODUCT_S3_TRIO64 0x8811 /* Trio32/64/64V+ */
+#define PCI_PRODUCT_S3_TRIO64 0x8811 /* Trio32/64 */
#define PCI_PRODUCT_S3_868 0x8880 /* 868 */
#define PCI_PRODUCT_S3_928 0x88b0 /* 928 */
-#define PCI_PRODUCT_S3_864_0 0x88c0 /* Vision 864-0 */
-#define PCI_PRODUCT_S3_864_1 0x88c1 /* Vision 864-1 */
-#define PCI_PRODUCT_S3_964 0x88d0 /* 964 */
+#define PCI_PRODUCT_S3_864_0 0x88c0 /* 864-0 */
+#define PCI_PRODUCT_S3_864_1 0x88c1 /* 864-1 */
+#define PCI_PRODUCT_S3_964_0 0x88d0 /* 964-0 */
+#define PCI_PRODUCT_S3_964_1 0x88d1 /* 964-1 */
#define PCI_PRODUCT_S3_968 0x88f0 /* 968 */
+/* Silicon Integrated System products */
+#define PCI_PRODUCT_SIS_86C201 0x0001 /* 86C201 */
+#define PCI_PRODUCT_SIS_86C202 0x0002 /* 86C202 */
+#define PCI_PRODUCT_SIS_86C205 0x0005 /* 86C205 */
+#define PCI_PRODUCT_SIS_85C503 0x0008 /* 85C503 */
+#define PCI_PRODUCT_SIS_85C501 0x0406 /* 85C501 */
+#define PCI_PRODUCT_SIS_85C496 0x0496 /* 85C496 */
+#define PCI_PRODUCT_SIS_85C601 0x0601 /* 85C601 */
+
/* SMC products */
-#define PCI_PRODUCT_SMC_37C665 0x1000 /* 37C665 */
+#define PCI_PRODUCT_SMC_37C665 0x1000 /* FDC 37C665 */
+
+/* Symphony Labs products */
+#define PCI_PRODUCT_SYMPHONY_82C101 0x0001 /* 82C101 */
+
+/* Tekram Technology products */
+#define PCI_PRODUCT_TEKRAM_DC290 0xdc29 /* DC290 */
+
+/* Trident products */
+#define PCI_PRODUCT_TRIDENT_TGUI_9320 0x9320 /* TGUI 9320 */
+#define PCI_PRODUCT_TRIDENT_TGUI_9420 0x9420 /* TGUI 9420 */
+#define PCI_PRODUCT_TRIDENT_TGUI_9440 0x9440 /* TGUI 9440 */
+#define PCI_PRODUCT_TRIDENT_TGUI_9660 0x9660 /* TGUI 9660 */
+#define PCI_PRODUCT_TRIDENT_TGUI_9680 0x9680 /* TGUI 9680 */
+#define PCI_PRODUCT_TRIDENT_TGUI_9682 0x9682 /* TGUI 9682 */
/* Tseng Labs products */
-#define PCI_PRODUCT_TSENG_W32P_A 0x3202 /* ET4000w32p rev A */
-#define PCI_PRODUCT_TSENG_W32P_D 0x3207 /* ET4000w32p rev D */
+#define PCI_PRODUCT_TSENG_ET4000_W32P_A 0x3202 /* ET4000w32p rev A */
+#define PCI_PRODUCT_TSENG_ET4000_W32P_B 0x3205 /* ET4000w32p rev B */
+#define PCI_PRODUCT_TSENG_ET4000_W32P_C 0x3206 /* ET4000w32p rev C */
+#define PCI_PRODUCT_TSENG_ET4000_W32P_D 0x3207 /* ET4000w32p rev D */
+#define PCI_PRODUCT_TSENG_ET6000 0x3208 /* ET6000 */
/* UMC products */
#define PCI_PRODUCT_UMC_UM8673F 0x0101 /* UM8673F */
#define PCI_PRODUCT_UMC_UM8881F 0x8881 /* UM8881F PCI-Host bridge */
#define PCI_PRODUCT_UMC_UM8886F 0x8886 /* UM8886F PCI-ISA bridge */
+#define PCI_PRODUCT_UMC_UM8886A 0x888a /* UM8886A */
+#define PCI_PRODUCT_UMC_UM8891A 0x8891 /* UM8891A */
+
+/* VIA Technologies products */
+#define PCI_PRODUCT_VIATECH_82C505 0x0505 /* 82C505 */
+#define PCI_PRODUCT_VIATECH_ALT_82C505 0x0561 /* 82C505 */
+#define PCI_PRODUCT_VIATECH_82C576 0x0505 /* 82C576 3V */
+
+/* Vortex Computer Systems products */
+#define PCI_PRODUCT_VORTEX_GDT_6000B 0x0001 /* GDT 6000b */
+
+/* VLSI products */
+#define PCI_PRODUCT_VLSI_82C592_FC1 0x0005 /* 82C592-FC1 */
+#define PCI_PRODUCT_VLSI_82C593_FC1 0x0006 /* 82C593-FC1 */
+
+/* Weitek products */
+#define PCI_PRODUCT_WEITEK_P9000 0x9001 /* P9000 */
+#define PCI_PRODUCT_WEITEK_P9100 0x9100 /* P9100 */
+
+/* Winbond Electronics products */
+#define PCI_PRODUCT_WINBOND_W83769F 0x0001 /* W83769F */
+
+/* Zeinet products */
+#define PCI_PRODUCT_ZEINET_1221 0x0001 /* 1221 */
+
+/* Cyclades products */
+#define PCI_PRODUCT_CYCLADES_CYCLOMY_1 0x0100 /* Cyclom-Y below 1M */
+#define PCI_PRODUCT_CYCLADES_CYCLOMY_2 0x0101 /* Cyclom-Y above 1M */
/* Cyclades products */
#define PCI_PRODUCT_CYCLADES_CYCLOMY_1 0x0100 /* Cyclom-Y below 1M */
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * OpenBSD: pcidevs,v 1.12 1996/10/14 09:00:53 deraadt Exp
+ * OpenBSD: pcidevs,v 1.13 1996/10/14 10:22:22 deraadt Exp
*/
-/* $NetBSD: pcidevs,v 1.8 1996/05/07 01:59:45 thorpej Exp $ */
+/* $NetBSD: pcidevs,v 1.20 1996/10/19 13:01:49 jonathan Exp $ */
struct pci_knowndev pci_knowndevs[] = {
"3c590 10Mbps",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595TX,
0,
"3Com",
"3c595 100Base-TX",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595T,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595T4,
0,
"3Com",
"3c595 100Base-T4",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595TM,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595MII,
0,
"3Com",
- "3c595 100Base-T/MII",
+ "3c595 10Mbps-MII",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900TPO,
0,
"3Com",
"3c900 10Base-T",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900T,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900COMBO,
0,
"3Com",
"3c900 10Mbps-Combo",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905TX,
0,
"3Com",
"3c905 100Base-TX",
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905T,
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905T4,
0,
"3Com",
"3c905 100Base-T4",
},
{
- PCI_VENDOR_ACER, PCI_PRODUCT_ACER_M1435,
+ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1445,
0,
- "Acer",
- "M1435",
+ "Acer Labs",
+ "M1445",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940U,
+ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1449,
+ 0,
+ "Acer Labs",
+ "M1449",
+ },
+ {
+ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1451,
+ 0,
+ "Acer Labs",
+ "M1451",
+ },
+ {
+ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M4803,
+ 0,
+ "Acer Labs",
+ "M4803",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7850,
0,
"Adaptec",
- "AHA-3940 Ultra",
+ "AIC-7850",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944U,
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7855,
0,
"Adaptec",
- "AHA-2944 Ultra",
+ "AIC-7855",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940U,
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7860,
0,
"Adaptec",
- "AHA-2940 Ultra",
+ "AIC-7860",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940,
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940AU,
0,
"Adaptec",
- "AHA-3940",
+ "AHA-2940A Ultra",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944,
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7870,
0,
"Adaptec",
- "AHA-2944",
+ "AIC-7870",
},
{
PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940,
"Adaptec",
"AHA-2940",
},
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940,
+ 0,
+ "Adaptec",
+ "AHA-3940",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944,
+ 0,
+ "Adaptec",
+ "AHA-2944",
+ },
{
PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7880,
0,
"AIC-7880 Ultra",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7870,
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940U,
0,
"Adaptec",
- "AIC-7870",
+ "AHA-2940 Ultra",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7850,
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940U,
0,
"Adaptec",
- "AIC-7850",
+ "AHA-3940 Ultra",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944U,
+ 0,
+ "Adaptec",
+ "AHA-2944 Ultra",
},
{
PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI,
0,
"AMD",
- "PCnet-PCI Ethernet",
+ "79c970 PCnet-PCI LANCE Ethernet",
+ },
+ {
+ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCSCSI_PCI,
+ 0,
+ "AMD",
+ "53c974 PCscsi-PCI SCSI",
+ },
+ {
+ PCI_VENDOR_ARK, PCI_PRODUCT_ARK_1000PV,
+ 0,
+ "Ark Logic (or Arc? or Hercules?)",
+ "1000PV",
+ },
+ {
+ PCI_VENDOR_ARK, PCI_PRODUCT_ARK_2000PV,
+ 0,
+ "Ark Logic (or Arc? or Hercules?)",
+ "2000PV",
},
{
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH32,
"ATI Technologies",
"Mach32",
},
+ {
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_CT,
+ 0,
+ "ATI Technologies",
+ "Mach64 CT",
+ },
{
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_CX,
0,
"ATI Technologies",
- "Mach64-CX",
+ "Mach64 CX",
+ },
+ {
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_ET,
+ 0,
+ "ATI Technologies",
+ "Mach64 ET",
+ },
+ {
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_VT,
+ 0,
+ "ATI Technologies",
+ "Mach64 VT",
+ },
+ {
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_GT,
+ 0,
+ "ATI Technologies",
+ "Mach64 GT",
},
{
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_GX,
0,
"ATI Technologies",
- "Mach64-GX",
+ "Mach64 GX",
+ },
+ {
+ PCI_VENDOR_ATRONICS, PCI_PRODUCT_ATRONICS_IDE_2015PL,
+ 0,
+ "Atronics",
+ "IDE-2015PL",
+ },
+ {
+ PCI_VENDOR_AVANCE, PCI_PRODUCT_AVANCE_ALG2301,
+ 0,
+ "Avance Logic",
+ "ALG2301",
},
{
PCI_VENDOR_BUSLOGIC, PCI_PRODUCT_BUSLOGIC_OLD946C,
0,
"BusLogic",
- "946C",
+ "946C 01",
},
{
PCI_VENDOR_BUSLOGIC, PCI_PRODUCT_BUSLOGIC_946C,
0,
"BusLogic",
- "946C",
+ "946C 10",
+ },
+ {
+ PCI_VENDOR_CHIPS, PCI_PRODUCT_CHIPS_65545,
+ 0,
+ "Chips and Technologies",
+ "65545",
},
{
- PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_5434,
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_GD_5430,
0,
"Cirrus Logic",
- "5434",
+ "GD 5430",
+ },
+ {
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_GD_5434_4,
+ 0,
+ "Cirrus Logic",
+ "GD 5434-4",
+ },
+ {
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_GD_5434_8,
+ 0,
+ "Cirrus Logic",
+ "GD 5434-8",
+ },
+ {
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_GD_5436,
+ 0,
+ "Cirrus Logic",
+ "GD 5436",
+ },
+ {
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_6729,
+ 0,
+ "Cirrus Logic",
+ "CL 6729",
+ },
+ {
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_7542,
+ 0,
+ "Cirrus Logic",
+ "CL 7542",
+ },
+ {
+ PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_640A,
+ 0,
+ "CMD Technology",
+ "640A",
+ },
+ {
+ PCI_VENDOR_CONTAQ, PCI_PRODUCT_CONTAQ_82C599,
+ 0,
+ "Contaq Microsystems",
+ "82C599",
},
{
PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21050,
"Digital Equipment",
"DECchip 21140 (\"FasterNet\")",
},
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PBXGB,
+ 0,
+ "Digital Equipment",
+ "TGA2",
+ },
{
PCI_VENDOR_DEC, PCI_PRODUCT_DEC_DEFPA,
0,
"Digital Equipment",
"DECchip 21041 (\"Tulip Pass 3\")",
},
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_DGLPB,
+ 0,
+ "Digital Equipment",
+ "DGLPB (\"OPPO\")",
+ },
{
PCI_VENDOR_DIAMOND, PCI_PRODUCT_DIAMOND_vIPER,
0,
"Viper/PCI",
},
{
- PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_PCI0640,
+ PCI_VENDOR_DPT, PCI_PRODUCT_DPT_SC_RAID,
0,
- "CMD Technology",
- "UNSUPP PCI to IDE Controller",
+ "Distributed Processing Technology",
+ "SmartCache/Raid",
},
{
PCI_VENDOR_FORE, PCI_PRODUCT_FORE_PCA200,
"FORE Systems",
"ATM PCA-200",
},
+ {
+ PCI_VENDOR_FORE, PCI_PRODUCT_FORE_PCA200E,
+ 0,
+ "FORE Systems",
+ "ATM PCA-200e",
+ },
+ {
+ PCI_VENDOR_FUTUREDOMAIN, PCI_PRODUCT_FUTUREDOMAIN_TMC_18C30,
+ 0,
+ "Future Domain",
+ "TMC-18C30 (36C70)",
+ },
{
PCI_VENDOR_EFFICIENTNETS, PCI_PRODUCT_EFFICIENTNETS_ENI155P,
0,
"Efficent Networks",
- "ENI-155P ATM",
+ "155P-MF1 ATM",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_J2585A,
+ 0,
+ "Hewlett-Packard",
+ "J2585A",
+ },
+ {
+ PCI_VENDOR_IBM, PCI_PRODUCT_IBM_82351,
+ 0,
+ "IBM",
+ "82351 PCI-PCI Bridge",
+ },
+ {
+ PCI_VENDOR_IMS, PCI_PRODUCT_IMS_8849,
+ 0,
+ "Integrated Micro Solutions",
+ "8849",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCEB,
"Intel",
"82434LX PCI, Cache, and Memory Controller",
},
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_SAA7116,
+ 0,
+ "Intel",
+ "SAA7116",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437,
+ 0,
+ "Intel",
+ "82437 Triton",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82471,
+ 0,
+ "Intel",
+ "82471 Triton",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82438,
+ 0,
+ "Intel",
+ "82438",
+ },
+ {
+ PCI_VENDOR_ITT, PCI_PRODUCT_ITT_AGX016,
+ 0,
+ "I. T. T. (or X technology?)",
+ "AGX016",
+ },
+ {
+ PCI_VENDOR_LEADTEK, PCI_PRODUCT_LEADTEK_S3_805,
+ 0,
+ "LeadTek Research",
+ "S3 805",
+ },
+ {
+ PCI_VENDOR_MATROX, PCI_PRODUCT_MATROX_ATLAS,
+ 0,
+ "Matrox",
+ "MGA-2 Atlas PX2085",
+ },
+ {
+ PCI_VENDOR_MATROX, PCI_PRODUCT_MATROX_IMPRESSION,
+ 0,
+ "Matrox",
+ "MGA Impression",
+ },
{
PCI_VENDOR_MYLEX, PCI_PRODUCT_MYLEX_960P,
0,
"Mylex",
"RAID controller",
},
+ {
+ PCI_VENDOR_MUTECH, PCI_PRODUCT_MUTECH_MV1000,
+ 0,
+ "Mutech",
+ "MV1000",
+ },
+ {
+ PCI_VENDOR_NS, PCI_PRODUCT_NS_87410,
+ 0,
+ "National Semiconductor",
+ "87410",
+ },
{
PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_810,
0,
"Imagine-128",
},
{
- PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C822,
+ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C557,
0,
"Opti",
- "82C822",
+ "82C557",
+ },
+ {
+ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558,
+ 0,
+ "Opti",
+ "82C558",
},
{
PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C621,
"Opti",
"82C621",
},
+ {
+ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C822,
+ 0,
+ "Opti",
+ "82C822",
+ },
+ {
+ PCI_VENDOR_PROMISE, PCI_PRODUCT_PROMISE_DC5030,
+ 0,
+ "Promise Technology",
+ "DC5030",
+ },
{
PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1020,
0,
"Q Logic",
"ISP1020",
},
+ {
+ PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1022,
+ 0,
+ "Q Logic",
+ "ISP1022",
+ },
+ {
+ PCI_VENDOR_QUANTUMDESIGNS, PCI_PRODUCT_QUANTUMDESIGNS_8500,
+ 0,
+ "Quantum Designs (or Vision?)",
+ "8500",
+ },
+ {
+ PCI_VENDOR_QUANTUMDESIGNS, PCI_PRODUCT_QUANTUMDESIGNS_8580,
+ 0,
+ "Quantum Designs (or Vision?)",
+ "8580",
+ },
+ {
+ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8029,
+ 0,
+ "Realtek Semiconductor",
+ "Ethernet",
+ },
{
PCI_VENDOR_S3, PCI_PRODUCT_S3_TRIO64,
0,
"S3",
- "Trio32/64/64V+",
+ "Trio32/64",
},
{
PCI_VENDOR_S3, PCI_PRODUCT_S3_868,
PCI_VENDOR_S3, PCI_PRODUCT_S3_864_0,
0,
"S3",
- "Vision 864-0",
+ "864-0",
},
{
PCI_VENDOR_S3, PCI_PRODUCT_S3_864_1,
0,
"S3",
- "Vision 864-1",
+ "864-1",
+ },
+ {
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_964_0,
+ 0,
+ "S3",
+ "964-0",
},
{
- PCI_VENDOR_S3, PCI_PRODUCT_S3_964,
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_964_1,
0,
"S3",
- "964",
+ "964-1",
},
{
PCI_VENDOR_S3, PCI_PRODUCT_S3_968,
"S3",
"968",
},
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_86C201,
+ 0,
+ "Silicon Integrated System",
+ "86C201",
+ },
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_86C202,
+ 0,
+ "Silicon Integrated System",
+ "86C202",
+ },
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_86C205,
+ 0,
+ "Silicon Integrated System",
+ "86C205",
+ },
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503,
+ 0,
+ "Silicon Integrated System",
+ "85C503",
+ },
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C501,
+ 0,
+ "Silicon Integrated System",
+ "85C501",
+ },
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C496,
+ 0,
+ "Silicon Integrated System",
+ "85C496",
+ },
+ {
+ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C601,
+ 0,
+ "Silicon Integrated System",
+ "85C601",
+ },
{
PCI_VENDOR_SMC, PCI_PRODUCT_SMC_37C665,
0,
"Standard Microsystems",
- "37C665",
+ "FDC 37C665",
+ },
+ {
+ PCI_VENDOR_SYMPHONY, PCI_PRODUCT_SYMPHONY_82C101,
+ 0,
+ "Symphony Labs",
+ "82C101",
+ },
+ {
+ PCI_VENDOR_TEKRAM, PCI_PRODUCT_TEKRAM_DC290,
+ 0,
+ "Tekram Technology",
+ "DC290",
+ },
+ {
+ PCI_VENDOR_TRIDENT, PCI_PRODUCT_TRIDENT_TGUI_9320,
+ 0,
+ "Trident Microsystems",
+ "TGUI 9320",
+ },
+ {
+ PCI_VENDOR_TRIDENT, PCI_PRODUCT_TRIDENT_TGUI_9420,
+ 0,
+ "Trident Microsystems",
+ "TGUI 9420",
+ },
+ {
+ PCI_VENDOR_TRIDENT, PCI_PRODUCT_TRIDENT_TGUI_9440,
+ 0,
+ "Trident Microsystems",
+ "TGUI 9440",
+ },
+ {
+ PCI_VENDOR_TRIDENT, PCI_PRODUCT_TRIDENT_TGUI_9660,
+ 0,
+ "Trident Microsystems",
+ "TGUI 9660",
+ },
+ {
+ PCI_VENDOR_TRIDENT, PCI_PRODUCT_TRIDENT_TGUI_9680,
+ 0,
+ "Trident Microsystems",
+ "TGUI 9680",
+ },
+ {
+ PCI_VENDOR_TRIDENT, PCI_PRODUCT_TRIDENT_TGUI_9682,
+ 0,
+ "Trident Microsystems",
+ "TGUI 9682",
},
{
- PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_W32P_A,
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_ET4000_W32P_A,
0,
"Tseng Labs",
"ET4000w32p rev A",
},
{
- PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_W32P_D,
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_ET4000_W32P_B,
+ 0,
+ "Tseng Labs",
+ "ET4000w32p rev B",
+ },
+ {
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_ET4000_W32P_C,
+ 0,
+ "Tseng Labs",
+ "ET4000w32p rev C",
+ },
+ {
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_ET4000_W32P_D,
0,
"Tseng Labs",
"ET4000w32p rev D",
},
+ {
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_ET6000,
+ 0,
+ "Tseng Labs",
+ "ET6000",
+ },
{
PCI_VENDOR_UMC, PCI_PRODUCT_UMC_UM8673F,
0,
"United Microelectronics",
"UM8886F PCI-ISA bridge",
},
+ {
+ PCI_VENDOR_UMC, PCI_PRODUCT_UMC_UM8886A,
+ 0,
+ "United Microelectronics",
+ "UM8886A",
+ },
+ {
+ PCI_VENDOR_UMC, PCI_PRODUCT_UMC_UM8891A,
+ 0,
+ "United Microelectronics",
+ "UM8891A",
+ },
+ {
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_82C505,
+ 0,
+ "VIA Technologies",
+ "82C505",
+ },
+ {
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_ALT_82C505,
+ 0,
+ "VIA Technologies",
+ "82C505",
+ },
+ {
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_82C576,
+ 0,
+ "VIA Technologies",
+ "82C576 3V",
+ },
+ {
+ PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B,
+ 0,
+ "Vortex Computer Systems",
+ "GDT 6000b",
+ },
+ {
+ PCI_VENDOR_VLSI, PCI_PRODUCT_VLSI_82C592_FC1,
+ 0,
+ "VLSI Technology",
+ "82C592-FC1",
+ },
+ {
+ PCI_VENDOR_VLSI, PCI_PRODUCT_VLSI_82C593_FC1,
+ 0,
+ "VLSI Technology",
+ "82C593-FC1",
+ },
+ {
+ PCI_VENDOR_WEITEK, PCI_PRODUCT_WEITEK_P9000,
+ 0,
+ "Weitek",
+ "P9000",
+ },
+ {
+ PCI_VENDOR_WEITEK, PCI_PRODUCT_WEITEK_P9100,
+ 0,
+ "Weitek",
+ "P9100",
+ },
+ {
+ PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W83769F,
+ 0,
+ "Winbond Electronics",
+ "W83769F",
+ },
+ {
+ PCI_VENDOR_ZEINET, PCI_PRODUCT_ZEINET_1221,
+ 0,
+ "Zeinet",
+ "1221",
+ },
+ {
+ PCI_VENDOR_CYCLADES, PCI_PRODUCT_CYCLADES_CYCLOMY_1,
+ 0,
+ "Cyclades",
+ "Cyclom-Y below 1M",
+ },
+ {
+ PCI_VENDOR_CYCLADES, PCI_PRODUCT_CYCLADES_CYCLOMY_2,
+ 0,
+ "Cyclades",
+ "Cyclom-Y above 1M",
+ },
{
PCI_VENDOR_CYCLADES, PCI_PRODUCT_CYCLADES_CYCLOMY_1,
0,
"Honeywell IASD",
NULL,
},
- {
- PCI_VENDOR_SYMPHONY, 0,
- PCI_KNOWNDEV_NOPROD,
- "Symphony Labs (or Winbond?)",
- NULL,
- },
{
PCI_VENDOR_CORNERSTONE, 0,
PCI_KNOWNDEV_NOPROD,
"Integrated Micro Solutions",
NULL,
},
- {
- PCI_VENDOR_TEKRAM, 0,
- PCI_KNOWNDEV_NOPROD,
- "Tekram Technology",
- NULL,
- },
{
PCI_VENDOR_APTIX, 0,
PCI_KNOWNDEV_NOPROD,
{
PCI_VENDOR_VIATECH, 0,
PCI_KNOWNDEV_NOPROD,
- "Via Technologies",
+ "VIA Technologies",
NULL,
},
{
NULL,
},
{
- PCI_VENDOR_SYMPHONY2, 0,
+ PCI_VENDOR_ZEINET, 0,
PCI_KNOWNDEV_NOPROD,
- "Symphony (duplicate? see 0x10ad)",
+ "Zeinet",
NULL,
},
{
- PCI_VENDOR_TEKRAM2, 0,
+ PCI_VENDOR_SYMPHONY, 0,
PCI_KNOWNDEV_NOPROD,
- "Tekram (mistyped? see 0x10e1)",
+ "Symphony Labs",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TEKRAM, 0,
+ PCI_KNOWNDEV_NOPROD,
+ "Tekram Technology",
NULL,
},
{
-/* $OpenBSD: pcireg.h,v 1.4 1996/10/31 03:29:11 millert Exp $ */
-/* $NetBSD: pcireg.h,v 1.7 1996/03/27 04:08:27 cgd Exp $ */
+/* $OpenBSD: pcireg.h,v 1.5 1996/11/28 23:28:13 niklas Exp $ */
+/* $NetBSD: pcireg.h,v 1.11 1996/08/10 15:42:33 mycroft Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
- * Copyright (c) 1994 Charles Hannum. All rights reserved.
+ * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#define PCI_MAPREG_MEM_ADDR(mr) \
((mr) & PCI_MAPREG_MEM_ADDR_MASK)
+#define PCI_MAPREG_MEM_SIZE(mr) \
+ (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
#define PCI_MAPREG_IO_ADDR(mr) \
((mr) & PCI_MAPREG_IO_ADDR_MASK)
+#define PCI_MAPREG_IO_SIZE(mr) \
+ (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe
/*
-/* $OpenBSD: pcivar.h,v 1.8 1996/11/12 20:30:59 niklas Exp $ */
-/* $NetBSD: pcivar.h,v 1.15 1996/03/28 02:16:23 cgd Exp $ */
+/* $OpenBSD: pcivar.h,v 1.9 1996/11/28 23:28:14 niklas Exp $ */
+/* $NetBSD: pcivar.h,v 1.16 1996/10/21 22:56:57 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
* provided by pci_machdep.h.
*/
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/pci/pcireg.h>
/*
* PCI bus attach arguments.
*/
struct pcibus_attach_args {
- char *pba_busname; /* XXX should be common */
- bus_chipset_tag_t pba_bc; /* XXX should be common */
+ char *pba_busname; /* XXX should be common */
+ bus_space_tag_t pba_iot; /* pci i/o space tag */
+ bus_space_tag_t pba_memt; /* pci mem space tag */
pci_chipset_tag_t pba_pc;
int pba_bus; /* PCI bus number */
* PCI device attach arguments.
*/
struct pci_attach_args {
- bus_chipset_tag_t pa_bc;
+ bus_space_tag_t pa_iot; /* pci i/o space tag */
+ bus_space_tag_t pa_memt; /* pci mem space tag */
pci_chipset_tag_t pa_pc;
u_int pa_device;
* Configuration space access and utility functions. (Note that most,
* e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.)
*/
-int pci_io_find __P((pci_chipset_tag_t, pcitag_t, int, bus_io_addr_t *,
- bus_io_size_t *));
-int pci_mem_find __P((pci_chipset_tag_t, pcitag_t, int, bus_mem_addr_t *,
- bus_mem_size_t *, int *));
+int pci_io_find __P((pci_chipset_tag_t, pcitag_t, int, bus_addr_t *,
+ bus_size_t *));
+int pci_mem_find __P((pci_chipset_tag_t, pcitag_t, int, bus_addr_t *,
+ bus_size_t *, int *));
/*
* Helper functions for autoconfiguration.
-/* $OpenBSD: ppb.c,v 1.4 1996/11/23 21:47:06 kstailey Exp $ */
-/* $NetBSD: ppb.c,v 1.8 1996/05/03 17:33:51 christos Exp $ */
+/* $OpenBSD: ppb.c,v 1.5 1996/11/28 23:28:14 niklas Exp $ */
+/* $NetBSD: ppb.c,v 1.12 1996/10/21 22:57:00 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
* Attach the PCI bus than hangs off of it.
*/
pba.pba_busname = "pci";
- pba.pba_bc = pa->pa_bc;
+ pba.pba_iot = pa->pa_iot;
+ pba.pba_memt = pa->pa_memt;
pba.pba_pc = pc;
pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
pba.pba_intrswiz = pa->pa_intrswiz;
-/* $OpenBSD: if_ep_pcmcia.c,v 1.5 1996/11/12 20:31:00 niklas Exp $ */
+/* $OpenBSD: if_ep_pcmcia.c,v 1.6 1996/11/28 23:28:15 niklas Exp $ */
/* $NetBSD: if_ep.c,v 1.90 1996/04/11 22:29:15 cgd Exp $ */
/*
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/ic/elink3var.h>
#include <dev/ic/elink3reg.h>
struct ep_softc *sc = (void *) match;
struct isa_attach_args *ia = aux;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
- extern int ifqmaxlen;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
+ extern int ifqmaxlen;
- bus_io_write_2(bc, ioh, EP_COMMAND, WINDOW_SELECT | 0);
- bus_io_write_2(bc, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
- bus_io_write_2(bc, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
+ bus_space_write_2(iot, ioh, EP_COMMAND, WINDOW_SELECT | 0);
+ bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
+ bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
/*
* ok til here. Now try to figure out which link we have.
* try coax first...
*/
#ifdef EP_COAX_DEFAULT
- bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG, 0xC000);
+ bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 0xC000);
#else
/* COAX as default is reported to be a problem */
- bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG, 0x0000);
+ bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, 0x0000);
#endif
ifp->if_snd.ifq_maxlen = ifqmaxlen;
{
struct ep_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
u_short conn = 0;
- if (bus_io_map(bc, ia->ia_iobase, ia->ia_iosize, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ia->ia_iosize, 0, &ioh))
panic("ep_isa_attach: can't map i/o space");
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
GO_WINDOW(0);
- conn = bus_io_read_2(bc, ioh, EP_W0_CONFIG_CTRL);
+ conn = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL);
printf(": ");
-/* $Id: pcmcia.c,v 1.7 1996/11/23 21:47:07 kstailey Exp $ */
+/* $Id: pcmcia.c,v 1.8 1996/11/28 23:28:16 niklas Exp $ */
/*
* Copyright (c) 1996 John T. Kohl. All rights reserved.
* Copyright (c) 1994 Stefan Grefen. All rights reserved.
*/
#define PCMCIA_MAP_MEM(a,b,c,d,e,f,g) ((a)->chip_link->pcmcia_map_mem(b,c,d,e,f,g))
-#define SCRATCH_MEM(a) ((a)->scratch_memh)
-#define SCRATCH_BC(a) ((a)->pa_bc)
+#define SCRATCH_MEM(a) ((caddr_t)(a)->scratch_memh)
+#define SCRATCH_MEMT(a) ((a)->pa_memt)
#define SCRATCH_SIZE(a) ((a)->scratch_memsiz)
#define SCRATCH_INUSE(a)((a)->scratch_inuse)
printf("\n");
sc->sc_driver = pca;
- sc->sc_bc = pba->pba_bc;
+ sc->sc_iot = pba->pba_iot;
+ sc->sc_memt = pba->pba_memt;
pcmcia_probe_bus(sc->sc_dev.dv_unit, -1);
}
SCRATCH_INUSE(pca) = 1;
splx(s);
for (i = 0; i < pc_cf->memwin; i++) {
- if ((err = PCMCIA_MAP_MEM(pca, link,
- pca->pa_bc,
+ if ((err = PCMCIA_MAP_MEM(pca, link, pca->pa_memt,
(caddr_t) pc_cf->mem[i].start,
pc_cf->mem[i].caddr,
pc_cf->mem[i].len,
}
}
/* Now we've mapped everything enable it */
- if ((err = PCMCIA_MAP_MEM(pca, link, SCRATCH_BC(pca), SCRATCH_MEM(pca),
- pc_cf->cfg_off & (~(SCRATCH_SIZE(pca) - 1)), SCRATCH_SIZE(pca),
- PCMCIA_MAP_ATTR | PCMCIA_LAST_WIN)) != 0) {
+ if ((err = PCMCIA_MAP_MEM(pca, link, SCRATCH_MEMT(pca),
+ SCRATCH_MEM(pca), pc_cf->cfg_off & (~(SCRATCH_SIZE(pca) - 1)),
+ SCRATCH_SIZE(pca), PCMCIA_MAP_ATTR | PCMCIA_LAST_WIN)) != 0) {
PPRINTF(("pcmcia_mapcard: enable err %d\n", err));
goto error;
}
goto error;
}
-#define GETMEM(x) bus_mem_read_1(pca->pa_bc, SCRATCH_MEM(pca), \
- (pc_cf->cfg_off & (SCRATCH_SIZE(pca)-1)) + x)
-#define PUTMEM(x,v) \
- bus_mem_write_1(pca->pa_bc, SCRATCH_MEM(pca), \
- (pc_cf->cfg_off & (SCRATCH_SIZE(pca)-1)) + x, v)
+#define GETMEM(x) bus_space_read_1(pca->pa_memt, \
+ (bus_space_handle_t)SCRATCH_MEM(pca), \
+ (pc_cf->cfg_off & (SCRATCH_SIZE(pca)-1)) + x)
+#define PUTMEM(x,v) bus_space_write_1(pca->pa_memt, \
+ (bus_space_handle_t)SCRATCH_MEM(pca), \
+ (pc_cf->cfg_off & (SCRATCH_SIZE(pca)-1)) + x, v)
if (ISSET(pc_cf->cfgtype, DOSRESET)) {
PUTMEM(0, PCMCIA_SRESET);
err = 0; /* XXX */
}
error:
- PCMCIA_MAP_MEM(pca, link, SCRATCH_BC(pca), SCRATCH_MEM(pca), 0,
+ PCMCIA_MAP_MEM(pca, link, SCRATCH_MEMT(pca), SCRATCH_MEM(pca), 0,
SCRATCH_SIZE(pca), PCMCIA_LAST_WIN | PCMCIA_UNMAP);
if (err != 0) {
PPRINTF(("pcmcia_mapcard: unmaping\n"));
for (i = 0; i < pc_cf->memwin; i++) {
PCMCIA_MAP_MEM(pca, link,
- pca->pa_bc,
+ pca->pa_memt,
(caddr_t) pc_cf->mem[i].start,
pc_cf->mem[i].caddr,
pc_cf->mem[i].len,
return ENODEV;
for (i = 0; i < link->memwin; i++)
- PCMCIA_MAP_MEM(pca, link, pca->pa_bc, 0, 0, 0,
+ PCMCIA_MAP_MEM(pca, link, pca->pa_memt, 0, 0, 0,
(i | PCMCIA_UNMAP));
for (i = 0; i < link->iowin; i++)
int tlen = min(len + toff, size / 2) - toff;
int i;
- if ((err = PCMCIA_MAP_MEM(pca, link, pca->pa_bc, p, pgoff,
+ if ((err = PCMCIA_MAP_MEM(pca, link, pca->pa_memt, p, pgoff,
size,
PCMCIA_MAP_ATTR |
PCMCIA_LAST_WIN)) != 0)
for (i = 0; i < tlen; j++, i++)
scratch[j] = p[toff + i * 2];
- PCMCIA_MAP_MEM(pca, link, pca->pa_bc, p, 0, size,
+ PCMCIA_MAP_MEM(pca, link, pca->pa_memt, p, 0, size,
PCMCIA_LAST_WIN | PCMCIA_UNMAP);
len -= tlen;
}
SCRATCH_INUSE(pca) = 1;
splx(s);
if ((err = PCMCIA_MAP_MEM(pca, link,
- SCRATCH_BC(pca),
+ SCRATCH_MEMT(pca),
SCRATCH_MEM(pca),
pc_cf.cfg_off &
~(SCRATCH_SIZE(pca)-1),
*d++ = 0xff;
*d++ = 0xff;
PCMCIA_MAP_MEM(pca, link,
- SCRATCH_BC(pca),
+ SCRATCH_MEMT(pca),
SCRATCH_MEM(pca),
0,SCRATCH_SIZE(pca),
PCMCIA_LAST_WIN|PCMCIA_UNMAP);
-/* $Id: pcmciavar.h,v 1.2 1996/11/12 20:31:01 niklas Exp $ */
+/* $Id: pcmciavar.h,v 1.3 1996/11/28 23:28:17 niklas Exp $ */
/*
* Copyright (c) 1995,1996 John T. Kohl. All rights reserved.
* Copyright (c) 1993, 1994 Stefan Grefen. All rights reserved.
#include <sys/queue.h>
#include <sys/select.h>
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
/*
* The following documentation tries to describe the relationship between the
/* 4 map io range */
int (*pcmcia_map_io) __P((struct pcmcia_link *, u_int, u_int, int));
/* 8 map memory window */
- int (*pcmcia_map_mem) __P((struct pcmcia_link *, bus_chipset_tag_t,
+ int (*pcmcia_map_mem) __P((struct pcmcia_link *, bus_space_tag_t,
caddr_t, u_int, u_int, int));
/*12 map interrupt */
int (*pcmcia_map_intr) __P((struct pcmcia_link *, int, int));
struct pcmcia_adapter {
struct pcmcia_funcs *chip_link;
struct pcmciabus_link *bus_link;
- bus_chipset_tag_t pa_bc; /* bus chipset */
- void * adapter_softc;
+ bus_space_tag_t pa_memt; /* mem access handle */
+ void *adapter_softc;
caddr_t scratch_mem; /* pointer to scratch window */
int scratch_memsiz; /* size of scratch window */
- bus_mem_handle_t scratch_memh; /* bus memory handle */
+ bus_space_handle_t scratch_memh;/* bus memory handle */
int scratch_inuse; /* window in use */
int nslots; /* # of slots controlled */
};
*/
struct pcmciabus_softc {
struct device sc_dev;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
+ bus_space_tag_t sc_memt;
struct pcmcia_link *sc_link[4]; /* up to 4 slots per bus */
struct pcmcia_adapter *sc_driver;
};
};
struct pcmciabus_attach_args {
- bus_chipset_tag_t pba_bc;
+ bus_space_tag_t pba_iot;
+ bus_space_tag_t pba_memt;
int pba_maddr;
int pba_msize;
void *pba_aux; /* driver specific */
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