-/* $OpenBSD: drmP.h,v 1.192 2015/04/12 03:54:10 jsg Exp $ */
+/* $OpenBSD: drmP.h,v 1.193 2015/04/12 11:26:54 jsg Exp $ */
/* drmP.h -- Private header for Direct Rendering Manager -*- linux-c -*-
* Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
*/
#define DRM_SUSER(p) (suser(p, 0) == 0)
#define DRM_MTRR_WC MDF_WRITECOMBINE
+extern int ticks;
+
#define drm_msleep(x, msg) mdelay(x)
extern struct cfdriver drm_cd;
-/* $OpenBSD: i915_drv.c,v 1.77 2015/04/11 02:24:43 jsg Exp $ */
+/* $OpenBSD: i915_drv.c,v 1.78 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
*
static int i965_do_reset(struct drm_device *dev)
{
+ int ret;
struct drm_i915_private *dev_priv = dev->dev_private;
pcireg_t reg;
- int retries;
/*
* Set the domains we want to reset (GRDOM/bits 2 and 3) as
reg |= ((GRDOM_RENDER | GRDOM_RESET_ENABLE) << 24);
pci_conf_write(dev_priv->pc, dev_priv->tag, I965_GDRST, reg);
- for (retries = 500; retries > 0 ; retries--) {
- if (i965_reset_complete(dev))
- break;
- DELAY(1000);
- }
- if (retries == 0) {
- DRM_ERROR("965 reset timed out\n");
- return -ETIMEDOUT;
- }
+ ret = wait_for(i965_reset_complete(dev), 500);
+ if (ret)
+ return ret;
/* We can't reset render&media without also resetting display ... */
reg = pci_conf_read(dev_priv->pc, dev_priv->tag, I965_GDRST);
reg |= ((GRDOM_MEDIA | GRDOM_RESET_ENABLE) << 24);
pci_conf_write(dev_priv->pc, dev_priv->tag, I965_GDRST, reg);
- for (retries = 500; retries > 0 ; retries--) {
- if (i965_reset_complete(dev))
- break;
- DELAY(1000);
- }
- if (retries == 0) {
- DRM_ERROR("965 reset 2 timed out\n");
- return -ETIMEDOUT;
- }
-
- return (0);
+ return wait_for(i965_reset_complete(dev), 500);
}
static int ironlake_do_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 gdrst;
- int retries;
+ int ret;
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
- for (retries = 500; retries > 0 ; retries--) {
- if (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
- DRM_ERROR("ironlake reset timed out\n");
- return -ETIMEDOUT;
- }
+ ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
+ if (ret)
+ return ret;
/* We can't reset render&media without also resetting display ... */
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- for (retries = 500; retries > 0 ; retries--) {
- if (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
- DRM_ERROR("ironlake reset timed out\n");
- return -ETIMEDOUT;
- }
-
- return (0);
+ return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
}
static int gen6_do_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int ret = 0;
unsigned long irqflags;
- int retries;
/* Hold gt_lock across reset to prevent any register access
* with forcewake not set correctly
I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
/* Spin waiting for the device to ack the reset request */
- for (retries = 500; retries > 0 ; retries--) {
- if ((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
- DRM_ERROR("gen6 reset timed out\n");
- ret = -ETIMEDOUT;
- }
+ ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
/* If reset with a user forcewake, try to restore, otherwise turn it off */
if (dev_priv->forcewake_count)
-/* $OpenBSD: intel_crt.c,v 1.10 2015/02/11 07:01:37 jsg Exp $ */
+/* $OpenBSD: intel_crt.c,v 1.11 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright © 2006-2007 Intel Corporation
*
struct drm_i915_private *dev_priv = dev->dev_private;
u32 adpa;
bool ret;
- int retries;
/* The first time through, trigger an explicit detection cycle */
if (crt->force_hotplug_required) {
I915_WRITE(PCH_ADPA, adpa);
- for (retries = 1000; retries > 0; retries--) {
- if ((I915_READ(PCH_ADPA) &
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
+ 1000))
DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
if (turn_off_dac) {
u32 adpa;
bool ret;
u32 save_adpa;
- int retries;
save_adpa = adpa = I915_READ(ADPA);
DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
I915_WRITE(ADPA, adpa);
-
- for (retries = 1000; retries > 0; retries--) {
- if ((I915_READ(PCH_ADPA) &
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
+ 1000)) {
DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
I915_WRITE(ADPA, save_adpa);
}
struct drm_i915_private *dev_priv = dev->dev_private;
u32 hotplug_en, orig, stat;
bool ret = false;
- int i, tries = 0, retries;
+ int i, tries = 0;
if (HAS_PCH_SPLIT(dev))
return intel_ironlake_crt_detect_hotplug(connector);
/* turn on the FORCE_DETECT */
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
/* wait for FORCE_DETECT to go off */
- for (retries = 1000; retries > 0; retries--) {
- if ((I915_READ(PORT_HOTPLUG_EN) &
- CRT_HOTPLUG_FORCE_DETECT) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
+ CRT_HOTPLUG_FORCE_DETECT) == 0,
+ 1000))
DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
}
-/* $OpenBSD: intel_display.c,v 1.47 2015/04/08 04:24:40 jsg Exp $ */
+/* $OpenBSD: intel_display.c,v 1.48 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright © 2006-2007 Intel Corporation
*
{
unsigned long flags;
u32 val = 0;
- int retries;
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0)
- break;
- DELAY(100);
- }
- if (retries == 0) {
+ if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
DRM_ERROR("DPIO idle wait timed out\n");
goto out_unlock;
}
I915_WRITE(DPIO_REG, reg);
I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
DPIO_BYTE);
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0)
- break;
- DELAY(100);
- }
- if (retries == 0) {
+ if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
DRM_ERROR("DPIO read wait timed out\n");
goto out_unlock;
}
u32 val)
{
unsigned long flags;
- int retries;
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0)
- break;
- DELAY(100);
- }
- if (retries == 0) {
+ if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
DRM_ERROR("DPIO idle wait timed out\n");
goto out_unlock;
}
I915_WRITE(DPIO_REG, reg);
I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
DPIO_BYTE);
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0)
- break;
- DELAY(100);
- }
- if (retries == 0)
+ if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
DRM_ERROR("DPIO write wait timed out\n");
out_unlock:
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 frame, frame_reg = PIPEFRAME(pipe);
- int retries;
frame = I915_READ(frame_reg);
- for (retries = 50; retries > 0; retries--) {
- if (I915_READ_NOTRACE(frame_reg) != frame)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
DRM_DEBUG_KMS("vblank wait timed out\n");
}
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipestat_reg = PIPESTAT(pipe);
- int retries;
if (INTEL_INFO(dev)->gen >= 5) {
ironlake_wait_for_vblank(dev, pipe);
I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
/* Wait for vblank interrupt bit to set */
- for (retries = 50; retries > 0; retries--) {
- if (I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for(I915_READ(pipestat_reg) &
+ PIPE_VBLANK_INTERRUPT_STATUS,
+ 50))
DRM_DEBUG_KMS("vblank wait timed out\n");
}
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
- int retries;
if (INTEL_INFO(dev)->gen >= 4) {
int reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
- for (retries = 100; retries > 0; retries--) {
- if ((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
+ 100))
WARN(1, "pipe_off wait timed out\n");
} else {
u32 last_line, line_mask;
int reg = PIPEDSL(pipe);
+ unsigned long timeout = ticks + msecs_to_jiffies(100);
if (IS_GEN2(dev))
line_mask = DSL_LINEMASK_GEN2;
line_mask = DSL_LINEMASK_GEN3;
/* Wait for the display line to settle */
- for (retries = 100; retries > 0; retries--) {
+ do {
last_line = I915_READ(reg) & line_mask;
mdelay(5);
- if ((I915_READ(reg) & line_mask) == last_line)
- break;
- }
- if (retries == 0)
+ } while (((I915_READ(reg) & line_mask) != last_line) &&
+ time_after(timeout, ticks));
+ if (time_after(ticks, timeout))
WARN(1, "pipe_off wait timed out\n");
}
}
{
unsigned long flags;
u32 tmp;
- int retries;
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
- for (retries = 100; retries > 0; retries--) {
- if ((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
goto out_unlock;
}
tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
- for (retries = 100; retries > 0; retries--) {
- if ((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
+ 100)) {
DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
goto out_unlock;
}
{
unsigned long flags;
u32 value = 0;
- int retries;
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
- for (retries = 100; retries > 0; retries--) {
- if ((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
goto out_unlock;
}
value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
- for (retries = 100; retries > 0; retries--) {
- if ((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
+ 100)) {
DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
goto out_unlock;
}
struct drm_device *dev = dev_priv->dev;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
uint32_t reg, val, pipeconf_val;
- int retries;
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
val |= TRANS_PROGRESSIVE;
I915_WRITE(reg, val | TRANS_ENABLE);
- for (retries = 100; retries > 0; retries--) {
- if (I915_READ(reg) & TRANS_STATE_ENABLE)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
DRM_ERROR("failed to enable transcoder %d\n", pipe);
}
enum transcoder cpu_transcoder)
{
u32 val, pipeconf_val;
- int retries;
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
val |= TRANS_PROGRESSIVE;
I915_WRITE(TRANSCONF(TRANSCODER_A), val);
- for (retries = 100; retries > 0; retries--) {
- if (I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
DRM_ERROR("Failed to enable PCH transcoder\n");
}
{
struct drm_device *dev = dev_priv->dev;
uint32_t reg, val;
- int retries;
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe);
val &= ~TRANS_ENABLE;
I915_WRITE(reg, val);
/* wait for PCH transcoder off, transcoder state */
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(reg) & TRANS_STATE_ENABLE) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
DRM_ERROR("failed to disable transcoder %d\n", pipe);
if (!HAS_PCH_IBX(dev)) {
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
{
u32 val;
- int retries;
val = I915_READ(_TRANSACONF);
val &= ~TRANS_ENABLE;
I915_WRITE(_TRANSACONF, val);
/* wait for PCH transcoder off, transcoder state */
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
DRM_ERROR("Failed to disable PCH transcoder\n");
/* Workaround: clear timing override bit. */
struct drm_i915_private *dev_priv = dev->dev_private;
int dslreg = PIPEDSL(pipe);
u32 temp;
- int retries;
temp = I915_READ(dslreg);
udelay(500);
- for (retries = 10; retries > 0; retries--) {
- if (I915_READ(dslreg) != temp)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
- DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
+ if (wait_for(I915_READ(dslreg) != temp, 5)) {
+ if (wait_for(I915_READ(dslreg) != temp, 5))
+ DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
}
}
u32 bestn, bestm1, bestm2, bestp1, bestp2;
bool is_sdvo;
u32 temp;
- int retries;
is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
POSTING_READ(DPLL(pipe));
- for (retries = 1; retries > 0; retries--) {
- if ((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
bool has_vga = false;
bool is_sdv = false;
u32 tmp;
- int retries;
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
switch (encoder->type) {
tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
I915_WRITE(SOUTH_CHICKEN2, tmp);
- for (retries = 100; retries > 0; retries--) {
- if (I915_READ(SOUTH_CHICKEN2) & FDI_MPHY_IOSFSB_RESET_STATUS)
- break;
- DELAY(100);
- }
- if (retries == 0)
+ if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
+ FDI_MPHY_IOSFSB_RESET_STATUS, 100))
DRM_ERROR("FDI mPHY reset assert timeout\n");
tmp = I915_READ(SOUTH_CHICKEN2);
tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
I915_WRITE(SOUTH_CHICKEN2, tmp);
- for (retries = 100; retries > 0; retries--) {
- if ((I915_READ(SOUTH_CHICKEN2) & FDI_MPHY_IOSFSB_RESET_STATUS) == 0)
- break;
- DELAY(100);
- }
- if (retries == 0)
+ if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
+ FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
+ 100))
DRM_ERROR("FDI mPHY reset de-assert timeout\n");
}
-/* $OpenBSD: intel_dp.c,v 1.23 2015/04/06 10:56:37 jsg Exp $ */
+/* $OpenBSD: intel_dp.c,v 1.24 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright © 2008 Intel Corporation
*
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
- int retries;
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
mask, value,
I915_READ(PCH_PP_STATUS),
I915_READ(PCH_PP_CONTROL));
- for (retries = 5000; retries > 0; retries--) {
- if ((I915_READ(PCH_PP_STATUS) & mask) == value)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
I915_READ(PCH_PP_STATUS),
I915_READ(PCH_PP_CONTROL));
+ }
}
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
enum port port = intel_dig_port->port;
int ret;
uint32_t temp;
- int retries;
if (IS_HASWELL(dev)) {
temp = I915_READ(DP_TP_CTL(port));
temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
I915_WRITE(DP_TP_CTL(port), temp);
- for (retries = 100; retries > 0; retries--) {
- if (I915_READ(DP_TP_STATUS(port)) &
- DP_TP_STATUS_IDLE_DONE)
- break;
- DELAY(100);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(DP_TP_STATUS(port)) &
+ DP_TP_STATUS_IDLE_DONE), 1))
DRM_ERROR("Timed out waiting for DP idle patterns\n");
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
-/* $OpenBSD: intel_drv.h,v 1.5 2014/01/23 03:49:53 jsg Exp $ */
+/* $OpenBSD: intel_drv.h,v 1.6 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
* Copyright (c) 2007-2008 Intel Corporation
#include <dev/pci/drm/drm_fb_helper.h>
#include <dev/pci/drm/drm_dp_helper.h>
+#define _wait_for(COND, MS, W) ({ \
+ int ret__ = 0; \
+ int retries__; \
+ for (retries__ = MS; retries__ > 0; retries__--) { \
+ if ((COND)) \
+ break; \
+ if (W && drm_can_sleep()) { \
+ drm_msleep(1, "wfc"); \
+ } else { \
+ mdelay(1); \
+ } \
+ } \
+ if (retries__ == 0) \
+ ret__ = -ETIMEDOUT; \
+ ret__; \
+})
+
+#define wait_for_atomic_us(COND, US) ({ \
+ int ret__ = 0; \
+ int retries__; \
+ for (retries__ = US; retries__ > 0; retries__--) { \
+ if ((COND)) \
+ break; \
+ DELAY(1); \
+ } \
+ if (retries__ == 0) \
+ ret__ = -ETIMEDOUT; \
+ ret__; \
+})
+
+#define wait_for(COND, MS) _wait_for(COND, MS, 1)
+#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
+
#define KHz(x) (1000*x)
#define MHz(x) KHz(1000*x)
-/* $OpenBSD: intel_lvds.c,v 1.13 2015/02/11 07:01:37 jsg Exp $ */
+/* $OpenBSD: intel_lvds.c,v 1.14 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright © 2006-2007 Intel Corporation
* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 ctl_reg, lvds_reg, stat_reg;
- int retries;
if (HAS_PCH_SPLIT(dev)) {
ctl_reg = PCH_PP_CONTROL;
I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
POSTING_READ(lvds_reg);
- for (retries = 1000; retries > 0; retries--) {
- if ((I915_READ(stat_reg) & PP_ON) != 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
DRM_ERROR("timed out waiting for panel to power on\n");
intel_panel_enable_backlight(dev, intel_crtc->pipe);
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 ctl_reg, lvds_reg, stat_reg;
- int retries;
if (HAS_PCH_SPLIT(dev)) {
ctl_reg = PCH_PP_CONTROL;
intel_panel_disable_backlight(dev);
I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
- for (retries = 1000; retries > 0; retries--) {
- if ((I915_READ(stat_reg) & PP_ON) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
DRM_ERROR("timed out waiting for panel to power off\n");
if (lvds_encoder->pfit_control) {
-/* $OpenBSD: intel_pm.c,v 1.31 2015/04/11 05:10:13 jsg Exp $ */
+/* $OpenBSD: intel_pm.c,v 1.32 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright © 2012 Intel Corporation
*
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 fbc_ctl;
- int retries;
/* Disable compression */
fbc_ctl = I915_READ(FBC_CONTROL);
I915_WRITE(FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
- for (retries = 10; retries > 0; retries--) {
- if ((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
DRM_DEBUG_KMS("FBC idle timed out\n");
return;
}
struct drm_i915_private *dev_priv = dev->dev_private;
u32 rgvmodectl = I915_READ(MEMMODECTL);
u8 fmax, fmin, fstart, vstart;
- int retries;
spin_lock_irq(&mchdev_lock);
rgvmodectl |= MEMMODE_SWMODE_EN;
I915_WRITE(MEMMODECTL, rgvmodectl);
- for (retries = 10; retries > 0; retries--) {
- if ((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
DRM_ERROR("stuck trying to change perf mode\n");
mdelay(1);
static void ironlake_disable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int retries;
if (I915_READ(PWRCTXA)) {
/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON)
- break;
- DELAY(1000);
- }
+ wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
+ 50);
I915_WRITE(PWRCTXA, 0);
POSTING_READ(PWRCTXA);
HSW_PWR_WELL_CTL2,
HSW_PWR_WELL_CTL4
};
- int i, retries;
+ int i;
if (!IS_HASWELL(dev))
return;
if ((well & HSW_PWR_WELL_STATE) == 0) {
I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
- for (retries = 20; retries > 0; retries--) {
- if (I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
}
}
static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
{
u32 gt_thread_status_mask;
- int retries;
if (IS_HASWELL(dev_priv->dev))
gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
/* w/a for a sporadic read returning 0 by waiting for the GT
* thread to wake up.
*/
- for (retries = 500; retries > 0; retries--) {
- if ((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) &
- gt_thread_status_mask) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
DRM_ERROR("GT thread status wait timed out\n");
}
static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
{
u32 forcewake_ack;
- int count;
if (IS_HASWELL(dev_priv->dev))
forcewake_ack = FORCEWAKE_ACK_HSW;
else
forcewake_ack = FORCEWAKE_ACK;
- count = 0;
- while (count++ < 50 && (I915_READ_NOTRACE(forcewake_ack) & 1))
- DELAY(10);
+ if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
+ FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
- count = 0;
- while (count++ < 50 && (I915_READ_NOTRACE(forcewake_ack) & 1) == 0)
- DELAY(10);
+ if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
+ FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
__gen6_gt_wait_for_thread_c0(dev_priv);
}
static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
{
u32 forcewake_ack;
- int count;
if (IS_HASWELL(dev_priv->dev))
forcewake_ack = FORCEWAKE_ACK_HSW;
else
forcewake_ack = FORCEWAKE_MT_ACK;
- count = 0;
- while (count++ < 50 && (I915_READ_NOTRACE(forcewake_ack) & 1))
- DELAY(10);
+ if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
+ FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
/* something from same cacheline, but !FORCEWAKE_MT */
POSTING_READ(ECOBUS);
- count = 0;
- while (count++ < 50 && (I915_READ_NOTRACE(forcewake_ack) & 1) == 0)
- DELAY(10);
+ if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
+ FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
__gen6_gt_wait_for_thread_c0(dev_priv);
}
static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
{
- int count;
-
- count = 0;
- while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1))
- DELAY(10);
+ if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
+ FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
- count = 0;
- while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
- DELAY(10);
+ if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
+ FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
__gen6_gt_wait_for_thread_c0(dev_priv);
}
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
{
- int retries;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
I915_WRITE(GEN6_PCODE_DATA, *val);
I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
- for (retries = 500; retries > 0; retries--) {
- if ((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+ 500)) {
DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
return -ETIMEDOUT;
}
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
{
- int retries;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
I915_WRITE(GEN6_PCODE_DATA, val);
I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
- for (retries = 500; retries > 0; retries--) {
- if ((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+ 500)) {
DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
return -ETIMEDOUT;
}
-/* $OpenBSD: intel_ringbuffer.c,v 1.26 2015/04/12 03:54:10 jsg Exp $ */
+/* $OpenBSD: intel_ringbuffer.c,v 1.27 2015/04/12 11:26:54 jsg Exp $ */
/*
* Copyright © 2008-2010 Intel Corporation
*
struct drm_i915_gem_object *obj = ring->obj;
int ret = 0;
u32 head;
- int retries;
if (HAS_FORCE_WAKE(dev))
gen6_gt_force_wake_get(dev_priv);
| RING_VALID);
/* If the head is still not zero, the ring is dead */
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ_CTL(ring) & RING_VALID) != 0 &&
- I915_READ_START(ring) == obj->gtt_offset &&
- (I915_READ_HEAD(ring) & HEAD_ADDR) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0) {
+ if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
+ I915_READ_START(ring) == obj->gtt_offset &&
+ (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
DRM_ERROR("%s initialization failed "
"ctl %08x head %08x tail %08x start %08x\n",
ring->name,
/* Flush the TLB for this page */
if (INTEL_INFO(dev)->gen >= 6) {
- int retries;
u32 reg = RING_INSTPM(ring->mmio_base);
I915_WRITE(reg,
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
INSTPM_SYNC_FLUSH));
- for (retries = 1000; retries > 0; retries--) {
- if ((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
+ 1000))
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
ring->name);
}
u32 value)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
- int retries;
/* Every tail move must follow the sequence below */
I915_WRITE64(GEN6_BSD_RNCID, 0x0);
/* Wait for the ring not to be idle, i.e. for it to wake up. */
- for (retries = 50; retries > 0; retries--) {
- if ((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
- GEN6_BSD_SLEEP_INDICATOR) == 0)
- break;
- DELAY(1000);
- }
- if (retries == 0)
+ if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
+ GEN6_BSD_SLEEP_INDICATOR) == 0,
+ 50))
DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
/* Now that the ring is fully powered up, update the tail */
projects / openbsd / commitdiff