-/* $OpenBSD: com.c,v 1.27 1996/11/12 20:30:27 niklas Exp $ */
+/* $OpenBSD: com.c,v 1.28 1996/11/29 22:54:52 niklas Exp $ */
/* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */
/*-
#include <sys/types.h>
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
struct com_softc {
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
struct tty *sc_tty;
int sc_overflows;
int sc_hayespbase;
#endif
- bus_io_handle_t sc_ioh;
- bus_io_handle_t sc_hayespioh;
+ bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_hayespioh;
+ isa_chipset_tag_t sc_ic;
u_char sc_hwflags;
#define COM_HW_NOIEN 0x01
};
#ifdef COM_HAYESP
-int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc));
+int comprobeHAYESP __P((bus_space_handle_t hayespioh, struct com_softc *sc));
#endif
void comdiag __P((void *));
int comspeed __P((long));
};
#endif
+#if NCOM_PICA
+#undef CONADDR /* This is stupid but using devs before config .. */
+#define CONADDR 0xe0006000
+
+struct cfattach com_pica_ca = {
+ sizeof(struct com_softc), comprobe, comattach
+};
+#endif
+
struct cfdriver com_cd = {
NULL, "com", DV_TTY
};
int comconsaddr;
int comconsinit;
int comconsattached;
-bus_chipset_tag_t comconsbc;
-bus_io_handle_t comconsioh;
+bus_space_tag_t comconsiot;
+bus_space_handle_t comconsioh;
tcflag_t comconscflag = TTYDEF_CFLAG;
int commajor;
(sc->sc_hwflags & (COM_HW_ABSENT_PENDING|COM_HW_CONSOLE));
} else
sc->sc_hwflags = 0;
+ sc->sc_ic = ia->ia_ic;
}
return rval;
}
ttyfree(sc->sc_tty);
sc->sc_tty = NULL;
ok:
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
+ isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
sc->sc_ih = NULL;
SET(sc->sc_hwflags, COM_HW_ABSENT);
return 0; /* OK! */
}
int
-comprobe1(bc, ioh, iobase)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+comprobe1(iot, ioh, iobase)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int iobase;
{
int i, k;
/* force access to id reg */
- bus_io_write_1(bc, ioh, com_lcr, 0);
- bus_io_write_1(bc, ioh, com_iir, 0);
+ bus_space_write_1(iot, ioh, com_lcr, 0);
+ bus_space_write_1(iot, ioh, com_iir, 0);
for (i = 0; i < 32; i++) {
- k = bus_io_read_1(bc, ioh, com_iir);
+ k = bus_space_read_1(iot, ioh, com_iir);
if (k & 0x38) {
- bus_io_read_1(bc, ioh, com_data); /* cleanup */
+ bus_space_read_1(iot, ioh, com_data); /* cleanup */
} else
break;
}
#ifdef COM_HAYESP
int
comprobeHAYESP(hayespioh, sc)
- bus_io_handle_t hayespioh;
+ bus_space_handle_t hayespioh;
struct com_softc *sc;
{
char val, dips;
int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
- bus_chipset_tag_t bc = sc->sc_bc;
+ bus_space_tag_t iot = sc->sc_iot;
/*
* Hayes ESP cards have two iobases. One is for compatibility with
*/
/* Test for ESP signature */
- if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0)
+ if ((bus_space_read_1(iot, hayespioh, 0) & 0xf3) == 0)
return 0;
/*
*/
/* Get the dip-switch configurations */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
- dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
+ dips = bus_space_read_1(iot, hayespioh, HAYESP_STATUS1);
/* Determine which com port this ESP card services: bits 0,1 of */
/* dips is the port # (0-3); combaselist[val] is the com_iobase */
/* Check ESP Self Test bits. */
/* Check for ESP version 2.0: bits 4,5,6 == 010 */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
+ val = bus_space_read_1(iot, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
+ val = bus_space_read_1(iot, hayespioh, HAYESP_STATUS2);
if ((val & 0x70) < 0x20) {
printf("-old (%o)", val & 0x70);
/* we do not support the necessary features */
struct device *parent;
void *match, *aux;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int iobase, needioh;
int rv = 1;
#elif NCOM_ISA
#define IS_ISA(parent) \
!strcmp((parent)->dv_cfdata->cf_driver->cd_name, "isa")
+#endif
+#if NCOM_PICA
+#define IS_PICA(parent) \
+ !strcmp((parent)->dv_cfdata->cf_driver->cd_name, "pica")
#endif
/*
* XXX should be broken out into functions for isa probe and
if (IS_ISA(parent)) {
struct isa_attach_args *ia = aux;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
iobase = ia->ia_iobase;
needioh = 1;
} else
if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave)
return (0);
- bc = ca->ca_bc;
+ iot = ca->ca_iot;
iobase = ca->ca_iobase;
ioh = ca->ca_ioh;
needioh = 0;
} else
+#endif
+#if NCOM_PICA
+ if(IS_PICA(parent)) {
+ struct confargs *ca = aux;
+ if(!BUS_MATCHNAME(ca, "com"))
+ return(0);
+ iobase = (long)BUS_CVTADDR(ca);
+ iot = 0;
+ needioh = 1;
+ } else
#endif
return(0); /* This cannot happen */
if (iobase == comconsaddr && !comconsattached)
goto out;
- if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (needioh && bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- rv = comprobe1(bc, ioh, iobase);
+ rv = comprobe1(iot, ioh, iobase);
if (needioh)
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
out:
#if NCOM_ISA || NCOM_PCMCIA
{
struct com_softc *sc = (void *)self;
int iobase, irq;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
#ifdef COM_HAYESP
int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
int *hayespp;
* We're living on an isa.
*/
iobase = ia->ia_iobase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
if (iobase != comconsaddr) {
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh))
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh))
panic("comattach: io mapping failed");
} else
ioh = comconsioh;
* We're living on a commulti.
*/
iobase = ca->ca_iobase;
- bc = ca->ca_bc;
+ iot = ca->ca_iot;
ioh = ca->ca_ioh;
irq = IRQUNK;
if (ca->ca_noien)
SET(sc->sc_hwflags, COM_HW_NOIEN);
} else
+#endif
+#if NCOM_PICA
+ if(IS_PICA(parent)) {
+ struct confargs *ca = aux;
+ iobase = (long)BUS_CVTADDR(ca);
+ iot = 0;
+ irq = 0;
+ ioh = iobase;
+ } else
#endif
panic("comattach: impossible");
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->sc_iobase = iobase;
#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
- bus_io_handle_t hayespioh;
+ bus_space_handle_t hayespioh;
#define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */
- if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh))
+ if (bus_space_map(iot, *hayespp, HAYESP_NPORTS, 0, &hayespioh))
continue;
if (comprobeHAYESP(hayespioh, sc)) {
sc->sc_hayespbase = *hayespp;
sc->sc_hayespioh = hayespioh;
break;
}
- bus_io_unmap(bc, hayespioh, HAYESP_NPORTS);
+ bus_space_unmap(iot, hayespioh, HAYESP_NPORTS);
}
/* No ESP; look for other things. */
if (*hayespp == 0) {
#endif
/* look for a NS 16550AF UART with FIFOs */
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
delay(100);
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) ==
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_FIFO_MASK) ==
IIR_FIFO_MASK)
- if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) ==
+ if (ISSET(bus_space_read_1(iot, ioh, com_fifo), FIFO_TRIGGER_14) ==
FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
printf(": ns16550a, working fifo\n");
printf(": ns16550, broken fifo\n");
else
printf(": ns8250 or ns16450, no fifo\n");
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
#ifdef COM_HAYESP
}
#endif
/* disable interrupts */
- bus_io_write_1(bc, ioh, com_ier, 0);
- bus_io_write_1(bc, ioh, com_mcr, 0);
+ bus_space_write_1(iot, ioh, com_ier, 0);
+ bus_space_write_1(iot, ioh, com_mcr, 0);
if (irq != IRQUNK) {
#if NCOM_ISA || NCOM_PCMCIA
IST_EDGE, IPL_TTY, comintr, sc,
sc->sc_dev.dv_xname);
} else
+#endif
+#if NCOM_PICA
+ if (IS_PICA(parent)) {
+ struct confargs *ca = aux;
+ BUS_INTR_ESTABLISH(ca, comintr, (void *)(long)sc);
+ } else
#endif
panic("comattach: IRQ but can't have one");
}
if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
kgdb_dev = -1; /* can't debug over console port */
else {
- cominit(bc, ioh, kgdb_rate);
+ cominit(iot, ioh, kgdb_rate);
if (kgdb_debug_init) {
/*
* Print prefix of device name,
{
int unit = DEVUNIT(dev);
struct com_softc *sc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct tty *tp;
int s;
int error = 0;
sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER;
sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
- bc = sc->sc_bc;
+ iot = sc->sc_iot;
ioh = sc->sc_ioh;
#ifdef COM_HAYESP
/* Setup the ESP board */
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- bus_io_handle_t hayespioh = sc->sc_hayespioh;
+ bus_space_handle_t hayespioh = sc->sc_hayespioh;
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_DMA_MODE|FIFO_ENABLE|
FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
/* Set 16550 compatibility mode */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
HAYESP_MODE_SCALE);
/* Set RTS/CTS flow control */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
/* Set flow control levels */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXLOWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
} else
#endif
* Set the FIFO threshold based on the receive speed.
*/
for (;;) {
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
delay(100);
- (void) bus_io_read_1(bc, ioh, com_data);
- bus_io_write_1(bc, ioh, com_fifo,
+ (void) bus_space_read_1(iot, ioh, com_data);
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
(tp->t_ispeed <= 1200 ?
FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
delay(100);
- if(!ISSET(bus_io_read_1(bc, ioh,
+ if(!ISSET(bus_space_read_1(iot, ioh,
com_lsr), LSR_RXRDY))
break;
}
}
/* flush any pending I/O */
- while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
- (void) bus_io_read_1(bc, ioh, com_data);
+ while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY))
+ (void) bus_space_read_1(iot, ioh, com_data);
/* you turn me on, baby */
sc->sc_mcr = MCR_DTR | MCR_RTS;
if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
SET(sc->sc_mcr, MCR_IENABLE);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
- sc->sc_msr = bus_io_read_1(bc, ioh, com_msr);
+ sc->sc_msr = bus_space_read_1(iot, ioh, com_msr);
if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) ||
ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF))
SET(tp->t_state, TS_CARR_ON);
int unit = DEVUNIT(dev);
struct com_softc *sc = com_cd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s;
/* XXX This is for cons.c. */
if (!ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
/* can't do any of this stuff .... */
CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
- bus_io_write_1(bc, ioh, com_ier, 0);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_ier, 0);
if (ISSET(tp->t_cflag, HUPCL) &&
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) {
/* XXX perhaps only clear DTR */
- bus_io_write_1(bc, ioh, com_mcr, 0);
+ bus_space_write_1(iot, ioh, com_mcr, 0);
}
}
CLR(tp->t_state, TS_BUSY | TS_FLUSH);
int unit = DEVUNIT(dev);
struct com_softc *sc = com_cd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int error;
if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
switch (cmd) {
case TIOCSBRK:
SET(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCCBRK:
CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCSDTR:
SET(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCCDTR:
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMSET:
CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
case TIOCMBIS:
SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMBIC:
CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMGET: {
u_char m;
SET(bits, TIOCM_DSR);
if (ISSET(m, MSR_RI | MSR_TERI))
SET(bits, TIOCM_RI);
- if (bus_io_read_1(bc, ioh, com_ier))
+ if (bus_space_read_1(iot, ioh, com_ier))
SET(bits, TIOCM_LE);
*(int *)data = bits;
break;
struct termios *t;
{
struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int ospeed = comspeed(t->c_ospeed);
u_char lcr;
tcflag_t oldcflag;
if (ospeed == 0) {
CLR(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
/*
}
}
- bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB);
- bus_io_write_1(bc, ioh, com_dlbl, ospeed);
- bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8);
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB);
+ bus_space_write_1(iot, ioh, com_dlbl, ospeed);
+ bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
SET(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
} else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) &&
ISSET(sc->sc_hwflags, COM_HW_FIFO))
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE |
(t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
} else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
/* When not using CRTSCTS, RTS follows DTR. */
if (!ISSET(t->c_cflag, CRTSCTS)) {
if (ISSET(sc->sc_mcr, MCR_DTR)) {
if (!ISSET(sc->sc_mcr, MCR_RTS)) {
SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
} else {
if (ISSET(sc->sc_mcr, MCR_RTS)) {
CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
}
sc->sc_dtr = MCR_DTR | MCR_RTS;
ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
/* Just to be sure... */
struct tty *tp;
{
struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s;
s = spltty();
if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
SET(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
}
#ifdef COM_HAYESP
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
u_char buffer[1024], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do
- bus_io_write_1(bc, ioh, com_data, *cp++);
+ bus_space_write_1(iot, ioh, com_data, *cp++);
while (--n);
}
else
u_char buffer[16], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do {
- bus_io_write_1(bc, ioh, com_data, *cp++);
+ bus_space_write_1(iot, ioh, com_data, *cp++);
} while (--n);
} else
- bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq));
+ bus_space_write_1(iot, ioh, com_data, getc(&tp->t_outq));
out:
splx(s);
return;
stopped:
if (ISSET(sc->sc_ier, IER_ETXRDY)) {
CLR(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
}
splx(s);
}
!ISSET(sc->sc_mcr, MCR_RTS)) {
/* XXX */
SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr,
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr,
sc->sc_mcr);
}
void *arg;
{
struct com_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct tty *tp;
u_char lsr, data, msr, delta;
#ifdef COM_DEBUG
#ifdef COM_DEBUG
n = 0;
- if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(iter[n].iir = bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (0);
#else
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (0);
#endif
#ifdef COM_DEBUG
iter[n].lsr =
#endif
- lsr = bus_io_read_1(bc, ioh, com_lsr);
+ lsr = bus_space_read_1(iot, ioh, com_lsr);
if (ISSET(lsr, LSR_RXRDY)) {
register u_char *p = sc->sc_ibufp;
comevents = 1;
do {
- data = bus_io_read_1(bc, ioh, com_data);
+ data = bus_space_read_1(iot, ioh, com_data);
if (ISSET(lsr, LSR_BI)) {
#ifdef notdef
printf("break %02x %02x %02x %02x\n",
ISSET(tp->t_cflag, CRTSCTS)) {
/* XXX */
CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr,
+ bus_space_write_1(iot, ioh, com_mcr,
sc->sc_mcr);
}
}
goto ohfudge;
iter[n].lsr =
#endif
- lsr = bus_io_read_1(bc, ioh, com_lsr);
+ lsr = bus_space_read_1(iot, ioh, com_lsr);
} while (ISSET(lsr, LSR_RXRDY));
sc->sc_ibufp = p;
#ifdef COM_DEBUG
iter[n].msr =
#endif
- msr = bus_io_read_1(bc, ioh, com_msr);
+ msr = bus_space_read_1(iot, ioh, com_msr);
if (msr != sc->sc_msr) {
delta = msr ^ sc->sc_msr;
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) &&
(*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
if (ISSET(delta & msr, MSR_CTS) &&
ISSET(tp->t_cflag, CRTSCTS)) {
#ifdef COM_DEBUG
if (++n >= 32)
goto ohfudge;
- if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(iter[n].iir = bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (1);
#else
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (1);
#endif
}
struct consdev *cp;
{
/* XXX NEEDS TO BE FIXED XXX */
- bus_chipset_tag_t bc = 0;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = 0;
+ bus_space_handle_t ioh;
int found;
+#if NCOM_PICA
+ /* XXX */
+#include <arc/arc/arctype.h>
+ extern int cputype;
+
+ if(cputype != ACER_PICA_61)
+ return;
+#endif
- if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, CONADDR, COM_NPORTS, 0, &ioh)) {
cp->cn_pri = CN_DEAD;
return;
}
- found = comprobe1(bc, ioh, CONADDR);
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ found = comprobe1(iot, ioh, CONADDR);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
if (!found) {
cp->cn_pri = CN_DEAD;
return;
#if 0
XXX NEEDS TO BE FIXED XXX
- comconsbc = ???;
+ comconsiot = ???;
#endif
- if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh))
+ if (bus_space_map(comconsiot, CONADDR, COM_NPORTS, 0, &comconsioh))
panic("comcninit: mapping failed");
- cominit(comconsbc, comconsioh, comdefaultrate);
+ cominit(comconsiot, comconsioh, comdefaultrate);
comconsaddr = CONADDR;
comconsinit = 0;
}
void
-cominit(bc, ioh, rate)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+cominit(iot, ioh, rate)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int rate;
{
int s = splhigh();
u_char stat;
- bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB);
+ bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB);
rate = comspeed(comdefaultrate);
- bus_io_write_1(bc, ioh, com_dlbl, rate);
- bus_io_write_1(bc, ioh, com_dlbh, rate >> 8);
- bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS);
- bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
- stat = bus_io_read_1(bc, ioh, com_iir);
+ bus_space_write_1(iot, ioh, com_dlbl, rate);
+ bus_space_write_1(iot, ioh, com_dlbh, rate >> 8);
+ bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS);
+ bus_space_write_1(iot, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
+ bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
}
dev_t dev;
{
int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
+ bus_space_tag_t iot = comconsiot;
+ bus_space_handle_t ioh = comconsioh;
u_char stat, c;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY))
;
- c = bus_io_read_1(bc, ioh, com_data);
- stat = bus_io_read_1(bc, ioh, com_iir);
+ c = bus_space_read_1(iot, ioh, com_data);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
return c;
}
int c;
{
int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
+ bus_space_tag_t iot = comconsiot;
+ bus_space_handle_t ioh = comconsioh;
u_char stat;
register int timo;
if (dev != kgdb_dev)
#endif
if (comconsinit == 0) {
- cominit(bc, ioh, comdefaultrate);
+ cominit(iot, ioh, comdefaultrate);
comconsinit = 1;
}
/* wait for any pending transmission to finish */
timo = 50000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo)
;
- bus_io_write_1(bc, ioh, com_data, c);
+ bus_space_write_1(iot, ioh, com_data, c);
/* wait for this transmission to complete */
timo = 1500000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo)
;
/* clear any interrupts generated by this transmission */
- stat = bus_io_read_1(bc, ioh, com_iir);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
}
-/* $OpenBSD: comvar.h,v 1.4 1996/10/30 15:01:50 niklas Exp $ */
+/* $OpenBSD: comvar.h,v 1.5 1996/11/29 22:54:52 niklas Exp $ */
/* $NetBSD: comvar.h,v 1.5 1996/05/05 19:50:47 christos Exp $ */
/*
struct commulti_attach_args {
int ca_slave; /* slave number */
- bus_chipset_tag_t ca_bc;
- bus_io_handle_t ca_ioh;
+ bus_space_tag_t ca_iot;
+ bus_space_handle_t ca_ioh;
int ca_iobase;
int ca_noien;
};
-int comprobe1 __P((bus_chipset_tag_t, bus_io_handle_t, int));
-void cominit __P((bus_chipset_tag_t, bus_io_handle_t, int));
+int comprobe1 __P((bus_space_tag_t, bus_space_handle_t, int));
+void cominit __P((bus_space_tag_t, bus_space_handle_t, int));
int comintr __P((void *));
extern int comconsaddr;
extern int comconsattached;
-extern bus_chipset_tag_t comconsbc;
-extern bus_io_handle_t comconsioh;
+extern bus_space_tag_t comconsiot;
+extern bus_space_handle_t comconsioh;
extern tcflag_t comconscflag;
-/* $OpenBSD: ast.c,v 1.14 1996/11/23 21:46:37 kstailey Exp $ */
+/* $OpenBSD: ast.c,v 1.15 1996/11/29 22:54:50 niklas Exp $ */
/* $NetBSD: ast.c,v 1.28 1996/05/12 23:51:45 mycroft Exp $ */
/*
#include <sys/device.h>
#include <sys/termios.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
int sc_iobase;
int sc_alive; /* mask of slave units attached */
void *sc_slaves[NSLAVES]; /* com device unit numbers */
- bus_io_handle_t sc_slaveioh[NSLAVES];
+ bus_space_handle_t sc_slaveioh[NSLAVES];
};
int astprobe __P((struct device *, void *, void *));
{
struct isa_attach_args *ia = aux;
int iobase = ia->ia_iobase;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int i, rv = 1;
/*
if (iobase == comconsaddr && !comconsattached)
goto checkmappings;
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- rv = comprobe1(bc, ioh, iobase);
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ rv = comprobe1(iot, ioh, iobase);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
if (rv == 0)
goto out;
if (iobase == comconsaddr && !comconsattached)
continue;
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
}
out:
struct commulti_attach_args ca;
int i;
- sc->sc_bc = ia->ia_bc;
+ sc->sc_iot = ia->ia_iot;
sc->sc_iobase = ia->ia_iobase;
for (i = 0; i < NSLAVES; i++)
- if (bus_io_map(sc->sc_bc, sc->sc_iobase + i * COM_NPORTS,
- COM_NPORTS, &sc->sc_slaveioh[i]))
+ if (bus_space_map(sc->sc_iot, sc->sc_iobase + i * COM_NPORTS,
+ COM_NPORTS, 0, &sc->sc_slaveioh[i]))
panic("astattach: couldn't map slave %d", i);
/*
* Enable the master interrupt.
*/
- bus_io_write_1(sc->sc_bc, sc->sc_slaveioh[3], 7, 0x80);
+ bus_space_write_1(sc->sc_iot, sc->sc_slaveioh[3], 7, 0x80);
printf("\n");
for (i = 0; i < NSLAVES; i++) {
ca.ca_slave = i;
- ca.ca_bc = sc->sc_bc;
+ ca.ca_iot = sc->sc_iot;
ca.ca_ioh = sc->sc_slaveioh[i];
ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
ca.ca_noien = 1;
void *arg;
{
struct ast_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
+ bus_space_tag_t iot = sc->sc_iot;
int alive = sc->sc_alive;
int bits;
- bits = ~bus_io_read_1(bc, sc->sc_slaveioh[3], 7) & alive;
+ bits = ~bus_space_read_1(iot, sc->sc_slaveioh[3], 7) & alive;
if (bits == 0)
return (0);
TRY(2);
TRY(3);
#undef TRY
- bits = ~bus_io_read_1(bc, sc->sc_slaveioh[3], 7) & alive;
+ bits = ~bus_space_read_1(iot, sc->sc_slaveioh[3], 7) & alive;
if (bits == 0)
return (1);
}
-/* $OpenBSD: boca.c,v 1.12 1996/11/23 21:46:38 kstailey Exp $ */
+/* $OpenBSD: boca.c,v 1.13 1996/11/29 22:54:51 niklas Exp $ */
/* $NetBSD: boca.c,v 1.15 1996/05/12 23:51:50 mycroft Exp $ */
/*
#include <sys/device.h>
#include <sys/termios.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
int sc_iobase;
int sc_alive; /* mask of slave units attached */
void *sc_slaves[NSLAVES]; /* com device unit numbers */
- bus_io_handle_t sc_slaveioh[NSLAVES];
+ bus_space_handle_t sc_slaveioh[NSLAVES];
};
int bocaprobe __P((struct device *, void *, void *));
{
struct isa_attach_args *ia = aux;
int iobase = ia->ia_iobase;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int i, rv = 1;
/*
if (iobase == comconsaddr && !comconsattached)
goto checkmappings;
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- rv = comprobe1(bc, ioh, iobase);
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ rv = comprobe1(iot, ioh, iobase);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
if (rv == 0)
goto out;
if (iobase == comconsaddr && !comconsattached)
continue;
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
}
out:
struct boca_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
struct commulti_attach_args ca;
- bus_chipset_tag_t bc = ia->ia_bc;
+ bus_space_tag_t iot = ia->ia_iot;
int i;
- sc->sc_bc = ia->ia_bc;
+ sc->sc_iot = ia->ia_iot;
sc->sc_iobase = ia->ia_iobase;
for (i = 0; i < NSLAVES; i++)
- if (bus_io_map(bc, sc->sc_iobase + i * COM_NPORTS, COM_NPORTS,
- &sc->sc_slaveioh[i]))
+ if (bus_space_map(iot, sc->sc_iobase + i * COM_NPORTS,
+ COM_NPORTS, 0, &sc->sc_slaveioh[i]))
panic("bocaattach: couldn't map slave %d", i);
printf("\n");
for (i = 0; i < NSLAVES; i++) {
ca.ca_slave = i;
- ca.ca_bc = sc->sc_bc;
+ ca.ca_iot = sc->sc_iot;
ca.ca_ioh = sc->sc_slaveioh[i];
ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
ca.ca_noien = 0;
void *arg;
{
struct boca_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
+ bus_space_tag_t iot = sc->sc_iot;
int alive = sc->sc_alive;
int bits;
- bits = bus_io_read_1(bc, sc->sc_slaveioh[0], 7) & alive;
+ bits = bus_space_read_1(iot, sc->sc_slaveioh[0], 7) & alive;
if (bits == 0)
return (0);
TRY(6);
TRY(7);
#undef TRY
- bits = bus_io_read_1(bc, sc->sc_slaveioh[0], 7) & alive;
+ bits = bus_space_read_1(iot, sc->sc_slaveioh[0], 7) & alive;
if (bits == 0)
return (1);
}
-/* $OpenBSD: com.c,v 1.27 1996/11/12 20:30:27 niklas Exp $ */
+/* $OpenBSD: com.c,v 1.28 1996/11/29 22:54:52 niklas Exp $ */
/* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */
/*-
#include <sys/types.h>
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
struct com_softc {
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
struct tty *sc_tty;
int sc_overflows;
int sc_hayespbase;
#endif
- bus_io_handle_t sc_ioh;
- bus_io_handle_t sc_hayespioh;
+ bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_hayespioh;
+ isa_chipset_tag_t sc_ic;
u_char sc_hwflags;
#define COM_HW_NOIEN 0x01
};
#ifdef COM_HAYESP
-int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc));
+int comprobeHAYESP __P((bus_space_handle_t hayespioh, struct com_softc *sc));
#endif
void comdiag __P((void *));
int comspeed __P((long));
};
#endif
+#if NCOM_PICA
+#undef CONADDR /* This is stupid but using devs before config .. */
+#define CONADDR 0xe0006000
+
+struct cfattach com_pica_ca = {
+ sizeof(struct com_softc), comprobe, comattach
+};
+#endif
+
struct cfdriver com_cd = {
NULL, "com", DV_TTY
};
int comconsaddr;
int comconsinit;
int comconsattached;
-bus_chipset_tag_t comconsbc;
-bus_io_handle_t comconsioh;
+bus_space_tag_t comconsiot;
+bus_space_handle_t comconsioh;
tcflag_t comconscflag = TTYDEF_CFLAG;
int commajor;
(sc->sc_hwflags & (COM_HW_ABSENT_PENDING|COM_HW_CONSOLE));
} else
sc->sc_hwflags = 0;
+ sc->sc_ic = ia->ia_ic;
}
return rval;
}
ttyfree(sc->sc_tty);
sc->sc_tty = NULL;
ok:
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
+ isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
sc->sc_ih = NULL;
SET(sc->sc_hwflags, COM_HW_ABSENT);
return 0; /* OK! */
}
int
-comprobe1(bc, ioh, iobase)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+comprobe1(iot, ioh, iobase)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int iobase;
{
int i, k;
/* force access to id reg */
- bus_io_write_1(bc, ioh, com_lcr, 0);
- bus_io_write_1(bc, ioh, com_iir, 0);
+ bus_space_write_1(iot, ioh, com_lcr, 0);
+ bus_space_write_1(iot, ioh, com_iir, 0);
for (i = 0; i < 32; i++) {
- k = bus_io_read_1(bc, ioh, com_iir);
+ k = bus_space_read_1(iot, ioh, com_iir);
if (k & 0x38) {
- bus_io_read_1(bc, ioh, com_data); /* cleanup */
+ bus_space_read_1(iot, ioh, com_data); /* cleanup */
} else
break;
}
#ifdef COM_HAYESP
int
comprobeHAYESP(hayespioh, sc)
- bus_io_handle_t hayespioh;
+ bus_space_handle_t hayespioh;
struct com_softc *sc;
{
char val, dips;
int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
- bus_chipset_tag_t bc = sc->sc_bc;
+ bus_space_tag_t iot = sc->sc_iot;
/*
* Hayes ESP cards have two iobases. One is for compatibility with
*/
/* Test for ESP signature */
- if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0)
+ if ((bus_space_read_1(iot, hayespioh, 0) & 0xf3) == 0)
return 0;
/*
*/
/* Get the dip-switch configurations */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
- dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
+ dips = bus_space_read_1(iot, hayespioh, HAYESP_STATUS1);
/* Determine which com port this ESP card services: bits 0,1 of */
/* dips is the port # (0-3); combaselist[val] is the com_iobase */
/* Check ESP Self Test bits. */
/* Check for ESP version 2.0: bits 4,5,6 == 010 */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
- val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
+ val = bus_space_read_1(iot, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
+ val = bus_space_read_1(iot, hayespioh, HAYESP_STATUS2);
if ((val & 0x70) < 0x20) {
printf("-old (%o)", val & 0x70);
/* we do not support the necessary features */
struct device *parent;
void *match, *aux;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int iobase, needioh;
int rv = 1;
#elif NCOM_ISA
#define IS_ISA(parent) \
!strcmp((parent)->dv_cfdata->cf_driver->cd_name, "isa")
+#endif
+#if NCOM_PICA
+#define IS_PICA(parent) \
+ !strcmp((parent)->dv_cfdata->cf_driver->cd_name, "pica")
#endif
/*
* XXX should be broken out into functions for isa probe and
if (IS_ISA(parent)) {
struct isa_attach_args *ia = aux;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
iobase = ia->ia_iobase;
needioh = 1;
} else
if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave)
return (0);
- bc = ca->ca_bc;
+ iot = ca->ca_iot;
iobase = ca->ca_iobase;
ioh = ca->ca_ioh;
needioh = 0;
} else
+#endif
+#if NCOM_PICA
+ if(IS_PICA(parent)) {
+ struct confargs *ca = aux;
+ if(!BUS_MATCHNAME(ca, "com"))
+ return(0);
+ iobase = (long)BUS_CVTADDR(ca);
+ iot = 0;
+ needioh = 1;
+ } else
#endif
return(0); /* This cannot happen */
if (iobase == comconsaddr && !comconsattached)
goto out;
- if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (needioh && bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- rv = comprobe1(bc, ioh, iobase);
+ rv = comprobe1(iot, ioh, iobase);
if (needioh)
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
out:
#if NCOM_ISA || NCOM_PCMCIA
{
struct com_softc *sc = (void *)self;
int iobase, irq;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
#ifdef COM_HAYESP
int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
int *hayespp;
* We're living on an isa.
*/
iobase = ia->ia_iobase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
if (iobase != comconsaddr) {
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh))
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh))
panic("comattach: io mapping failed");
} else
ioh = comconsioh;
* We're living on a commulti.
*/
iobase = ca->ca_iobase;
- bc = ca->ca_bc;
+ iot = ca->ca_iot;
ioh = ca->ca_ioh;
irq = IRQUNK;
if (ca->ca_noien)
SET(sc->sc_hwflags, COM_HW_NOIEN);
} else
+#endif
+#if NCOM_PICA
+ if(IS_PICA(parent)) {
+ struct confargs *ca = aux;
+ iobase = (long)BUS_CVTADDR(ca);
+ iot = 0;
+ irq = 0;
+ ioh = iobase;
+ } else
#endif
panic("comattach: impossible");
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->sc_iobase = iobase;
#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
- bus_io_handle_t hayespioh;
+ bus_space_handle_t hayespioh;
#define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */
- if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh))
+ if (bus_space_map(iot, *hayespp, HAYESP_NPORTS, 0, &hayespioh))
continue;
if (comprobeHAYESP(hayespioh, sc)) {
sc->sc_hayespbase = *hayespp;
sc->sc_hayespioh = hayespioh;
break;
}
- bus_io_unmap(bc, hayespioh, HAYESP_NPORTS);
+ bus_space_unmap(iot, hayespioh, HAYESP_NPORTS);
}
/* No ESP; look for other things. */
if (*hayespp == 0) {
#endif
/* look for a NS 16550AF UART with FIFOs */
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
delay(100);
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) ==
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_FIFO_MASK) ==
IIR_FIFO_MASK)
- if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) ==
+ if (ISSET(bus_space_read_1(iot, ioh, com_fifo), FIFO_TRIGGER_14) ==
FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
printf(": ns16550a, working fifo\n");
printf(": ns16550, broken fifo\n");
else
printf(": ns8250 or ns16450, no fifo\n");
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
#ifdef COM_HAYESP
}
#endif
/* disable interrupts */
- bus_io_write_1(bc, ioh, com_ier, 0);
- bus_io_write_1(bc, ioh, com_mcr, 0);
+ bus_space_write_1(iot, ioh, com_ier, 0);
+ bus_space_write_1(iot, ioh, com_mcr, 0);
if (irq != IRQUNK) {
#if NCOM_ISA || NCOM_PCMCIA
IST_EDGE, IPL_TTY, comintr, sc,
sc->sc_dev.dv_xname);
} else
+#endif
+#if NCOM_PICA
+ if (IS_PICA(parent)) {
+ struct confargs *ca = aux;
+ BUS_INTR_ESTABLISH(ca, comintr, (void *)(long)sc);
+ } else
#endif
panic("comattach: IRQ but can't have one");
}
if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
kgdb_dev = -1; /* can't debug over console port */
else {
- cominit(bc, ioh, kgdb_rate);
+ cominit(iot, ioh, kgdb_rate);
if (kgdb_debug_init) {
/*
* Print prefix of device name,
{
int unit = DEVUNIT(dev);
struct com_softc *sc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct tty *tp;
int s;
int error = 0;
sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER;
sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
- bc = sc->sc_bc;
+ iot = sc->sc_iot;
ioh = sc->sc_ioh;
#ifdef COM_HAYESP
/* Setup the ESP board */
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- bus_io_handle_t hayespioh = sc->sc_hayespioh;
+ bus_space_handle_t hayespioh = sc->sc_hayespioh;
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_DMA_MODE|FIFO_ENABLE|
FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
/* Set 16550 compatibility mode */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
HAYESP_MODE_SCALE);
/* Set RTS/CTS flow control */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
/* Set flow control levels */
- bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXHIWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXLOWMARK));
- bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
+ bus_space_write_1(iot, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
} else
#endif
* Set the FIFO threshold based on the receive speed.
*/
for (;;) {
- bus_io_write_1(bc, ioh, com_fifo, 0);
+ bus_space_write_1(iot, ioh, com_fifo, 0);
delay(100);
- (void) bus_io_read_1(bc, ioh, com_data);
- bus_io_write_1(bc, ioh, com_fifo,
+ (void) bus_space_read_1(iot, ioh, com_data);
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
(tp->t_ispeed <= 1200 ?
FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
delay(100);
- if(!ISSET(bus_io_read_1(bc, ioh,
+ if(!ISSET(bus_space_read_1(iot, ioh,
com_lsr), LSR_RXRDY))
break;
}
}
/* flush any pending I/O */
- while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
- (void) bus_io_read_1(bc, ioh, com_data);
+ while (ISSET(bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY))
+ (void) bus_space_read_1(iot, ioh, com_data);
/* you turn me on, baby */
sc->sc_mcr = MCR_DTR | MCR_RTS;
if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
SET(sc->sc_mcr, MCR_IENABLE);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
- sc->sc_msr = bus_io_read_1(bc, ioh, com_msr);
+ sc->sc_msr = bus_space_read_1(iot, ioh, com_msr);
if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) ||
ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF))
SET(tp->t_state, TS_CARR_ON);
int unit = DEVUNIT(dev);
struct com_softc *sc = com_cd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s;
/* XXX This is for cons.c. */
if (!ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
/* can't do any of this stuff .... */
CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
- bus_io_write_1(bc, ioh, com_ier, 0);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_ier, 0);
if (ISSET(tp->t_cflag, HUPCL) &&
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) {
/* XXX perhaps only clear DTR */
- bus_io_write_1(bc, ioh, com_mcr, 0);
+ bus_space_write_1(iot, ioh, com_mcr, 0);
}
}
CLR(tp->t_state, TS_BUSY | TS_FLUSH);
int unit = DEVUNIT(dev);
struct com_softc *sc = com_cd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int error;
if (ISSET(sc->sc_hwflags, COM_HW_ABSENT|COM_HW_ABSENT_PENDING)) {
switch (cmd) {
case TIOCSBRK:
SET(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCCBRK:
CLR(sc->sc_lcr, LCR_SBREAK);
- bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCSDTR:
SET(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCCDTR:
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMSET:
CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
case TIOCMBIS:
SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMBIC:
CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMGET: {
u_char m;
SET(bits, TIOCM_DSR);
if (ISSET(m, MSR_RI | MSR_TERI))
SET(bits, TIOCM_RI);
- if (bus_io_read_1(bc, ioh, com_ier))
+ if (bus_space_read_1(iot, ioh, com_ier))
SET(bits, TIOCM_LE);
*(int *)data = bits;
break;
struct termios *t;
{
struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int ospeed = comspeed(t->c_ospeed);
u_char lcr;
tcflag_t oldcflag;
if (ospeed == 0) {
CLR(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
/*
}
}
- bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB);
- bus_io_write_1(bc, ioh, com_dlbl, ospeed);
- bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8);
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr | LCR_DLAB);
+ bus_space_write_1(iot, ioh, com_dlbl, ospeed);
+ bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
SET(sc->sc_mcr, MCR_DTR);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
} else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) &&
ISSET(sc->sc_hwflags, COM_HW_FIFO))
- bus_io_write_1(bc, ioh, com_fifo,
+ bus_space_write_1(iot, ioh, com_fifo,
FIFO_ENABLE |
(t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
} else
- bus_io_write_1(bc, ioh, com_lcr, lcr);
+ bus_space_write_1(iot, ioh, com_lcr, lcr);
/* When not using CRTSCTS, RTS follows DTR. */
if (!ISSET(t->c_cflag, CRTSCTS)) {
if (ISSET(sc->sc_mcr, MCR_DTR)) {
if (!ISSET(sc->sc_mcr, MCR_RTS)) {
SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
} else {
if (ISSET(sc->sc_mcr, MCR_RTS)) {
CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
}
sc->sc_dtr = MCR_DTR | MCR_RTS;
ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
/* Just to be sure... */
struct tty *tp;
{
struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int s;
s = spltty();
if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
SET(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
}
#ifdef COM_HAYESP
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
u_char buffer[1024], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do
- bus_io_write_1(bc, ioh, com_data, *cp++);
+ bus_space_write_1(iot, ioh, com_data, *cp++);
while (--n);
}
else
u_char buffer[16], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do {
- bus_io_write_1(bc, ioh, com_data, *cp++);
+ bus_space_write_1(iot, ioh, com_data, *cp++);
} while (--n);
} else
- bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq));
+ bus_space_write_1(iot, ioh, com_data, getc(&tp->t_outq));
out:
splx(s);
return;
stopped:
if (ISSET(sc->sc_ier, IER_ETXRDY)) {
CLR(sc->sc_ier, IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
}
splx(s);
}
!ISSET(sc->sc_mcr, MCR_RTS)) {
/* XXX */
SET(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr,
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_mcr,
sc->sc_mcr);
}
void *arg;
{
struct com_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct tty *tp;
u_char lsr, data, msr, delta;
#ifdef COM_DEBUG
#ifdef COM_DEBUG
n = 0;
- if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(iter[n].iir = bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (0);
#else
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (0);
#endif
#ifdef COM_DEBUG
iter[n].lsr =
#endif
- lsr = bus_io_read_1(bc, ioh, com_lsr);
+ lsr = bus_space_read_1(iot, ioh, com_lsr);
if (ISSET(lsr, LSR_RXRDY)) {
register u_char *p = sc->sc_ibufp;
comevents = 1;
do {
- data = bus_io_read_1(bc, ioh, com_data);
+ data = bus_space_read_1(iot, ioh, com_data);
if (ISSET(lsr, LSR_BI)) {
#ifdef notdef
printf("break %02x %02x %02x %02x\n",
ISSET(tp->t_cflag, CRTSCTS)) {
/* XXX */
CLR(sc->sc_mcr, MCR_RTS);
- bus_io_write_1(bc, ioh, com_mcr,
+ bus_space_write_1(iot, ioh, com_mcr,
sc->sc_mcr);
}
}
goto ohfudge;
iter[n].lsr =
#endif
- lsr = bus_io_read_1(bc, ioh, com_lsr);
+ lsr = bus_space_read_1(iot, ioh, com_lsr);
} while (ISSET(lsr, LSR_RXRDY));
sc->sc_ibufp = p;
#ifdef COM_DEBUG
iter[n].msr =
#endif
- msr = bus_io_read_1(bc, ioh, com_msr);
+ msr = bus_space_read_1(iot, ioh, com_msr);
if (msr != sc->sc_msr) {
delta = msr ^ sc->sc_msr;
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) &&
(*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ bus_space_write_1(iot, ioh, com_mcr, sc->sc_mcr);
}
if (ISSET(delta & msr, MSR_CTS) &&
ISSET(tp->t_cflag, CRTSCTS)) {
#ifdef COM_DEBUG
if (++n >= 32)
goto ohfudge;
- if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(iter[n].iir = bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (1);
#else
- if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ if (ISSET(bus_space_read_1(iot, ioh, com_iir), IIR_NOPEND))
return (1);
#endif
}
struct consdev *cp;
{
/* XXX NEEDS TO BE FIXED XXX */
- bus_chipset_tag_t bc = 0;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = 0;
+ bus_space_handle_t ioh;
int found;
+#if NCOM_PICA
+ /* XXX */
+#include <arc/arc/arctype.h>
+ extern int cputype;
+
+ if(cputype != ACER_PICA_61)
+ return;
+#endif
- if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, CONADDR, COM_NPORTS, 0, &ioh)) {
cp->cn_pri = CN_DEAD;
return;
}
- found = comprobe1(bc, ioh, CONADDR);
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ found = comprobe1(iot, ioh, CONADDR);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
if (!found) {
cp->cn_pri = CN_DEAD;
return;
#if 0
XXX NEEDS TO BE FIXED XXX
- comconsbc = ???;
+ comconsiot = ???;
#endif
- if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh))
+ if (bus_space_map(comconsiot, CONADDR, COM_NPORTS, 0, &comconsioh))
panic("comcninit: mapping failed");
- cominit(comconsbc, comconsioh, comdefaultrate);
+ cominit(comconsiot, comconsioh, comdefaultrate);
comconsaddr = CONADDR;
comconsinit = 0;
}
void
-cominit(bc, ioh, rate)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+cominit(iot, ioh, rate)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int rate;
{
int s = splhigh();
u_char stat;
- bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB);
+ bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB);
rate = comspeed(comdefaultrate);
- bus_io_write_1(bc, ioh, com_dlbl, rate);
- bus_io_write_1(bc, ioh, com_dlbh, rate >> 8);
- bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS);
- bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
- bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
- stat = bus_io_read_1(bc, ioh, com_iir);
+ bus_space_write_1(iot, ioh, com_dlbl, rate);
+ bus_space_write_1(iot, ioh, com_dlbh, rate >> 8);
+ bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS);
+ bus_space_write_1(iot, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
+ bus_space_write_1(iot, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
}
dev_t dev;
{
int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
+ bus_space_tag_t iot = comconsiot;
+ bus_space_handle_t ioh = comconsioh;
u_char stat, c;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_RXRDY))
;
- c = bus_io_read_1(bc, ioh, com_data);
- stat = bus_io_read_1(bc, ioh, com_iir);
+ c = bus_space_read_1(iot, ioh, com_data);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
return c;
}
int c;
{
int s = splhigh();
- bus_chipset_tag_t bc = comconsbc;
- bus_io_handle_t ioh = comconsioh;
+ bus_space_tag_t iot = comconsiot;
+ bus_space_handle_t ioh = comconsioh;
u_char stat;
register int timo;
if (dev != kgdb_dev)
#endif
if (comconsinit == 0) {
- cominit(bc, ioh, comdefaultrate);
+ cominit(iot, ioh, comdefaultrate);
comconsinit = 1;
}
/* wait for any pending transmission to finish */
timo = 50000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo)
;
- bus_io_write_1(bc, ioh, com_data, c);
+ bus_space_write_1(iot, ioh, com_data, c);
/* wait for this transmission to complete */
timo = 1500000;
- while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_space_read_1(iot, ioh, com_lsr), LSR_TXRDY) && --timo)
;
/* clear any interrupts generated by this transmission */
- stat = bus_io_read_1(bc, ioh, com_iir);
+ stat = bus_space_read_1(iot, ioh, com_iir);
splx(s);
}
-/* $OpenBSD: comvar.h,v 1.4 1996/10/30 15:01:50 niklas Exp $ */
+/* $OpenBSD: comvar.h,v 1.5 1996/11/29 22:54:52 niklas Exp $ */
/* $NetBSD: comvar.h,v 1.5 1996/05/05 19:50:47 christos Exp $ */
/*
struct commulti_attach_args {
int ca_slave; /* slave number */
- bus_chipset_tag_t ca_bc;
- bus_io_handle_t ca_ioh;
+ bus_space_tag_t ca_iot;
+ bus_space_handle_t ca_ioh;
int ca_iobase;
int ca_noien;
};
-int comprobe1 __P((bus_chipset_tag_t, bus_io_handle_t, int));
-void cominit __P((bus_chipset_tag_t, bus_io_handle_t, int));
+int comprobe1 __P((bus_space_tag_t, bus_space_handle_t, int));
+void cominit __P((bus_space_tag_t, bus_space_handle_t, int));
int comintr __P((void *));
extern int comconsaddr;
extern int comconsattached;
-extern bus_chipset_tag_t comconsbc;
-extern bus_io_handle_t comconsioh;
+extern bus_space_tag_t comconsiot;
+extern bus_space_handle_t comconsioh;
extern tcflag_t comconscflag;
-/* $OpenBSD: cy_isa.c,v 1.2 1996/11/12 20:30:28 niklas Exp $ */
+/* $OpenBSD: cy_isa.c,v 1.3 1996/11/29 22:54:53 niklas Exp $ */
/*
* cy.c
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/systm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/isa/isareg.h>
#include <dev/ic/cyreg.h>
int cy_probe_isa __P((struct device *, void *, void *));
-int cy_probe_common __P((int card, bus_chipset_tag_t,
- bus_mem_handle_t, int bustype));
+int cy_probe_common __P((int card, bus_space_tag_t,
+ bus_space_handle_t, int bustype));
void cyattach __P((struct device *, struct device *, void *));
{
int card = ((struct device *)match)->dv_unit;
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc;
- bus_mem_handle_t memh;
+ bus_space_tag_t memt;
+ bus_space_handle_t memh;
if(ia->ia_irq == IRQUNK) {
printf("cy%d error: interrupt not defined\n", card);
return 0;
}
- bc = ia->ia_bc;
- if(bus_mem_map(bc, ia->ia_maddr, 0x2000, 0, &memh) != 0)
+ memt = ia->ia_memt;
+ if(bus_space_map(memt, ia->ia_maddr, 0x2000, 0, &memh) != 0)
return 0;
- if(cy_probe_common(card, bc, memh, CY_BUSTYPE_ISA) == 0) {
- bus_mem_unmap(bc, memh, 0x2000);
+ if(cy_probe_common(card, memt, memh, CY_BUSTYPE_ISA) == 0) {
+ bus_space_unmap(memt, memh, 0x2000);
return 0;
}
#include <sys/malloc.h>
#include <sys/queue.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/elink.h>
* NOTE: the caller MUST provide an i/o handle for ELINK_ID_PORT!
*/
void
-elink_reset(bc, ioh, bus)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+elink_reset(iot, ioh, bus)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int bus;
{
struct elink_done_reset *er;
LIST_INSERT_HEAD(&elink_all_resets, er, er_link);
/* Haven't reset the cards on this bus, yet. */
- bus_io_write_1(bc, ioh, 0, ELINK_RESET);
+ bus_space_write_1(iot, ioh, 0, ELINK_RESET);
out:
- bus_io_write_1(bc, ioh, 0, 0x00);
- bus_io_write_1(bc, ioh, 0, 0x00);
+ bus_space_write_1(iot, ioh, 0, 0x00);
+ bus_space_write_1(iot, ioh, 0, 0x00);
}
/*
* NOTE: the caller MUST provide an i/o handle for ELINK_ID_PORT!
*/
void
-elink_idseq(bc, ioh, p)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+elink_idseq(iot, ioh, p)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
register u_char p;
{
register int i;
c = 0xff;
for (i = 255; i; i--) {
- bus_io_write_1(bc, ioh, 0, c);
+ bus_space_write_1(iot, ioh, 0, c);
if (c & 0x80) {
c <<= 1;
c ^= p;
#define ELINK_507_POLY 0xe7
#define ELINK_509_POLY 0xcf
-void elink_reset __P((bus_chipset_tag_t, bus_io_handle_t, int));
-void elink_idseq __P((bus_chipset_tag_t, bus_io_handle_t, u_char p));
+void elink_reset __P((bus_space_tag_t, bus_space_handle_t, int));
+void elink_idseq __P((bus_space_tag_t, bus_space_handle_t, u_char p));
-/* $OpenBSD: fd.c,v 1.28 1996/11/12 20:30:31 niklas Exp $ */
+/* $OpenBSD: fd.c,v 1.29 1996/11/29 22:54:55 niklas Exp $ */
/* $NetBSD: fd.c,v 1.90 1996/05/12 23:12:03 mycroft Exp $ */
/*-
#include <sys/queue.h>
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/conf.h>
#include <machine/intr.h>
#include <machine/ioctl_fd.h>
struct cfdata *cf = match;
struct fdc_attach_args *fa = aux;
int drive = fa->fa_drive;
- bus_chipset_tag_t bc = fdc->sc_bc;
- bus_io_handle_t ioh = fdc->sc_ioh;
+ bus_space_tag_t iot = fdc->sc_iot;
+ bus_space_handle_t ioh = fdc->sc_ioh;
int n;
if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != drive)
fa->fa_flags = cf->cf_flags;
/* select drive and turn on motor */
- bus_io_write_1(bc, ioh, fdout, drive | FDO_FRST | FDO_MOEN(drive));
+ bus_space_write_1(iot, ioh, fdout, drive | FDO_FRST | FDO_MOEN(drive));
/* wait for motor to spin up */
delay(250000);
- out_fdc(bc, ioh, NE7CMD_RECAL);
- out_fdc(bc, ioh, drive);
+ out_fdc(iot, ioh, NE7CMD_RECAL);
+ out_fdc(iot, ioh, drive);
/* wait for recalibrate */
delay(2000000);
- out_fdc(bc, ioh, NE7CMD_SENSEI);
+ out_fdc(iot, ioh, NE7CMD_SENSEI);
n = fdcresult(fdc);
#ifdef FD_DEBUG
{
if (n != 2 || (fdc->sc_status[0] & 0xf8) != 0x20)
return 0;
/* turn off motor */
- bus_io_write_1(bc, ioh, fdout, FDO_FRST);
+ bus_space_write_1(iot, ioh, fdout, FDO_FRST);
return 1;
}
if ((fd = fdc->sc_link.fdlink.sc_fd[n])
&& (fd->sc_flags & FD_MOTOR))
status |= FDO_MOEN(n);
- bus_io_write_1(fdc->sc_bc, fdc->sc_ioh, fdout, status);
+ bus_space_write_1(fdc->sc_iot, fdc->sc_ioh, fdout, status);
}
void
#define cyl fdc->sc_status[1]
struct fd_softc *fd;
struct buf *bp;
- bus_chipset_tag_t bc = fdc->sc_bc;
- bus_io_handle_t ioh = fdc->sc_ioh;
+ bus_space_tag_t iot = fdc->sc_iot;
+ bus_space_handle_t ioh = fdc->sc_ioh;
int read, head, sec, i, nblks;
struct fd_type *type;
struct fd_formb *finfo = NULL;
if (fd->sc_cylin == bp->b_cylin)
goto doio;
- out_fdc(bc, ioh, NE7CMD_SPECIFY);/* specify command */
- out_fdc(bc, ioh, fd->sc_type->steprate);
- out_fdc(bc, ioh, 6); /* XXX head load time == 6ms */
+ out_fdc(iot, ioh, NE7CMD_SPECIFY);/* specify command */
+ out_fdc(iot, ioh, fd->sc_type->steprate);
+ out_fdc(iot, ioh, 6); /* XXX head load time == 6ms */
- out_fdc(bc, ioh, NE7CMD_SEEK); /* seek function */
- out_fdc(bc, ioh, fd->sc_drive); /* drive number */
- out_fdc(bc, ioh, bp->b_cylin * fd->sc_type->step);
+ out_fdc(iot, ioh, NE7CMD_SEEK); /* seek function */
+ out_fdc(iot, ioh, fd->sc_drive); /* drive number */
+ out_fdc(iot, ioh, bp->b_cylin * fd->sc_type->step);
fd->sc_cylin = -1;
fdc->sc_state = SEEKWAIT;
isa_dmastart(read, bp->b_data + fd->sc_skip, fd->sc_nbytes,
fdc->sc_drq);
#endif
- bus_io_write_1(bc, ioh, fdctl, type->rate);
+ bus_space_write_1(iot, ioh, fdctl, type->rate);
#ifdef FD_DEBUG
printf("fdintr: %s drive %d track %d head %d sec %d nblks %d\n",
read ? "read" : "write", fd->sc_drive, fd->sc_cylin, head,
#endif
if (finfo) {
/* formatting */
- if (out_fdc(bc, ioh, NE7CMD_FORMAT) < 0) {
+ if (out_fdc(iot, ioh, NE7CMD_FORMAT) < 0) {
fdc->sc_errors = 4;
fdretry(fd);
goto loop;
}
- out_fdc(bc, ioh, (head << 2) | fd->sc_drive);
- out_fdc(bc, ioh, finfo->fd_formb_secshift);
- out_fdc(bc, ioh, finfo->fd_formb_nsecs);
- out_fdc(bc, ioh, finfo->fd_formb_gaplen);
- out_fdc(bc, ioh, finfo->fd_formb_fillbyte);
+ out_fdc(iot, ioh, (head << 2) | fd->sc_drive);
+ out_fdc(iot, ioh, finfo->fd_formb_secshift);
+ out_fdc(iot, ioh, finfo->fd_formb_nsecs);
+ out_fdc(iot, ioh, finfo->fd_formb_gaplen);
+ out_fdc(iot, ioh, finfo->fd_formb_fillbyte);
} else {
if (read)
- out_fdc(bc, ioh, NE7CMD_READ); /* READ */
+ out_fdc(iot, ioh, NE7CMD_READ); /* READ */
else
- out_fdc(bc, ioh, NE7CMD_WRITE); /* WRITE */
- out_fdc(bc, ioh, (head << 2) | fd->sc_drive);
- out_fdc(bc, ioh, fd->sc_cylin); /* track */
- out_fdc(bc, ioh, head);
- out_fdc(bc, ioh, sec + 1); /* sector +1 */
- out_fdc(bc, ioh, type->secsize); /* sector size */
- out_fdc(bc, ioh, type->sectrac); /* sectors/track */
- out_fdc(bc, ioh, type->gap1); /* gap1 size */
- out_fdc(bc, ioh, type->datalen); /* data length */
+ out_fdc(iot, ioh, NE7CMD_WRITE);/* WRITE */
+ out_fdc(iot, ioh, (head << 2) | fd->sc_drive);
+ out_fdc(iot, ioh, fd->sc_cylin); /* track */
+ out_fdc(iot, ioh, head);
+ out_fdc(iot, ioh, sec + 1); /* sec +1 */
+ out_fdc(iot, ioh, type->secsize); /* sec size */
+ out_fdc(iot, ioh, type->sectrac); /* secs/track */
+ out_fdc(iot, ioh, type->gap1); /* gap1 size */
+ out_fdc(iot, ioh, type->datalen); /* data len */
}
fdc->sc_state = IOCOMPLETE;
disk_unbusy(&fd->sc_dk, 0); /* no data on seek */
/* Make sure seek really happened. */
- out_fdc(bc, ioh, NE7CMD_SENSEI);
+ out_fdc(iot, ioh, NE7CMD_SENSEI);
if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 ||
cyl != bp->b_cylin * fd->sc_type->step) {
#ifdef FD_DEBUG
untimeout(fdtimeout, fd);
/* clear the controller output buffer */
for (i = 0; i < 4; i++) {
- out_fdc(bc, ioh, NE7CMD_SENSEI);
+ out_fdc(iot, ioh, NE7CMD_SENSEI);
(void) fdcresult(fdc);
}
/* fall through */
case DORECAL:
- out_fdc(bc, ioh, NE7CMD_RECAL); /* recalibrate function */
- out_fdc(bc, ioh, fd->sc_drive);
+ out_fdc(iot, ioh, NE7CMD_RECAL); /* recal function */
+ out_fdc(iot, ioh, fd->sc_drive);
fdc->sc_state = RECALWAIT;
timeout(fdtimeout, fd, 5 * hz);
return 1; /* will return later */
return 1; /* will return later */
case RECALCOMPLETE:
- out_fdc(bc, ioh, NE7CMD_SENSEI);
+ out_fdc(iot, ioh, NE7CMD_SENSEI);
if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
#ifdef FD_DEBUG
fdcstatus(&fd->sc_dev, 2, "recalibrate failed");
-/* $OpenBSD: fdc.c,v 1.7 1996/11/23 21:46:40 kstailey Exp $ */
+/* $OpenBSD: fdc.c,v 1.8 1996/11/29 22:54:55 niklas Exp $ */
/* $NetBSD: fd.c,v 1.90 1996/05/12 23:12:03 mycroft Exp $ */
/*-
#include <sys/queue.h>
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/conf.h>
#include <machine/intr.h>
#include <machine/ioctl_fd.h>
void *match, *aux;
{
register struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int rv;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
rv = 0;
+#ifdef NEWCONFIG
+ if (ia->ia_iobase == IOBASEUNK || ia->ia_drq == DRQUNK)
+ return 0;
+#endif
+
/* Map the i/o space. */
- if (bus_io_map(bc, ia->ia_iobase, FDC_NPORT, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, FDC_NPORT, 0, &ioh))
return 0;
/* reset */
- bus_io_write_1(bc, ioh, fdout, 0);
+ bus_space_write_1(iot, ioh, fdout, 0);
delay(100);
- bus_io_write_1(bc, ioh, fdout, FDO_FRST);
+ bus_space_write_1(iot, ioh, fdout, FDO_FRST);
/* see if it can handle a command */
- if (out_fdc(bc, ioh, NE7CMD_SPECIFY) < 0)
+ if (out_fdc(iot, ioh, NE7CMD_SPECIFY) < 0)
goto out;
- out_fdc(bc, ioh, 0xdf);
- out_fdc(bc, ioh, 2);
+ out_fdc(iot, ioh, 0xdf);
+ out_fdc(iot, ioh, 2);
#ifdef NEWCONFIG
- if (ia->ia_iobase == IOBASEUNK || ia->ia_drq == DRQUNK)
- return 0;
-
if (ia->ia_irq == IRQUNK) {
ia->ia_irq = isa_discoverintr(fdcforceintr, aux);
if (ia->ia_irq == IRQNONE)
goto out;
/* reset it again */
- bus_io_write_1(bc, ioh, fdout, 0);
+ bus_space_write_1(iot, ioh, fdout, 0);
delay(100);
- bus_io_write_1(bc, ioh, fdout, FDO_FRST);
+ bus_space_write_1(iot, ioh, fdout, FDO_FRST);
}
#endif
ia->ia_msize = 0;
out:
- bus_io_unmap(bc, ioh, FDC_NPORT);
+ bus_space_unmap(iot, ioh, FDC_NPORT);
return rv;
}
/* the motor is off; this should generate an error with or
without a disk drive present */
- out_fdc(bc, ioh, NE7CMD_SEEK);
- out_fdc(bc, ioh, 0);
- out_fdc(bc, ioh, 0);
+ out_fdc(iot, ioh, NE7CMD_SEEK);
+ out_fdc(iot, ioh, 0);
+ out_fdc(iot, ioh, 0);
}
#endif
void *aux;
{
struct fdc_softc *fdc = (void *)self;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct isa_attach_args *ia = aux;
struct fdc_attach_args fa;
int type;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
/* Re-map the I/O space. */
- if (bus_io_map(bc, ia->ia_iobase, FDC_NPORT, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, FDC_NPORT, 0, &ioh))
panic("fdcattach: couldn't map I/O ports");
- fdc->sc_bc = bc;
+ fdc->sc_iot = iot;
fdc->sc_ioh = ioh;
fdc->sc_drq = ia->ia_drq;
fdcresult(fdc)
struct fdc_softc *fdc;
{
- bus_chipset_tag_t bc = fdc->sc_bc;
- bus_io_handle_t ioh = fdc->sc_ioh;
+ bus_space_tag_t iot = fdc->sc_iot;
+ bus_space_handle_t ioh = fdc->sc_ioh;
u_char i;
int j = 100000, n = 0;
for (; j; j--) {
- i = bus_io_read_1(bc, ioh, fdsts) &
+ i = bus_space_read_1(iot, ioh, fdsts) &
(NE7_DIO | NE7_RQM | NE7_CB);
if (i == NE7_RQM)
return n;
log(LOG_ERR, "fdcresult: overrun\n");
return -1;
}
- fdc->sc_status[n++] = bus_io_read_1(bc, ioh, fddata);
+ fdc->sc_status[n++] = bus_space_read_1(iot, ioh, fddata);
}
}
log(LOG_ERR, "fdcresult: timeout\n");
}
int
-out_fdc(bc, ioh, x)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+out_fdc(iot, ioh, x)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_char x;
{
int i = 100000;
- while ((bus_io_read_1(bc, ioh, fdsts) & NE7_DIO) && i-- > 0);
+ while ((bus_space_read_1(iot, ioh, fdsts) & NE7_DIO) && i-- > 0);
if (i <= 0)
return -1;
- while ((bus_io_read_1(bc, ioh, fdsts) & NE7_RQM) == 0 && i-- > 0);
+ while ((bus_space_read_1(iot, ioh, fdsts) & NE7_RQM) == 0 && i-- > 0);
if (i <= 0)
return -1;
- bus_io_write_1(bc, ioh, fddata, x);
+ bus_space_write_1(iot, ioh, fddata, x);
return 0;
}
struct fdc_softc *fdc = (void *)dv->dv_parent;
if (n == 0) {
- out_fdc(fdc->sc_bc, fdc->sc_ioh, NE7CMD_SENSEI);
+ out_fdc(fdc->sc_iot, fdc->sc_ioh, NE7CMD_SENSEI);
(void) fdcresult(fdc);
n = 2;
}
-/* $OpenBSD: fdlink.h,v 1.2 1996/10/28 00:06:22 downsj Exp $ */
+/* $OpenBSD: fdlink.h,v 1.3 1996/11/29 22:54:56 niklas Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995 Charles Hannum.
struct isadev sc_id;
void *sc_ih;
- bus_chipset_tag_t sc_bc; /* ISA chipset identifier */
- bus_io_handle_t sc_ioh; /* ISA io handle */
+ bus_space_tag_t sc_iot; /* ISA chipset identifier */
+ bus_space_handle_t sc_ioh; /* ISA io handle */
int sc_drq;
};
/* Functions from fdc.c. */
-int fdcresult __P((struct fdc_softc *fdc));
-int out_fdc __P((bus_chipset_tag_t bc, bus_io_handle_t ioh, u_char x));
-void fdcstart __P((struct fdc_softc *fdc));
-void fdcstatus __P((struct device *dv, int n, char *s));
-void fdcpseudointr __P((void *arg));
+int fdcresult __P((struct fdc_softc *));
+int out_fdc __P((bus_space_tag_t, bus_space_handle_t, u_char));
+void fdcstart __P((struct fdc_softc *));
+void fdcstatus __P((struct device *, int, char *));
+void fdcpseudointr __P((void *));
/* Functions from fd.c. */
struct fd_type *fd_nvtotype __P((char *, int, int));
-# $OpenBSD: files.isa,v 1.27 1996/08/14 14:36:14 shawn Exp $
+# $OpenBSD: files.isa,v 1.28 1996/11/29 22:54:57 niklas Exp $
# $NetBSD: files.isa,v 1.21 1996/05/16 03:45:55 mycroft Exp $
#
# Config.new file and device description for machine-independent ISA code.
attach com at isa with com_isa
attach com at commulti with com_commulti
attach com at pcmcia with com_pcmcia
-file dev/isa/com.c com & (com_isa | com_commulti | com_pcmcia) needs-flag
+file dev/isa/com.c com & (com_isa | com_commulti | com_pcmcia | com_pica) needs-flag
# Cyclades Cyclom multiport serial cards
attach cy at isa with cy_isa
# PC parallel ports (XXX what chip?)
device lpt
attach lpt at isa with lpt_isa
-file dev/isa/lpt.c lpt needs-flag
+file dev/isa/lpt.c lpt & (lpt_isa | lpt_pica) needs-flag
+file dev/isa/lpt_isa.c lpt_isa needs-flag
#
# SCSI host adapters
file dev/isa/seagate.c sea
# UltraStor UHA-[13]4f boards
-device uha: scsi, isa_dma
-attach uha at isa
-file dev/isa/ultra14f.c uha
+# device declaration in sys/conf/files
+attach uha at isa with uha_isa: isa_dma
+file dev/isa/uha_isa.c uha_isa
# Western Digital WD7000 and Future Domain TMC-7000 boards
device wds: scsi, isa_dma
-/* $OpenBSD: if_ed.c,v 1.24 1996/11/12 20:30:34 niklas Exp $ */
-/* $NetBSD: if_ed.c,v 1.100 1996/05/12 23:52:19 mycroft Exp $ */
+/* $OpenBSD: if_ed.c,v 1.25 1996/11/29 22:54:58 niklas Exp $ */
+/* $NetBSD: if_ed.c,v 1.105 1996/10/21 22:40:45 thorpej Exp $ */
/*
* Device driver for National Semiconductor DS8390/WD83C690 based ethernet
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isareg.h>
*/
struct ed_softc {
struct device sc_dev;
- void *sc_ih;
+ void *sc_ih;
struct arpcom sc_arpcom; /* ethernet common */
- void *sc_sh; /* shutdown hook */
+ void *sc_sh; /* shutdown hook */
char *type_str; /* pointer to type string */
u_char vendor; /* interface vendor */
#define ED_NOTPRESENT 0x0002 /* card not present; do not allow
reconfiguration */
- bus_chipset_tag_t sc_bc; /* bus identifier */
- bus_io_handle_t sc_ioh; /* io handle */
- bus_io_handle_t sc_delayioh; /* io handle for `delay port' */
- bus_mem_handle_t sc_memh; /* bus memory handle */
+ bus_space_tag_t sc_iot; /* bus identifier */
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_ioh; /* io handle */
+ bus_space_handle_t sc_delaybah; /* io handle for `delay port' */
+ bus_space_handle_t sc_memh; /* bus memory handle */
+ isa_chipset_tag_t sc_ic;
- bus_io_size_t asic_base; /* offset of ASIC I/O port */
- bus_io_size_t nic_base; /* offset of NIC (DS8390) I/O port */
+ bus_size_t asic_base; /* offset of ASIC I/O port */
+ bus_size_t nic_base; /* offset of NIC (DS8390) I/O port */
/*
* The following 'proto' variable is part of a work-around for 8013EBT asics
void edattach __P((struct device *, struct device *, void *));
int ed_find __P((struct ed_softc *, struct cfdata *,
struct isa_attach_args *ia));
-int ed_probe_generic8390 __P((bus_chipset_tag_t, bus_io_handle_t, int));
+int ed_probe_generic8390 __P((bus_space_tag_t, bus_space_handle_t, int));
int ed_find_WD80x3 __P((struct ed_softc *, struct cfdata *,
struct isa_attach_args *ia));
int ed_find_3Com __P((struct ed_softc *, struct cfdata *,
void ed_getmcaf __P((struct arpcom *, u_long *));
void edread __P((struct ed_softc *, int, int));
struct mbuf *edget __P((struct ed_softc *, int, int));
-static inline void ed_rint __P((struct ed_softc *));
-static inline void ed_xmit __P((struct ed_softc *));
-static inline int ed_ring_copy __P((struct ed_softc *, int, caddr_t,
+static __inline void ed_rint __P((struct ed_softc *));
+static __inline void ed_xmit __P((struct ed_softc *));
+static __inline int ed_ring_copy __P((struct ed_softc *, int, caddr_t,
u_short));
void ed_pio_readmem __P((struct ed_softc *, u_short, caddr_t, u_short));
sizeof(struct ed_softc), ed_pcmcia_match, edattach, ed_pcmcia_detach
};
-static int ed_pcmcia_isa_attach __P((struct device *, void *,
- void *, struct pcmcia_link *));
-
-static int edmod __P((struct pcmcia_link *, struct device *,
- struct pcmcia_conf *, struct cfdata *cf));
-
-static int ed_remove __P((struct pcmcia_link *, struct device *));
+int ed_pcmcia_isa_attach __P((struct device *, void *, void *,
+ struct pcmcia_link *));
+int edmod __P((struct pcmcia_link *, struct device *, struct pcmcia_conf *,
+ struct cfdata *cf));
+int ed_remove __P((struct pcmcia_link *, struct device *));
/* additional setup needed for pcmcia devices */
-static int
+int
ed_pcmcia_isa_attach(parent, match, aux, pc_link)
struct device *parent;
void *match;
sc->spec_flags=pc_link->flags&PCMCIA_REATTACH?ED_REATTACH:0;
sc->type_str = dev->model;
sc->sc_arpcom.ac_if.if_snd.ifq_maxlen=ifqmaxlen;
+ sc->sc_ic = ia->ia_ic;
return 1;
} else
return 0;
}
/* modify config entry */
-static int
+int
edmod(pc_link, self, pc_cf, cf)
struct pcmcia_link *pc_link;
struct device *self;
return err;
}
-
-static int
+int
ed_remove(pc_link,self)
struct pcmcia_link *pc_link;
struct device *self;
shutdownhook_disestablish(sc->sc_sh);
ifp->if_flags &= ~(IFF_RUNNING|IFF_UP);
sc->spec_flags |= ED_NOTPRESENT;
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
+ isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
return PCMCIA_BUS_UNCONFIG(pc_link->adapter, pc_link);
}
#endif
-#define NIC_PUT(bc, ioh, nic, reg, val) \
- bus_io_write_1((bc), (ioh), ((nic) + (reg)), (val))
-#define NIC_GET(bc, ioh, nic, reg) \
- bus_io_read_1((bc), (ioh), ((nic) + (reg)))
+#define NIC_PUT(t, bah, nic, reg, val) \
+ bus_space_write_1((t), (bah), ((nic) + (reg)), (val))
+#define NIC_GET(t, bah, nic, reg) \
+ bus_space_read_1((t), (bah), ((nic) + (reg)))
/*
* Determine if the device is present.
* Return 1 if 8390 was found, 0 if not.
*/
int
-ed_probe_generic8390(bc, ioh, nicbase)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ed_probe_generic8390(t, bah, nicbase)
+ bus_space_tag_t t;
+ bus_space_handle_t bah;
int nicbase;
{
- if ((NIC_GET(bc, ioh, nicbase, ED_P0_CR) &
+ if ((NIC_GET(t, bah, nicbase, ED_P0_CR) &
(ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
(ED_CR_RD2 | ED_CR_STP))
return (0);
- if ((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
+ if ((NIC_GET(t, bah, nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
return (0);
return (1);
struct cfdata *cf;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- bus_io_handle_t delayioh = ia->ia_delayioh;
- bus_mem_handle_t memh;
+ bus_space_tag_t iot;
+ bus_space_tag_t memt;
+ bus_space_handle_t ioh;
+ bus_space_handle_t delaybah = ia->ia_delaybah;
+ bus_space_handle_t memh;
u_int memsize;
u_char iptr, isa16bit, sum;
int i, rv, memfail, mapped_mem = 0;
int asicbase, nicbase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
+ memt = ia->ia_memt;
rv = 0;
/* Set initial values for width/size. */
memsize = 8192;
isa16bit = 0;
- if (bus_io_map(bc, ia->ia_iobase, ED_WD_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ED_WD_IO_PORTS, 0, &ioh))
return (0);
sc->asic_base = asicbase = 0;
sc->is790 = 0;
#ifdef TOSH_ETHER
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_POW);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_POW);
delay(10000);
#endif
* Danpex boards for one.
*/
for (sum = 0, i = 0; i < 8; ++i)
- sum += bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + i);
+ sum += bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + i);
if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
/*
* clones. In this case, the checksum byte (the eighth byte)
* seems to always be zero.
*/
- if (bus_io_read_1(bc, ioh, asicbase + ED_WD_CARD_ID) !=
+ if (bus_space_read_1(iot, ioh, asicbase + ED_WD_CARD_ID) !=
ED_TYPE_WD8003E ||
- bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + 7) != 0)
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + 7) != 0)
goto out;
}
/* Reset card to force it into a known state. */
#ifdef TOSH_ETHER
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
ED_WD_MSR_RST | ED_WD_MSR_POW);
#else
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST);
#endif
delay(100);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
- bus_io_read_1(bc, ioh, asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST);
/* Wait in the case this card is reading it's EEROM. */
delay(5000);
sc->vendor = ED_VENDOR_WD_SMC;
- sc->type = bus_io_read_1(bc, ioh, asicbase + ED_WD_CARD_ID);
+ sc->type = bus_space_read_1(iot, ioh, asicbase + ED_WD_CARD_ID);
switch (sc->type) {
case ED_TYPE_WD8003S:
isa16bit = 1;
break;
case ED_TYPE_WD8013EP: /* also WD8003EP */
- if (bus_io_read_1(bc, ioh, asicbase + ED_WD_ICR)
+ if (bus_space_read_1(iot, ioh, asicbase + ED_WD_ICR)
& ED_WD_ICR_16BIT) {
isa16bit = 1;
memsize = 16384;
case ED_TYPE_SMC8216C:
case ED_TYPE_SMC8216T:
sc->type_str = (sc->type == ED_TYPE_SMC8216C) ?
- "SMC8216/SMC8216C" : "SMC8216T";
- bus_io_write_1(bc, ioh, asicbase + ED_WD790_HWR,
- bus_io_read_1(bc, ioh, asicbase + ED_WD790_HWR)
- | ED_WD790_HWR_SWH);
- switch (bus_io_read_1(bc, ioh, asicbase + ED_WD790_RAR) &
+ "SMC8216/SMC8216C" : "SMC8216T";
+ bus_space_write_1(iot, ioh, asicbase + ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, asicbase + ED_WD790_HWR)
+ | ED_WD790_HWR_SWH);
+ switch (bus_space_read_1(iot, ioh, asicbase + ED_WD790_RAR) &
ED_WD790_RAR_SZ64) {
case ED_WD790_RAR_SZ64:
memsize = 65536;
memsize = 8192;
break;
}
- bus_io_write_1(bc, ioh, asicbase + ED_WD790_HWR,
- bus_io_read_1(bc, ioh,
- asicbase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, asicbase + ED_WD790_HWR) &
+ ~ED_WD790_HWR_SWH);
isa16bit = 1;
sc->is790 = 1;
#ifdef TOSH_ETHER
(sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) &&
#endif
- ((bus_io_read_1(bc, ioh,
- asicbase + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
+ ((bus_space_read_1(iot, ioh, asicbase + ED_WD_ICR) &
+ ED_WD_ICR_16BIT) == 0)) {
isa16bit = 0;
memsize = 8192;
}
sc->type, sc->type_str ?: "unknown", isa16bit, memsize,
ia->ia_msize);
for (i = 0; i < 8; i++)
- printf("%x -> %x\n", i, inb(asicbase + i));
+ printf("%x -> %x\n", i, bus_space_read_1(iot, ioh,
+ asicbase + i));
#endif
/* Allow the user to override the autoconfiguration. */
if (ia->ia_msize)
*/
if (sc->is790) {
u_char x;
+
/* Assemble together the encoded interrupt number. */
- bus_io_write_1(bc, ioh, ED_WD790_HWR,
- bus_io_read_1(bc, ioh, ED_WD790_HWR) | ED_WD790_HWR_SWH);
- x = bus_io_read_1(bc, ioh, ED_WD790_GCR);
+ bus_space_write_1(iot, ioh, ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, ED_WD790_HWR) |
+ ED_WD790_HWR_SWH);
+ x = bus_space_read_1(iot, ioh, ED_WD790_GCR);
iptr = ((x & ED_WD790_GCR_IR2) >> 4) |
((x & (ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2);
- bus_io_write_1(bc, ioh, ED_WD790_HWR,
- bus_io_read_1(bc, ioh, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+ bus_space_write_1(iot, ioh, ED_WD790_HWR,
+ bus_space_read_1(iot, ioh, ED_WD790_HWR) &
+ ~ED_WD790_HWR_SWH);
/*
* Translate it using translation table, and check for
* correctness.
} else
ia->ia_irq = ed_wd790_irq[iptr];
/* Enable the interrupt. */
- bus_io_write_1(bc, ioh, ED_WD790_ICR,
- bus_io_read_1(bc, ioh, ED_WD790_ICR) | ED_WD790_ICR_EIL);
+ bus_space_write_1(iot, ioh, ED_WD790_ICR,
+ bus_space_read_1(iot, ioh, ED_WD790_ICR) |
+ ED_WD790_ICR_EIL);
} else if (sc->type & ED_WD_SOFTCONFIG) {
/* Assemble together the encoded interrupt number. */
- iptr = (bus_io_read_1(bc, ioh, ED_WD_ICR) & ED_WD_ICR_IR2) |
- ((bus_io_read_1(bc, ioh, ED_WD_IRR) &
+ iptr = (bus_space_read_1(iot, ioh, ED_WD_ICR) &
+ ED_WD_ICR_IR2) |
+ ((bus_space_read_1(iot, ioh, ED_WD_IRR) &
(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
/*
* Translate it using translation table, and check for
} else
ia->ia_irq = ed_wd584_irq[iptr];
/* Enable the interrupt. */
- bus_io_write_1(bc, ioh, ED_WD_IRR,
- bus_io_read_1(bc, ioh, ED_WD_IRR) | ED_WD_IRR_IEN);
+ bus_space_write_1(iot, ioh, ED_WD_IRR,
+ bus_space_read_1(iot, ioh, ED_WD_IRR) | ED_WD_IRR_IEN);
} else {
if (ia->ia_irq == IRQUNK) {
printf("%s: %s does not have soft configuration\n",
sc->isa16bit = isa16bit;
sc->mem_shared = 1;
ia->ia_msize = memsize;
- if (bus_mem_map(bc, ia->ia_maddr, memsize, 0, &memh))
+ if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh))
goto out;
mapped_mem = 1;
sc->mem_start = 0; /* offset */
/* Get station address from on-board ROM. */
for (i = 0; i < ETHER_ADDR_LEN; ++i)
sc->sc_arpcom.ac_enaddr[i] =
- bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + i);
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + i);
/*
* Set upper address bits and 8/16 bit access to shared memory.
if (isa16bit) {
if (sc->is790) {
sc->wd_laar_proto =
- bus_io_read_1(bc, ioh, asicbase + ED_WD_LAAR) &
+ bus_space_read_1(iot, ioh, asicbase + ED_WD_LAAR) &
~ED_WD_LAAR_M16EN;
} else {
- sc->wd_laar_proto =
- ED_WD_LAAR_L16EN |
- ((ia->ia_maddr >> 19) &
- ED_WD_LAAR_ADDRHI);
+ sc->wd_laar_proto = ED_WD_LAAR_L16EN |
+ ((ia->ia_maddr >> 19) & ED_WD_LAAR_ADDRHI);
}
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
} else {
if ((sc->type & ED_WD_SOFTCONFIG) ||
sc->wd_laar_proto =
((ia->ia_maddr >> 19) &
ED_WD_LAAR_ADDRHI);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
}
}
*/
if (!sc->is790) {
#ifdef TOSH_ETHER
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR + 1,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR + 1,
((ia->ia_maddr >> 8) & 0xe0) | 4);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR + 2,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR + 2,
((ia->ia_maddr >> 16) & 0x0f));
sc->wd_msr_proto = ED_WD_MSR_POW;
#else
#endif
sc->cr_proto = ED_CR_RD2;
} else {
- bus_io_write_1(bc, ioh, asicbase + 0x04,
- bus_io_read_1(bc, ioh, asicbase + 0x04) | 0x80);
- bus_io_write_1(bc, ioh, asicbase + 0x0b,
+ bus_space_write_1(iot, ioh, asicbase + 0x04,
+ bus_space_read_1(iot, ioh, asicbase + 0x04) | 0x80);
+ bus_space_write_1(iot, ioh, asicbase + 0x0b,
((ia->ia_maddr >> 13) & 0x0f) |
((ia->ia_maddr >> 11) & 0x40) |
- (bus_io_read_1(bc, ioh, asicbase + 0x0b) & 0xb0));
- bus_io_write_1(bc, ioh, asicbase + 0x04,
- bus_io_read_1(bc, ioh, asicbase + 0x04) & ~0x80);
+ (bus_space_read_1(iot, ioh, asicbase + 0x0b) & 0xb0));
+ bus_space_write_1(iot, ioh, asicbase + 0x04,
+ bus_space_read_1(iot, ioh, asicbase + 0x04) & ~0x80);
sc->wd_msr_proto = 0x00;
sc->cr_proto = 0;
}
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
- (void) bus_io_read_1(bc, delayioh, 0);
- (void) bus_io_read_1(bc, delayioh, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
/* Now zero memory and verify that it is clear. */
if (isa16bit) {
for (i = 0; i < memsize; i += 2)
- bus_mem_write_2(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_2(memt, memh, sc->mem_start + i, 0);
} else {
for (i = 0; i < memsize; ++i)
- bus_mem_write_1(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_1(memt, memh, sc->mem_start + i, 0);
}
memfail = 0;
if (isa16bit) {
for (i = 0; i < memsize; i += 2) {
- if (bus_mem_read_2(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_2(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
}
} else {
for (i = 0; i < memsize; ++i) {
- if (bus_mem_read_1(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_1(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
(ia->ia_maddr + sc->mem_start + i));
/* Disable 16 bit access to shared memory. */
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc, delayioh, 0);
- (void) bus_io_read_1(bc, delayioh, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
goto out;
}
* and 2) so that other 8 bit devices with shared memory can be
* used in this 128k region, too.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto);
if (isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc, delayioh, 0);
- (void) bus_io_read_1(bc, delayioh, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
+ (void) bus_space_read_1(iot, delaybah, 0);
ia->ia_iosize = ED_WD_IO_PORTS;
rv = 1;
* XXX Need to squish "indirect" first.
*/
if (rv == 0) {
- bus_io_unmap(bc, ioh, ED_WD_IO_PORTS);
+ bus_space_unmap(iot, ioh, ED_WD_IO_PORTS);
if (mapped_mem)
- bus_mem_unmap(bc, memh, memsize);
+ bus_space_unmap(memt, memh, memsize);
} else {
/* XXX this is all "indirect" brokenness */
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
+ sc->sc_memt = memt;
sc->sc_ioh = ioh;
sc->sc_memh = memh;
}
return (rv);
}
-int ed_3com_iobase[] = {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300};
-int ed_3com_maddr[] = {MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000};
+int ed_3com_iobase[] =
+ {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300};
+int ed_3com_maddr[] = {
+ MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000
+};
#if 0
int ed_3com_irq[] = {IRQUNK, IRQUNK, IRQUNK, IRQUNK, 9, 3, 4, 5};
#endif
struct cfdata *cf;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- bus_mem_handle_t memh;
+ bus_space_tag_t iot;
+ bus_space_tag_t memt;
+ bus_space_handle_t ioh;
+ bus_space_handle_t memh;
int i;
u_int memsize, memfail;
u_char isa16bit, x;
*/
memsize = 8192;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
+ memt = ia->ia_memt;
- if (bus_io_map(bc, ia->ia_iobase, ED_WD_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ED_3COM_IO_PORTS, 0, &ioh))
return (0);
sc->asic_base = asicbase = ED_3COM_ASIC_OFFSET;
* board is there; after all, we are already talking it at that
* address.
*/
- x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_BCFR);
+ x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_BCFR);
if (x == 0 || (x & (x - 1)) != 0)
goto err;
ptr = ffs(x) - 1;
} else
ia->ia_iobase = ed_3com_iobase[ptr]; /* XXX --thorpej */
- x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_PCFR);
- if (x == 0 || (x & (x - 1)) != 0)
+ x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_PCFR);
+ if (x == 0 || (x & (x - 1)) != 0) {
+ printf("%s: The 3c503 is not currently supported with memory "
+ "mapping disabled.\n%s: Reconfigure the card to "
+ "enable memory mapping.\n",
+ sc->sc_dev.dv_xname, sc->sc_dev.dv_xname);
goto err;
+ }
ptr = ffs(x) - 1;
if (ia->ia_maddr != MADDRUNK) {
if (ia->ia_maddr != ed_3com_maddr[ptr]) {
ia->ia_maddr = ed_3com_maddr[ptr];
#if 0
- x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_IDCFR) &
+ x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_IDCFR) &
ED_3COM_IDCFR_IRQ;
if (x == 0 || (x & (x - 1)) != 0)
goto out;
* sequence because it'll lock up if the cable isn't connected if we
* don't.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR,
ED_3COM_CR_RST | ED_3COM_CR_XSEL);
/* Wait for a while, then un-reset it. */
* reset - it's important to set it again after the following outb
* (this is done when we map the PROM below).
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
/* Wait a bit for the NIC to recover from the reset. */
delay(5000);
* First, map ethernet address PROM over the top of where the NIC
* registers normally appear.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR,
ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
for (i = 0; i < ETHER_ADDR_LEN; ++i)
- sc->sc_arpcom.ac_enaddr[i] = NIC_GET(bc, ioh, nicbase, i);
+ sc->sc_arpcom.ac_enaddr[i] = NIC_GET(iot, ioh, nicbase, i);
/*
* Unmap PROM - select NIC registers. The proper setting of the
* tranceiver is set in edinit so that the attach code is given a
* chance to set the default based on a compile-time config option.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
/* Determine if this is an 8bit or 16bit board. */
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
/*
* Attempt to clear WTS bit. If it doesn't clear, then this is a
* 16-bit board.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, 0);
/* Select page 2 registers. */
- NIC_PUT(bc, ioh, nicbase,
+ NIC_PUT(iot, ioh, nicbase,
ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_2 | ED_CR_STP);
/* The 3c503 forces the WTS bit to a one if this is a 16bit board. */
- if (NIC_GET(bc, ioh, nicbase, ED_P2_DCR) & ED_DCR_WTS)
+ if (NIC_GET(iot, ioh, nicbase, ED_P2_DCR) & ED_DCR_WTS)
isa16bit = 1;
else
isa16bit = 0;
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P2_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P2_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
- if (bus_mem_map(bc, ia->ia_maddr, memsize, 0, &memh))
+ if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh))
goto err;
sc->mem_start = 0; /* offset */
sc->mem_size = memsize;
* Initialize GA page start/stop registers. Probably only needed if
* doing DMA, but what the Hell.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_PSTR, sc->rec_page_start);
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_PSPR, sc->rec_page_stop);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_PSTR, sc->rec_page_start);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_PSPR, sc->rec_page_stop);
/* Set IRQ. 3c503 only allows a choice of irq 3-5 or 9. */
switch (ia->ia_irq) {
case 9:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ2);
break;
case 3:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ3);
break;
case 4:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ4);
break;
case 5:
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR,
ED_3COM_IDCFR_IRQ5);
break;
default:
* Initialize GA configuration register. Set bank and enable shared
* mem.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_GACFR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
/*
* shared memory is disabled. We set them to 0xffff0...allegedly the
* reset vector.
*/
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR2, 0xff);
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR1, 0xff);
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR0, 0x00);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR2, 0xff);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR1, 0xff);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR0, 0x00);
/* Now zero memory and verify that it is clear. */
if (isa16bit) {
for (i = 0; i < memsize; i += 2)
- bus_mem_write_2(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_2(memt, memh, sc->mem_start + i, 0);
} else {
for (i = 0; i < memsize; ++i)
- bus_mem_write_1(bc, memh, sc->mem_start + i, 0);
+ bus_space_write_1(memt, memh, sc->mem_start + i, 0);
}
memfail = 0;
if (isa16bit) {
for (i = 0; i < memsize; i += 2) {
- if (bus_mem_read_2(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_2(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
}
} else {
for (i = 0; i < memsize; ++i) {
- if (bus_mem_read_1(bc, memh, sc->mem_start + i)) {
+ if (bus_space_read_1(memt, memh, sc->mem_start + i)) {
memfail = 1;
break;
}
* XXX Sould always unmap, but we can't yet.
* XXX Need to squish "indirect" first.
*/
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
+ sc->sc_memt = memt;
sc->sc_ioh = ioh;
sc->sc_memh = memh;
return 1;
out:
- bus_mem_unmap(bc, memh, memsize);
+ bus_space_unmap(memt, memh, memsize);
err:
- bus_io_unmap(bc, ioh, ED_3COM_IO_PORTS);
+ bus_space_unmap(iot, ioh, ED_3COM_IO_PORTS);
return 0;
}
struct cfdata *cf;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int memsize, n;
u_char romdata[16], tmp;
static u_char test_pattern[32] = "THIS is A memory TEST pattern";
u_char test_buffer[32];
int asicbase, nicbase;
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
- if (bus_io_map(bc, ia->ia_iobase, ED_NOVELL_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ED_NOVELL_IO_PORTS, 0, &ioh))
return (0);
sc->asic_base = asicbase = ED_NOVELL_ASIC_OFFSET;
/* Reset the board. */
#ifdef GWETHER
- bus_io_write_1(bc, ioh, asicbase + ED_NOVELL_RESET, 0);
+ bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, 0);
delay(200);
#endif /* GWETHER */
- tmp = bus_io_read_1(bc, ioh, asicbase + ED_NOVELL_RESET);
+ tmp = bus_space_read_1(iot, ioh, asicbase + ED_NOVELL_RESET);
/*
* I don't know if this is necessary; probably cruft leftover from
* complete documentation on what the 'right' thing to do is...so we do
* the invasive thing for now. Yuck.]
*/
- bus_io_write_1(bc, ioh, asicbase + ED_NOVELL_RESET, tmp);
+ bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, tmp);
delay(5000);
/*
* XXX - this makes the probe invasive! ...Done against my better
* judgement. -DLG
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
delay(5000);
/* Make sure that we really have an 8390 based board. */
- if (!ed_probe_generic8390(bc, ioh, nicbase))
+ if (!ed_probe_generic8390(iot, ioh, nicbase))
goto out;
sc->vendor = ED_VENDOR_NOVELL;
* This prevents packets from being stored in the NIC memory when the
* readmem routine turns on the start bit in the CR.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
/* Temporarily initialize DCR for byte operations. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
sc->isa16bit = 0;
/*
* XXX indirect brokenness, used by ed_pio{read,write}mem()
*/
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
/*
if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
/* not an NE1000 - try NE2000 */
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR,
ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
sc->isa16bit = 1;
#endif /* GWETHER */
/* Clear any pending interrupts that might have occurred above. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, 0xff);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff);
ia->ia_iosize = ED_NOVELL_IO_PORTS;
* XXX Sould always unmap, but we can't yet.
* XXX Need to squish "indirect" first.
*/
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
/* sc_memh is not used by this driver */
return 1;
out:
- bus_io_unmap(bc, ioh, ED_NOVELL_IO_PORTS);
+ bus_space_unmap(iot, ioh, ED_NOVELL_IO_PORTS);
return 0;
}
struct device *parent, *self;
void *aux;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct ed_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
struct cfdata *cf = sc->sc_dev.dv_cfdata;
* XXX Should re-map io and mem, but can't
* XXX until we squish "indirect" brokenness.
*/
- bc = sc->sc_bc; /* XXX */
+ iot = sc->sc_iot; /* XXX */
ioh = sc->sc_ioh; /* XXX */
asicbase = sc->asic_base;
- sc->sc_delayioh = ia->ia_delayioh;
+ sc->sc_delaybah = ia->ia_delaybah;
/* Set interface to stopped condition (reset). */
edstop(sc);
case ED_VENDOR_WD_SMC:
if ((sc->type & ED_WD_SOFTCONFIG) == 0)
break;
- if ((bus_io_read_1(bc, ioh, asicbase + ED_WD_IRR) &
+ if ((bus_space_read_1(iot, ioh, asicbase + ED_WD_IRR) &
ED_WD_IRR_OUT2) == 0)
ifp->if_flags |= IFF_LINK0;
break;
edstop(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
int n = 5000;
/* Stop everything on the interface, and select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
/*
* 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
* just in case it's an old one.
*/
- while (((NIC_GET(bc, ioh, nicbase,
+ while (((NIC_GET(iot, ioh, nicbase,
ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
}
edinit(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int nicbase = sc->nic_base, asicbase = sc->asic_base;
int i;
sc->txb_next_tx = 0;
/* Set interface for page 0, remote DMA complete, stopped. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
if (sc->isa16bit) {
* Set FIFO threshold to 8, No auto-init Remote DMA, byte
* order=80x86, word-wide DMA xfers,
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR,
ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
} else {
/* Same as above, but byte-wide DMA xfers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
}
/* Clear remote byte count registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, 0);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, 0);
/* Tell RCR to do nothing for now. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
/* Place NIC in internal loopback mode. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TCR, ED_TCR_LB0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TCR, ED_TCR_LB0);
/* Set lower bits of byte addressable framing to 0. */
if (sc->is790)
- NIC_PUT(bc, ioh, nicbase, 0x09, 0);
+ NIC_PUT(iot, ioh, nicbase, 0x09, 0);
/* Initialize receive buffer ring. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_BNRY, sc->rec_page_start);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, sc->rec_page_start);
- NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, sc->rec_page_stop);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_BNRY, sc->rec_page_start);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, sc->rec_page_start);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, sc->rec_page_stop);
/*
* Clear all interrupts. A '1' in each bit position clears the
* corresponding flag.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, 0xff);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff);
/*
* Enable the following interrupts: receive/transmit complete,
*
* Counter overflow and Remote DMA complete are *not* enabled.
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_IMR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_IMR,
ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE |
ED_IMR_OVWE);
/* Program command register for page 1. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
/* Copy out our station address. */
for (i = 0; i < ETHER_ADDR_LEN; ++i)
- NIC_PUT(bc, ioh, nicbase, ED_P1_PAR0 + i,
+ NIC_PUT(iot, ioh, nicbase, ED_P1_PAR0 + i,
sc->sc_arpcom.ac_enaddr[i]);
/* Set multicast filter on chip. */
ed_getmcaf(&sc->sc_arpcom, mcaf);
for (i = 0; i < 8; i++)
- NIC_PUT(bc, ioh, nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
+ NIC_PUT(iot, ioh, nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
/*
* Set current page pointer to one page after the boundary pointer, as
* recommended in the National manual.
*/
sc->next_packet = sc->rec_page_start + 1;
- NIC_PUT(bc, ioh, nicbase, ED_P1_CURR, sc->next_packet);
+ NIC_PUT(iot, ioh, nicbase, ED_P1_CURR, sc->next_packet);
/* Program command register for page 0. */
- NIC_PUT(bc, ioh, nicbase, ED_P1_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P1_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
i = ED_RCR_AB | ED_RCR_AM;
*/
i |= ED_RCR_PRO | ED_RCR_AR | ED_RCR_SEP;
}
- NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, i);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, i);
/* Take interface out of loopback. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TCR, 0);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TCR, 0);
/*
* If this is a 3Com board, the tranceiver must be software enabled
u_char x;
case ED_VENDOR_3COM:
if (ifp->if_flags & IFF_LINK0)
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, 0);
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, 0);
else
- bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR,
+ bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR,
ED_3COM_CR_XSEL);
break;
case ED_VENDOR_WD_SMC:
if ((sc->type & ED_WD_SOFTCONFIG) == 0)
break;
- x = bus_io_read_1(bc, ioh, asicbase + ED_WD_IRR);
+ x = bus_space_read_1(iot, ioh, asicbase + ED_WD_IRR);
if (ifp->if_flags & IFF_LINK0)
x &= ~ED_WD_IRR_OUT2;
else
x |= ED_WD_IRR_OUT2;
- bus_io_write_1(bc, ioh, asicbase + ED_WD_IRR, x);
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_IRR, x);
break;
}
/* Fire up the interface. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/* Set 'running' flag, and clear output active flag. */
/*
* This routine actually starts the transmission on the interface.
*/
-static inline void
+static __inline void
ed_xmit(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int nicbase = sc->nic_base;
u_short len;
len = sc->txb_len[sc->txb_next_tx];
/* Set NIC for page 0 register access. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/* Set TX buffer start page. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TPSR, sc->tx_page_start +
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TPSR, sc->tx_page_start +
sc->txb_next_tx * ED_TXBUF_SIZE);
/* Set TX length. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_TBCR0, len);
- NIC_PUT(bc, ioh, nicbase, ED_P0_TBCR1, len >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TBCR0, len);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_TBCR1, len >> 8);
/* Set page 0, remote DMA complete, transmit packet, and *start*. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA);
/* Point to next transmit buffer slot and wrap if necessary. */
struct ifnet *ifp;
{
struct ed_softc *sc = ifp->if_softc;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct mbuf *m0, *m;
int buffer;
int asicbase = sc->asic_base;
*/
case ED_VENDOR_3COM:
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL);
break;
*/
case ED_VENDOR_WD_SMC:
if (sc->isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
break;
}
switch (sc->vendor) {
case ED_VENDOR_3COM:
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
break;
case ED_VENDOR_WD_SMC:
- bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (sc->isa16bit)
- bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR,
+ bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc, sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot, sc->sc_delaybah, 0);
break;
}
} else
/*
* Ethernet interface receiver interrupt.
*/
-static inline void
+static __inline void
ed_rint(sc)
struct ed_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
u_int8_t boundary, current;
u_int16_t len;
loop:
/* Set NIC to page 1 registers to get 'current' pointer. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
/*
* until the logical beginning equals the logical end (or in other
* words, until the ring-buffer is empty).
*/
- current = NIC_GET(bc, ioh, nicbase, ED_P1_CURR);
+ current = NIC_GET(iot, ioh, nicbase, ED_P1_CURR);
if (sc->next_packet == current)
return;
/* Set NIC to page 0 registers to update boundary register. */
- NIC_PUT(bc, ioh, nicbase, ED_P1_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P1_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
do {
boundary = sc->next_packet - 1;
if (boundary < sc->rec_page_start)
boundary = sc->rec_page_stop - 1;
- NIC_PUT(bc, ioh, nicbase, ED_P0_BNRY, boundary);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_BNRY, boundary);
} while (sc->next_packet != current);
goto loop;
void *arg;
{
struct ed_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int nicbase = sc->nic_base, asicbase = sc->asic_base;
u_char isr;
/* Set NIC to page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
- isr = NIC_GET(bc, ioh, nicbase, ED_P0_ISR);
+ isr = NIC_GET(iot, ioh, nicbase, ED_P0_ISR);
if (!isr)
return (0);
* '1' to each bit position that was set.
* (Writing a '1' *clears* the bit.)
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, isr);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, isr);
/*
* Handle transmitter interrupts. Handle these first because
* the receiver will reset the board under some conditions.
*/
if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
- u_char collisions = NIC_GET(bc, ioh, nicbase,
+ u_char collisions = NIC_GET(iot, ioh, nicbase,
ED_P0_NCR) & 0x0f;
/*
* course, with UDP we're screwed, but this is expected
* when a network is heavily loaded.
*/
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_TSR);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_TSR);
if (isr & ED_ISR_TXE) {
/*
* Excessive collisions (16).
*/
- if ((NIC_GET(bc, ioh, nicbase, ED_P0_TSR) &
+ if ((NIC_GET(iot, ioh, nicbase, ED_P0_TSR) &
ED_TSR_ABT) && (collisions == 0)) {
/*
* When collisions total 16, the P0_NCR
*/
if (sc->vendor == ED_VENDOR_WD_SMC) {
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_LAAR,
sc->wd_laar_proto |
ED_WD_LAAR_M16EN);
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
}
ed_rint(sc);
/* Disable 16-bit access. */
if (sc->vendor == ED_VENDOR_WD_SMC) {
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (sc->isa16bit)
- bus_io_write_1(bc, ioh,
+ bus_space_write_1(iot, ioh,
asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
- (void) bus_io_read_1(bc,
- sc->sc_delayioh, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
+ (void) bus_space_read_1(iot,
+ sc->sc_delaybah, 0);
}
}
}
* set in the transmit routine, is *okay* - it is 'edge'
* triggered from low to high).
*/
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/*
* otherwise - resulting in an infinite loop.
*/
if (isr & ED_ISR_CNT) {
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR0);
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR1);
- (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR2);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR0);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR1);
+ (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR2);
}
- isr = NIC_GET(bc, ioh, nicbase, ED_P0_ISR);
+ isr = NIC_GET(iot, ioh, nicbase, ED_P0_ISR);
if (!isr)
return (1);
}
caddr_t dst;
u_short amount;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Round up to a word. */
++amount;
/* Set up DMA byte count. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, amount);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, amount >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, amount);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, amount >> 8);
/* Set up source address in NIC mem. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, src);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, src >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, src);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, src >> 8);
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
if (sc->isa16bit)
- bus_io_read_raw_multi_2(bc, ioh,
+ bus_space_read_raw_multi_2(iot, ioh,
sc->asic_base + ED_NOVELL_DATA, dst, amount);
else
- bus_io_read_multi_1(bc, ioh, sc->asic_base + ED_NOVELL_DATA,
- dst, amount);
+ bus_space_read_multi_1(iot, ioh,
+ sc->asic_base + ED_NOVELL_DATA, dst, amount);
}
/*
u_short dst;
u_short len;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base;
int maxwait = 100; /* about 120us */
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Reset remote DMA complete flag. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
/* Set up DMA byte count. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, len);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, len >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8);
/* Set up destination address in NIC mem. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, dst);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
/* Set remote DMA write. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
if (sc->isa16bit)
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
sc->asic_base + ED_NOVELL_DATA, src, len);
else
- bus_io_write_multi_1(bc, ioh, sc->asic_base + ED_NOVELL_DATA,
- src, len);
+ bus_space_write_multi_1(iot, ioh,
+ sc->asic_base + ED_NOVELL_DATA, src, len);
/*
* Wait for remote DMA complete. This is necessary because on the
* waiting causes really bad things to happen - like the NIC
* irrecoverably jamming the ISA bus.
*/
- while (((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
+ while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
ED_ISR_RDC) && --maxwait);
}
struct mbuf *m;
u_short dst;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int nicbase = sc->nic_base, asicbase = sc->asic_base;
u_short len;
int maxwait = 100; /* about 120us */
len = m->m_pkthdr.len;
/* Select page 0 registers. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Reset remote DMA complete flag. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
/* Set up DMA byte count. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, len);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, len >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8);
/* Set up destination address in NIC mem. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, dst);
- NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst);
+ NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
/* Set remote DMA write. */
- NIC_PUT(bc, ioh, nicbase, ED_P0_CR,
+ NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
/*
/* NE1000s are easy. */
for (; m != 0; m = m->m_next) {
if (m->m_len) {
- bus_io_write_multi_1(bc, ioh,
+ bus_space_write_multi_1(iot, ioh,
asicbase + ED_NOVELL_DATA,
mtod(m, u_char *), m->m_len);
}
/* Finish the last word. */
if (wantbyte) {
savebyte[1] = *data;
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
asicbase + ED_NOVELL_DATA, savebyte, 2);
data++;
len--;
}
/* Output contiguous words. */
if (len > 1) {
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
asicbase + ED_NOVELL_DATA, data, len & ~1);
}
/* Save last byte, if necessary. */
if (wantbyte) {
savebyte[1] = 0;
- bus_io_write_raw_multi_2(bc, ioh,
+ bus_space_write_raw_multi_2(iot, ioh,
asicbase + ED_NOVELL_DATA, savebyte, 2);
}
}
* waiting causes really bad things to happen - like the NIC
* irrecoverably jamming the ISA bus.
*/
- while (((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
+ while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
ED_ISR_RDC) && --maxwait);
if (!maxwait) {
* Given a source and destination address, copy 'amount' of a packet from the
* ring buffer into a linear destination buffer. Takes into account ring-wrap.
*/
-static inline int
+static __inline int
ed_ring_copy(sc, src, dst, amount)
struct ed_softc *sc;
int src;
caddr_t from;
int card, len;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_mem_handle_t memh = sc->sc_memh;
+ bus_space_tag_t memt = sc->sc_memt;
+ bus_space_handle_t memh = sc->sc_memh;
u_int16_t word;
/*
* keep accesses 16-bit wide.
*/
if (len > 0 && (card & 1)) {
- word = bus_mem_read_2(bc, memh, card & ~1);
+ word = bus_space_read_2(memt, memh, card & ~1);
word = (word & 0xff) | (*from << 8);
- bus_mem_write_2(bc, memh, card & ~1, word);
+ bus_space_write_2(memt, memh, card & ~1, word);
from++;
card++;
len--;
}
+ /* XXX I think maybe a bus_space_write_raw_region is needed. */
while (len > 1) {
word = (u_int8_t)from[0] | (u_int8_t)from[1] << 8;
- bus_mem_write_2(bc, memh, card, word);
+ bus_space_write_2(memt, memh, card, word);
from += 2;
card += 2;
len -= 2;
}
if (len == 1) {
word = *from;
- bus_mem_write_2(bc, memh, card, word);
+ bus_space_write_2(memt, memh, card, word);
}
} else {
while (len--)
- bus_mem_write_1(bc, memh, card++, *from++);
+ bus_space_write_1(memt, memh, card++, *from++);
}
}
caddr_t to;
int card, len;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_mem_handle_t memh = sc->sc_memh;
+ bus_space_tag_t memt = sc->sc_memt;
+ bus_space_handle_t memh = sc->sc_memh;
u_int16_t word;
/*
* See comment above re. 16-bit cards.
*/
if (sc->isa16bit) {
+ /* XXX I think maybe a bus_space_read_raw_region is needed. */
while (len > 1) {
- word = bus_mem_read_2(bc, memh, card);
+ word = bus_space_read_2(memt, memh, card);
*to++ = word & 0xff;
*to++ = word >> 8 & 0xff;
card += 2;
len -= 2;
}
if (len == 1)
- *to = bus_mem_read_2(bc, memh, card) & 0xff;
+ *to = bus_space_read_2(memt, memh, card) & 0xff;
} else {
while (len--)
- *to++ = bus_mem_read_1(bc, memh, card++);
+ *to++ = bus_space_read_1(memt, memh, card++);
}
}
#endif
#include <machine/cpu.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/ic/elink3var.h>
void *match, *aux;
{
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int slot, iobase, irq, i;
u_int16_t vendor, model;
struct ep_isa_done_probe *er;
/*
* Map the Etherlink ID port for the probe sequence.
*/
- if (bus_io_map(bc, ELINK_ID_PORT, 1, &ioh)) {
+ if (bus_space_map(iot, ELINK_ID_PORT, 1, 0, &ioh)) {
printf("ep_isa_probe: can't map Etherlink ID port\n");
return 0;
}
for (slot = 0; slot < MAXEPCARDS; slot++) {
- elink_reset(bc, ioh, parent->dv_unit);
- elink_idseq(bc, ioh, ELINK_509_POLY);
+ elink_reset(iot, ioh, parent->dv_unit);
+ elink_idseq(iot, ioh, ELINK_509_POLY);
/* Untag all the adapters so they will talk to us. */
if (slot == 0)
- bus_io_write_1(bc, ioh, 0, TAG_ADAPTER + 0);
+ bus_space_write_1(iot, ioh, 0, TAG_ADAPTER + 0);
- vendor = htons(epreadeeprom(bc, ioh, EEPROM_MFG_ID));
+ vendor = htons(epreadeeprom(iot, ioh, EEPROM_MFG_ID));
if (vendor != MFG_ID)
continue;
- model = htons(epreadeeprom(bc, ioh, EEPROM_PROD_ID));
+ model = htons(epreadeeprom(iot, ioh, EEPROM_PROD_ID));
if ((model & 0xfff0) != PROD_ID) {
#ifndef trusted
printf(
continue;
}
- iobase = epreadeeprom(bc, ioh, EEPROM_ADDR_CFG);
+ iobase = epreadeeprom(iot, ioh, EEPROM_ADDR_CFG);
iobase = (iobase & 0x1f) * 0x10 + 0x200;
- irq = epreadeeprom(bc, ioh, EEPROM_RESOURCE_CFG);
+ irq = epreadeeprom(iot, ioh, EEPROM_RESOURCE_CFG);
irq >>= 12;
epaddcard(bus, iobase, irq);
/* so card will not respond to contention again */
- bus_io_write_1(bc, ioh, 0, TAG_ADAPTER + 1);
+ bus_space_write_1(iot, ioh, 0, TAG_ADAPTER + 1);
/*
* XXX: this should probably not be done here
* the board. Perhaps it should be done after
* we have checked for irq/drq collisions?
*/
- bus_io_write_1(bc, ioh, 0, ACTIVATE_ADAPTER_TO_CONFIG);
+ bus_space_write_1(iot, ioh, 0, ACTIVATE_ADAPTER_TO_CONFIG);
}
/* XXX should we sort by ethernet address? */
- bus_io_unmap(bc, ioh, 1);
+ bus_space_unmap(iot, ioh, 1);
bus_probed:
{
struct ep_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
u_short conn = 0;
/* Map i/o space. */
- if (bus_io_map(bc, ia->ia_iobase, ia->ia_iosize, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, ia->ia_iosize, 0, &ioh))
panic("ep_isa_attach: can't map i/o space");
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->bustype = EP_BUS_ISA;
GO_WINDOW(0);
- conn = bus_io_read_2(bc, ioh, EP_W0_CONFIG_CTRL);
+ conn = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL);
printf(": <3Com 3C509 Ethernet> ");
-/* $OpenBSD: if_ie.c,v 1.15 1996/11/12 20:30:37 niklas Exp $ */
+/* $OpenBSD: if_ie.c,v 1.16 1996/11/29 22:55:00 niklas Exp $ */
/* $NetBSD: if_ie.c,v 1.51 1996/05/12 23:52:48 mycroft Exp $ */
/*-
#include <machine/cpu.h>
#include <machine/pio.h> /* XXX convert this driver! */
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isareg.h>
struct ie_softc *sc;
struct isa_attach_args *ia;
{
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
u_char c;
int i, rval = 0;
u_char signature[] = "*3COM*";
/*
* Map the Etherlink ID port for the probe sequence.
*/
- if (bus_io_map(bc, ELINK_ID_PORT, 1, &ioh)) {
+ if (bus_space_map(iot, ELINK_ID_PORT, 1, 0, &ioh)) {
printf("3c507 probe: can't map Etherlink ID port\n");
return 0;
}
* Reset and put card in CONFIG state without changing address.
* XXX Indirect brokenness here!
*/
- elink_reset(bc, ioh, sc->sc_dev.dv_parent->dv_unit);
- elink_idseq(bc, ioh, ELINK_507_POLY);
- elink_idseq(bc, ioh, ELINK_507_POLY);
+ elink_reset(iot, ioh, sc->sc_dev.dv_parent->dv_unit);
+ elink_idseq(iot, ioh, ELINK_507_POLY);
+ elink_idseq(iot, ioh, ELINK_507_POLY);
outb(ELINK_ID_PORT, 0xff);
/* Check for 3COM signature before proceeding. */
/* Go to RUN state. */
outb(ELINK_ID_PORT, 0x00);
- elink_idseq(bc, ioh, ELINK_507_POLY);
+ elink_idseq(iot, ioh, ELINK_507_POLY);
outb(ELINK_ID_PORT, 0x00);
/* Set bank 2 for version info and read BCD version byte. */
rval = 1;
out:
- bus_io_unmap(bc, ioh, 1);
+ bus_space_unmap(iot, ioh, 1);
return rval;
}
struct am7990_softc sc_am7990; /* glue to MI code */
void *sc_ih;
- bus_io_handle_t sc_ioh;
+ bus_space_handle_t sc_ioh;
int sc_card;
int sc_rap, sc_rdp; /* offsets to LANCE registers */
};
-/* $OpenBSD: isa.c,v 1.19 1996/11/23 21:46:41 kstailey Exp $ */
+/* $OpenBSD: isa.c,v 1.20 1996/11/29 22:55:01 niklas Exp $ */
/* $NetBSD: isa.c,v 1.85 1996/05/14 00:31:04 thorpej Exp $ */
/*-
isa_attach_hook(parent, self, iba);
printf("\n");
- sc->sc_bc = iba->iba_bc;
+ sc->sc_iot = iba->iba_iot;
+ sc->sc_memt = iba->iba_memt;
sc->sc_ic = iba->iba_ic;
/*
* Map port 0x84, which causes a 1.25us delay when read.
* We do this now, since several drivers need it.
*/
- if (bus_io_map(sc->sc_bc, 0x84, 1, &sc->sc_delayioh))
+ if (bus_space_map(sc->sc_iot, 0x84, 1, 0, &sc->sc_delaybah))
panic("isaattach: can't map `delay port'"); /* XXX */
TAILQ_INIT(&sc->sc_subdevs);
irq_map = find_emap("irq");
drq_map = find_emap("drq");
- ia.ia_bc = sc->sc_bc;
+ ia.ia_iot = sc->sc_iot;
+ ia.ia_memt = sc->sc_memt;
ia.ia_ic = sc->sc_ic;
ia.ia_iobase = cf->cf_loc[0];
ia.ia_iosize = 0x666;
ia.ia_msize = cf->cf_loc[3];
ia.ia_irq = cf->cf_loc[4] == 2 ? 9 : cf->cf_loc[4];
ia.ia_drq = cf->cf_loc[5];
- ia.ia_delayioh = sc->sc_delayioh;
+ ia.ia_delaybah = sc->sc_delaybah;
if (cf->cf_fstate == FSTATE_STAR) {
struct isa_attach_args ia2 = ia;
-/* $OpenBSD: isadma.c,v 1.9 1996/11/23 21:46:41 kstailey Exp $ */
+/* $OpenBSD: isadma.c,v 1.10 1996/11/29 22:55:01 niklas Exp $ */
/* $NetBSD: isadma.c,v 1.19 1996/04/29 20:03:26 christos Exp $ */
#include <sys/param.h>
#include <vm/vm.h>
+#include <machine/bus.h>
#include <machine/pio.h>
#include <dev/isa/isareg.h>
struct isadma_seg phys[1];
};
+static struct isadma_softc *isadma_sc; /*XXX ugly */
static struct dma_info dma_info[8];
static u_int8_t dma_finished;
/* high byte of address is stored in this port for i-th dma channel */
static int dmapageport[2][4] = {
- {0x87, 0x83, 0x81, 0x82},
- {0x8f, 0x8b, 0x89, 0x8a}
+ {0x7, 0x3, 0x1, 0x2},
+ {0xf, 0xb, 0x9, 0xa}
};
static u_int8_t dmamode[4] = {
void isadmaattach __P((struct device *, struct device *, void *));
int isadmaprint __P((void *, const char *));
+struct isadma_softc {
+ struct device sc_dev;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh1;
+ bus_space_handle_t sc_ioh2;
+ bus_space_handle_t sc_iohpg;
+};
+
struct cfattach isadma_ca = {
sizeof(struct device), isadmamatch, isadmaattach
};
struct device *parent, *self;
void *aux;
{
+ struct isadma_softc *sc = (void *)self;
+ struct isa_attach_args *ia = aux;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+
printf("\n");
+ iot = sc->sc_iot = ia->ia_iot;
+ if (bus_space_map(iot, IO_DMA1, DMA_NREGS(1), 0, &ioh))
+ panic("isadmaattach: couldn't map I/O ports at IO_DMA1");
+ sc->sc_ioh1 = ioh;
+ if (bus_space_map(iot, IO_DMA2, DMA_NREGS(2), 0, &ioh))
+ panic("isadmaattach: couldn't map I/O ports at IO_DMA2");
+ sc->sc_ioh2 = ioh;
+ if (bus_space_map(iot, IO_DMAPG, 16 /* XXX */, 0, &ioh))
+ panic("isadmaattach: couldn't map I/O ports at IO_DMAPG");
+ sc->sc_iohpg = ioh;
+ isadma_sc = sc;
}
/*
isadma_cascade(chan)
int chan;
{
+ struct isadma_softc *sc = isadma_sc;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh;
+ int dma_unit;
#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7)
/* set dma channel mode, and set dma channel mode */
if ((chan & 4) == 0) {
- outb(DMA1_MODE, chan | DMA37MD_CASCADE);
- outb(DMA1_SMSK, chan);
+ ioh = sc->sc_ioh1;
+ dma_unit = 1;
} else {
+ ioh = sc->sc_ioh2;
chan &= 3;
-
- outb(DMA2_MODE, chan | DMA37MD_CASCADE);
- outb(DMA2_SMSK, chan);
+ dma_unit = 2;
}
+ bus_space_write_1(iot, ioh, DMA_MODE(dma_unit),
+ chan | DMA37MD_CASCADE);
+ bus_space_write_1(iot, ioh, DMA_SMSK(dma_unit), chan);
}
/*
int chan;
int flags;
{
+ struct isadma_softc *sc = isadma_sc;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh;
struct dma_info *di;
int waport;
int mflags;
+ int dma_unit;
#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7 ||
* Program one of DMA channels 0..3. These are
* byte mode channels.
*/
- /* set dma channel mode, and reset address ff */
- outb(DMA1_MODE, chan | dmamode[flags]);
- outb(DMA1_FFC, 0);
-
- /* send start address */
- waport = DMA1_CHN(chan);
- outb(dmapageport[0][chan], di->phys[0].addr>>16);
- outb(waport, di->phys[0].addr);
- outb(waport, di->phys[0].addr>>8);
-
- /* send count */
- outb(waport + 1, --nbytes);
- outb(waport + 1, nbytes>>8);
-
- /* unmask channel */
- outb(DMA1_SMSK, chan | DMA37SM_CLEAR);
+ ioh = sc->sc_ioh1;
+ dma_unit = 1;
} else {
/*
* Program one of DMA channels 4..7. These are
* word mode channels.
*/
- /* set dma channel mode, and reset address ff */
- outb(DMA2_MODE, (chan & 3) | dmamode[flags]);
- outb(DMA2_FFC, 0);
-
- /* send start address */
- waport = DMA2_CHN(chan & 3);
- outb(dmapageport[1][chan], di->phys[0].addr>>16);
- outb(waport, di->phys[0].addr>>1);
- outb(waport, di->phys[0].addr>>9);
-
- /* send count */
+ ioh = sc->sc_ioh2;
+ dma_unit = 2;
+ chan &= 3;
nbytes >>= 1;
- outb(waport + 2, --nbytes);
- outb(waport + 2, nbytes>>8);
-
- /* unmask channel */
- outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR);
}
+ /* set dma channel mode, and reset address ff */
+ bus_space_write_1(iot, ioh, DMA_MODE(dma_unit), chan | dmamode[flags]);
+ bus_space_write_1(iot, ioh, DMA_FFC(dma_unit), 0);
+
+ /* send start address */
+ waport = DMA_CHN(dma_unit, chan);
+ bus_space_write_1(iot, sc->sc_iohpg,
+ dmapageport[dma_unit - 1][chan], di->phys[0].addr>>16);
+ bus_space_write_1(iot, ioh, waport, di->phys[0].addr);
+ bus_space_write_1(iot, ioh, waport, di->phys[0].addr>>8);
+
+ /* send count */
+ bus_space_write_1(iot, ioh, waport + dma_unit, --nbytes & 0xff);
+ bus_space_write_1(iot, ioh, waport + dma_unit, nbytes >> 8);
+
+ /* unmask channel */
+ bus_space_write_1(iot, ioh, DMA_SMSK(dma_unit), chan | DMA37SM_CLEAR);
}
void
isadma_abort(chan)
int chan;
{
+ struct isadma_softc *sc = isadma_sc;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh;
struct dma_info *di;
+ int dma_unit;
#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7)
}
/* mask channel */
- if ((chan & 4) == 0)
- outb(DMA1_SMSK, DMA37SM_SET | chan);
- else
- outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
-
+ if ((chan & 4) == 0) {
+ ioh = sc->sc_ioh1;
+ dma_unit = 1;
+ } else {
+ ioh = sc->sc_ioh2;
+ chan &= 3;
+ dma_unit = 2;
+ }
+ bus_space_write_1(iot, ioh, DMA_SMSK(dma_unit), DMA37SM_SET | chan);
isadma_unmap(di->addr, di->nbytes, 1, di->phys);
di->active = 0;
}
isadma_finished(chan)
int chan;
{
+ struct isadma_softc *sc = isadma_sc;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh;
+ int dma_unit;
#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7)
#endif
/* check that the terminal count was reached */
- if ((chan & 4) == 0)
- dma_finished |= inb(DMA1_SR) & 0x0f;
- else
- dma_finished |= (inb(DMA2_SR) & 0x0f) << 4;
-
+ if ((chan & 4) == 0) {
+ ioh = sc->sc_ioh1;
+ dma_unit = 1;
+ } else {
+ ioh = sc->sc_ioh2;
+ chan &= 3;
+ dma_unit = 2;
+ }
+ dma_finished |= bus_space_read_1(iot, ioh, DMA_SR(dma_unit)) & 0x0f;
return ((dma_finished & (1 << chan)) != 0);
}
isadma_done(chan)
int chan;
{
+ struct isadma_softc *sc = isadma_sc;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh;
+ int dma_unit;
struct dma_info *di;
u_char tc;
}
/* check that the terminal count was reached */
- if ((chan & 4) == 0)
- tc = inb(DMA1_SR) & (1 << chan);
- else
- tc = inb(DMA2_SR) & (1 << (chan & 3));
+ if ((chan & 4) == 0) {
+ ioh = sc->sc_ioh1;
+ dma_unit = 1;
+ } else {
+ ioh = sc->sc_ioh2;
+ chan &= 3;
+ dma_unit = 2;
+ }
+ tc = bus_space_read_1(iot, ioh, DMA_SR(dma_unit)) & (1 << chan);
+
if (tc == 0)
/* XXX probably should panic or something */
- log(LOG_ERR, "dma channel %d not finished\n", chan);
+ log(LOG_ERR, "dma channel %d not finished\n",
+ dma_unit == 1 ? chan : (chan | 4));
/* mask channel */
- if ((chan & 4) == 0)
- outb(DMA1_SMSK, DMA37SM_SET | chan);
- else
- outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
+ bus_space_write_1(iot, ioh, DMA_SMSK(dma_unit), DMA37SM_SET | chan);
/* XXX Will this do what we want with DMAMODE_LOOP? */
if (di->flags & DMAMODE_READ)
+/* $OpenBSD: isadmareg.h,v 1.2 1996/11/29 22:55:02 niklas Exp $ */
/* $NetBSD: isadmareg.h,v 1.4 1995/06/28 04:31:48 cgd Exp $ */
#include <dev/ic/i8237reg.h>
/*
- * Register definitions for DMA controller 1 (channels 0..3):
+ * Register definitions for the DMA controllers
*/
-#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
-#define DMA1_SR (IO_DMA1 + 1*8) /* status register */
-#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
-#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
-#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
+#define DMA_CHN(u, c) ((u) * (2 * (c))) /* addr reg for channel c */
+#define DMA_SR(u) ((u) * 8) /* status register */
+#define DMA_SMSK(u) ((u) * 10) /* single mask register */
+#define DMA_MODE(u) ((u) * 11) /* mode register */
+#define DMA_FFC(u) ((u) * 12) /* clear first/last FF */
-/*
- * Register definitions for DMA controller 2 (channels 4..7):
- */
-#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
-#define DMA2_SR (IO_DMA2 + 2*8) /* status register */
-#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
-#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
-#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
+#define DMA_NREGS(u) ((u) * 13) /* XXX true? */
-/* $OpenBSD: isadmavar.h,v 1.4 1996/04/22 20:03:05 hannken Exp $ */
+/* $OpenBSD: isadmavar.h,v 1.5 1996/11/29 22:55:02 niklas Exp $ */
/* $NetBSD: isadmavar.h,v 1.4 1996/03/01 04:08:46 mycroft Exp $ */
#define DMAMODE_WRITE 0
-/* $OpenBSD: isapnp.c,v 1.8 1996/11/23 21:46:42 kstailey Exp $ */
+/* $OpenBSD: isapnp.c,v 1.9 1996/11/29 22:55:03 niklas Exp $ */
/*
* Copyright (c) 1996, Shawn Hsiao <shawn@alpha.secc.fju.edu.tw>
#include <sys/malloc.h>
#include <sys/queue.h>
#include <sys/extent.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include "isapnpreg.h"
#include "isapnpvar.h"
-#define SEND(d, r) { bus_io_write_1(sc->bc, sc->addrh, 0, d); \
- bus_io_write_1(sc->bc, sc->wdh, 0, r); }
+#define SEND(d, r) { bus_space_write_1(sc->iot, sc->addrh, 0, d); \
+ bus_space_write_1(sc->iot, sc->wdh, 0, r); }
int isapnpmatch __P((struct device *, void *, void *));
void isapnpattach __P((struct device *, struct device *, void *));
struct device sc_dev;
struct device *parent;
- bus_chipset_tag_t bc;
- bus_io_handle_t addrh;
- bus_io_handle_t wdh;
- bus_io_handle_t rdh;
+ bus_space_tag_t iot;
+ bus_space_handle_t addrh;
+ bus_space_handle_t wdh;
+ bus_space_handle_t rdh;
int rd_offset;
int rd_port;
*/
isc->pnpsc = sc;
- sc->bc = ia->ia_bc;
+ sc->iot = ia->ia_iot;
sc->parent = parent;
TAILQ_INIT(&sc->q_card);
* from ADDRESS port,
* and valid READ_DATA ports are from 0x203 to 0x3ff.
*/
- if (bus_io_map(sc->bc, ADDRESS, 1, &(sc->addrh)) ||
- bus_io_map(sc->bc, ADDRESS+0x0800, 1, &(sc->wdh)) ||
- bus_io_map(sc->bc, 0x0200, 0x200, &(sc->rdh)))
+ if (bus_space_map(sc->iot, ADDRESS, 1, 0, &(sc->addrh)) ||
+ bus_space_map(sc->iot, ADDRESS+0x0800, 1, 0, &(sc->wdh)) ||
+ bus_space_map(sc->iot, 0x0200, 0x200, 0, &(sc->rdh)))
panic("isapnpattach: io mapping failed");
/* Try various READ_DATA ports from 0x203-0x3ff */
struct isa_attach_args ia;
bzero(&ia, sizeof(ia));
- ia.ia_bc = iba->iba_bc;
+ ia.ia_iot = iba->iba_iot;
ia.ia_ic = iba->iba_ic;
ia.id = dev->id;
ia.comp_id = dev->comp_id;
send_Initiation_LFSR(sc)
struct isapnp_softc *sc;
{
- bus_chipset_tag_t bc = sc->bc;
- bus_io_handle_t addrh = sc->addrh;
+ bus_space_tag_t iot = sc->iot;
+ bus_space_handle_t addrh = sc->addrh;
int cur, i;
/* Reset the LSFR */
- bus_io_write_1(bc, addrh, 0, 0);
- bus_io_write_1(bc, addrh, 0, 0);
+ bus_space_write_1(iot, addrh, 0, 0);
+ bus_space_write_1(iot, addrh, 0, 0);
cur = 0x6a;
- bus_io_write_1(bc, addrh, 0, cur);
+ bus_space_write_1(iot, addrh, 0, cur);
for (i = 1; i < 32; i++) {
cur = (cur >> 1) | (((cur ^ (cur >> 1)) << 7) & 0xff);
- bus_io_write_1(bc, addrh, 0, cur);
+ bus_space_write_1(iot, addrh, 0, cur);
}
}
struct isapnp_softc *sc;
unsigned char *data;
{
- bus_chipset_tag_t bc = sc->bc;
- bus_io_handle_t rdh = sc->rdh;
+ bus_space_tag_t iot = sc->iot;
+ bus_space_handle_t rdh = sc->rdh;
int i, bit, valid = 0, sum = 0x6a;
sc->rd_offset = ((sc->rd_port - 0x80) << 2) | 0x3;
for (i = 0; i < 72; i++) {
- bit = bus_io_read_1(bc, rdh, sc->rd_offset) == 0x55;
+ bit = bus_space_read_1(iot, rdh, sc->rd_offset) == 0x55;
delay(250); /* Delay 250 usec */
/* Can't Short Circuit the next evaluation, so 'and' is last */
- bit = (bus_io_read_1(bc, rdh, sc->rd_offset) == 0xaa) && bit;
+ bit = (bus_space_read_1(iot, rdh, sc->rd_offset) == 0xaa) &&
+ bit;
delay(250); /* Delay 250 usec */
valid = valid || bit;
int i, j;
for (i = 0; i < len; i++) {
- bus_io_write_1(sc->bc, sc->addrh, 0, STATUS);
+ bus_space_write_1(sc->iot, sc->addrh, 0, STATUS);
for (j = 0; j < 100; j++) {
- if ((bus_io_read_1(sc->bc, sc->rdh, sc->rd_offset))
+ if ((bus_space_read_1(sc->iot, sc->rdh, sc->rd_offset))
& 0x1)
break;
delay(1);
sc->sc_dev.dv_xname);
return 0;
}
- bus_io_write_1(sc->bc, sc->addrh, 0, RESOURCE_DATA);
- buffer[i] = bus_io_read_1(sc->bc, sc->rdh, sc->rd_offset);
+ bus_space_write_1(sc->iot, sc->addrh, 0, RESOURCE_DATA);
+ buffer[i] = bus_space_read_1(sc->iot, sc->rdh, sc->rd_offset);
}
return 1;
}
/* Wake up cards without a CSN */
SEND(WAKE, 0);
SEND(SET_RD_DATA, sc->rd_port);
- bus_io_write_1(sc->bc, sc->addrh, 0, SERIAL_ISOLATION);
+ bus_space_write_1(sc->iot, sc->addrh, 0, SERIAL_ISOLATION);
delay(1000); /* Delay 1 msec */
if (get_serial(sc, data)) {
int desc, min_addr, max_addr, size, alignment, range_check;
{
int addr, i, success = 0;
- bus_io_handle_t data;
+ bus_space_handle_t data;
struct emap *io_map;
if (range_check) {
SEND(IO_CONFIG_BASE + desc * 2, addr >> 8);
SEND(IO_CONFIG_BASE + desc * 2 + 1, addr & 0xff);
SEND(IO_RANGE_CHECK, 0x2);
- bus_io_map(sc->bc, addr, size, &data);
+ bus_space_map(sc->iot, addr, size, 0, &data);
i = 0;
for (i = 0; i < size; i++) {
- if (bus_io_read_1(sc->bc, data, i) != 0xAA) {
- bus_io_unmap(sc->bc, data, size);
+ if (bus_space_read_1(sc->iot, data, i) !=
+ 0xAA) {
+ bus_space_unmap(sc->iot, data, size);
break;
}
}
if (i == size) {
success = 1;
- bus_io_unmap(sc->bc, data, size);
+ bus_space_unmap(sc->iot, data, size);
break;
}
}
-/* $OpenBSD: isavar.h,v 1.19 1996/11/23 21:46:43 kstailey Exp $ */
-/* $NetBSD: isavar.h,v 1.23 1996/05/08 23:32:31 thorpej Exp $ */
+/* $OpenBSD: isavar.h,v 1.20 1996/11/29 22:55:04 niklas Exp $ */
+/* $NetBSD: isavar.h,v 1.24 1996/10/21 22:41:11 thorpej Exp $ */
/*
* Copyright (c) 1995 Chris G. Demetriou
*/
#include <sys/queue.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
/*
* Structures and definitions needed by the machine-dependent header.
* ISA bus attach arguments
*/
struct isabus_attach_args {
- char *iba_busname; /* XXX should be common */
- bus_chipset_tag_t iba_bc; /* XXX should be common */
+ char *iba_busname; /* XXX should be common */
+ bus_space_tag_t iba_iot; /* isa i/o space tag */
+ bus_space_tag_t iba_memt; /* isa mem space tag */
isa_chipset_tag_t iba_ic;
};
* ISA driver attach arguments
*/
struct isa_attach_args {
- bus_chipset_tag_t ia_bc;
+ bus_space_tag_t ia_iot; /* isa i/o space tag */
+ bus_space_tag_t ia_memt; /* isa mem space tag */
+
isa_chipset_tag_t ia_ic;
int ia_iobase; /* base i/o address */
u_int ia_msize; /* size of i/o memory */
void *ia_aux; /* driver specific */
- bus_io_handle_t ia_delayioh; /* i/o handle for `delay port' */
+ bus_space_handle_t ia_delaybah; /* i/o handle for `delay port' */
/* XXX need fixes, some are duplicated */
/* begin isapnp section */
TAILQ_HEAD(, isadev)
sc_subdevs; /* list of all children */
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot; /* isa io space tag */
+ bus_space_tag_t sc_memt; /* isa mem space tag */
+
isa_chipset_tag_t sc_ic;
/*
* This i/o handle is used to map port 0x84, which is
- * read to provide a 1.25us delay. This i/o handle
+ * read to provide a 1.25us delay. This access handle
* is mapped in isaattach(), and exported to drivers
* via isa_attach_args.
*/
- bus_io_handle_t sc_delayioh;
+ bus_space_handle_t sc_delaybah;
/*
* This points to the isapnp_softc structure that holds
-/* $OpenBSD: lpt.c,v 1.19 1996/11/12 20:30:41 niklas Exp $ */
-/* $NetBSD: lpt.c,v 1.39 1996/05/12 23:53:06 mycroft Exp $ */
+/* $OpenBSD: lpt.c,v 1.20 1996/11/29 22:55:04 niklas Exp $ */
+/* $NetBSD: lpt.c,v 1.42 1996/10/21 22:41:14 thorpej Exp $ */
/*
* Copyright (c) 1993, 1994 Charles Hannum.
#include <sys/conf.h>
#include <sys/syslog.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
#include <dev/isa/lptreg.h>
+#include "lpt.h"
+
#define TIMEOUT hz*16 /* wait up to 16 seconds for a ready */
#define STEP hz/4
u_char *sc_cp;
int sc_spinmax;
int sc_iobase;
- bus_chipset_tag_t sc_bc;
- bus_io_handle_t sc_ioh;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
int sc_irq;
u_char sc_state;
#define LPT_OPEN 0x01 /* device is open */
int lptintr __P((void *));
-int lptprobe __P((struct device *, void *, void *));
-void lptattach __P((struct device *, struct device *, void *));
+#if NLPT_ISA
+int lpt_isa_probe __P((struct device *, void *, void *));
+void lpt_isa_attach __P((struct device *, struct device *, void *));
struct cfattach lpt_isa_ca = {
- sizeof(struct lpt_softc), lptprobe, lptattach
+ sizeof(struct lpt_softc), lpt_isa_probe, lpt_isa_attach
};
+#endif
struct cfdriver lpt_cd = {
NULL, "lpt", DV_TTY
#define LPS_INVERT (LPS_SELECT|LPS_NERR|LPS_NBSY|LPS_NACK)
#define LPS_MASK (LPS_SELECT|LPS_NERR|LPS_NBSY|LPS_NACK|LPS_NOPAPER)
-#define NOT_READY() ((bus_io_read_1(bc, ioh, lpt_status) ^ LPS_INVERT) & LPS_MASK)
-#define NOT_READY_ERR() not_ready(bus_io_read_1(bc, ioh, lpt_status), sc)
+#define NOT_READY() ((bus_space_read_1(iot, ioh, lpt_status) ^ LPS_INVERT) & LPS_MASK)
+#define NOT_READY_ERR() not_ready(bus_space_read_1(iot, ioh, lpt_status), sc)
static int not_ready __P((u_char, struct lpt_softc *));
static void lptwakeup __P((void *arg));
static int pushbytes __P((struct lpt_softc *));
-int lpt_port_test __P((bus_chipset_tag_t, bus_io_handle_t, bus_io_addr_t,
- bus_io_size_t, u_char, u_char));
+int lpt_port_test __P((bus_space_tag_t, bus_space_handle_t, bus_addr_t,
+ bus_size_t, u_char, u_char));
/*
* Internal routine to lptprobe to do port tests of one byte value.
*/
int
-lpt_port_test(bc, ioh, base, off, data, mask)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
- bus_io_addr_t base;
- bus_io_size_t off;
+lpt_port_test(iot, ioh, base, off, data, mask)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+ bus_addr_t base;
+ bus_size_t off;
u_char data, mask;
{
int timeout;
u_char temp;
data &= mask;
- bus_io_write_1(bc, ioh, off, data);
+ bus_space_write_1(iot, ioh, off, data);
timeout = 1000;
do {
delay(10);
- temp = bus_io_read_1(bc, ioh, off) & mask;
+ temp = bus_space_read_1(iot, ioh, off) & mask;
} while (temp != data && --timeout);
LPRINTF(("lpt: port=0x%x out=0x%x in=0x%x timeout=%d\n", base + off,
data, temp, timeout));
*
* 3) Set the data and control ports to a value of 0
*/
+#if NLPT_ISA
int
-lptprobe(parent, match, aux)
+lpt_isa_probe(parent, match, aux)
struct device *parent;
void *match, *aux;
{
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_long base;
u_char mask, data;
int i, rv;
#ifdef DEBUG
-#define ABORT do {printf("lptprobe: mask %x data %x failed\n", mask, data); \
- goto out;} while (0)
+#define ABORT \
+ do { \
+ printf("lpt_isa_probe: mask %x data %x failed\n", mask, \
+ data); \
+ goto out; \
+ } while (0)
#else
#define ABORT goto out
#endif
- bc = ia->ia_bc;
+ iot = ia->ia_iot;
base = ia->ia_iobase;
- if (bus_io_map(bc, base, LPT_NPORTS, &ioh))
+ if (bus_space_map(iot, base, LPT_NPORTS, 0, &ioh))
return 0;
rv = 0;
mask = 0xff;
data = 0x55; /* Alternating zeros */
- if (!lpt_port_test(bc, ioh, base, lpt_data, data, mask))
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
ABORT;
data = 0xaa; /* Alternating ones */
- if (!lpt_port_test(bc, ioh, base, lpt_data, data, mask))
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
ABORT;
for (i = 0; i < CHAR_BIT; i++) { /* Walking zero */
data = ~(1 << i);
- if (!lpt_port_test(bc, ioh, base, lpt_data, data, mask))
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
ABORT;
}
for (i = 0; i < CHAR_BIT; i++) { /* Walking one */
data = (1 << i);
- if (!lpt_port_test(bc, ioh, base, lpt_data, data, mask))
+ if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))
ABORT;
}
- bus_io_write_1(bc, ioh, lpt_data, 0);
- bus_io_write_1(bc, ioh, lpt_control, 0);
+ bus_space_write_1(iot, ioh, lpt_data, 0);
+ bus_space_write_1(iot, ioh, lpt_control, 0);
ia->ia_iosize = LPT_NPORTS;
ia->ia_msize = 0;
rv = 1;
out:
- bus_io_unmap(bc, ioh, LPT_NPORTS);
+ bus_space_unmap(iot, ioh, LPT_NPORTS);
return rv;
}
+#endif
+#if NLPT_ISA
void
-lptattach(parent, self, aux)
+lpt_isa_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct lpt_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
if (ia->ia_irq != IRQUNK)
printf("\n");
sc->sc_irq = ia->ia_irq;
sc->sc_state = 0;
- bc = sc->sc_bc = ia->ia_bc;
- if (bus_io_map(bc, sc->sc_iobase, LPT_NPORTS, &ioh))
- panic("lptattach: couldn't map I/O ports");
+ iot = sc->sc_iot = ia->ia_iot;
+ if (bus_space_map(iot, sc->sc_iobase, LPT_NPORTS, 0, &ioh))
+ panic("lpt_isa_attach: couldn't map I/O ports");
sc->sc_ioh = ioh;
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
+ bus_space_write_1(iot, ioh, lpt_control, LPC_NINIT);
if (ia->ia_irq != IRQUNK)
sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE,
IPL_TTY, lptintr, sc, sc->sc_dev.dv_xname);
}
+#endif
/*
* Reset the printer, then wait until it's selected and not busy.
int unit = LPTUNIT(dev);
u_char flags = LPTFLAGS(dev);
struct lpt_softc *sc;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_char control;
int error;
int spin;
sc->sc_state = LPT_INIT;
sc->sc_flags = flags;
LPRINTF(("%s: open: flags=0x%x\n", sc->sc_dev.dv_xname, flags));
- bc = sc->sc_bc;
+ iot = sc->sc_iot;
ioh = sc->sc_ioh;
if ((flags & LPT_NOPRIME) == 0) {
/* assert INIT for 100 usec to start up printer */
- bus_io_write_1(bc, ioh, lpt_control, LPC_SELECT);
+ bus_space_write_1(iot, ioh, lpt_control, LPC_SELECT);
delay(100);
}
control = LPC_SELECT | LPC_NINIT;
- bus_io_write_1(bc, ioh, lpt_control, control);
+ bus_space_write_1(iot, ioh, lpt_control, control);
/* wait till ready (printer running diagnostics) */
for (spin = 0; NOT_READY_ERR(); spin += STEP) {
if (flags & LPT_AUTOLF)
control |= LPC_AUTOLF;
sc->sc_control = control;
- bus_io_write_1(bc, ioh, lpt_control, control);
+ bus_space_write_1(iot, ioh, lpt_control, control);
sc->sc_inbuf = geteblk(LPT_BSIZE);
sc->sc_count = 0;
{
int unit = LPTUNIT(dev);
struct lpt_softc *sc = lpt_cd.cd_devs[unit];
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
if (sc->sc_count)
(void) pushbytes(sc);
if ((sc->sc_flags & LPT_NOINTR) == 0)
untimeout(lptwakeup, sc);
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
+ bus_space_write_1(iot, ioh, lpt_control, LPC_NINIT);
sc->sc_state = 0;
- bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
+ bus_space_write_1(iot, ioh, lpt_control, LPC_NINIT);
brelse(sc->sc_inbuf);
LPRINTF(("%s: closed\n", sc->sc_dev.dv_xname));
pushbytes(sc)
struct lpt_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
int error;
if (sc->sc_flags & LPT_NOINTR) {
break;
}
- bus_io_write_1(bc, ioh, lpt_data, *sc->sc_cp++);
- bus_io_write_1(bc, ioh, lpt_control, control | LPC_STROBE);
+ bus_space_write_1(iot, ioh, lpt_data, *sc->sc_cp++);
+ bus_space_write_1(iot, ioh, lpt_control, control | LPC_STROBE);
sc->sc_count--;
- bus_io_write_1(bc, ioh, lpt_control, control);
+ bus_space_write_1(iot, ioh, lpt_control, control);
/* adapt busy-wait algorithm */
if (spin*2 + 16 < sc->sc_spinmax)
void *arg;
{
struct lpt_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
if (((sc->sc_state & LPT_OPEN) == 0 && sc->sc_count == 0) || (sc->sc_flags & LPT_NOINTR))
return 0;
if (sc->sc_count) {
u_char control = sc->sc_control;
/* send char */
- bus_io_write_1(bc, ioh, lpt_data, *sc->sc_cp++);
+ bus_space_write_1(iot, ioh, lpt_data, *sc->sc_cp++);
delay (50);
- bus_io_write_1(bc, ioh, lpt_control, control | LPC_STROBE);
+ bus_space_write_1(iot, ioh, lpt_control, control | LPC_STROBE);
sc->sc_count--;
- bus_io_write_1(bc, ioh, lpt_control, control);
+ bus_space_write_1(iot, ioh, lpt_control, control);
sc->sc_state |= LPT_OBUSY;
} else
sc->sc_state &= ~LPT_OBUSY;
-/* $OpenBSD: opti.h,v 1.3 1996/05/03 12:01:05 mickey Exp $ */
+/* $OpenBSD: opti.h,v 1.4 1996/11/29 22:55:05 niklas Exp $ */
/*
* Copyright (c) 1996 Michael Shalayeff
-/* $OpenBSD: pcmcia_isa.c,v 1.8 1996/11/23 21:46:44 kstailey Exp $ */
+/* $OpenBSD: pcmcia_isa.c,v 1.9 1996/11/29 22:55:05 niklas Exp $ */
/*
* Copyright (c) 1995,1996 John T. Kohl. All rights reserved.
* Copyright (c) 1994 Stefan Grefen. All rights reserved.
#include <sys/device.h>
#include <vm/vm.h>
+#include <machine/bus.h>
+
#include <dev/pcmcia/pcmciavar.h>
#include <dev/pcmcia/pcmciareg.h>
int flag;
{
struct pcmciabus_attach_args *pa = aux;
- bus_mem_handle_t memh;
+ bus_space_handle_t memh;
#ifdef PCMCIA_ISA_DEBUG
if (parent != NULL)
printf("PARENT %s\n", parent->dv_xname);
#endif
if (flag == 0) { /* match */
- if (bus_mem_map(pa->pba_bc, pa->pba_maddr, pa->pba_msize, 0,
- &memh))
+ if (bus_space_map(pa->pba_memt, pa->pba_maddr, pa->pba_msize,
+ 0, &memh))
return 0;
pca->scratch_memsiz = pa->pba_msize;
pca->scratch_memh = memh;
- pca->pa_bc = pa->pba_bc;
+ pca->pa_memt = pa->pba_memt;
#ifdef PCMCIA_ISA_DEBUG
printf("pbaaddr %p maddr %x msize %x\n",
- pa, pa->pba_maddr, pa->pba_msize);
- printf("PCA %p mem %p size %d chip %x memh %x\n",
- pca, pca->scratch_mem, pca->scratch_memsiz,
- pca->pa_bc, pca->scratch_memh);
+ pa, pa->pba_maddr, pa->pba_msize);
+ printf("PCA %p mem %p size %d memt %x memh %x\n",
+ pca, pca->scratch_mem, pca->scratch_memsiz,
+ pca->pa_memt, pca->scratch_memh);
#endif
}
return 1;
ia.ia_msize = cf->cf_loc[3];
ia.ia_irq = cf->cf_loc[4] == 2 ? 9 : cf->cf_loc[4] ;
ia.ia_drq = cf->cf_loc[5];
- ia.ia_bc = pc_link->bus->sc_bc;
+ ia.ia_iot = pc_link->bus->sc_iot;
+ ia.ia_memt = pc_link->bus->sc_memt;
#ifdef PCMCIA_ISA_DEBUG
printf("pcmcia probe %x %x %p\n", ia.ia_iobase, ia.ia_irq,
struct softc {
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
+ bus_space_tag_t sc_memt;
} *sc = pc_link->devp;
if (sc)
- isa_intr_disestablish(sc->sc_bc, sc->sc_ih);
+ isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
}
#endif
return 0;
-/* $Id: pcmcia_pcic.c,v 1.9 1996/11/23 21:46:44 kstailey Exp $ */
+/* $Id: pcmcia_pcic.c,v 1.10 1996/11/29 22:55:06 niklas Exp $ */
/*
* Copyright (c) 1995, 1996 John T. Kohl
* All rights reserved.
#include <sys/proc.h>
#include <sys/user.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/ic/i82365reg.h>
struct pcic_softc {
struct device sc_dev;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
+ bus_space_tag_t sc_memt;
struct pcmcia_adapter sc_adapter;
void *sc_ih;
int sc_polltimo;
int sc_pcic_irq;
- bus_io_handle_t sc_ioh;
- bus_mem_handle_t sc_memh;
+ bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_memh;
u_short pcic_base; /* base port for each board */
u_char chip_inf;
struct slot slot[4]; /* treat up to 4 as on the same pcic */
};
#define pcic_parent(sc) ((struct pcicmaster_softc *)(sc)->sc_dev.dv_parent)
-static int pcic_map_io __P((struct pcmcia_link *, u_int, u_int, int));
-static int pcic_map_mem __P((struct pcmcia_link *, bus_chipset_tag_t,
- bus_mem_handle_t,
+int pcic_map_io __P((struct pcmcia_link *, u_int, u_int, int));
+int pcic_map_mem __P((struct pcmcia_link *, bus_space_tag_t, caddr_t,
u_int, u_int, int));
-static int pcic_map_intr __P((struct pcmcia_link *, int, int));
-static int pcic_service __P((struct pcmcia_link *, int, void *, int));
+int pcic_map_intr __P((struct pcmcia_link *, int, int));
+int pcic_service __P((struct pcmcia_link *, int, void *, int));
static struct pcmcia_funcs pcic_funcs = {
pcic_map_io,
int pcicmaster_probe __P((struct device *, void *, void *));
void pcicmaster_attach __P((struct device *, struct device *, void *));
int pcicmaster_print __P((void *, const char *));
+int pcic_intr __P((void *));
+
extern struct pcmciabus_link pcmcia_isa_link;
struct pcicmaster_softc {
struct device sc_dev;
- bus_chipset_tag_t sc_bc;
- bus_io_handle_t sc_ioh;
+ isa_chipset_tag_t sc_ic;
+ bus_space_tag_t sc_iot;
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_ioh;
struct pcic_softc *sc_ctlrs[2];
char sc_slavestate[2];
#define SLAVE_NOTPRESENT 0
struct pcic_attach_args {
int pia_ctlr; /* pcic ctlr number */
- bus_chipset_tag_t pia_bc; /* bus chipset tag */
- bus_io_handle_t pia_ioh; /* base i/o address */
+ isa_chipset_tag_t pia_ic; /* isa chipset tag */
+ bus_space_tag_t pia_iot; /* bus chipset tag */
+ bus_space_tag_t pia_memt; /* bus chipset tag */
+ bus_space_handle_t pia_ioh; /* base i/o address */
int pia_iosize; /* span of ports used */
int pia_irq; /* interrupt request */
int pia_drq; /* DMA request */
u_int pia_msize; /* size of i/o memory */
};
-static u_char pcic_rd __P((struct slot *, int));
-static void pcic_wr __P((struct slot *, int, int));
-
+static __inline u_char pcic_rd __P((struct slot *, int));
+static __inline void pcic_wr __P((struct slot *, int, int));
+static __inline int pcic_wait __P((struct slot *, int));
static __inline u_char
pcic_rd(slot, reg)
int reg;
{
u_char res;
- bus_chipset_tag_t bc = slot->chip->sc_bc;
- bus_io_handle_t ioh = slot->chip->sc_ioh;
+ bus_space_tag_t iot = slot->chip->sc_iot;
+ bus_space_handle_t ioh = slot->chip->sc_ioh;
if (PDEBUG(PCDRW))
printf("pcic_rd(%x [%x %x]) = ", reg, slot->reg_off, ioh);
- bus_io_write_1(bc, ioh, 0, slot->reg_off + reg);
+ bus_space_write_1(iot, ioh, 0, slot->reg_off + reg);
delay(1);
- res = bus_io_read_1(bc, ioh, 1);
+ res = bus_space_read_1(iot, ioh, 1);
if (PDEBUG(PCDRW))
printf("%x\n", res);
return res;
struct slot *slot;
int reg, val;
{
- bus_chipset_tag_t bc = slot->chip->sc_bc;
- bus_io_handle_t ioh = slot->chip->sc_ioh;
- bus_io_write_1(bc, ioh, 0, slot->reg_off + reg);
+ bus_space_tag_t iot = slot->chip->sc_iot;
+ bus_space_handle_t ioh = slot->chip->sc_ioh;
+ bus_space_write_1(iot, ioh, 0, slot->reg_off + reg);
delay(1);
- bus_io_write_1(bc, ioh, 1, val);
+ bus_space_write_1(iot, ioh, 1, val);
if (PDEBUG(PCDRW)) {
int res;
delay(1);
- bus_io_write_1(bc, ioh, 0, slot->reg_off + reg);
+ bus_space_write_1(iot, ioh, 0, slot->reg_off + reg);
delay(1);
- res = bus_io_read_1(bc, ioh, 1);
+ res = bus_space_read_1(iot, ioh, 1);
printf("pcic_wr(%x %x) = %x\n", reg, val, res);
}
}
-static __inline int pcic_wait __P((struct slot *, int));
-
static __inline int
pcic_wait(slot, i)
struct slot *slot;
struct pcic_softc *pcic = self;
struct pcicmaster_softc *pcicm = (struct pcicmaster_softc *) parent;
struct pcic_attach_args *pia = aux;
- bus_mem_handle_t memh;
+ bus_space_handle_t memh;
u_int chip_inf = 0, ochip_inf = 0;
int first = 1;
int i, j, maxslot;
* For other controllers, we only take up to 2 slots.
*/
pcic->sc_ioh = pia->pia_ioh;
- pcic->sc_bc = pia->pia_bc;
+ pcic->sc_iot = pia->pia_iot;
pcic->sc_adapter.nslots = 0;
maxslot = 2;
for (i = j = 0; i < maxslot; i++) {
printf("pcic_probe failed\n");
delay(2000000);
}
- bus_mem_unmap(pia->pia_bc, memh, pia->pia_msize);
+ bus_space_unmap(pia->pia_memt, memh, pia->pia_msize);
return 0;
}
-int
-pcic_intr __P((void *));
-
int
pcic_print(aux, name)
void *aux;
pcic->sc_polltimo = hz/2;
timeout((void (*)(void *))pcic_intr, pcic, pcic->sc_polltimo);
} else {
- pcic->sc_ih = isa_intr_establish(pia->pia_bc,
- pia->pia_irq, IST_EDGE,
- IPL_PCMCIA, pcic_intr, pcic, pcic->sc_dev.dv_xname);
+ pcic->sc_ih = isa_intr_establish(pia->pia_ic, pia->pia_irq,
+ IST_EDGE, IPL_PCMCIA, pcic_intr, pcic, pcic->sc_dev.dv_xname);
pcic->sc_polltimo = 0;
}
/*
* Probe the pcmciabus at this controller.
*/
- pba.pba_bc = pia->pia_bc;
+ pba.pba_iot = pia->pia_iot;
+ pba.pba_memt = pia->pia_memt;
pba.pba_maddr = pia->pia_maddr;
pba.pba_msize = pia->pia_msize;
pba.pba_aux = &pcic->sc_adapter;
int
pcic_intr(arg)
-void *arg;
+ void *arg;
{
struct pcic_softc *pcic = arg;
u_char statchg, intgen;
return 1;
}
-static int
+int
pcic_map_io(link, start, len, flags)
struct pcmcia_link *link;
u_int start, len;
}
}
-static int
-pcic_map_mem(link, bc, ioh, start, len, flags)
+int
+pcic_map_mem(link, memt, haddr, start, len, flags)
struct pcmcia_link *link;
- bus_chipset_tag_t bc;
- bus_mem_handle_t ioh;
+ bus_space_tag_t memt;
+ caddr_t haddr;
u_int start, len;
int flags;
{
vm_offset_t physaddr;
struct pcic_softc *sc = link->adapter->adapter_softc;
struct slot *slot;
- caddr_t haddr = ioh; /* XXX */
if (link->slot >= sc->sc_adapter.nslots)
return ENXIO;
}
}
-static int
+int
pcic_map_intr(link, irq, flags)
struct pcmcia_link *link;
int irq, flags;
}
-static int
+int
pcic_service(link, opcode, arg, flags)
struct pcmcia_link *link;
int opcode;
struct pcicmaster_softc *pcicm = self;
struct isa_attach_args *ia = aux;
struct cfdata *cf = pcicm->sc_dev.dv_cfdata;
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int chip_inf = 0;
int i, j;
- int rval = 0;
+ int rval = 0;
struct pcic_softc pcic; /* faked up for probing only */
if (PDEBUG(PCDCONF)) {
printf("pcicmaster_probe\n");
delay(2000000);
}
- bc = ia->ia_bc;
- if (bus_io_map(bc, ia->ia_iobase, PCIC_NPORTS, &ioh))
+ iot = ia->ia_iot;
+ if (bus_space_map(iot, ia->ia_iobase, PCIC_NPORTS, 0, &ioh))
return (0);
/*
* Probe the slots for each of the possible child controllers,
}
if (rval) {
ia->ia_iosize = 2;
- pcicm->sc_bc = bc;
+ pcicm->sc_ic = ia->ia_ic;
+ pcicm->sc_iot = iot;
+ pcicm->sc_memt = ia->ia_memt;
pcicm->sc_ioh = ioh;
} else
- bus_io_unmap(bc, ioh, PCIC_NPORTS);
+ bus_space_unmap(iot, ioh, PCIC_NPORTS);
return rval;
}
struct device *parent, *self;
void *aux;
{
- struct pcicmaster_softc *pcicm = (void *) self;
+ struct pcicmaster_softc *pcicm = (void *)self;
struct isa_attach_args *ia = aux;
struct pcic_attach_args pia;
int i;
+
printf("\n");
if (PDEBUG(PCDCONF)) {
printf("pcicmaster_attach\n");
/*
* share the I/O space and memory mapping space.
*/
- pia.pia_bc = pcicm->sc_bc;
+ pia.pia_ic = pcicm->sc_ic;
+ pia.pia_iot = pcicm->sc_iot;
+ pia.pia_memt = pcicm->sc_memt;
pia.pia_ioh = pcicm->sc_ioh;
pia.pia_iosize = ia->ia_iosize;
pia.pia_drq = ia->ia_drq;
-/* $OpenBSD: rtfps.c,v 1.13 1996/11/23 21:46:45 kstailey Exp $ */
-/* $NetBSD: rtfps.c,v 1.23 1996/05/12 23:53:29 mycroft Exp $ */
+/* $OpenBSD: rtfps.c,v 1.14 1996/11/29 22:55:07 niklas Exp $ */
+/* $NetBSD: rtfps.c,v 1.27 1996/10/21 22:41:18 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
#include <sys/device.h>
#include <sys/termios.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
struct device sc_dev;
void *sc_ih;
- bus_chipset_tag_t sc_bc;
+ bus_space_tag_t sc_iot;
+ isa_chipset_tag_t sc_ic;
int sc_iobase;
int sc_irqport;
- bus_io_handle_t sc_irqioh;
+ bus_space_handle_t sc_irqioh;
int sc_alive; /* mask of slave units attached */
void *sc_slaves[NSLAVES]; /* com device unit numbers */
- bus_io_handle_t sc_slaveioh[NSLAVES];
+ bus_space_handle_t sc_slaveioh[NSLAVES];
};
int rtfpsprobe __P((struct device *, void *, void *));
{
struct isa_attach_args *ia = aux;
int iobase = ia->ia_iobase;
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
int i, rv = 1;
/*
if (iobase == comconsaddr && !comconsattached)
goto checkmappings;
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- rv = comprobe1(bc, ioh, iobase);
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ rv = comprobe1(iot, ioh, iobase);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
if (rv == 0)
goto out;
if (iobase == comconsaddr && !comconsattached)
continue;
- if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
- bus_io_unmap(bc, ioh, COM_NPORTS);
+ bus_space_unmap(iot, ioh, COM_NPORTS);
}
out:
IOBASEUNK, 0x2f2, 0x6f2, 0x6f3,
IOBASEUNK, IOBASEUNK, IOBASEUNK, IOBASEUNK
};
- bus_chipset_tag_t bc = ia->ia_bc;
+ bus_space_tag_t iot = ia->ia_iot;
int i;
- sc->sc_bc = ia->ia_bc;
+ sc->sc_iot = ia->ia_iot;
+ sc->sc_ic = ia->ia_ic;
sc->sc_iobase = ia->ia_iobase;
if (ia->ia_irq >= 16 || irqport[ia->ia_irq] == IOBASEUNK)
sc->sc_irqport = irqport[ia->ia_irq];
for (i = 0; i < NSLAVES; i++)
- if (bus_io_map(bc, sc->sc_iobase + i * COM_NPORTS, COM_NPORTS,
- &sc->sc_slaveioh[i]))
+ if (bus_space_map(iot, sc->sc_iobase + i * COM_NPORTS,
+ COM_NPORTS, 0, &sc->sc_slaveioh[i]))
panic("rtfpsattach: couldn't map slave %d", i);
- if (bus_io_map(bc, sc->sc_irqport, 1, &sc->sc_irqioh))
+ if (bus_space_map(iot, sc->sc_irqport, 1, 0, &sc->sc_irqioh))
panic("rtfpsattach: couldn't map irq port at 0x%x\n",
sc->sc_irqport);
- bus_io_write_1(bc, sc->sc_irqioh, 0, 0);
+ bus_space_write_1(iot, sc->sc_irqioh, 0, 0);
printf("\n");
for (i = 0; i < NSLAVES; i++) {
ca.ca_slave = i;
- ca.ca_bc = sc->sc_bc;
+ ca.ca_iot = sc->sc_iot;
+ ca.ca_ic = sc->sc_ic;
ca.ca_ioh = sc->sc_slaveioh[i];
ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
ca.ca_noien = 0;
void *arg;
{
struct rtfps_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
+ bus_space_tag_t iot = sc->sc_iot;
int alive = sc->sc_alive;
- bus_io_write_1(bc, sc->sc_irqioh, 0, 0);
+ bus_space_write_1(iot, sc->sc_irqioh, 0, 0);
#define TRY(n) \
if (alive & (1 << (n))) \
-/* $OpenBSD: sbdspvar.h,v 1.5 1996/05/07 07:37:46 deraadt Exp $ */
+/* $OpenBSD: sbdspvar.h,v 1.6 1996/11/29 22:55:07 niklas Exp $ */
/* $NetBSD: sbdspvar.h,v 1.13 1996/04/29 20:28:50 christos Exp $ */
/*
-/* $OpenBSD: wd.c,v 1.22 1996/11/28 08:23:38 downsj Exp $ */
+/* $OpenBSD: wd.c,v 1.23 1996/11/29 22:55:08 niklas Exp $ */
/* $NetBSD: wd.c,v 1.150 1996/05/12 23:54:03 mycroft Exp $ */
/*
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h>
}
#ifndef WD_DUMP_NOT_TRUSTED
- if (wdccommand(d_link, WDCC_WRITE, d_link->sc_drive, cylin, head, sector, 1) != 0 ||
+ if (wdccommand(d_link, WDCC_WRITE, d_link->sc_drive, cylin,
+ head, sector, 1) != 0 ||
wait_for_drq(wdc) != 0) {
wderror(d_link, NULL, "wddump: write failed");
return EIO;
}
/* XXX XXX XXX */
- bus_io_write_multi_2(wdc->sc_bc, wdc->sc_ioh, wd_data,
+ bus_space_write_multi_2(wdc->sc_iot, wdc->sc_ioh, wd_data,
(u_int16_t *)va, lp->d_secsize >> 1);
/* Check data request (should be done). */
-/* $OpenBSD: wdc.c,v 1.16 1996/11/28 08:23:39 downsj Exp $ */
+/* $OpenBSD: wdc.c,v 1.17 1996/11/29 22:55:09 niklas Exp $ */
/* $NetBSD: wd.c,v 1.150 1996/05/12 23:54:03 mycroft Exp $ */
/*
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h>
struct device *parent;
void *match, *aux;
{
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
struct wdc_softc *wdc = match;
struct isa_attach_args *ia = aux;
}
#endif
- wdc->sc_bc = bc = ia->ia_bc;
- if (bus_io_map(bc, ia->ia_iobase, 8, &ioh))
+ wdc->sc_iot = iot = ia->ia_iot;
+ if (bus_space_map(iot, ia->ia_iobase, 8, 0, &ioh))
return (0);
wdc->sc_ioh = ioh;
/* Check if we have registers that work. */
/* Error register not writable, */
- bus_io_write_1(bc, ioh, wd_error, 0x5a);
+ bus_space_write_1(iot, ioh, wd_error, 0x5a);
/* but all of cyl_lo are. */
- bus_io_write_1(bc, ioh, wd_cyl_lo, 0xa5);
- if (bus_io_read_1(bc, ioh, wd_error) == 0x5a ||
- bus_io_read_1(bc, ioh, wd_cyl_lo) != 0xa5) {
+ bus_space_write_1(iot, ioh, wd_cyl_lo, 0xa5);
+ if (bus_space_read_1(iot, ioh, wd_error) == 0x5a ||
+ bus_space_read_1(iot, ioh, wd_cyl_lo) != 0xa5) {
/*
* Test for a controller with no IDE master, just one
* ATAPI device. Select drive 1, and try again.
*/
- bus_io_write_1(bc, ioh, wd_sdh, WDSD_IBM | 0x10);
- bus_io_write_1(bc, ioh, wd_error, 0x5a);
- bus_io_write_1(bc, ioh, wd_cyl_lo, 0xa5);
- if (bus_io_read_1(bc, ioh, wd_error) == 0x5a ||
- bus_io_read_1(bc, ioh, wd_cyl_lo) != 0xa5)
+ bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM | 0x10);
+ bus_space_write_1(iot, ioh, wd_error, 0x5a);
+ bus_space_write_1(iot, ioh, wd_cyl_lo, 0xa5);
+ if (bus_space_read_1(iot, ioh, wd_error) == 0x5a ||
+ bus_space_read_1(iot, ioh, wd_cyl_lo) != 0xa5)
return 0;
wdc->sc_flags |= WDCF_ONESLAVE;
}
/* Select drive 0 or ATAPI slave device */
if (wdc->sc_flags & WDCF_ONESLAVE)
- bus_io_write_1(bc, ioh, wd_sdh, WDSD_IBM | 0x10);
+ bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM | 0x10);
else
- bus_io_write_1(bc, ioh, wd_sdh, WDSD_IBM);
+ bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM);
/* Wait for controller to become ready. */
if (wait_for_unbusy(wdc) < 0)
return 0;
/* Start drive diagnostics. */
- bus_io_write_1(bc, ioh, wd_command, WDCC_DIAGNOSE);
+ bus_space_write_1(iot, ioh, wd_command, WDCC_DIAGNOSE);
/* Wait for command to complete. */
if (wait_for_unbusy(wdc) < 0)
struct wdc_softc *wdc;
struct wdc_xfer *xfer;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
struct wd_link *d_link = xfer->d_link;
struct buf *bp = xfer->c_bp;
int nblks;
xfer->c_blkno = blkno / (d_link->sc_lp->d_secsize / DEV_BSIZE);
} else {
WDDEBUG_PRINT((" %d)0x%x", xfer->c_skip,
- bus_io_read_1(bc, ioh, wd_altsts)));
+ bus_space_read_1(iot, ioh, wd_altsts)));
}
/*
WDDEBUG_PRINT(("sector %d cylin %d head %d addr %x sts %x\n",
sector, cylin, head, xfer->databuf,
- bus_io_read_1(bc, ioh, wd_altsts)));
+ bus_space_read_1(iot, ioh, wd_altsts)));
} else if (xfer->c_nblks > 1) {
/* The number of blocks in the last stretch may be smaller. */
/* Push out data. */
if ((d_link->sc_flags & WDF_32BIT) == 0)
- bus_io_write_raw_multi_2(bc, ioh, wd_data,
+ bus_space_write_raw_multi_2(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, xfer->c_nbytes);
else
- bus_io_write_raw_multi_4(bc, ioh, wd_data,
+ bus_space_write_raw_multi_4(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, xfer->c_nbytes);
}
struct wdc_softc *wdc;
int wphase;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
int i, phase;
for (i = 20000; i; i--) {
- phase = (bus_io_read_1(bc, ioh, wd_ireason) &
+ phase = (bus_space_read_1(iot, ioh, wd_ireason) &
(WDCI_CMD | WDCI_IN)) |
- (bus_io_read_1(bc, ioh, wd_status)
+ (bus_space_read_1(iot, ioh, wd_status)
& WDCS_DRQ);
if (phase == wphase)
break;
struct wdc_softc *wdc;
int wphase;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
int i, phase;
for (i = 20000; i; i--) {
- phase = (bus_io_read_1(bc, ioh, wd_ireason) &
+ phase = (bus_space_read_1(iot, ioh, wd_ireason) &
(WDCI_CMD | WDCI_IN)) |
- (bus_io_read_1(bc, ioh, wd_status)
+ (bus_space_read_1(iot, ioh, wd_status)
& WDCS_DRQ);
if (phase != wphase)
break;
struct wdc_softc *wdc;
struct wdc_xfer *xfer;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
struct atapi_command_packet *acp = xfer->atapi_cmd;
#ifdef ATAPI_DEBUG_WDC
#endif
if (wdc->sc_errors >= WDIORETRIES) {
acp->status |= ERROR;
- acp->error = bus_io_read_1(bc, ioh, wd_error);
+ acp->error = bus_space_read_1(iot, ioh, wd_error);
wdc_atapi_done(wdc, xfer);
return;
}
int phase = wait_for_phase(wdc, PHASE_CMDOUT);
if (phase != PHASE_CMDOUT) {
- printf("wdc_atapi_start: timeout waiting PHASE_CMDOUT, got 0x%x\n", phase);
+ printf("wdc_atapi_start: timeout waiting "
+ "PHASE_CMDOUT, got 0x%x\n", phase);
/* NEC SUCKS. */
wdc->sc_flags |= WDCF_BROKENPOLL;
} else
DELAY(10); /* Simply pray for the data. */
- bus_io_write_raw_multi_2(bc, ioh, wd_data, acp->command,
+ bus_space_write_raw_multi_2(iot, ioh, wd_data, acp->command,
acp->command_size);
}
wdc->sc_flags |= WDCF_IRQ_WAIT;
struct wdc_xfer *xfer;
if ((wdc->sc_flags & WDCF_IRQ_WAIT) == 0) {
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
u_char s;
#ifdef ATAPI_DEBUG_WDC
u_char e, i;
DELAY(100);
/* Clear the pending interrupt and abort. */
- s = bus_io_read_1(bc, ioh, wd_status);
+ s = bus_space_read_1(iot, ioh, wd_status);
if (s != (WDCS_DRDY|WDCS_DSC)) {
#ifdef ATAPI_DEBUG_WDC
- e = bus_io_read_1(bc, ioh, wd_error);
- i = bus_io_read_1(bc, ioh, wd_seccnt);
+ e = bus_space_read_1(iot, ioh, wd_error);
+ i = bus_space_read_1(iot, ioh, wd_seccnt);
printf("wdcintr: inactive controller, "
"punting st=%02x er=%02x irr=%02x\n", s, e, i);
#else
- (void)bus_io_read_1(bc, ioh, wd_error);
- (void)bus_io_read_1(bc, ioh, wd_seccnt);
+ (void)bus_space_read_1(iot, ioh, wd_error);
+ (void)bus_space_read_1(iot, ioh, wd_seccnt);
#endif
if (s & WDCS_DRQ) {
- int len = bus_io_read_1(bc, ioh, wd_cyl_lo) +
- 256 * bus_io_read_1(bc, ioh, wd_cyl_hi);
+ int len = 256 * bus_space_read_1(iot, ioh,
+ wd_cyl_hi) +
+ bus_space_read_1(iot, ioh, wd_cyl_lo);
#ifdef ATAPI_DEBUG_WDC
- printf ("wdcintr: clearing up %d bytes\n", len);
+ printf ("wdcintr: clearing up %d bytes\n",
+ len);
#endif
wdcbit_bucket (wdc, len);
}
struct wdc_softc *wdc;
struct wdc_xfer *xfer;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
struct wd_link *d_link = xfer->d_link;
if (wait_for_unbusy(wdc) < 0) {
/* Pull in data. */
if ((d_link->sc_flags & WDF_32BIT) == 0)
- bus_io_read_raw_multi_2(bc, ioh, wd_data,
+ bus_space_read_raw_multi_2(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, xfer->c_nbytes);
else
- bus_io_read_raw_multi_4(bc, ioh, wd_data,
+ bus_space_read_raw_multi_4(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, xfer->c_nbytes);
}
wdcreset(wdc)
struct wdc_softc *wdc;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
/* Reset the device. */
- bus_io_write_1(bc, ioh, wd_ctlr, WDCTL_RST|WDCTL_IDS);
+ bus_space_write_1(iot, ioh, wd_ctlr, WDCTL_RST|WDCTL_IDS);
delay(1000);
- bus_io_write_1(bc, ioh, wd_ctlr, WDCTL_IDS);
+ bus_space_write_1(iot, ioh, wd_ctlr, WDCTL_IDS);
delay(1000);
- (void) bus_io_read_1(bc, ioh, wd_error);
- bus_io_write_1(bc, ioh, wd_ctlr, WDCTL_4BIT);
+ (void) bus_space_read_1(iot, ioh, wd_error);
+ bus_space_write_1(iot, ioh, wd_ctlr, WDCTL_4BIT);
if (wait_for_unbusy(wdc) < 0) {
printf("%s: reset failed\n", wdc->sc_dev.dv_xname);
struct wdc_softc *wdc;
int mask;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
int timeout = 0;
u_char status;
#ifdef WDCNDELAY_DEBUG
WDDEBUG_PRINT(("wdcwait\n"));
for (;;) {
- wdc->sc_status = status = bus_io_read_1(bc, ioh, wd_status);
+ wdc->sc_status = status = bus_space_read_1(iot, ioh,
+ wd_status);
/*
* XXX
* If a single slave ATAPI device is attached, it may
* have released the bus. Select it and try again.
*/
if (status == 0xff && wdc->sc_flags & WDCF_ONESLAVE) {
- bus_io_write_1(bc, ioh, wd_sdh,
+ bus_space_write_1(iot, ioh, wd_sdh,
WDSD_IBM | 0x10);
- wdc->sc_status = status = bus_io_read_1(bc, ioh,
+ wdc->sc_status = status = bus_space_read_1(iot, ioh,
wd_status);
}
if ((status & WDCS_BSY) == 0 && (status & mask) == mask)
delay(WDCDELAY);
}
if (status & WDCS_ERR) {
- wdc->sc_error = bus_io_read_1(bc, ioh, wd_error);
+ wdc->sc_error = bus_space_read_1(iot, ioh, wd_error);
return WDCS_ERR;
}
#ifdef WDCNDELAY_DEBUG
int drive, cylin, head, sector, count;
{
struct wdc_softc *wdc = (void*)d_link->wdc_softc;
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
int stat;
WDDEBUG_PRINT(("wdccommand drive %d\n", drive));
#endif
/* Select drive, head, and addressing mode. */
- bus_io_write_1(bc, ioh, wd_sdh, WDSD_IBM | (drive << 4) | head);
+ bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM | (drive << 4) | head);
/* Wait for it to become ready to accept a command. */
if (command == WDCC_IDP || d_link->type == BUS)
/* Load parameters. */
if (d_link->type == DRIVE && d_link->sc_lp->d_type == DTYPE_ST506)
- bus_io_write_1(bc, ioh, wd_precomp,
+ bus_space_write_1(iot, ioh, wd_precomp,
d_link->sc_lp->d_precompcyl / 4);
else
- bus_io_write_1(bc, ioh, wd_features, 0);
- bus_io_write_1(bc, ioh, wd_cyl_lo, cylin);
- bus_io_write_1(bc, ioh, wd_cyl_hi, cylin >> 8);
- bus_io_write_1(bc, ioh, wd_sector, sector);
- bus_io_write_1(bc, ioh, wd_seccnt, count);
+ bus_space_write_1(iot, ioh, wd_features, 0);
+ bus_space_write_1(iot, ioh, wd_cyl_lo, cylin);
+ bus_space_write_1(iot, ioh, wd_cyl_hi, cylin >> 8);
+ bus_space_write_1(iot, ioh, wd_sector, sector);
+ bus_space_write_1(iot, ioh, wd_seccnt, count);
/* Send command. */
- bus_io_write_1(bc, ioh, wd_command, command);
+ bus_space_write_1(iot, ioh, wd_command, command);
return 0;
}
int drive;
int command;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
WDDEBUG_PRINT(("wdccommandshort\n"));
#endif
/* Select drive. */
- bus_io_write_1(bc, ioh, wd_sdh, WDSD_IBM|(drive << 4));
+ bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM|(drive << 4));
if (wdcwait(wdc, WDCS_DRDY) < 0)
return -1;
- bus_io_write_1(bc, ioh, wd_command, command);
+ bus_space_write_1(iot, ioh, wd_command, command);
return 0;
}
struct wd_link *d_link;
{
struct wdc_softc *wdc = (void *)d_link->wdc_softc;
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
WDDEBUG_PRINT(("wdccontrol\n"));
multimode:
if (d_link->sc_mode != WDM_PIOMULTI)
goto ready;
- bus_io_write_1(bc, ioh, wd_seccnt, d_link->sc_multiple);
+ bus_space_write_1(iot, ioh, wd_seccnt, d_link->sc_multiple);
if (wdccommandshort(wdc, d_link->sc_drive,
WDCC_SETMULTI) != 0) {
wderror(d_link, NULL,
struct wd_link *d_link;
{
struct wdc_softc *wdc = (struct wdc_softc *)d_link->wdc_softc;
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
u_int16_t tb[DEV_BSIZE / sizeof(u_int16_t)];
int s, error;
d_link->sc_lp->d_type = DTYPE_ESDI;
/* Read in parameter block. */
- bus_io_read_multi_2(bc, ioh, wd_data, tb,
+ bus_space_read_multi_2(iot, ioh, wd_data, tb,
sizeof(tb) / sizeof(u_int16_t));
d_link->sc_params.wdp_config = (u_int16_t)tb[0];
d_link->sc_params.wdp_cylinders = (u_int16_t)tb[1];
}
/* Clear any leftover interrupt. */
- (void) bus_io_read_1(bc, ioh, wd_status);
+ (void) bus_space_read_1(iot, ioh, wd_status);
/* Restart the queue. */
WDDEBUG_PRINT(("wdcstart from wdc_get_parms flags %d\n",
struct atapi_identify *id;
{
struct wdc_softc *wdc = (void*)ab_link->wdc_softc;
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
int status, len, excess = 0;
int s, error;
error = 0;
goto end;
}
- len = bus_io_read_1(bc, ioh, wd_cyl_lo) + 256 *
- bus_io_read_1(bc, ioh, wd_cyl_hi);
+ len = bus_space_read_1(iot, ioh, wd_cyl_lo) + 256 *
+ bus_space_read_1(iot, ioh, wd_cyl_hi);
if (len != sizeof(struct atapi_identify)) {
if (len < 142) { /* XXX */
printf("%s: drive %d returned %d/%d of identify device data, device unusuable\n", wdc->sc_dev.dv_xname, drive, len, sizeof(struct atapi_identify));
if (excess < 0)
excess = 0;
}
- bus_io_read_raw_multi_2(bc, ioh, wd_data, (u_int8_t *)id,
+ bus_space_read_raw_multi_2(iot, ioh, wd_data, (u_int8_t *)id,
sizeof(struct atapi_identify));
wdcbit_bucket(wdc, excess);
struct atapi_command_packet *acp;
{
struct wdc_softc *wdc = (void*)ab_link->wdc_softc;
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
struct wdc_xfer *xfer;
u_int8_t flags = acp->flags & 0xff;
printf("wdc_atapi_intr: got wrong phase (0x%x)\n",
phase);
- bus_io_write_raw_multi_2(bc, ioh, wd_data, acp->command,
+ bus_space_write_raw_multi_2(iot, ioh, wd_data, acp->command,
acp->command_size);
/* Wait for data i/o phase. */
while (wdc_atapi_intr(wdc, xfer)) {
for (i = 2000; i > 0; --i)
- if ((bus_io_read_1(bc, ioh, wd_status) &
+ if ((bus_space_read_1(iot, ioh, wd_status) &
WDCS_DRQ) == 0)
break;
#ifdef ATAPI_DEBUG_WDC
struct wdc_softc *wdc;
int size;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
int i;
for (i = 0 ; i < size / 2 ; i++) {
u_int16_t null;
- (void)bus_io_read_multi_2(bc, ioh, wd_data, &null, 1);
+
+ bus_space_read_multi_2(iot, ioh, wd_data, &null, 1);
}
if (size % 2)
- (void)bus_io_read_1(bc, ioh, wd_data);
+ (void)bus_space_read_1(iot, ioh, wd_data);
}
int
struct wdc_softc *wdc;
struct wdc_xfer *xfer;
{
- bus_chipset_tag_t bc = wdc->sc_bc;
- bus_io_handle_t ioh = wdc->sc_ioh;
+ bus_space_tag_t iot = wdc->sc_iot;
+ bus_space_handle_t ioh = wdc->sc_ioh;
struct atapi_command_packet *acp = xfer->atapi_cmd;
int len, phase, i, retries = 0;
int err, st, ire;
if (wait_for_unbusy(wdc) < 0) {
printf("wdc_atapi_intr: controller busy\n");
acp->status = ERROR;
- acp->error = bus_io_read_1(bc, ioh, wd_error);
+ acp->error = bus_space_read_1(iot, ioh, wd_error);
return 0;
}
#endif
again:
- len = bus_io_read_1(bc, ioh, wd_cyl_lo) +
- 256 * bus_io_read_1(bc, ioh, wd_cyl_hi);
+ len = bus_space_read_1(iot, ioh, wd_cyl_lo) +
+ 256 * bus_space_read_1(iot, ioh, wd_cyl_hi);
- st = bus_io_read_1(bc, ioh, wd_status);
- err = bus_io_read_1(bc, ioh, wd_error);
- ire = bus_io_read_1(bc, ioh, wd_ireason);
+ st = bus_space_read_1(iot, ioh, wd_status);
+ err = bus_space_read_1(iot, ioh, wd_error);
+ ire = bus_space_read_1(iot, ioh, wd_ireason);
phase = (ire & (WDCI_CMD | WDCI_IN)) | (st & WDCS_DRQ);
#ifdef ATAPI_DEBUG_WDC
#endif
wdc->sc_flags |= WDCF_IRQ_WAIT;
- bus_io_write_raw_multi_2(bc, ioh, wd_data, acp->command,
+ bus_space_write_raw_multi_2(iot, ioh, wd_data, acp->command,
acp->command_size);
return 1;
if (xfer->c_bcount < len) {
printf("wdc_atapi_intr: warning: write only "
"%d of %d requested bytes\n", xfer->c_bcount, len);
- bus_io_write_raw_multi_2(bc, ioh, wd_data,
+ bus_space_write_raw_multi_2(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, xfer->c_bcount);
for (i = xfer->c_bcount; i < len; i += sizeof(short))
- bus_io_write_2(bc, ioh, wd_data, 0);
+ bus_space_write_2(iot, ioh, wd_data, 0);
xfer->c_bcount = 0;
return 1;
} else {
- bus_io_write_raw_multi_2(bc, ioh, wd_data,
+ bus_space_write_raw_multi_2(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, len);
xfer->c_skip += len;
xfer->c_bcount -= len;
if (xfer->c_bcount < len) {
printf("wdc_atapi_intr: warning: reading only "
"%d of %d bytes\n", xfer->c_bcount, len);
- bus_io_read_raw_multi_2(bc, ioh, wd_data,
+ bus_space_read_raw_multi_2(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip,
xfer->c_bcount);
wdcbit_bucket(wdc, len - xfer->c_bcount);
xfer->c_bcount = 0;
return 1;
} else {
- bus_io_read_raw_multi_2(bc, ioh, wd_data,
+ bus_space_read_raw_multi_2(iot, ioh, wd_data,
xfer->databuf + xfer->c_skip, len);
xfer->c_skip += len;
xfer->c_bcount -=len;
printf("PHASE_COMPLETED\n");
#endif
if (st & WDCS_ERR) {
- acp->error = bus_io_read_1(bc, ioh, wd_error);
+ acp->error = bus_space_read_1(iot, ioh, wd_error);
acp->status = ERROR;
}
#ifdef ATAPI_DEBUG_WDC
-/* $OpenBSD: wdlink.h,v 1.5 1996/11/28 08:23:40 downsj Exp $ */
+/* $OpenBSD: wdlink.h,v 1.6 1996/11/29 22:55:10 niklas Exp $ */
/*
* Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved.
struct wd_link *d_link[2];
struct bus_link *ab_link;
struct wdc_link ctlr_link;
- bus_chipset_tag_t sc_bc;
- bus_io_handle_t sc_ioh;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
int sc_drq; /* DMA channel */
TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
-/* $OpenBSD: wds.c,v 1.10 1996/11/23 21:46:49 kstailey Exp $ */
-/* $NetBSD: wds.c,v 1.7 1996/05/12 23:54:09 mycroft Exp $ */
+/* $OpenBSD: wds.c,v 1.11 1996/11/29 22:55:10 niklas Exp $ */
+/* $NetBSD: wds.c,v 1.13 1996/11/03 16:20:31 mycroft Exp $ */
#undef WDSDIAG
+#ifdef DDB
#define integrate
+#else
+#define integrate static inline
+#endif
/*
* XXX
#include <sys/proc.h>
#include <sys/user.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <machine/pio.h>
struct isadev sc_id;
void *sc_ih;
- bus_chipset_tag_t sc_bc; /* bus identifier */
- bus_io_handle_t sc_ioh; /* io handle */
+ bus_space_tag_t sc_iot; /* bus identifier */
+ bus_space_handle_t sc_ioh; /* io handle */
int sc_irq, sc_drq;
int sc_revision;
#endif
integrate void wds_wait
- __P((bus_chipset_tag_t, bus_io_handle_t, int, int, int));
+ __P((bus_space_tag_t, bus_space_handle_t, int, int, int));
int wds_cmd __P((struct wds_softc *, u_char *, int));
integrate void wds_finish_scbs __P((struct wds_softc *));
int wdsintr __P((void *));
int wds_poll __P((struct wds_softc *, struct scsi_xfer *, int));
int wds_ipoll __P((struct wds_softc *, struct wds_scb *, int));
void wds_timeout __P((void *));
+int wdsprint __P((void *, const char *));
struct scsi_adapter wds_switch = {
wds_scsi_cmd,
int wdsprobe __P((struct device *, void *, void *));
void wdsattach __P((struct device *, struct device *, void *));
-int wdsprint __P((void *, const char *));
struct cfattach wds_ca = {
sizeof(struct wds_softc), wdsprobe, wdsattach
#define WDS_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
integrate void
-wds_wait(bc, ioh, port, mask, val)
- bus_chipset_tag_t bc;
- bus_io_handle_t ioh;
+wds_wait(iot, ioh, port, mask, val)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
int port;
int mask;
int val;
{
- while ((bus_io_read_1(bc, ioh, port) & mask) != val)
+ while ((bus_space_read_1(iot, ioh, port) & mask) != val)
;
}
u_int8_t *ibuf;
int icnt;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
u_int8_t c;
- wds_wait(bc, ioh, WDS_STAT, WDSS_RDY, WDSS_RDY);
+ wds_wait(iot, ioh, WDS_STAT, WDSS_RDY, WDSS_RDY);
while (icnt--) {
- bus_io_write_1(bc, ioh, WDS_CMD, *ibuf++);
- wds_wait(bc, ioh, WDS_STAT, WDSS_RDY, WDSS_RDY);
- c = bus_io_read_1(bc, ioh, WDS_STAT);
+ bus_space_write_1(iot, ioh, WDS_CMD, *ibuf++);
+ wds_wait(iot, ioh, WDS_STAT, WDSS_RDY, WDSS_RDY);
+ c = bus_space_read_1(iot, ioh, WDS_STAT);
if (c & WDSS_REJ)
return 1;
}
/*
* fill in the prototype scsi_link.
*/
+#ifdef notyet
+ sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE;
+#endif
sc->sc_link.adapter_softc = sc;
sc->sc_link.adapter_target = sc->sc_scsi_dev;
sc->sc_link.adapter = &wds_switch;
void *arg;
{
struct wds_softc *sc = arg;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
u_char c;
/* Was it really an interrupt from the board? */
- if ((bus_io_read_1(bc, ioh, WDS_STAT) & WDSS_IRQ) == 0)
+ if ((bus_space_read_1(iot, ioh, WDS_STAT) & WDSS_IRQ) == 0)
return 0;
/* Get the interrupt status byte. */
- c = bus_io_read_1(bc, ioh, WDS_IRQSTAT) & WDSI_MASK;
+ c = bus_space_read_1(iot, ioh, WDS_IRQSTAT) & WDSI_MASK;
/* Acknowledge (which resets) the interrupt. */
- bus_io_write_1(bc, ioh, WDS_IRQACK, 0x00);
+ bus_space_write_1(iot, ioh, WDS_IRQACK, 0x00);
switch (c) {
case WDSI_MSVC:
struct isa_attach_args *ia;
struct wds_softc *sc;
{
- bus_chipset_tag_t bc = ia->ia_bc;
- bus_io_handle_t ioh;
+ bus_space_tag_t iot = ia->ia_iot;
+ bus_space_handle_t ioh;
u_char c;
int i;
/* XXXXX */
- if (bus_io_map(bc, ia->ia_iobase, WDS_IO_PORTS, &ioh))
+ if (bus_space_map(iot, ia->ia_iobase, WDS_IO_PORTS, 0, &ioh))
return (0);
/*
* Sending a command causes the CMDRDY bit to clear.
*/
- c = bus_io_read_1(bc, ioh, WDS_STAT);
+ c = bus_space_read_1(iot, ioh, WDS_STAT);
for (i = 0; i < 4; i++)
- if ((bus_io_read_1(bc, ioh, WDS_STAT) & WDSS_RDY) != 0) {
+ if ((bus_space_read_1(iot, ioh, WDS_STAT) & WDSS_RDY) != 0) {
goto ready;
delay(10);
}
return 1;
ready:
- bus_io_write_1(bc, ioh, WDS_CMD, WDSC_NOOP);
- if (bus_io_read_1(bc, ioh, WDS_STAT) & WDSS_RDY)
+ bus_space_write_1(iot, ioh, WDS_CMD, WDSC_NOOP);
+ if (bus_space_read_1(iot, ioh, WDS_STAT) & WDSS_RDY)
return 1;
- bus_io_write_1(bc, ioh, WDS_HCR, WDSH_SCSIRESET|WDSH_ASCRESET);
+ bus_space_write_1(iot, ioh, WDS_HCR, WDSH_SCSIRESET|WDSH_ASCRESET);
delay(10000);
- bus_io_write_1(bc, ioh, WDS_HCR, 0x00);
+ bus_space_write_1(iot, ioh, WDS_HCR, 0x00);
delay(500000);
- wds_wait(bc, ioh, WDS_STAT, WDSS_RDY, WDSS_RDY);
- if (bus_io_read_1(bc, ioh, WDS_IRQSTAT) != 1)
- if (bus_io_read_1(bc, ioh, WDS_IRQSTAT) != 7)
+ wds_wait(iot, ioh, WDS_STAT, WDSS_RDY, WDSS_RDY);
+ if (bus_space_read_1(iot, ioh, WDS_IRQSTAT) != 1)
+ if (bus_space_read_1(iot, ioh, WDS_IRQSTAT) != 7)
printf("%s: failed reset!!! %2x\n",
sc ? sc->sc_dev.dv_xname : "wds?",
- bus_io_read_1(bc, ioh, WDS_IRQSTAT));
+ bus_space_read_1(iot, ioh, WDS_IRQSTAT));
- if ((bus_io_read_1(bc, ioh, WDS_STAT) & (WDSS_RDY)) != WDSS_RDY) {
+ if ((bus_space_read_1(iot, ioh, WDS_STAT) & (WDSS_RDY)) != WDSS_RDY) {
printf("%s: waiting for controller to become ready.",
sc ? sc->sc_dev.dv_xname : "wds?");
for (i = 0; i < 20; i++) {
- if ((bus_io_read_1(bc, ioh, WDS_STAT) & (WDSS_RDY)) ==
- WDSS_RDY)
+ if ((bus_space_read_1(iot, ioh, WDS_STAT) &
+ (WDSS_RDY)) == WDSS_RDY)
break;
printf(".");
delay(10000);
}
- if ((bus_io_read_1(bc, ioh, WDS_STAT) & (WDSS_RDY)) !=
+ if ((bus_space_read_1(iot, ioh, WDS_STAT) & (WDSS_RDY)) !=
WDSS_RDY) {
printf(" failed\n");
return 1;
/* who are we on the scsi bus? */
sc->sc_scsi_dev = 7;
- sc->sc_bc = bc;
+ sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->sc_irq = ia->ia_irq;
sc->sc_drq = ia->ia_drq;
} else
- bus_io_unmap(bc, ioh, WDS_IO_PORTS);
+ bus_space_unmap(iot, ioh, WDS_IO_PORTS);
return 0;
}
wds_init(sc)
struct wds_softc *sc;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct wds_setup init;
u_char c;
int i;
init.nomb = init.nimb = WDS_MBX_SIZE;
wds_cmd(sc, (u_char *)&init, sizeof init);
- wds_wait(bc, ioh, WDS_STAT, WDSS_INIT, WDSS_INIT);
+ wds_wait(iot, ioh, WDS_STAT, WDSS_INIT, WDSS_INIT);
c = WDSC_DISUNSOL;
wds_cmd(sc, &c, sizeof c);
- bus_io_write_1(bc, ioh, WDS_HCR, WDSH_DRQEN);
+ bus_space_write_1(iot, ioh, WDS_HCR, WDSH_DRQEN);
}
/*
scb->cmd.opcode = WDSX_GETFIRMREV;
/* Will poll card, await result. */
- bus_io_write_1(sc->sc_bc, sc->sc_ioh, WDS_HCR, WDSH_DRQEN);
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, WDS_HCR, WDSH_DRQEN);
scb->flags |= SCB_POLLED;
s = splbio();
wdsminphys(bp)
struct buf *bp;
{
-
if (bp->b_bcount > ((WDS_NSEG - 1) << PGSHIFT))
bp->b_bcount = ((WDS_NSEG - 1) << PGSHIFT);
minphys(bp);
{
struct scsi_link *sc_link = xs->sc_link;
struct wds_softc *sc = sc_link->adapter_softc;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
struct wds_scb *scb;
struct wds_scat_gath *sg;
int seg;
/* XXX Do we really want to do this? */
if (flags & SCSI_POLL) {
/* Will poll card, await result. */
- bus_io_write_1(bc, ioh, WDS_HCR, WDSH_DRQEN);
+ bus_space_write_1(iot, ioh, WDS_HCR, WDSH_DRQEN);
scb->flags |= SCB_POLLED;
} else {
/* Will send command, let interrupt routine handle result. */
- bus_io_write_1(bc, ioh, WDS_HCR, WDSH_IRQEN | WDSH_DRQEN);
+ bus_space_write_1(iot, ioh, WDS_HCR, WDSH_IRQEN | WDSH_DRQEN);
}
s = splbio();
struct scsi_xfer *xs;
int count;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
/* timeouts are in msec, so we loop in 1000 usec cycles */
while (count) {
* If we had interrupts enabled, would we
* have got an interrupt?
*/
- if (bus_io_read_1(bc, ioh, WDS_STAT) & WDSS_IRQ)
+ if (bus_space_read_1(iot, ioh, WDS_STAT) & WDSS_IRQ)
wdsintr(sc);
if (xs->flags & ITSDONE)
return 0;
struct wds_scb *scb;
int count;
{
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
/* timeouts are in msec, so we loop in 1000 usec cycles */
while (count) {
* If we had interrupts enabled, would we
* have got an interrupt?
*/
- if (bus_io_read_1(bc, ioh, WDS_STAT) & WDSS_IRQ)
+ if (bus_space_read_1(iot, ioh, WDS_STAT) & WDSS_IRQ)
wdsintr(sc);
if (scb->flags & SCB_DONE)
return 0;
projects / openbsd / commitdiff