Align more register addresses and data structures with ath12k.
authorpatrick <patrick@openbsd.org>
Fri, 16 Aug 2024 00:26:54 +0000 (00:26 +0000)
committerpatrick <patrick@openbsd.org>
Fri, 16 Aug 2024 00:26:54 +0000 (00:26 +0000)
sys/dev/ic/qwz.c
sys/dev/ic/qwzreg.h
sys/dev/ic/qwzvar.h
sys/dev/pci/if_qwz_pci.c

index 906114a..063631b 100644 (file)
@@ -1,4 +1,4 @@
-/*     $OpenBSD: qwz.c,v 1.3 2024/08/15 23:23:06 patrick Exp $ */
+/*     $OpenBSD: qwz.c,v 1.4 2024/08/16 00:26:54 patrick Exp $ */
 
 /*
  * Copyright 2023 Stefan Sperling <stsp@openbsd.org>
@@ -1027,14 +1027,14 @@ qwz_hw_wcn7850_reo_setup(struct qwz_softc *sc)
            FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
        sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val);
 
-       val = sc->ops.read32(sc, reo_base + HAL_REO1_MISC_CTL(sc));
-       val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
+       val = sc->ops.read32(sc, reo_base + HAL_REO1_MISC_CTRL_ADDR(sc));
+       val &= ~HAL_REO1_MISC_CTL_FRAG_DST_RING;
        val &= ~HAL_REO1_MISC_CTL_BAR_DST_RING;
-       val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING,
+       val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAG_DST_RING,
            HAL_SRNG_RING_ID_REO2SW0);
        val |= FIELD_PREP(HAL_REO1_MISC_CTL_BAR_DST_RING,
            HAL_SRNG_RING_ID_REO2SW0);
-       sc->ops.write32(sc, reo_base + HAL_REO1_MISC_CTL(sc), val);
+       sc->ops.write32(sc, reo_base + HAL_REO1_MISC_CTRL_ADDR(sc), val);
 
        sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_0(sc),
            HAL_DEFAULT_REO_TIMEOUT_USEC);
@@ -3028,9 +3028,6 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
 
 const struct ath12k_hw_regs wcn7850_regs = {
        /* SW2TCL(x) R0 ring configuration address */
-       .hal_tcl1_ring_cmn_ctrl_reg = 0x00000020,
-       .hal_tcl1_ring_dscp_tid_map = 0x00000240,
-       .hal_tcl1_ring_base_lsb = 0x00000900,
        .hal_tcl1_ring_id = 0x00000908,
        .hal_tcl1_ring_misc = 0x00000910,
        .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
@@ -3040,16 +3037,13 @@ const struct ath12k_hw_regs wcn7850_regs = {
        .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
        .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
        .hal_tcl1_ring_msi1_data = 0x00000950,
-       .hal_tcl2_ring_base_lsb = 0x00000978,
        .hal_tcl_ring_base_lsb = 0x00000b58,
-       .hal_tcl_ring_hp = 0x00002028,
 
        /* TCL STATUS ring address */
        .hal_tcl_status_ring_base_lsb = 0x00000d38,
-       .hal_tcl_status_ring_hp = 0x00002048,
 
-       .hal_wbm_idle_link_ring_base_lsb = 0x00000d3c,
-       .hal_wbm_idle_link_ring_misc = 0x00000d4c,
+       .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
+       .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
        .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
        .hal_wbm_r0_idle_list_size_addr = 0x00000244,
        .hal_wbm_scattered_ring_base_lsb = 0x00000250,
@@ -3060,13 +3054,10 @@ const struct ath12k_hw_regs wcn7850_regs = {
        .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
        .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c,
 
-       .hal_wbm_release_ring_base_lsb = 0x0000037c,
-       .hal_wbm_release_ring_hp = 0x00003010,
+       .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
        .hal_wbm_sw1_release_ring_base_lsb = 0x00000284,
        .hal_wbm0_release_ring_base_lsb = 0x00000e08,
-       .hal_wbm0_release_ring_hp = 0x000030c8,
        .hal_wbm1_release_ring_base_lsb = 0x00000e80,
-       .hal_wbm1_release_ring_hp = 0x000030d0,
 
        /* PCIe base address */
        .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
@@ -3076,8 +3067,8 @@ const struct ath12k_hw_regs wcn7850_regs = {
        .hal_ppe_rel_ring_base = 0x0000043c,
 
        /* REO DEST ring address */
-       .hal_reo2_ring_base_lsb = 0x0000055c,
-       .hal_reo1_misc_ctl = 0x00000b7c,
+       .hal_reo2_ring_base = 0x0000055c,
+       .hal_reo1_misc_ctrl_addr = 0x00000b7c,
        .hal_reo1_sw_cookie_cfg0 = 0x00000050,
        .hal_reo1_sw_cookie_cfg1 = 0x00000054,
        .hal_reo1_qdesc_lut_base0 = 0x00000058,
@@ -3101,30 +3092,14 @@ const struct ath12k_hw_regs wcn7850_regs = {
        .hal_reo2_sw0_ring_base = 0x000008a4,
 
        /* REO Reinject ring address */
-       .hal_sw2reo_ring_base_lsb = 0x00000304,
-       .hal_sw2reo_ring_hp = 0x00003028,
+       .hal_sw2reo_ring_base = 0x00000304,
        .hal_sw2reo1_ring_base = 0x0000037c,
 
        /* REO cmd ring address */
-       .hal_reo_cmd_ring_base_lsb = 0x0000028c,
-       .hal_reo_cmd_ring_hp = 0x00003020,
+       .hal_reo_cmd_ring_base = 0x0000028c,
 
        /* REO status ring address */
-       .hal_reo_status_ring_base_lsb = 0x00000a84,
-       .hal_reo_status_hp = 0x000030a8,
-
-       /* REO2SW(x) R2 ring pointers (head/tail) address */
-       .hal_reo1_ring_hp = 0x00003048,
-       .hal_reo1_ring_tp = 0x0000304c,
-       .hal_reo2_ring_hp = 0x00003050,
-
-       /* WCSS relative address */
-       .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
-       .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
-       .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
-
-       /* Shadow register area */
-       .hal_shadow_base_addr = 0x000008fc,
+       .hal_reo_status_ring_base = 0x00000a84,
 };
 
 #define QWZ_SLEEP_CLOCK_SELECT_INTERNAL_BIT    0x02
@@ -8601,19 +8576,19 @@ qwz_hal_setup_link_idle_list(struct qwz_softc *sc,
        }
 
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(sc),
            FIELD_PREP(HAL_WBM_SCATTER_BUFFER_SIZE, reg_scatter_buf_sz) |
            FIELD_PREP(HAL_WBM_LINK_DESC_IDLE_LIST_MODE, 0x1));
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(sc),
            FIELD_PREP(HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
            reg_scatter_buf_sz * nsbufs));
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_RING_BASE_LSB,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_RING_BASE_LSB(sc),
            FIELD_PREP(BUFFER_ADDR_INFO0_ADDR,
            sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK));
        sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_WBM_REG +
-           HAL_WBM_SCATTERED_RING_BASE_MSB,
+           HAL_WBM_SCATTERED_RING_BASE_MSB(sc),
            FIELD_PREP(HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32,
            (uint64_t)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT) |
            FIELD_PREP(HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG,
@@ -8622,29 +8597,29 @@ qwz_hal_setup_link_idle_list(struct qwz_softc *sc,
        /* Setup head and tail pointers for the idle list */
        sc->ops.write32(sc,
            HAL_SEQ_WCSS_UMAC_WBM_REG +
-           HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0,
+           HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(sc),
            FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, sbuf[nsbufs - 1].paddr));
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(sc),
            FIELD_PREP(HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32,
            ((uint64_t)sbuf[nsbufs - 1].paddr >> HAL_ADDR_MSB_REG_SHIFT)) |
            FIELD_PREP(HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1,
            (end_offset >> 2)));
        sc->ops.write32(sc,
            HAL_SEQ_WCSS_UMAC_WBM_REG +
-           HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0,
+           HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(sc),
            FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, sbuf[0].paddr));
 
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(sc),
            FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, sbuf[0].paddr));
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(sc),
            FIELD_PREP(HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32,
            ((uint64_t)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT)) |
            FIELD_PREP(HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1, 0));
        sc->ops.write32(sc,
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR,
+           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(sc),
            2 * tot_link_desc);
 
        /* Enable the SRNG */
@@ -19409,7 +19384,7 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
        [HAL_REO_DST] = {
                .start_ring_id = HAL_SRNG_RING_ID_REO2SW1,
                .max_rings = 8,
-               .entry_size = sizeof(struct ath12k_hal_reo_dest_ring) >> 2,
+               .entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_UMAC,
                .ring_dir = HAL_SRNG_DIR_DST,
                .max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE,
@@ -19420,7 +19395,7 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                 */
                .start_ring_id = HAL_SRNG_RING_ID_REO2SW0,
                .max_rings = 1,
-               .entry_size = sizeof(struct ath12k_hal_reo_dest_ring) >> 2,
+               .entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_UMAC,
                .ring_dir = HAL_SRNG_DIR_DST,
                .max_size = HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE,
@@ -19437,7 +19412,7 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .start_ring_id = HAL_SRNG_RING_ID_REO_CMD,
                .max_rings = 1,
                .entry_size = (sizeof(struct hal_tlv_64_hdr) +
-                   sizeof(struct ath12k_hal_reo_get_queue_stats)) >> 2,
+                   sizeof(struct hal_reo_get_queue_stats)) >> 2,
                .mac_type = ATH12K_HAL_SRNG_UMAC,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE,
@@ -19454,7 +19429,7 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
        [HAL_TCL_DATA] = {
                .start_ring_id = HAL_SRNG_RING_ID_SW2TCL1,
                .max_rings = 6,
-               .entry_size = sizeof(struct ath12k_hal_tcl_data_cmd) >> 2,
+               .entry_size = sizeof(struct hal_tcl_data_cmd) >> 2,
                .mac_type = ATH12K_HAL_SRNG_UMAC,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
@@ -19529,7 +19504,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 1,
                .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_DMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        },
@@ -19538,7 +19512,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 0,
                .entry_size = 0,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_DST,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        },
@@ -19547,7 +19520,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 1,
                .entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        },
@@ -19558,17 +19530,14 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 2,
                .entry_size = 8 >> 2, /* TODO: Define the struct */
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        },
        [HAL_PPE2TCL] = {
                .start_ring_id = HAL_SRNG_RING_ID_PPE2TCL1,
                .max_rings = 1,
-               .entry_size =
-                   sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2,
+               .entry_size = sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
        },
@@ -19577,7 +19546,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 1,
                .entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE,
        },
@@ -19586,7 +19554,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 1,
                .entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_SRC,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        },
@@ -19595,7 +19562,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 1,
                .entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_DST,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        },
@@ -19604,7 +19570,6 @@ static const struct hal_srng_config hw_srng_config_templ[] = {
                .max_rings = 1,
                .entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
                .mac_type = ATH12K_HAL_SRNG_PMAC,
-               .lmac_ring = true,
                .ring_dir = HAL_SRNG_DIR_DST,
                .max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
        }
@@ -19625,121 +19590,91 @@ qwz_hal_srng_create_config(struct qwz_softc *sc)
            sizeof(hw_srng_config_templ));
 
        s = &hal->srng_config[HAL_REO_DST];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(sc);
-       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP(sc);
-       s->reg_size[0] =
-           HAL_REO2_RING_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc);
-       s->reg_size[1] = HAL_REO2_RING_HP(sc) - HAL_REO1_RING_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP;
+       s->reg_size[0] = HAL_REO2_RING_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc);
+       s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP;
 
        s = &hal->srng_config[HAL_REO_EXCEPTION];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(sc);
        s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP;
 
        s = &hal->srng_config[HAL_REO_REINJECT];
        s->max_rings = 1;
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(sc);
-       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
 
        s = &hal->srng_config[HAL_REO_CMD];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(sc);
-       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
 
        s = &hal->srng_config[HAL_REO_STATUS];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(sc);
-       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP;
 
        s = &hal->srng_config[HAL_TCL_DATA];
        s->max_rings = 5;
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB;
        s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;
-       s->reg_size[0] =
-           HAL_TCL2_RING_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc);
+       s->reg_size[0] = HAL_TCL2_RING_BASE_LSB - HAL_TCL1_RING_BASE_LSB;
        s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP;
 
        s = &hal->srng_config[HAL_TCL_CMD];
        s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(sc);
-       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;
 
        s = &hal->srng_config[HAL_TCL_STATUS];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(sc);
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;
 
        s = &hal->srng_config[HAL_CE_SRC];
        s->max_rings = 12;
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) + HAL_CE_DST_RING_BASE_LSB;
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) + HAL_CE_DST_RING_HP;
-       s->reg_size[0] =
-           HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(sc) -
-           HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc);
-       s->reg_size[1] =
-           HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(sc) -
-           HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB;
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP;
+       s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG -
+               HAL_SEQ_WCSS_UMAC_CE0_SRC_REG;
+       s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG -
+               HAL_SEQ_WCSS_UMAC_CE0_SRC_REG;
 
        s = &hal->srng_config[HAL_CE_DST];
        s->max_rings = 12;
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) + HAL_CE_DST_RING_BASE_LSB;
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) + HAL_CE_DST_RING_HP;
-       s->reg_size[0] =
-           HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) -
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc);
-       s->reg_size[1] =
-           HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) -
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_BASE_LSB;
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP;
+       s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG -
+               HAL_SEQ_WCSS_UMAC_CE0_DST_REG;
+       s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG -
+               HAL_SEQ_WCSS_UMAC_CE0_DST_REG;
 
        s = &hal->srng_config[HAL_CE_DST_STATUS];
        s->max_rings = 12;
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) + HAL_CE_DST_STATUS_RING_BASE_LSB;
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) + HAL_CE_DST_STATUS_RING_HP;
-       s->reg_size[0] =
-           HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) -
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc);
-       s->reg_size[1] =
-           HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) -
-           HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG +
+               HAL_CE_DST_STATUS_RING_BASE_LSB;
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_HP;
+       s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG -
+               HAL_SEQ_WCSS_UMAC_CE0_DST_REG;
+       s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG -
+               HAL_SEQ_WCSS_UMAC_CE0_DST_REG;
 
        s = &hal->srng_config[HAL_WBM_IDLE_LINK];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc);
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
 
        s = &hal->srng_config[HAL_SW2WBM_RELEASE];
        s->max_rings = 1;
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(sc);
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
+               HAL_WBM_SW_RELEASE_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
 
        s = &hal->srng_config[HAL_WBM2SW_RELEASE];
-       s->reg_start[0] =
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(sc);
-       s->reg_start[1] =
-           HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP(sc);
-       s->reg_size[0] =
-           HAL_WBM1_RELEASE_RING_BASE_LSB(sc) -
-           HAL_WBM0_RELEASE_RING_BASE_LSB(sc);
-       s->reg_size[1] =
-           HAL_WBM1_RELEASE_RING_HP(sc) -
-           HAL_WBM0_RELEASE_RING_HP(sc);
+       s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(sc);
+       s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
+       s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(sc) -
+               HAL_WBM0_RELEASE_RING_BASE_LSB(sc);
+       s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP;
 
        s = &hal->srng_config[HAL_RXDMA_BUF];
        s->max_rings = 2;
        s->mac_type = ATH12K_HAL_SRNG_PMAC;
-       s->lmac_ring = true;
 
        s = &hal->srng_config[HAL_RXDMA_DST];
        s->max_rings = 1;
@@ -19808,11 +19743,11 @@ qwz_hal_srng_update_hp_tp_addr(struct qwz_softc *sc, int shadow_cfg_idx,
 
        if (srng_config->ring_dir == HAL_SRNG_DIR_DST)
                srng->u.dst_ring.tp_addr = (uint32_t *)(
-                   HAL_SHADOW_REG(sc, shadow_cfg_idx) +
+                   HAL_SHADOW_REG(shadow_cfg_idx) +
                    (unsigned long)sc->mem);
        else
                srng->u.src_ring.hp_addr = (uint32_t *)(
-                   HAL_SHADOW_REG(sc, shadow_cfg_idx) +
+                   HAL_SHADOW_REG(shadow_cfg_idx) +
                    (unsigned long)sc->mem);
 }
 
@@ -19857,7 +19792,7 @@ qwz_hal_srng_update_shadow_config(struct qwz_softc *sc,
 
        DPRINTF("%s: target_reg %x, shadow reg 0x%x shadow_idx 0x%x, "
            "ring_type %d, ring num %d\n", __func__, target_reg,
-            HAL_SHADOW_REG(sc, shadow_cfg_idx), shadow_cfg_idx,
+            HAL_SHADOW_REG(shadow_cfg_idx), shadow_cfg_idx,
             ring_type, ring_num);
 
        return 0;
@@ -20064,7 +19999,7 @@ qwz_hal_srng_dst_hw_init(struct qwz_softc *sc, struct hal_srng *srng)
        /* Initialize head and tail pointers to indicate ring is empty */
        reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2];
        sc->ops.write32(sc, reg_base, 0);
-       sc->ops.write32(sc, reg_base + HAL_REO1_RING_TP_OFFSET(sc), 0);
+       sc->ops.write32(sc, reg_base + HAL_REO1_RING_TP_OFFSET, 0);
        *srng->u.dst_ring.hp_addr = 0;
 
        reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
@@ -20113,7 +20048,7 @@ qwz_hal_srng_src_hw_init(struct qwz_softc *sc, struct hal_srng *srng)
            ((uint64_t)srng->ring_base_paddr >> HAL_ADDR_MSB_REG_SHIFT)) |
            FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE,
            (srng->entry_size * srng->num_entries));
-       sc->ops.write32(sc, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(sc), val);
+       sc->ops.write32(sc, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET, val);
 
        val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
        sc->ops.write32(sc, reg_base + HAL_TCL1_RING_ID_OFFSET(sc), val);
@@ -20171,9 +20106,8 @@ qwz_hal_srng_src_hw_init(struct qwz_softc *sc, struct hal_srng *srng)
 
        val |= HAL_TCL1_RING_MISC_SRNG_ENABLE;
 
-       if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) {
-               val |= ATH12K_HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE;
-       }
+       if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK)
+               val |= HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE;
 
        sc->ops.write32(sc, reg_base + HAL_TCL1_RING_MISC_OFFSET(sc), val);
 }
@@ -20307,12 +20241,7 @@ qwz_hal_srng_setup(struct qwz_softc *sc, enum hal_ring_type type,
                srng->u.src_ring.tp_addr = (void *)(hal->rdp.vaddr + ring_id);
                srng->u.src_ring.low_threshold = params->low_threshold *
                    srng->entry_size;
-               if (srng_config->lmac_ring) {
-                       lmac_idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START;
-                       srng->u.src_ring.hp_addr = (void *)(hal->wrp.vaddr +
-                           lmac_idx);
-                       srng->flags |= HAL_SRNG_FLAGS_LMAC_RING;
-               } else {
+               if (srng_config->mac_type == ATH12K_HAL_SRNG_UMAC) {
                        if (!sc->hw_params.supports_shadow_regs)
                                srng->u.src_ring.hp_addr =
                                    (uint32_t *)((unsigned long)sc->mem +
@@ -20323,6 +20252,11 @@ qwz_hal_srng_setup(struct qwz_softc *sc, enum hal_ring_type type,
                                    sc->sc_dev.dv_xname, type, ring_num, reg_base,
                                   (unsigned long)srng->u.src_ring.hp_addr -
                                   (unsigned long)sc->mem);
+               } else {
+                       lmac_idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START;
+                       srng->u.src_ring.hp_addr = (void *)(hal->wrp.vaddr +
+                           lmac_idx);
+                       srng->flags |= HAL_SRNG_FLAGS_LMAC_RING;
                }
        } else {
                /* During initialization loop count in all the descriptors
@@ -20337,32 +20271,32 @@ qwz_hal_srng_setup(struct qwz_softc *sc, enum hal_ring_type type,
                srng->u.dst_ring.tp = 0;
                srng->u.dst_ring.cached_hp = 0;
                srng->u.dst_ring.hp_addr = (void *)(hal->rdp.vaddr + ring_id);
-               if (srng_config->lmac_ring) {
-                       /* For LMAC rings, tail pointer updates will be done
-                        * through FW by writing to a shared memory location
-                        */
-                       lmac_idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START;
-                       srng->u.dst_ring.tp_addr = (void *)(hal->wrp.vaddr +
-                           lmac_idx);
-                       srng->flags |= HAL_SRNG_FLAGS_LMAC_RING;
-               } else {
+               if (srng_config->mac_type == ATH12K_HAL_SRNG_UMAC) {
                        if (!sc->hw_params.supports_shadow_regs)
                                srng->u.dst_ring.tp_addr =
                                    (uint32_t *)((unsigned long)sc->mem +
-                                   reg_base + (HAL_REO1_RING_TP(sc) -
-                                   HAL_REO1_RING_HP(sc)));
+                                   reg_base + (HAL_REO1_RING_TP -
+                                   HAL_REO1_RING_HP));
                        else
                                DPRINTF("%s: type %d ring_num %d target_reg "
                                    "0x%x shadow 0x%lx\n", sc->sc_dev.dv_xname,
                                    type, ring_num,
-                                   reg_base + (HAL_REO1_RING_TP(sc) -
-                                   HAL_REO1_RING_HP(sc)),
+                                   reg_base + (HAL_REO1_RING_TP -
+                                   HAL_REO1_RING_HP),
                                    (unsigned long)srng->u.dst_ring.tp_addr -
                                    (unsigned long)sc->mem);
+               } else {
+                       /* For LMAC rings, tail pointer updates will be done
+                        * through FW by writing to a shared memory location
+                        */
+                       lmac_idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START;
+                       srng->u.dst_ring.tp_addr = (void *)(hal->wrp.vaddr +
+                           lmac_idx);
+                       srng->flags |= HAL_SRNG_FLAGS_LMAC_RING;
                }
        }
 
-       if (srng_config->lmac_ring)
+       if (srng_config->mac_type != ATH12K_HAL_SRNG_UMAC)
                return ring_id;
 
        qwz_hal_srng_hw_init(sc, srng);
index d85bc07..02050a4 100644 (file)
@@ -1,4 +1,4 @@
-/*     $OpenBSD: qwzreg.h,v 1.3 2024/08/15 23:23:06 patrick Exp $      */
+/*     $OpenBSD: qwzreg.h,v 1.4 2024/08/16 00:26:54 patrick Exp $      */
 
 /*
  * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc.
@@ -7005,13 +7005,12 @@ enum ath12k_qmi_bdf_type {
 #define HAL_DSCP_TID_TBL_SIZE                  24
 
 /* calculate the register address from bar0 of shadow register x */
-#define HAL_SHADOW_BASE_ADDR(sc)               \
-       (sc->hw_params.regs->hal_shadow_base_addr)
+#define HAL_SHADOW_BASE_ADDR                   0x000008fc
 #define HAL_SHADOW_NUM_REGS                    40
 #define HAL_HP_OFFSET_IN_REG_START             1
 #define HAL_OFFSET_FROM_HP_TO_TP               4
 
-#define HAL_SHADOW_REG(sc, x) (HAL_SHADOW_BASE_ADDR(sc) + (4 * (x)))
+#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
 
 enum hal_srng_ring_id {
        HAL_SRNG_RING_ID_REO2SW0 = 0,
@@ -7220,31 +7219,23 @@ enum hal_reo_cmd_status {
 #define HAL_SEQ_WCSS_UMAC_OFFSET               0x00a00000
 #define HAL_SEQ_WCSS_UMAC_REO_REG              0x00a38000
 #define HAL_SEQ_WCSS_UMAC_TCL_REG              0x00a44000
-#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) \
-       (sc->hal_seq_wcss_umac_ce0_src_reg)
-#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) \
-       (sc->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)
-#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(sc) \
-       (sc->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)
-#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) \
-       (sc->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)
+#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG          0x01b80000
+#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG          0x01b81000
+#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG          0x01b82000
+#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG          0x01b83000
 #define HAL_SEQ_WCSS_UMAC_WBM_REG              0x00a34000
 
 #define HAL_CE_WFSS_CE_REG_BASE                        0x01b80000
-#define HAL_WLAON_REG_BASE                     0x01f80000
+
+#define HAL_TCL_SW_CONFIG_BANK_ADDR            0x00a4408c
 
 /* SW2TCL(x) R0 ring configuration address */
-#define HAL_TCL1_RING_CMN_CTRL_REG             \
-       (sc->hw_params.regs->hal_tcl1_ring_cmn_ctrl_reg)
-#define HAL_TCL1_RING_DSCP_TID_MAP             \
-       (sc->hw_params.regs->hal_tcl1_ring_dscp_tid_map)
-#define HAL_TCL1_RING_BASE_LSB(sc)             \
-       (sc->hw_params.regs->hal_tcl1_ring_base_lsb)
-#define HAL_TCL1_RING_BASE_MSB(sc)             \
-       (sc->hw_params.regs->hal_tcl1_ring_base_msb)
-#define HAL_TCL1_RING_ID(sc)                   \
-       (sc->hw_params.regs->hal_tcl1_ring_id)
-#define HAL_TCL1_RING_MISC(sc)                 \
+#define HAL_TCL1_RING_CMN_CTRL_REG             0x00000020
+#define HAL_TCL1_RING_DSCP_TID_MAP             0x00000240
+#define HAL_TCL1_RING_BASE_LSB                 0x00000900
+#define HAL_TCL1_RING_BASE_MSB                 0x00000904
+#define HAL_TCL1_RING_ID(sc)                   (sc->hw_params.regs->hal_tcl1_ring_id)
+#define HAL_TCL1_RING_MISC(sc) \
        (sc->hw_params.regs->hal_tcl1_ring_misc)
 #define HAL_TCL1_RING_TP_ADDR_LSB(sc) \
        (sc->hw_params.regs->hal_tcl1_ring_tp_addr_lsb)
@@ -7260,39 +7251,36 @@ enum hal_reo_cmd_status {
        (sc->hw_params.regs->hal_tcl1_ring_msi1_base_msb)
 #define HAL_TCL1_RING_MSI1_DATA(sc) \
        (sc->hw_params.regs->hal_tcl1_ring_msi1_data)
-#define HAL_TCL2_RING_BASE_LSB(sc)             \
-       (sc->hw_params.regs->hal_tcl2_ring_base_lsb)
-#define HAL_TCL_RING_BASE_LSB(sc)              \
+#define HAL_TCL2_RING_BASE_LSB                 0x00000978
+#define HAL_TCL_RING_BASE_LSB(sc) \
        (sc->hw_params.regs->hal_tcl_ring_base_lsb)
 
 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(sc)                         \
-       (HAL_TCL1_RING_MSI1_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+       (HAL_TCL1_RING_MSI1_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(sc)                         \
-       (HAL_TCL1_RING_MSI1_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+       (HAL_TCL1_RING_MSI1_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(sc)                             \
-       (HAL_TCL1_RING_MSI1_DATA(sc) - HAL_TCL1_RING_BASE_LSB(sc))
-#define HAL_TCL1_RING_BASE_MSB_OFFSET(sc)                              \
-       (HAL_TCL1_RING_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+       (HAL_TCL1_RING_MSI1_DATA(sc) - HAL_TCL1_RING_BASE_LSB)
+#define HAL_TCL1_RING_BASE_MSB_OFFSET                          \
+       (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_ID_OFFSET(sc)                            \
-       (HAL_TCL1_RING_ID(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+       (HAL_TCL1_RING_ID(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc)                   \
-       (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+       (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc) \
-               (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) - \
-               HAL_TCL1_RING_BASE_LSB(sc))
+               (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(sc) \
-               (HAL_TCL1_RING_TP_ADDR_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+               (HAL_TCL1_RING_TP_ADDR_LSB(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(sc) \
-               (HAL_TCL1_RING_TP_ADDR_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+               (HAL_TCL1_RING_TP_ADDR_MSB(sc) - HAL_TCL1_RING_BASE_LSB)
 #define HAL_TCL1_RING_MISC_OFFSET(sc) \
-               (HAL_TCL1_RING_MISC(sc) - HAL_TCL1_RING_BASE_LSB(sc))
+               (HAL_TCL1_RING_MISC(sc) - HAL_TCL1_RING_BASE_LSB)
 
 /* SW2TCL(x) R2 ring pointers (head/tail) address */
 #define HAL_TCL1_RING_HP                       0x00002000
 #define HAL_TCL1_RING_TP                       0x00002004
 #define HAL_TCL2_RING_HP                       0x00002008
-#define HAL_TCL_RING_HP(sc)                    \
-       (sc->hw_params.regs->hal_tcl_ring_hp)
+#define HAL_TCL_RING_HP                                0x00002028
 
 #define HAL_TCL1_RING_TP_OFFSET \
                (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
@@ -7300,24 +7288,40 @@ enum hal_reo_cmd_status {
 /* TCL STATUS ring address */
 #define HAL_TCL_STATUS_RING_BASE_LSB(sc)       \
        (sc->hw_params.regs->hal_tcl_status_ring_base_lsb)
-#define HAL_TCL_STATUS_RING_HP(sc)             \
-       (sc->hw_params.regs->hal_tcl_status_ring_hp)
+#define HAL_TCL_STATUS_RING_HP                 0x00002048
+
+/* PPE2TCL1 Ring address */
+#define HAL_TCL_PPE2TCL1_RING_BASE_LSB         0x00000c48
+#define HAL_TCL_PPE2TCL1_RING_HP               0x00002038
+
+/* WBM PPE Release Ring address */
+#define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_ppe_rel_ring_base)
+#define HAL_WBM_PPE_RELEASE_RING_HP            0x00003020
 
 /* REO2SW(x) R0 ring configuration address */
 #define HAL_REO1_GEN_ENABLE                    0x00000000
+#define HAL_REO1_MISC_CTRL_ADDR(sc) \
+       (sc->hw_params.regs->hal_reo1_misc_ctrl_addr)
 #define HAL_REO1_DEST_RING_CTRL_IX_0           0x00000004
 #define HAL_REO1_DEST_RING_CTRL_IX_1           0x00000008
 #define HAL_REO1_DEST_RING_CTRL_IX_2           0x0000000c
 #define HAL_REO1_DEST_RING_CTRL_IX_3           0x00000010
-#define HAL_REO1_MISC_CTL(sc)                  \
-       (sc->hw_params.regs->hal_reo1_misc_ctl)
-#define HAL_REO1_RING_BASE_LSB(sc)             \
+#define HAL_REO1_SW_COOKIE_CFG0(sc) \
+       (sc->hw_params.regs->hal_reo1_sw_cookie_cfg0)
+#define HAL_REO1_SW_COOKIE_CFG1(sc) \
+       (sc->hw_params.regs->hal_reo1_sw_cookie_cfg1)
+#define HAL_REO1_QDESC_LUT_BASE0(sc) \
+       (sc->hw_params.regs->hal_reo1_qdesc_lut_base0)
+#define HAL_REO1_QDESC_LUT_BASE1(sc) \
+       (sc->hw_params.regs->hal_reo1_qdesc_lut_base1)
+#define HAL_REO1_RING_BASE_LSB(sc) \
        (sc->hw_params.regs->hal_reo1_ring_base_lsb)
-#define HAL_REO1_RING_BASE_MSB(sc)             \
+#define HAL_REO1_RING_BASE_MSB(sc) \
        (sc->hw_params.regs->hal_reo1_ring_base_msb)
-#define HAL_REO1_RING_ID(sc)                   \
+#define HAL_REO1_RING_ID(sc) \
        (sc->hw_params.regs->hal_reo1_ring_id)
-#define HAL_REO1_RING_MISC(sc)                 \
+#define HAL_REO1_RING_MISC(sc) \
        (sc->hw_params.regs->hal_reo1_ring_misc)
 #define HAL_REO1_RING_HP_ADDR_LSB(sc) \
        (sc->hw_params.regs->hal_reo1_ring_hp_addr_lsb)
@@ -7331,80 +7335,69 @@ enum hal_reo_cmd_status {
        (sc->hw_params.regs->hal_reo1_ring_msi1_base_msb)
 #define HAL_REO1_RING_MSI1_DATA(sc) \
        (sc->hw_params.regs->hal_reo1_ring_msi1_data)
-#define HAL_REO2_RING_BASE_LSB(sc)             \
-       (sc->hw_params.regs->hal_reo2_ring_base_lsb)
+#define HAL_REO2_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_reo2_ring_base)
 #define HAL_REO1_AGING_THRESH_IX_0(sc) \
-       (sc->hw_params.regs->hal_reo1_aging_thresh_ix_0)
+       (sc->hw_params.regs->hal_reo1_aging_thres_ix0)
 #define HAL_REO1_AGING_THRESH_IX_1(sc) \
-       (sc->hw_params.regs->hal_reo1_aging_thresh_ix_1)
+       (sc->hw_params.regs->hal_reo1_aging_thres_ix1)
 #define HAL_REO1_AGING_THRESH_IX_2(sc) \
-       (sc->hw_params.regs->hal_reo1_aging_thresh_ix_2)
+       (sc->hw_params.regs->hal_reo1_aging_thres_ix2)
 #define HAL_REO1_AGING_THRESH_IX_3(sc) \
-       (sc->hw_params.regs->hal_reo1_aging_thresh_ix_3)
+       (sc->hw_params.regs->hal_reo1_aging_thres_ix3)
 
 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(sc) \
-               (HAL_REO1_RING_MSI1_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_MSI1_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc) \
-               (HAL_REO1_RING_MSI1_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_MSI1_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_MSI1_DATA_OFFSET(sc) \
-               (HAL_REO1_RING_MSI1_DATA(sc) - HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_MSI1_DATA(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_BASE_MSB_OFFSET(sc) \
-               (HAL_REO1_RING_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
-#define HAL_REO1_RING_ID_OFFSET(sc) (HAL_REO1_RING_ID(sc) - \
-                                       HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
+#define HAL_REO1_RING_ID_OFFSET(sc) \
+       (HAL_REO1_RING_ID(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc) \
-               (HAL_REO1_RING_PRODUCER_INT_SETUP(sc) - \
-               HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_PRODUCER_INT_SETUP(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(sc) \
-               (HAL_REO1_RING_HP_ADDR_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_HP_ADDR_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(sc) \
-               (HAL_REO1_RING_HP_ADDR_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
+       (HAL_REO1_RING_HP_ADDR_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
 #define HAL_REO1_RING_MISC_OFFSET(sc) \
        (HAL_REO1_RING_MISC(sc) - HAL_REO1_RING_BASE_LSB(sc))
 
 /* REO2SW(x) R2 ring pointers (head/tail) address */
-#define HAL_REO1_RING_HP(sc)                   \
-       (sc->hw_params.regs->hal_reo1_ring_hp)
-#define HAL_REO1_RING_TP(sc)                   \
-       (sc->hw_params.regs->hal_reo1_ring_tp)
-#define HAL_REO2_RING_HP(sc)                   \
-       (sc->hw_params.regs->hal_reo2_ring_hp)
+#define HAL_REO1_RING_HP                       0x00003048
+#define HAL_REO1_RING_TP                       0x0000304c
+#define HAL_REO2_RING_HP                       0x00003050
 
-#define HAL_REO1_RING_TP_OFFSET(sc)    \
-       (HAL_REO1_RING_TP(sc) - HAL_REO1_RING_HP(sc))
+#define HAL_REO1_RING_TP_OFFSET                        (HAL_REO1_RING_TP - HAL_REO1_RING_HP)
 
 /* REO2SW0 ring configuration address */
 #define HAL_REO_SW0_RING_BASE_LSB(sc)          \
        ((sc)->hw_params.regs->hal_reo2_sw0_ring_base)
 
 /* REO2SW0 R2 ring pointer (head/tail) address */
-#define HAL_REO_SW0_RING_HP    0x00003088
-
-/* REO2TCL R0 ring configuration address */
-#define HAL_REO_TCL_RING_BASE_LSB(sc) \
-       (sc->hw_params.regs->hal_reo_tcl_ring_base_lsb)
-
-/* REO2TCL R2 ring pointer (head/tail) address */
-#define HAL_REO_TCL_RING_HP(sc)                        \
-       (sc->hw_params.regs->hal_reo_tcl_ring_hp)
+#define HAL_REO_SW0_RING_HP                    0x00003088
 
 /* REO CMD R0 address */
 #define HAL_REO_CMD_RING_BASE_LSB(sc) \
-       (sc->hw_params.regs->hal_reo_cmd_ring_base_lsb)
+       (sc->hw_params.regs->hal_reo_cmd_ring_base)
 
 /* REO CMD R2 address */
-#define HAL_REO_CMD_HP(sc)                     \
-       (sc->hw_params.regs->hal_reo_cmd_ring_hp)
+#define HAL_REO_CMD_HP                         0x00003020
 
 /* SW2REO R0 address */
 #define HAL_SW2REO_RING_BASE_LSB(sc) \
-       (sc->hw_params.regs->hal_sw2reo_ring_base_lsb)
+       (sc->hw_params.regs->hal_sw2reo_ring_base)
+#define HAL_SW2REO1_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_sw2reo1_ring_base)
 
 /* SW2REO R2 address */
-#define HAL_SW2REO_RING_HP(sc)                 \
-       (sc->hw_params.regs->hal_sw2reo_ring_hp)
+#define HAL_SW2REO_RING_HP                     0x00003028
+#define HAL_SW2REO1_RING_HP                    0x00003030
 
 /* CE ring R0 address */
+#define HAL_CE_SRC_RING_BASE_LSB               0x00000000
 #define HAL_CE_DST_RING_BASE_LSB               0x00000000
 #define HAL_CE_DST_STATUS_RING_BASE_LSB                0x00000058
 #define HAL_CE_DST_RING_CTRL                   0x000000b0
@@ -7415,62 +7408,83 @@ enum hal_reo_cmd_status {
 
 /* REO status address */
 #define HAL_REO_STATUS_RING_BASE_LSB(sc) \
-       (sc->hw_params.regs->hal_reo_status_ring_base_lsb)
-#define HAL_REO_STATUS_HP(sc)                  \
-       (sc->hw_params.regs->hal_reo_status_hp)
+       (sc->hw_params.regs->hal_reo_status_ring_base)
+#define HAL_REO_STATUS_HP                      0x000030a8
 
 /* WBM Idle R0 address */
-#define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \
-               (sc->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)
-#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \
-               (sc->hw_params.regs->hal_wbm_idle_link_ring_misc)
-#define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR      0x00000048
-#define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR         0x0000004c
-#define HAL_WBM_SCATTERED_RING_BASE_LSB                0x00000058
-#define HAL_WBM_SCATTERED_RING_BASE_MSB                0x0000005c
-#define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068
-#define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c
-#define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078
-#define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c
-#define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR      0x00000084
+#define HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_wbm_idle_ring_base_lsb)
+#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(sc) \
+       (sc->hw_params.regs->hal_wbm_idle_ring_misc_addr)
+#define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(sc) \
+       (sc->hw_params.regs->hal_wbm_r0_idle_list_cntl_addr)
+#define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(sc) \
+       (sc->hw_params.regs->hal_wbm_r0_idle_list_size_addr)
+#define HAL_WBM_SCATTERED_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_ring_base_lsb)
+#define HAL_WBM_SCATTERED_RING_BASE_MSB(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_ring_base_msb)
+#define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_desc_head_info_ix0)
+#define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_desc_head_info_ix1)
+#define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_desc_tail_info_ix0)
+#define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_desc_tail_info_ix1)
+#define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(sc) \
+       (sc->hw_params.regs->hal_wbm_scattered_desc_ptr_hp_addr)
 
 /* WBM Idle R2 address */
-#define HAL_WBM_IDLE_LINK_RING_HP(sc)  \
-       (sc->hw_params.regs->hal_wbm_idle_link_ring_up)
+#define HAL_WBM_IDLE_LINK_RING_HP              0x000030b8
 
 /* SW2WBM R0 release address */
-#define HAL_WBM_RELEASE_RING_BASE_LSB(x)       \
-       (sc->hw_params.regs->hal_wbm_release_ring_base_lsb)
+#define HAL_WBM_SW_RELEASE_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_wbm_sw_release_ring_base_lsb)
+#define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(sc) \
+       (sc->hw_params.regs->hal_wbm_sw1_release_ring_base_lsb)
 
 /* SW2WBM R2 release address */
-#define HAL_WBM_RELEASE_RING_HP(sc)            \
-       (sc->hw_params.regs->hal_wbm_release_ring_hp)
+#define HAL_WBM_SW_RELEASE_RING_HP             0x00003010
+#define HAL_WBM_SW1_RELEASE_RING_HP            0x00003018
 
 /* WBM2SW R0 release address */
-#define HAL_WBM0_RELEASE_RING_BASE_LSB(x)      \
+#define HAL_WBM0_RELEASE_RING_BASE_LSB(sc)     \
        (sc->hw_params.regs->hal_wbm0_release_ring_base_lsb)
-#define HAL_WBM1_RELEASE_RING_BASE_LSB(x)      \
+
+#define HAL_WBM1_RELEASE_RING_BASE_LSB(sc)     \
        (sc->hw_params.regs->hal_wbm1_release_ring_base_lsb)
 
 /* WBM2SW R2 release address */
-#define HAL_WBM0_RELEASE_RING_HP(sc)           \
-       (sc->hw_params.regs->hal_wbm0_release_ring_hp)
-#define HAL_WBM1_RELEASE_RING_HP(sc)           \
-       (sc->hw_params.regs->hal_wbm1_release_ring_hp)
+#define HAL_WBM0_RELEASE_RING_HP               0x000030c8
+#define HAL_WBM1_RELEASE_RING_HP               0x000030d0
 
 /* WBM cookie config address and mask */
-#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN  0x00000002
-#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN  0x00000004
-#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN  0x00000008
-#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN  0x00000010
-#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN  0x00000020
-#define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN   0x00000100
+#define HAL_WBM_SW_COOKIE_CFG0                 0x00000040
+#define HAL_WBM_SW_COOKIE_CFG1                 0x00000044
+#define HAL_WBM_SW_COOKIE_CFG2                 0x00000090
+#define HAL_WBM_SW_COOKIE_CONVERT_CFG          0x00000094
+
+#define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB       GENMASK(7, 0)
+#define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB           GENMASK(12, 8)
+#define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB           GENMASK(17, 13)
+#define HAL_WBM_SW_COOKIE_CFG_ALIGN                    BIT(18)
+#define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN          BIT(0)
+#define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN              BIT(1)
+#define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN              BIT(3)
+
+#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN          BIT(1)
+#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN          BIT(2)
+#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN          BIT(3)
+#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN          BIT(4)
+#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN          BIT(5)
+#define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN           BIT(8)
 
 /* TCL ring field mask and offset */
 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE               GENMASK(27, 8)
 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB      GENMASK(7, 0)
 #define HAL_TCL1_RING_ID_ENTRY_SIZE                    GENMASK(7, 0)
-#define ATH12K_HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE  BIT(0)
+#define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE         BIT(0)
 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE         BIT(1)
 #define HAL_TCL1_RING_MISC_MSI_SWAP                    BIT(3)
 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP                        BIT(4)
@@ -7505,11 +7519,16 @@ enum hal_reo_cmd_status {
 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE                BIT(8)
 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR               GENMASK(7, 0)
-#define HAL_REO1_GEN_ENABLE_FRAG_DST_RING              GENMASK(25, 23)
+#define HAL_REO1_MISC_CTL_FRAG_DST_RING                        GENMASK(20, 17)
+#define HAL_REO1_MISC_CTL_BAR_DST_RING                 GENMASK(24, 21)
 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE          BIT(2)
 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE         BIT(3)
-#define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING            GENMASK(20, 17)
-#define HAL_REO1_MISC_CTL_BAR_DST_RING                 GENMASK(24, 21)
+#define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB      GENMASK(7, 0)
+#define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB          GENMASK(12, 8)
+#define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB          GENMASK(17, 13)
+#define HAL_REO1_SW_COOKIE_CFG_ALIGN                   BIT(18)
+#define HAL_REO1_SW_COOKIE_CFG_ENABLE                  BIT(19)
+#define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE           BIT(20)
 
 /* CE ring bit field mask and shift */
 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN                        GENMASK(15, 0)
@@ -7533,29 +7552,25 @@ enum hal_reo_cmd_status {
 
 #define BASE_ADDR_MATCH_TAG_VAL 0x5
 
-#define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE                        0x000fffff
-#define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE                        0x000fffff
-#define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE                        0x000fffff
-#define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE                 0x0000ffff
-#define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE                    0x0000ffff
-#define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE                 0x0000ffff
-#define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE                    0x000fffff
-#define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE                        0x000fffff
-#define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE                 0x0000ffff
-#define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE                     0x0000ffff
-#define HAL_CE_DST_RING_BASE_MSB_RING_SIZE                     0x0000ffff
-#define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE              0x0000ffff
-#define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE              0x0000ffff
-#define ATH12K_HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE       0x000fffff
-#define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE             0x0000ffff
-#define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE             0x000fffff
-#define HAL_RXDMA_RING_MAX_SIZE                                        0x0000ffff
-#define HAL_RXDMA_RING_MAX_SIZE_BE                             0x000fffff
-#define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE            0x000fffff
-
-/* IPQ5018 ce registers */
-#define HAL_IPQ5018_CE_WFSS_REG_BASE           0x08400000
-#define HAL_IPQ5018_CE_SIZE                    0x200000
+#define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE                0x000fffff
+#define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE                0x000fffff
+#define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE         0x0000ffff
+#define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE            0x0000ffff
+#define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE         0x0000ffff
+#define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE            0x000fffff
+#define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE                0x000fffff
+#define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE         0x0000ffff
+#define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE             0x0000ffff
+#define HAL_CE_DST_RING_BASE_MSB_RING_SIZE             0x0000ffff
+#define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE      0x0000ffff
+#define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE      0x000fffff
+#define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE     0x0000ffff
+#define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE     0x000fffff
+#define HAL_RXDMA_RING_MAX_SIZE                                0x0000ffff
+#define HAL_RXDMA_RING_MAX_SIZE_BE                     0x000fffff
+#define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE    0x000fffff
+
+#define HAL_WBM2SW_REL_ERR_RING_NUM 3
 
 #define BUFFER_ADDR_INFO0_ADDR         GENMASK(31, 0)
 
@@ -8692,10 +8707,6 @@ struct hal_reo_get_queue_stats {
        uint32_t queue_addr_lo;
        uint32_t info0;
        uint32_t rsvd0[6];
-} __packed;
-
-struct ath12k_hal_reo_get_queue_stats {
-        struct hal_reo_get_queue_stats stats;
        uint32_t tlv64_pad;
 } __packed;
 
@@ -8833,154 +8844,10 @@ struct hal_tcl_data_cmd {
        uint32_t info2;
        uint32_t info3;
        uint32_t info4;
-} __packed;
-
-/* hal_tcl_data_cmd
- *
- * buf_addr_info
- *             Details of the physical address of a buffer or MSDU
- *             link descriptor.
- *
- * desc_type
- *             Indicates the type of address provided in the buf_addr_info.
- *             Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
- *
- * epd
- *             When this bit is set then input packet is an EPD type.
- *
- * encap_type
- *             Indicates the encapsulation that HW will perform. Values are
- *             defined in enum %HAL_TCL_ENCAP_TYPE_.
- *
- * encrypt_type
- *             Field only valid for encap_type: RAW
- *             Values are defined in enum %HAL_ENCRYPT_TYPE_.
- *
- * src_buffer_swap
- *             Treats source memory (packet buffer) organization as big-endian.
- *             1'b0: Source memory is little endian
- *             1'b1: Source memory is big endian
- *
- * link_meta_swap
- *             Treats link descriptor and Metadata as big-endian.
- *             1'b0: memory is little endian
- *             1'b1: memory is big endian
- *
- * search_type
- *             Search type select
- *             0 - Normal search, 1 - Index based address search,
- *             2 - Index based flow search
- *
- * addrx_en
- * addry_en
- *             Address X/Y search enable in ASE correspondingly.
- *             1'b0: Search disable
- *             1'b1: Search Enable
- *
- * cmd_num
- *             This number can be used to match against status.
- *
- * data_length
- *             MSDU length in case of direct descriptor. Length of link
- *             extension descriptor in case of Link extension descriptor.
- *
- * *_checksum_en
- *             Enable checksum replacement for ipv4, udp_over_ipv4, ipv6,
- *             udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6.
- *
- * to_fw
- *             Forward packet to FW along with classification result. The
- *             packet will not be forward to TQM when this bit is set.
- *             1'b0: Use classification result to forward the packet.
- *             1'b1: Override classification result & forward packet only to fw
- *
- * packet_offset
- *             Packet offset from Metadata in case of direct buffer descriptor.
- *
- * buffer_timestamp
- * buffer_timestamp_valid
- *             Frame system entrance timestamp. It shall be filled by first
- *             module (SW, TCL or TQM) that sees the frames first.
- *
- * mesh_enable
- *             For raw WiFi frames, this indicates transmission to a mesh STA,
- *             enabling the interpretation of the 'Mesh Control Present' bit
- *             (bit 8) of QoS Control.
- *             For native WiFi frames, this indicates that a 'Mesh Control'
- *             field is present between the header and the LLC.
- *
- * hlos_tid_overwrite
- *
- *             When set, TCL shall ignore the IP DSCP and VLAN PCP
- *             fields and use HLOS_TID as the final TID. Otherwise TCL
- *             shall consider the DSCP and PCP fields as well as HLOS_TID
- *             and choose a final TID based on the configured priority
- *
- * hlos_tid
- *             HLOS MSDU priority
- *             Field is used when HLOS_TID_overwrite is set.
- *
- * lmac_id
- *             TCL uses this LMAC_ID in address search, i.e, while
- *             finding matching entry for the packet in AST corresponding
- *             to given LMAC_ID
- *
- *             If LMAC ID is all 1s (=> value 3), it indicates wildcard
- *             match for any MAC
- *
- * dscp_tid_table_num
- *             DSCP to TID mapping table number that need to be used
- *             for the MSDU.
- *
- * search_index
- *             The index that will be used for index based address or
- *             flow search. The field is valid when 'search_type' is  1 or 2.
- *
- * cache_set_num
- *
- *             Cache set number that should be used to cache the index
- *             based search results, for address and flow search. This
- *             value should be equal to LSB four bits of the hash value of
- *             match data, in case of search index points to an entry which
- *             may be used in content based search also. The value can be
- *             anything when the entry pointed by search index will not be
- *             used for content based search.
- *
- * ring_id
- *             The buffer pointer ring ID.
- *             0 refers to the IDLE ring
- *             1 - N refers to other rings
- *
- * looping_count
- *
- *             A count value that indicates the number of times the
- *             producer of entries into the Ring has looped around the
- *             ring.
- *
- *             At initialization time, this value is set to 0. On the
- *             first loop, this value is set to 1. After the max value is
- *             reached allowed by the number of bits for this field, the
- *             count value continues with 0 again.
- *
- *             In case SW is the consumer of the ring entries, it can
- *             use this field to figure out up to where the producer of
- *             entries has created new entries. This eliminates the need to
- *             check where the head pointer' of the ring is located once
- *             the SW starts processing an interrupt indicating that new
- *             entries have been put into this ring...
- *
- *             Also note that SW if it wants only needs to look at the
- *             LSB bit of this count value.
- */
-
-#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd)
-
-struct ath12k_hal_tcl_data_cmd {
-       struct hal_tcl_data_cmd cmd;
        uint32_t info5;
 } __packed;
 
-/* ath12k_hal_tcl_data_cmd
+/* hal_tcl_data_cmd
  *
  * buf_addr_info
  *             Details of the physical address of a buffer or MSDU
@@ -9130,7 +8997,7 @@ struct ath12k_hal_tcl_data_cmd {
  *             LSB bit of this count value.
  */
 
-#define ATH12K_HAL_TCL_DESC_LEN sizeof(struct ath12k_hal_tcl_data_cmd)
+#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd)
 
 enum hal_tcl_gse_ctrl {
        HAL_TCL_GSE_CTRL_RD_STAT,
index 74c6e5a..c172020 100644 (file)
@@ -1,4 +1,4 @@
-/*     $OpenBSD: qwzvar.h,v 1.3 2024/08/15 23:23:06 patrick Exp $      */
+/*     $OpenBSD: qwzvar.h,v 1.4 2024/08/16 00:26:54 patrick Exp $      */
 
 /*
  * Copyright (c) 2018-2019 The Linux Foundation.
@@ -310,10 +310,6 @@ struct ath12k_hw_ops {
 extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850;
 
 struct ath12k_hw_regs {
-       uint32_t hal_tcl1_ring_cmn_ctrl_reg;
-       uint32_t hal_tcl1_ring_dscp_tid_map;
-       uint32_t hal_tcl1_ring_base_lsb;
-       uint32_t hal_tcl1_ring_base_msb;
        uint32_t hal_tcl1_ring_id;
        uint32_t hal_tcl1_ring_misc;
        uint32_t hal_tcl1_ring_tp_addr_lsb;
@@ -323,52 +319,12 @@ struct ath12k_hw_regs {
        uint32_t hal_tcl1_ring_msi1_base_lsb;
        uint32_t hal_tcl1_ring_msi1_base_msb;
        uint32_t hal_tcl1_ring_msi1_data;
-       uint32_t hal_tcl2_ring_base_lsb;
        uint32_t hal_tcl_ring_base_lsb;
-       uint32_t hal_tcl_ring_hp;
 
        uint32_t hal_tcl_status_ring_base_lsb;
-       uint32_t hal_tcl_status_ring_hp;
 
-       uint32_t hal_reo1_ring_base_lsb;
-       uint32_t hal_reo1_ring_base_msb;
-       uint32_t hal_reo1_ring_id;
-       uint32_t hal_reo1_ring_misc;
-       uint32_t hal_reo1_ring_hp_addr_lsb;
-       uint32_t hal_reo1_ring_hp_addr_msb;
-       uint32_t hal_reo1_ring_producer_int_setup;
-       uint32_t hal_reo1_ring_msi1_base_lsb;
-       uint32_t hal_reo1_ring_msi1_base_msb;
-       uint32_t hal_reo1_ring_msi1_data;
-       uint32_t hal_reo2_ring_base_lsb;
-       uint32_t hal_reo1_aging_thresh_ix_0;
-       uint32_t hal_reo1_aging_thresh_ix_1;
-       uint32_t hal_reo1_aging_thresh_ix_2;
-       uint32_t hal_reo1_aging_thresh_ix_3;
-
-       uint32_t hal_reo1_ring_hp;
-       uint32_t hal_reo1_ring_tp;
-       uint32_t hal_reo2_ring_hp;
-
-       uint32_t hal_reo_tcl_ring_base_lsb;
-       uint32_t hal_reo_tcl_ring_hp;
-
-       uint32_t hal_reo_status_ring_base_lsb;
-       uint32_t hal_reo_status_hp;
-
-       uint32_t hal_reo_cmd_ring_base_lsb;
-       uint32_t hal_reo_cmd_ring_hp;
-
-       uint32_t hal_sw2reo_ring_base_lsb;
-       uint32_t hal_sw2reo_ring_hp;
-
-       uint32_t hal_seq_wcss_umac_ce0_dst_reg;
-       uint32_t hal_seq_wcss_umac_ce1_src_reg;
-       uint32_t hal_seq_wcss_umac_ce1_dst_reg;
-
-       uint32_t hal_wbm_idle_link_ring_base_lsb;
-       uint32_t hal_wbm_idle_link_ring_misc;
-       uint32_t hal_wbm_idle_link_ring_up;
+       uint32_t hal_wbm_idle_ring_base_lsb;
+       uint32_t hal_wbm_idle_ring_misc_addr;
        uint32_t hal_wbm_r0_idle_list_cntl_addr;
        uint32_t hal_wbm_r0_idle_list_size_addr;
        uint32_t hal_wbm_scattered_ring_base_lsb;
@@ -379,33 +335,45 @@ struct ath12k_hw_regs {
        uint32_t hal_wbm_scattered_desc_tail_info_ix1;
        uint32_t hal_wbm_scattered_desc_ptr_hp_addr;
 
-       uint32_t hal_wbm_release_ring_base_lsb;
-       uint32_t hal_wbm_release_ring_hp;
+       uint32_t hal_wbm_sw_release_ring_base_lsb;
        uint32_t hal_wbm_sw1_release_ring_base_lsb;
-
        uint32_t hal_wbm0_release_ring_base_lsb;
-       uint32_t hal_wbm0_release_ring_hp;
        uint32_t hal_wbm1_release_ring_base_lsb;
-       uint32_t hal_wbm1_release_ring_hp;
 
        uint32_t pcie_qserdes_sysclk_en_sel;
        uint32_t pcie_pcs_osc_dtct_config_base;
 
        uint32_t hal_ppe_rel_ring_base;
 
-       uint32_t hal_shadow_base_addr;
-       uint32_t hal_reo1_misc_ctl;
+       uint32_t hal_reo2_ring_base;
+       uint32_t hal_reo1_misc_ctrl_addr;
        uint32_t hal_reo1_sw_cookie_cfg0;
        uint32_t hal_reo1_sw_cookie_cfg1;
        uint32_t hal_reo1_qdesc_lut_base0;
        uint32_t hal_reo1_qdesc_lut_base1;
+       uint32_t hal_reo1_ring_base_lsb;
+       uint32_t hal_reo1_ring_base_msb;
+       uint32_t hal_reo1_ring_id;
+       uint32_t hal_reo1_ring_misc;
+       uint32_t hal_reo1_ring_hp_addr_lsb;
+       uint32_t hal_reo1_ring_hp_addr_msb;
+       uint32_t hal_reo1_ring_producer_int_setup;
+       uint32_t hal_reo1_ring_msi1_base_lsb;
+       uint32_t hal_reo1_ring_msi1_base_msb;
+       uint32_t hal_reo1_ring_msi1_data;
        uint32_t hal_reo1_aging_thres_ix0;
        uint32_t hal_reo1_aging_thres_ix1;
        uint32_t hal_reo1_aging_thres_ix2;
        uint32_t hal_reo1_aging_thres_ix3;
 
        uint32_t hal_reo2_sw0_ring_base;
+
+       uint32_t hal_sw2reo_ring_base;
        uint32_t hal_sw2reo1_ring_base;
+
+       uint32_t hal_reo_cmd_ring_base;
+
+       uint32_t hal_reo_status_ring_base;
 };
 
 extern const struct ath12k_hw_regs wcn7850_regs;
@@ -678,7 +646,6 @@ struct hal_srng_config {
        uint16_t entry_size;
        uint32_t reg_start[HAL_SRNG_NUM_REG_GRP];
        uint16_t reg_size[HAL_SRNG_NUM_REG_GRP];
-       uint8_t lmac_ring;
        enum hal_srng_mac_type mac_type;
        enum hal_srng_dir ring_dir;
        uint32_t max_size;
@@ -2046,7 +2013,6 @@ struct qwz_softc {
        struct qwz_ops                  ops;
        bus_dma_tag_t                   sc_dmat;
        enum ath12k_hw_rev              sc_hw_rev;
-       uint32_t                        hal_seq_wcss_umac_ce0_src_reg;
        int                             static_window_map;
        struct qwz_device_id            id;
        char                            sc_bus_str[4]; /* "pci" or "ahb" */
index 19f3c8c..d4cad8d 100644 (file)
@@ -1,4 +1,4 @@
-/*     $OpenBSD: if_qwz_pci.c,v 1.2 2024/08/15 22:01:37 patrick Exp $  */
+/*     $OpenBSD: if_qwz_pci.c,v 1.3 2024/08/16 00:26:54 patrick Exp $  */
 
 /*
  * Copyright 2023 Stefan Sperling <stsp@openbsd.org>
@@ -824,7 +824,6 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
        switch (PCI_PRODUCT(pa->pa_id)) {
        case PCI_PRODUCT_QUALCOMM_WCN7850:
                sc->static_window_map = 0;
-               sc->hal_seq_wcss_umac_ce0_src_reg = 0x01b80000;
                psc->sc_pci_ops = &qwz_pci_ops_wcn7850;
                sc->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
                qwz_pci_read_hw_version(sc, &soc_hw_version_major,
@@ -1690,7 +1689,7 @@ qwz_pci_get_window_start(struct qwz_softc *sc, uint32_t offset)
        if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH12K_PCI_WINDOW_RANGE_MASK)
                /* if offset lies within DP register range, use 3rd window */
                return 3 * ATH12K_PCI_WINDOW_START;
-       else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc)) <
+       else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG) <
                 ATH12K_PCI_WINDOW_RANGE_MASK)
                 /* if offset lies within CE register range, use 2nd window */
                return 2 * ATH12K_PCI_WINDOW_START;