Increase NPTECL, as cache-lines are 64-bytes nowadays.

Also move it from pmap.h to pmap.c because it is an internal detail.

diff --git a/sys/arch/i386/i386/pmap.c b/sys/arch/i386/i386/pmap.c
index 1fc5261..eaea6c1 100644 (file)
--- a/sys/arch/i386/i386/pmap.c
+++ b/sys/arch/i386/i386/pmap.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: pmap.c,v 1.158 2013/02/13 20:45:41 kurt Exp $ */
+/*     $OpenBSD: pmap.c,v 1.159 2014/01/06 14:29:25 sf Exp $   */
 /*     $NetBSD: pmap.c,v 1.91 2000/06/02 17:46:37 thorpej Exp $        */
 
 /*
@@ -288,6 +288,12 @@ struct pmap_head pmaps;
 
 struct pool pmap_pmap_pool;
 
+/*
+ * Number of PTE's per cache line.  4 byte pte, 64-byte cache line
+ * Used to avoid false sharing of cache lines.
+ */
+#define NPTECL                 16
+
 /*
  * MULTIPROCESSOR: special VA's/ PTE's are actually allocated inside a
  * MAXCPUS*NPTECL array of PTE's, to avoid cache line thrashing
@@ -858,7 +864,7 @@ pmap_bootstrap(vaddr_t kva_start)
        /*
         * Waste some VA space to avoid false sharing of cache lines
         * for page table pages: Give each possible CPU a cache line
-        * of PTE's (8) to play with, though we only need 4.  We could
+        * of PTE's (16) to play with, though we only need 4.  We could
         * recycle some of this waste by putting the idle stacks here
         * as well; we could waste less space if we knew the largest
         * CPU ID beforehand.

diff --git a/sys/arch/i386/i386/pmapae.c b/sys/arch/i386/i386/pmapae.c
index f8b7924..2617fd1 100644 (file)
--- a/sys/arch/i386/i386/pmapae.c
+++ b/sys/arch/i386/i386/pmapae.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: pmapae.c,v 1.22 2013/02/09 20:37:41 miod Exp $        */
+/*     $OpenBSD: pmapae.c,v 1.23 2014/01/06 14:29:25 sf Exp $  */
 
 /*
  * Copyright (c) 2006 Michael Shalayeff
@@ -516,10 +516,10 @@ typedef u_int64_t pd_entry_t;     /* PDE */
 typedef u_int64_t pt_entry_t;  /* PTE */
 
 /*
- * Number of PTE's per cache line. 8 byte pte, 32-byte cache line
+ * Number of PTE's per cache line. 8 byte pte, 64-byte cache line
  * Used to avoid false sharing of cache lines.
  */
-#define        NPTECL          4
+#define        NPTECL          8
 
 /*
  * other data structures

diff --git a/sys/arch/i386/include/pmap.h b/sys/arch/i386/include/pmap.h
index ff132c6..33bad6e 100644 (file)
--- a/sys/arch/i386/include/pmap.h
+++ b/sys/arch/i386/include/pmap.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: pmap.h,v 1.62 2013/03/31 17:07:03 deraadt Exp $       */
+/*     $OpenBSD: pmap.h,v 1.63 2014/01/06 14:29:25 sf Exp $    */
 /*     $NetBSD: pmap.h,v 1.44 2000/04/24 17:18:18 thorpej Exp $        */
 
 /*
@@ -230,12 +230,6 @@
 #define PG_PVLIST      PG_AVAIL2       /* mapping has entry on pvlist */
 #define        PG_X            PG_AVAIL3       /* executable mapping */
 
-/*
- * Number of PTE's per cache line.  4 byte pte, 32-byte cache line
- * Used to avoid false sharing of cache lines.
- */
-#define NPTECL                 8
-
 #ifdef _KERNEL
 /*
  * pmap data structures: see pmap.c for details of locking.