Fix IA32_EPT_VPID_CAP_XO_TRANSLATIONS specification

Per Intel SDM (Vol 3D, App. A.10) bit 0 should be read as a 1 if enabled.

From Adam Steen. ok mlarkin@

diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index e023288..2d64a12 100644 (file)
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: specialreg.h,v 1.88 2020/09/13 05:57:28 jsg Exp $     */
+/*     $OpenBSD: specialreg.h,v 1.89 2021/03/29 12:39:02 dv Exp $      */
 /*     $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $      */
 /*     $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $  */
 
@@ -957,7 +957,7 @@
 #define IA32_VMX_TRUE_ENTRY_CTLS       0x490
 #define IA32_VMX_VMFUNC                        0x491
 
-#define IA32_EPT_VPID_CAP_XO_TRANSLATIONS      0x0
+#define IA32_EPT_VPID_CAP_XO_TRANSLATIONS      (1ULL << 0)
 #define IA32_EPT_VPID_CAP_PAGE_WALK_4          (1ULL << 6)
 #define IA32_EPT_VPID_CAP_WB                   (1ULL << 14)
 #define IA32_EPT_VPID_CAP_AD_BITS              (1ULL << 21)