-/* $OpenBSD: dec_2100_a50.c,v 1.19 2008/07/16 20:03:20 miod Exp $ */
+/* $OpenBSD: dec_2100_a50.c,v 1.20 2008/07/24 16:34:22 miod Exp $ */
/* $NetBSD: dec_2100_a50.c,v 1.43 2000/05/22 20:13:31 thorpej Exp $ */
/*
#include <machine/autoconf.h>
#include <machine/bus.h>
#include <machine/cpuconf.h>
+#include <machine/logout.h>
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
static void dec_2100_a50_cons_init(void);
static void dec_2100_a50_device_register(struct device *, void *);
+#ifndef SMALL_KERNEL
+static void dec_2100_a50_mcheck_handler(unsigned long, struct trapframe *,
+ unsigned long, unsigned long);
+static void dec_2100_a50_mcheck(unsigned long, unsigned long, unsigned long,
+ struct trapframe *);
+#endif
+
const struct alpha_variation_table dec_2100_a50_variations[] = {
{ SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" },
{ SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" },
platform.iobus = "apecs";
platform.cons_init = dec_2100_a50_cons_init;
platform.device_register = dec_2100_a50_device_register;
+#ifndef SMALL_KERNEL
+ platform.mcheck_handler = dec_2100_a50_mcheck_handler;
+#endif
}
static void
found = 1;
}
}
+
+#ifndef SMALL_KERNEL
+static void
+dec_2100_a50_mcheck(mces, type, logout, framep)
+ unsigned long mces;
+ unsigned long type;
+ unsigned long logout;
+ struct trapframe *framep;
+{
+ struct mchkinfo *mcp;
+ static const char *fmt1 = " %-25s = 0x%016lx\n";
+ int i, sysaddr;
+ mc_hdr_avanti *hdr;
+ mc_uc_avanti *ptr;
+
+ /*
+ * If we expected a machine check, just go handle it in common code.
+ */
+ mcp = &curcpu()->ci_mcinfo;
+ if (mcp->mc_expected) {
+ machine_check(mces, framep, type, logout);
+ return;
+ }
+
+ hdr = (mc_hdr_avanti *) logout;
+ ptr = (mc_uc_avanti *) (logout + sizeof (*hdr));
+
+ printf(" Processor Machine Check (%lx), Code 0x%x\n",
+ type, hdr->mcheck_code);
+ printf("CPU state:\n");
+ /* Print PAL fields */
+ for (i = 0; i < 32; i += 2) {
+ printf("\tPAL temp[%d-%d]\t\t= 0x%16lx 0x%16lx\n", i, i+1,
+ ptr->paltemp[i], ptr->paltemp[i+1]);
+ }
+ printf(fmt1, "Excepting Instruction Addr", ptr->exc_addr);
+ printf(fmt1, "Summary of arithmetic traps", ptr->exc_sum);
+ printf(fmt1, "Exception mask", ptr->exc_mask);
+ printf(fmt1, "ICCSR", ptr->iccsr);
+ printf(fmt1, "Base address for PALcode", ptr->pal_base);
+ printf(fmt1, "HIER", ptr->hier);
+ printf(fmt1, "HIRR", ptr->hirr);
+ printf(fmt1, "MM_CSR", ptr->mm_csr);
+ printf(fmt1, "DC_STAT", ptr->dc_stat);
+ printf(fmt1, "DC_ADDR", ptr->dc_addr);
+ printf(fmt1, "ABOX_CTL", ptr->abox_ctl);
+ printf(fmt1, "Bus Interface Unit status", ptr->biu_stat);
+ printf(fmt1, "Bus Interface Unit addr", ptr->biu_addr);
+ printf(fmt1, "Bus Interface Unit control", ptr->biu_ctl);
+ printf(fmt1, "Fill Syndrome", ptr->fill_syndrome);
+ printf(fmt1, "Fill Address", ptr->fill_addr);
+ printf(fmt1, "Effective VA", ptr->va);
+ printf(fmt1, "BC_TAG", ptr->bc_tag);
+
+ printf("\nCache and Memory Controller (21071-CA) state:\n");
+ printf(fmt1, "COMA_GCR", ptr->coma_gcr);
+ printf(fmt1, "COMA_EDSR", ptr->coma_edsr);
+ printf(fmt1, "COMA_TER", ptr->coma_ter);
+ printf(fmt1, "COMA_ELAR", ptr->coma_elar);
+ printf(fmt1, "COMA_EHAR", ptr->coma_ehar);
+ printf(fmt1, "COMA_LDLR", ptr->coma_ldlr);
+ printf(fmt1, "COMA_LDHR", ptr->coma_ldhr);
+ printf(fmt1, "COMA_BASE0", ptr->coma_base0);
+ printf(fmt1, "COMA_BASE1", ptr->coma_base1);
+ printf(fmt1, "COMA_BASE2", ptr->coma_base2);
+ printf(fmt1, "COMA_CNFG0", ptr->coma_cnfg0);
+ printf(fmt1, "COMA_CNFG1", ptr->coma_cnfg1);
+ printf(fmt1, "COMA_CNFG2", ptr->coma_cnfg2);
+
+ printf("\nPCI bridge (21071-DA) state:\n");
+
+ printf(fmt1, "EPIC Diag. control/status", ptr->epic_dcsr);
+ printf(fmt1, "EPIC_PEAR", ptr->epic_pear);
+ printf(fmt1, "EPIC_SEAR", ptr->epic_sear);
+ printf(fmt1, "EPIC_TBR1", ptr->epic_tbr1);
+ printf(fmt1, "EPIC_TBR2", ptr->epic_tbr2);
+ printf(fmt1, "EPIC_PBR1", ptr->epic_pbr1);
+ printf(fmt1, "EPIC_PBR2", ptr->epic_pbr2);
+ printf(fmt1, "EPIC_PMR1", ptr->epic_pmr1);
+ printf(fmt1, "EPIC_PMR2", ptr->epic_pmr2);
+ printf(fmt1, "EPIC_HARX1", ptr->epic_harx1);
+ printf(fmt1, "EPIC_HARX2", ptr->epic_harx2);
+ printf(fmt1, "EPIC_PMLT", ptr->epic_pmlt);
+ printf(fmt1, "EPIC_TAG0", ptr->epic_tag0);
+ printf(fmt1, "EPIC_TAG1", ptr->epic_tag1);
+ printf(fmt1, "EPIC_TAG2", ptr->epic_tag2);
+ printf(fmt1, "EPIC_TAG3", ptr->epic_tag3);
+ printf(fmt1, "EPIC_TAG4", ptr->epic_tag4);
+ printf(fmt1, "EPIC_TAG5", ptr->epic_tag5);
+ printf(fmt1, "EPIC_TAG6", ptr->epic_tag6);
+ printf(fmt1, "EPIC_TAG7", ptr->epic_tag7);
+ printf(fmt1, "EPIC_DATA0", ptr->epic_data0);
+ printf(fmt1, "EPIC_DATA1", ptr->epic_data1);
+ printf(fmt1, "EPIC_DATA2", ptr->epic_data2);
+ printf(fmt1, "EPIC_DATA3", ptr->epic_data3);
+ printf(fmt1, "EPIC_DATA4", ptr->epic_data4);
+ printf(fmt1, "EPIC_DATA5", ptr->epic_data5);
+ printf(fmt1, "EPIC_DATA6", ptr->epic_data6);
+ printf(fmt1, "EPIC_DATA7", ptr->epic_data7);
+
+ printf("\n");
+
+ if (type == ALPHA_SYS_MCHECK) {
+ printf("\nPCI bridge fault\n");
+ switch(hdr->mcheck_code) {
+ case AVANTI_RETRY_TIMEOUT:
+ printf("\tRetry timeout error accessing 0x%08lx.\n",
+ ptr->epic_pear & 0xffffffff);
+ break;
+
+ case AVANTI_DMA_DATA_PARITY:
+ printf("\tDMA data parity error accessing 0x%08lx.\n",
+ ptr->epic_pear & 0xffffffff);
+ break;
+
+ case AVANTI_IO_PARITY:
+ printf("\tI/O parity error at 0x%08lx during PCI cycle 0x%0lx.\n",
+ ptr->epic_pear & 0xffffffff,
+ (ptr->epic_dcsr >> 18) & 0xf);
+ break;
+
+ case AVANTI_TARGET_ABORT:
+ printf("\tPCI target abort at 0x%08lx during PCI cycle 0x%0lx.\n",
+ ptr->epic_pear & 0xffffffff,
+ (ptr->epic_dcsr >> 18) & 0xf);
+ break;
+
+ case AVANTI_NO_DEVICE:
+ printf("\tNo device responded at 0x%08lx during PCI cycle 0x%0lx\n.",
+ ptr->epic_pear & 0xffffffff,
+ (ptr->epic_dcsr >> 18) & 0xf);
+ break;
+
+ case AVANTI_CORRRECTABLE_MEMORY:
+ printf("\tCorrectable memory error reported.\n"
+ "\tWARNING ECC not implemented on this system!\n"
+ "\tError is incorrect.\n");
+ break;
+
+ case AVANTI_UNCORRECTABLE_PCI_MEMORY:
+ printf("\tUncorrectable memory error at %016lx reported "
+ "during DMA read.\n",
+ (ptr->epic_sear & 0xfffffff0) << 2);
+ break;
+
+ case AVANTI_INVALID_PT_LOOKUP:
+ printf("\tInvalid page table lookup during scatter/gather.\n" );
+ if (ptr->epic_dcsr & 0xf20)
+ printf("\tAddress lost.\n");
+ else
+ printf("\tBus address to 0x%08lx, PCI cycle 0x%0lx\n",
+ ptr->epic_pear & 0xffffffff,
+ (ptr->epic_dcsr >> 18) & 0xf);
+ break;
+
+ case AVANTI_MEMORY:
+ printf("\tMemory error at %016lx, ",
+ (ptr->epic_sear & 0xfffffff0) << 2);
+ sysaddr = (ptr->epic_sear & 0xffffffff) >> 21;
+ if (sysaddr >= ((ptr->coma_base0 >> 5) & 0x7ff) &&
+ sysaddr < (((ptr->coma_base0 >> 5) & 0x7ff) +
+ (1 << (7 - (ptr->coma_cnfg0 >> 1)))))
+ printf("SIMM bank 0\n");
+ else if (sysaddr >= ((ptr->coma_base1 >> 5) & 0x7ff) &&
+ sysaddr < (((ptr->coma_base1 >> 5) & 0x7ff) +
+ (1 << (7 - (ptr->coma_cnfg1 >> 1)))))
+ printf("SIMM bank 1\n");
+ else if (sysaddr >= ((ptr->coma_base2 >> 5) & 0x7ff) &&
+ sysaddr < (((ptr->coma_base2 >> 5) & 0x7ff) +
+ (1 << (7 - (ptr->coma_cnfg2 >> 1)))))
+ printf("SIMM bank 2\n");
+ else
+ printf("invalid memory bank?\n");
+ break;
+
+ case AVANTI_BCACHE_TAG_ADDR_PARITY:
+ printf("\tBcache tag address parity error, caused by ");
+ if (ptr->coma_edsr & 0x20)
+ printf("victim write\n");
+ else if (ptr->coma_edsr & 0x10)
+ printf("DMA. ioCmd<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
+ else
+ printf("CPU. cpuCReq<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
+ break;
+
+ case AVANTI_BCACHE_TAG_CTRL_PARITY:
+ printf("\tBcache tag control parity error, caused by ");
+ if (ptr->coma_edsr & 0x20)
+ printf("victim write\n");
+ else if (ptr->coma_edsr & 0x10)
+ printf("DMA. ioCmd<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
+ else
+ printf("CPU. cpuCReq<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
+ break;
+
+ case AVANTI_NONEXISTENT_MEMORY:
+ printf("\tNonexistent memory error, caused by ");
+ if (ptr->coma_edsr & 0x20)
+ printf("victim write\n");
+ else if (ptr->coma_edsr & 0x10)
+ printf("DMA. ioCmd<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
+ else
+ printf("CPU. cpuCReq<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
+ break;
+
+ case AVANTI_IO_BUS:
+ printf("\tI/O bus error at %08lx during PCI cycle %0lx\n",
+ ptr->epic_pear & 0xffffffff, (ptr->epic_dcsr >> 18) & 0xf);
+ break;
+
+ case AVANTI_BCACHE_TAG_PARITY:
+ printf("\tBcache tag address parity error.\n"
+ "\tcReg_h cycle %0lx, address<7:0> 0x%02lx\n",
+ (ptr->biu_stat >> 4) & 7,
+ ptr->biu_addr & 0xff);
+ break;
+
+ case AVANTI_BCACHE_TAG_CTRL_PARITY2:
+ printf("\tBcache tag control parity error.\n"
+ "\tcReg_h cycle %0lx, address<7:0> 0x%02lx\n",
+ (ptr->biu_stat >> 4) & 7,
+ ptr->biu_addr & 0xff);
+ break;
+
+ }
+ } else { /* ALPHA_PROC_MCHECK */
+ printf("\nProcessor fault\n");
+ switch(hdr->mcheck_code) {
+ case AVANTI_HARD_ERROR:
+ printf("\tHard error cycle.\n");
+ break;
+
+ case AVANTI_CORRECTABLE_ECC:
+ printf("\tCorrectable ECC error.\n"
+ "\tWARNING ECC not implemented on this system!\n"
+ "\tError is incorrect.\n");
+ break;
+
+ case AVANTI_NONCORRECTABLE_ECC:
+ printf("\tNoncorrectable ECC error.\n"
+ "\tWARNING ECC not implemented on this system!\n"
+ "\tError is incorrect.\n");
+ break;
+
+ case AVANTI_UNKNOWN_ERROR:
+ printf("\tUnknown error.\n");
+ break;
+
+ case AVANTI_SOFT_ERROR:
+ printf("\tSoft error cycle.\n");
+ break;
+
+ case AVANTI_BUGCHECK:
+ printf("\tBugcheck.\n");
+ break;
+
+ case AVANTI_OS_BUGCHECK:
+ printf("\tOS Bugcheck.\n");
+ break;
+
+ case AVANTI_DCACHE_FILL_PARITY:
+ printf("\tPrimary Dcache data fill parity error.\n"
+ "\tDcache Quadword %lx, address %08lx\n",
+ (ptr->biu_stat >> 12) & 0x3,
+ (ptr->fill_addr >> 8) & 0x7f);
+ break;
+
+ case AVANTI_ICACHE_FILL_PARITY:
+ printf("\tPrimary Icache data fill parity error.\n"
+ "\tDcache Quadword %lx, address %08lx\n",
+ (ptr->biu_stat >> 12) & 0x3,
+ (ptr->fill_addr >> 8) & 0x7f);
+ break;
+ }
+ }
+
+ /*
+ * Now that we've printed all sorts of useful information
+ * and have decided that we really can't do any more to
+ * respond to the error, go on to the common code for
+ * final disposition. Usually this means that we die.
+ */
+ /*
+ * XXX: HANDLE PCI ERRORS HERE?
+ */
+ machine_check(mces, framep, type, logout);
+}
+
+static void
+dec_2100_a50_mcheck_handler(mces, framep, vector, param)
+ unsigned long mces;
+ struct trapframe *framep;
+ unsigned long vector;
+ unsigned long param;
+{
+ switch (vector) {
+ case ALPHA_SYS_MCHECK:
+ case ALPHA_PROC_MCHECK:
+ dec_2100_a50_mcheck(mces, vector, param, framep);
+ break;
+ default:
+ printf("2100_A50_MCHECK: unknown check vector 0x%lx\n", vector);
+ machine_check(mces, framep, vector, param);
+ break;
+ }
+}
+#endif /* !SMALL_KERNEL */
--- /dev/null
+/* $OpenBSD: logout.h,v 1.1 2008/07/24 16:34:25 miod Exp $ */
+/* $NetBSD: logout.h,v 1.6 2005/12/11 12:16:16 christos Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice immediately at the beginning of the file, without modification,
+ * this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Various Alpha OSF/1 PAL Logout error definitions.
+ */
+
+/*
+ * Information gathered from: DEC documentation
+ */
+
+/*
+ * Avanti (AlphaStation 200 and 400) Specific PALcode Exception Logout
+ * Area Definitions
+ */
+
+/*
+ * Avanti Specific common logout frame header.
+ * *Almost* identical to the generic logout header listed in alpha_cpu.h.
+ */
+
+typedef struct {
+ unsigned int la_frame_size; /* frame size */
+ unsigned int la_flags; /* flags; see alpha_cpu.h */
+ unsigned int la_cpu_offset; /* offset to CPU area */
+ unsigned int la_system_offset; /* offset to system area */
+ unsigned int mcheck_code; /* machine check code */
+ unsigned int :32;
+} mc_hdr_avanti;
+
+/* Machine Check Codes */
+
+/* SCB 660 Fatal Machine Checks */
+#define AVANTI_RETRY_TIMEOUT 0x201L
+#define AVANTI_DMA_DATA_PARITY 0x202L
+#define AVANTI_IO_PARITY 0x203L
+#define AVANTI_TARGET_ABORT 0x204L
+#define AVANTI_NO_DEVICE 0x205L
+#define AVANTI_CORRRECTABLE_MEMORY 0x206L /* Should never occur */
+#define AVANTI_UNCORRECTABLE_PCI_MEMORY 0x207L
+#define AVANTI_INVALID_PT_LOOKUP 0x208L
+#define AVANTI_MEMORY 0x209L
+#define AVANTI_BCACHE_TAG_ADDR_PARITY 0x20AL
+#define AVANTI_BCACHE_TAG_CTRL_PARITY 0x20BL
+#define AVANTI_NONEXISTENT_MEMORY 0x20CL
+#define AVANTI_IO_BUS 0x20DL
+#define AVANTI_BCACHE_TAG_PARITY 0x80L
+#define AVANTI_BCACHE_TAG_CTRL_PARITY2 0x82L
+
+/* SCB 670 Processor Fatal Machine Checks */
+#define AVANTI_HARD_ERROR 0x84L
+#define AVANTI_CORRECTABLE_ECC 0x86L
+#define AVANTI_NONCORRECTABLE_ECC 0x88L
+#define AVANTI_UNKNOWN_ERROR 0x8AL
+#define AVANTI_SOFT_ERROR 0x8CL
+#define AVANTI_BUGCHECK 0x8EL
+#define AVANTI_OS_BUGCHECK 0x90L
+#define AVANTI_DCACHE_FILL_PARITY 0x92L
+#define AVANTI_ICACHE_FILL_PARITY 0x94L
+
+typedef struct {
+ /* Registers from the CPU */
+ u_int64_t paltemp[32]; /* PAL TEMP REGS. */
+ u_int64_t exc_addr; /* Address of excepting ins. */
+ u_int64_t exc_sum; /* Summary of arithmetic traps. */
+ u_int64_t exc_mask; /* Exception mask. */
+ u_int64_t iccsr;
+ u_int64_t pal_base; /* Base address for PALcode. */
+ u_int64_t hier;
+ u_int64_t hirr;
+ u_int64_t mm_csr;
+ u_int64_t dc_stat;
+ u_int64_t dc_addr;
+ u_int64_t abox_ctl;
+ u_int64_t biu_stat; /* Bus Interface Unit Status. */
+ u_int64_t biu_addr;
+ u_int64_t biu_ctl;
+ u_int64_t fill_syndrome;
+ u_int64_t fill_addr;
+ u_int64_t va;
+ u_int64_t bc_tag;
+
+ /* Registers from the cache and memory controller (21071-CA) */
+ u_int64_t coma_gcr; /* Error and Diag. Status. */
+ u_int64_t coma_edsr;
+ u_int64_t coma_ter;
+ u_int64_t coma_elar;
+ u_int64_t coma_ehar;
+ u_int64_t coma_ldlr;
+ u_int64_t coma_ldhr;
+ u_int64_t coma_base0;
+ u_int64_t coma_base1;
+ u_int64_t coma_base2;
+ u_int64_t coma_cnfg0;
+ u_int64_t coma_cnfg1;
+ u_int64_t coma_cnfg2;
+
+ /* Registers from the PCI bridge (21071-DA) */
+ u_int64_t epic_dcsr; /* Diag. Control and Status. */
+ u_int64_t epic_pear;
+ u_int64_t epic_sear;
+ u_int64_t epic_tbr1;
+ u_int64_t epic_tbr2;
+ u_int64_t epic_pbr1;
+ u_int64_t epic_pbr2;
+ u_int64_t epic_pmr1;
+ u_int64_t epic_pmr2;
+ u_int64_t epic_harx1;
+ u_int64_t epic_harx2;
+ u_int64_t epic_pmlt;
+ u_int64_t epic_tag0;
+ u_int64_t epic_tag1;
+ u_int64_t epic_tag2;
+ u_int64_t epic_tag3;
+ u_int64_t epic_tag4;
+ u_int64_t epic_tag5;
+ u_int64_t epic_tag6;
+ u_int64_t epic_tag7;
+ u_int64_t epic_data0;
+ u_int64_t epic_data1;
+ u_int64_t epic_data2;
+ u_int64_t epic_data3;
+ u_int64_t epic_data4;
+ u_int64_t epic_data5;
+ u_int64_t epic_data6;
+ u_int64_t epic_data7;
+} mc_uc_avanti;
+
+/*
+ * Information gathered from: OSF/1 header files.
+ */
+
+
+/*
+ * EV5 Specific OSF/1 Pal Code Exception Logout Area Definitions
+ * (inspired from OSF/1 Header files).
+ */
+
+/*
+ * EV5 Specific common logout frame header.
+ * *Almost* identical to the generic logout header listed in alpha_cpu.h.
+ */
+
+typedef struct {
+ unsigned int la_frame_size; /* frame size */
+ unsigned int la_flags; /* flags; see alpha_cpu.h */
+ unsigned int la_cpu_offset; /* offset to CPU area */
+ unsigned int la_system_offset; /* offset to system area */
+ unsigned long mcheck_code; /* machine check code */
+} mc_hdr_ev5;
+
+/* Machine Check Codes */
+#define EV5_CORRECTED 0x86L
+#define SYSTEM_CORRECTED 0x201L
+
+/*
+ * EV5 Specific Machine Check logout frame for uncorrectable errors.
+ * This is used to log uncorrectable errors such as double bit ECC errors.
+ *
+ * This typically resides in the CPU offset area of the logout frame.
+ */
+
+typedef struct {
+ u_int64_t shadow[8]; /* Shadow reg. 8-14, 25 */
+ u_int64_t paltemp[24]; /* PAL TEMP REGS. */
+ u_int64_t exc_addr; /* Address of excepting ins. */
+ u_int64_t exc_sum; /* Summary of arithmetic traps. */
+ u_int64_t exc_mask; /* Exception mask. */
+ u_int64_t pal_base; /* Base address for PALcode. */
+ u_int64_t isr; /* Interrupt Status Reg. */
+ u_int64_t icsr; /* CURRENT SETUP OF EV5 IBOX */
+ u_int64_t ic_perr_stat; /*
+ * I-CACHE Reg:
+ * <13> IBOX Timeout
+ * <12> TAG parity
+ * <11> Data parity
+ */
+ u_int64_t dc_perr_stat; /* D-CACHE error Reg:
+ * Bits set to 1:
+ * <2> Data error in bank 0
+ * <3> Data error in bank 1
+ * <4> Tag error in bank 0
+ * <5> Tag error in bank 1
+ */
+ u_int64_t va; /* Effective VA of fault or miss. */
+ u_int64_t mm_stat; /*
+ * Holds the reason for D-stream
+ * fault or D-cache parity errors
+ */
+ u_int64_t sc_addr; /*
+ * Address that was being accessed
+ * when EV5 detected Secondary cache
+ * failure.
+ */
+ u_int64_t sc_stat; /*
+ * Helps determine if the error was
+ * TAG/Data parity(Secondary Cache)
+ */
+ u_int64_t bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
+ u_int64_t ei_addr; /*
+ * Physical address of any transfer
+ * that is logged in the EV5 EI_STAT
+ */
+ u_int64_t fill_syndrome; /* For correcting ECC errors. */
+ u_int64_t ei_stat; /*
+ * Helps identify reason of any
+ * processor uncorrectable error
+ * at its external interface.
+ */
+ u_int64_t ld_lock; /* Contents of EV5 LD_LOCK register*/
+} mc_uc_ev5;
+#define EV5_IC_PERR_IBOXTMO 0x2000
+
+/*
+ * EV5 Specific Machine Check logout frame for correctable errors.
+ *
+ * This is used to log correctable errors such as Single bit ECC errors.
+ */
+typedef struct {
+ u_int64_t ei_addr; /*
+ * Physical address of any transfer
+ * that is logged in the EV5 EI_STAT
+ */
+ u_int64_t fill_syndrome; /* For correcting ECC errors. */
+ u_int64_t ei_stat; /*
+ * Helps identify reason of any
+ * processor uncorrectable error
+ * at its external interface.
+ */
+ u_int64_t isr; /* Interrupt Status Reg. */
+} mc_cc_ev5;
+
+
+#ifdef _KERNEL
+extern void ev5_logout_print(mc_hdr_ev5 *, mc_uc_ev5 *);
+#endif
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