drm/radeon: fix possible division-by-zero errors
authorjsg <jsg@openbsd.org>
Thu, 20 Jul 2023 08:43:49 +0000 (08:43 +0000)
committerjsg <jsg@openbsd.org>
Thu, 20 Jul 2023 08:43:49 +0000 (08:43 +0000)
From Nikita Zhandarovich
1420545b8a155416b8bc2bb86a7709e9ca0c620c in linux-6.1.y/6.1.39
1becc57cd1a905e2aa0e1eca60d2a37744525c4a in mainline linux

sys/dev/pci/drm/radeon/cypress_dpm.c
sys/dev/pci/drm/radeon/ni_dpm.c
sys/dev/pci/drm/radeon/rv740_dpm.c

index fdddbba..72a0768 100644 (file)
@@ -557,8 +557,12 @@ static int cypress_populate_mclk_value(struct radeon_device *rdev,
                                                     ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
                        u32 reference_clock = rdev->clock.mpll.reference_freq;
                        u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
-                       u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
-                       u32 clk_v = ss.percentage *
+                       u32 clk_s, clk_v;
+
+                       if (!decoded_ref)
+                               return -EINVAL;
+                       clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
+                       clk_v = ss.percentage *
                                (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
 
                        mpll_ss1 &= ~CLKV_MASK;
index 672d223..3e1c1a3 100644 (file)
@@ -2241,8 +2241,12 @@ static int ni_populate_mclk_value(struct radeon_device *rdev,
                                                     ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
                        u32 reference_clock = rdev->clock.mpll.reference_freq;
                        u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
-                       u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
-                       u32 clk_v = ss.percentage *
+                       u32 clk_s, clk_v;
+
+                       if (!decoded_ref)
+                               return -EINVAL;
+                       clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
+                       clk_v = ss.percentage *
                                (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
 
                        mpll_ss1 &= ~CLKV_MASK;
index d57a3e1..4464fd2 100644 (file)
@@ -249,8 +249,12 @@ int rv740_populate_mclk_value(struct radeon_device *rdev,
                                                     ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
                        u32 reference_clock = rdev->clock.mpll.reference_freq;
                        u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
-                       u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
-                       u32 clk_v = 0x40000 * ss.percentage *
+                       u32 clk_s, clk_v;
+
+                       if (!decoded_ref)
+                               return -EINVAL;
+                       clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
+                       clk_v = 0x40000 * ss.percentage *
                                (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
 
                        mpll_ss1 &= ~CLKV_MASK;