#define R40_CLK_BUS_MMC1 33
#define R40_CLK_BUS_MMC2 34
#define R40_CLK_BUS_MMC3 35
+#define R40_CLK_BUS_SATA 45
#define R40_CLK_BUS_EHCI0 47
#define R40_CLK_BUS_EHCI1 48
#define R40_CLK_BUS_EHCI2 49
#define R40_CLK_MMC1 108
#define R40_CLK_MMC2 109
#define R40_CLK_MMC3 110
+#define R40_CLK_SATA 123
#define R40_CLK_USB_PHY0 124
#define R40_CLK_USB_PHY1 125
#define R40_CLK_USB_PHY2 126
[R40_CLK_BUS_MMC1] = { 0x0060, 9 },
[R40_CLK_BUS_MMC2] = { 0x0060, 10 },
[R40_CLK_BUS_MMC3] = { 0x0060, 11 },
+ [R40_CLK_BUS_SATA] = { 0x0060, 24 },
[R40_CLK_BUS_EHCI0] = { 0x0060, 26 },
[R40_CLK_BUS_EHCI1] = { 0x0060, 27 },
[R40_CLK_BUS_EHCI2] = { 0x0060, 28 },
[R40_CLK_MMC1] = { 0x008c, 31 },
[R40_CLK_MMC2] = { 0x0090, 31 },
[R40_CLK_MMC3] = { 0x0094, 31 },
+ [R40_CLK_SATA] = { 0x00c8, 31 },
[R40_CLK_USB_PHY0] = { 0x00cc, 8 },
[R40_CLK_USB_PHY1] = { 0x00cc, 9 },
[R40_CLK_USB_PHY2] = { 0x00cc, 10 },
#define R40_RST_BUS_MMC1 9
#define R40_RST_BUS_MMC2 10
#define R40_RST_BUS_MMC3 11
+#define R40_RST_BUS_SATA 21
#define R40_RST_BUS_EHCI0 23
#define R40_RST_BUS_EHCI1 24
#define R40_RST_BUS_EHCI2 25
[R40_RST_BUS_MMC1] = { 0x02c0, 9 },
[R40_RST_BUS_MMC2] = { 0x02c0, 10 },
[R40_RST_BUS_MMC3] = { 0x02c0, 11 },
+ [R40_RST_BUS_SATA] = { 0x02c0, 24 },
[R40_RST_BUS_EHCI0] = { 0x02c0, 26 },
[R40_RST_BUS_EHCI1] = { 0x02c0, 27 },
[R40_RST_BUS_EHCI2] = { 0x02c0, 28 },