* Force CPU into protected mode
* by making an intersegment jump (to ourselves, just a few lines
* down from here. We rely on the kernel to fixup the jump
- * target addres previously.
+ * target address previously.
*
*/
ljmpl $0x8, $.Lacpi_protected_mode_trampoline
-/* $OpenBSD: locore.S,v 1.13 2021/07/02 10:42:22 kettenis Exp $ */
+/* $OpenBSD: locore.S,v 1.14 2022/01/02 03:41:08 jsg Exp $ */
/*-
* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
sd t0, RISCV_BOOTPARAMS_DTBP_VIRT(sp)
sd a1, RISCV_BOOTPARAMS_DTBP_PHYS(sp)
- /* Set esym to virtual addres of symbol table end */
+ /* Set esym to virtual address of symbol table end */
lla t0, esym
sub t1, a0, s9
li t2, KERNBASE
-/* $OpenBSD: if_skreg.h,v 1.61 2017/04/08 03:36:50 jmatthew Exp $ */
+/* $OpenBSD: if_skreg.h,v 1.62 2022/01/02 03:41:08 jsg Exp $ */
/*
* Copyright (c) 1997, 1998, 1999, 2000
/* SMI Data Register (SMIDR) */
#define YUKON_SMIDR 0x0084
-/* PHY Addres Register (PAR) */
+/* PHY Address Register (PAR) */
#define YUKON_PAR 0x0088
#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */
-/* $OpenBSD: pci.c,v 1.120 2021/07/23 00:29:14 jmatthew Exp $ */
+/* $OpenBSD: pci.c,v 1.121 2022/01/02 03:41:08 jsg Exp $ */
/* $NetBSD: pci.c,v 1.31 1997/06/06 23:48:04 thorpej Exp $ */
/*
splx(s);
/*
- * Section 6.2.5.2 `Expansion ROM Base Addres Register',
+ * Section 6.2.5.2 `Expansion ROM Base Address Register',
*
* tells us that only the upper 21 bits are writable.
* This means that the size of a ROM must be a