drm/amd/display: Remove stutter only configurations

From Nasir Osman
5e1574aa0639abf811375aaba1d6799d035dc97b in linux-6.1.y/6.1.28
71c4ca2d3b079d0ba4d9b3033641fea906cebfb6 in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
index 020f512..e958f83 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1641,7 +1641,8 @@ noinline bool dcn30_internal_validate_bw(
                display_e2e_pipe_params_st *pipes,
                int *pipe_cnt_out,
                int *vlevel_out,
-               bool fast_validate)
+               bool fast_validate,
+               bool allow_self_refresh_only)
 {
        bool out = false;
        bool repopulate_pipes = false;
@@ -1668,7 +1669,7 @@ noinline bool dcn30_internal_validate_bw(
 
        dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
 
-       if (!fast_validate) {
+       if (!fast_validate || !allow_self_refresh_only) {
                /*
                 * DML favors voltage over p-state, but we're more interested in
                 * supporting p-state over voltage. We can't support p-state in
@@ -1681,11 +1682,12 @@ noinline bool dcn30_internal_validate_bw(
                if (vlevel < context->bw_ctx.dml.soc.num_states)
                        vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
        }
-       if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
-                       vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+       if (allow_self_refresh_only &&
+           (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
+                       vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
                /*
-                * If mode is unsupported or there's still no p-state support then
-                * fall back to favoring voltage.
+                * If mode is unsupported or there's still no p-state support
+                * then fall back to favoring voltage.
                 *
                 * We don't actually support prefetch mode 2, so require that we
                 * at least support prefetch mode 1.
@@ -2056,7 +2058,7 @@ bool dcn30_validate_bandwidth(struct dc *dc,
        BW_VAL_TRACE_COUNT();
 
        DC_FP_START();
-       out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
+       out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
        DC_FP_END();
 
        if (pipe_cnt == 0)

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.h b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.h
index 7d063c7..8e6b8b7 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -64,7 +64,8 @@ bool dcn30_internal_validate_bw(
                display_e2e_pipe_params_st *pipes,
                int *pipe_cnt_out,
                int *vlevel_out,
-               bool fast_validate);
+               bool fast_validate,
+               bool allow_self_refresh_only);
 void dcn30_calculate_wm_and_dlg(
                struct dc *dc, struct dc_state *context,
                display_e2e_pipe_params_st *pipes,

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_resource.c
index fddc21a..d825f11 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1770,7 +1770,7 @@ bool dcn31_validate_bandwidth(struct dc *dc,
        BW_VAL_TRACE_COUNT();
 
        DC_FP_START();
-       out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
+       out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
        DC_FP_END();
 
        // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
index 9918bcc..2f9c6d6 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1689,6 +1689,61 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi
        *panel_config = panel_config_defaults;
 }
 
+bool dcn314_validate_bandwidth(struct dc *dc,
+               struct dc_state *context,
+               bool fast_validate)
+{
+       bool out = false;
+
+       BW_VAL_TRACE_SETUP();
+
+       int vlevel = 0;
+       int pipe_cnt = 0;
+       display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
+       DC_LOGGER_INIT(dc->ctx->logger);
+
+       BW_VAL_TRACE_COUNT();
+
+       DC_FP_START();
+       // do not support self refresh only
+       out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
+       DC_FP_END();
+
+       // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
+       if (pipe_cnt == 0)
+               fast_validate = false;
+
+       if (!out)
+               goto validate_fail;
+
+       BW_VAL_TRACE_END_VOLTAGE_LEVEL();
+
+       if (fast_validate) {
+               BW_VAL_TRACE_SKIP(fast);
+               goto validate_out;
+       }
+
+       dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
+
+       BW_VAL_TRACE_END_WATERMARKS();
+
+       goto validate_out;
+
+validate_fail:
+       DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
+               dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
+
+       BW_VAL_TRACE_SKIP(fail);
+       out = false;
+
+validate_out:
+       kfree(pipes);
+
+       BW_VAL_TRACE_FINISH();
+
+       return out;
+}
+
 static struct resource_funcs dcn314_res_pool_funcs = {
        .destroy = dcn314_destroy_resource_pool,
        .link_enc_create = dcn31_link_encoder_create,
@@ -1696,7 +1751,7 @@ static struct resource_funcs dcn314_res_pool_funcs = {
        .link_encs_assign = link_enc_cfg_link_encs_assign,
        .link_enc_unassign = link_enc_cfg_link_enc_unassign,
        .panel_cntl_create = dcn31_panel_cntl_create,
-       .validate_bandwidth = dcn31_validate_bandwidth,
+       .validate_bandwidth = dcn314_validate_bandwidth,
        .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
        .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
        .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.h b/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.h
index 0dd3153..49ffe71 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.h
+++ b/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.h
@@ -39,6 +39,10 @@ struct dcn314_resource_pool {
        struct resource_pool base;
 };
 
+bool dcn314_validate_bandwidth(struct dc *dc,
+               struct dc_state *context,
+               bool fast_validate);
+
 struct resource_pool *dcn314_create_resource_pool(
                const struct dc_init_data *init_data,
                struct dc *dc);

diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index e1e92da..990dbd7 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -636,7 +636,7 @@ int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
        while (dummy_latency_index < max_latency_table_entries) {
                context->bw_ctx.dml.soc.dram_clock_change_latency_us =
                                dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
-               dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
+               dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);
 
                if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==
                        dm_allow_self_refresh_and_mclk_switch)