-/* $OpenBSD: rkclock.c,v 1.88 2024/04/01 11:16:11 patrick Exp $ */
+/* $OpenBSD: rkclock.c,v 1.89 2024/06/11 09:15:33 kettenis Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
SEL(11, 10), 0,
{ RK3588_CLK_200M_SRC, RK3588_CLK_150M_SRC, RK3588_XIN24M },
},
+ {
+ RK3588_CLK_TSADC, RK3588_CRU_CLKSEL_CON(41),
+ SEL(8, 8), DIV(7, 0),
+ { RK3588_PLL_GPLL, RK3588_XIN24M },
+ },
{
RK3588_CLK_UART1_SRC, RK3588_CRU_CLKSEL_CON(41),
SEL(14, 14), DIV(13, 9),
uint32_t bit, mask, reg;
switch (idx) {
+ case RK3588_SRST_P_TSADC:
+ reg = RK3588_CRU_SOFTRST_CON(12);
+ bit = 0;
+ break;
+ case RK3588_SRST_TSADC:
+ reg = RK3588_CRU_SOFTRST_CON(12);
+ bit = 1;
+ break;
case RK3588_SRST_A_GMAC0:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 10;
#define RK3588_CLK_SPI2 153
#define RK3588_CLK_SPI3 154
#define RK3588_CLK_SPI4 155
+#define RK3588_CLK_TSADC 158
#define RK3588_CLK_UART1_SRC 168
#define RK3588_CLK_UART1_FRAC 169
#define RK3588_CLK_UART1 170
#define RK3588_PLL_SPLL 1022
#define RK3588_XIN24M 1023
+#define RK3588_SRST_P_TSADC 86
+#define RK3588_SRST_TSADC 87
#define RK3588_SRST_A_GMAC0 291
#define RK3588_SRST_A_GMAC1 292
#define RK3588_SRST_PCIE0_POWER_UP 294