drm/amd/display: Do not set DRR on pipe Commit

From Wesley Chalmers
f8080f1e300e7abcc03025ec8b5bab69ae98daaa in linux-6.1.y/6.1.21
56574f89dbd84004c3fd6485bcaafb5aa9b8be14 in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 8c50457..c20e9f7 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -992,8 +992,5 @@ void dcn30_prepare_bandwidth(struct dc *dc,
                        dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
 
        dcn20_prepare_bandwidth(dc, context);
-
-       dc_dmub_srv_p_state_delegate(dc,
-               context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context);
 }