Tighten up BTCFI by flipping the bits that make PACIASP and PACIBSP

behave like BTI c instead of BTI jc.

ok deraadt@, tobhe@

diff --git a/sys/arch/arm64/arm64/cpu.c b/sys/arch/arm64/arm64/cpu.c
index 34444bd..b11bf36 100644 (file)
--- a/sys/arch/arm64/arm64/cpu.c
+++ b/sys/arch/arm64/arm64/cpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cpu.c,v 1.107 2024/03/01 15:57:43 kettenis Exp $      */
+/*     $OpenBSD: cpu.c,v 1.108 2024/03/05 18:42:20 kettenis Exp $      */
 
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
@@ -1042,6 +1042,13 @@ cpu_init(void)
                WRITE_SPECIALREG(sctlr_el1, sctlr);
        }
 
+       /* Enable strict BTI compatibility for PACIASP and PACIBSP. */
+       if (ID_AA64PFR1_BT(cpu_id_aa64pfr1) >= ID_AA64PFR1_BT_IMPL) {
+               sctlr = READ_SPECIALREG(sctlr_el1);
+               sctlr |= SCTLR_BT0 | SCTLR_BT1;
+               WRITE_SPECIALREG(sctlr_el1, sctlr);
+       }
+
        /* Initialize debug registers. */
        WRITE_SPECIALREG(mdscr_el1, DBG_MDSCR_TDCC);
        WRITE_SPECIALREG(oslar_el1, 0);

diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index 91d2f40..59983aa 100644 (file)
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.30 2023/11/29 23:32:16 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.31 2024/03/05 18:42:20 kettenis Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -656,6 +656,8 @@
 #define        SCTLR_EnDA      0x0000000008000000
 #define        SCTLR_EnIB      0x0000000040000000
 #define        SCTLR_EnIA      0x0000000080000000
+#define        SCTLR_BT0       0x0000000800000000
+#define        SCTLR_BT1       0x0000001000000000
 
 /* SPSR_EL1 */
 /*