Support Allwinner D1's ethernet controller clocks and reset.

ok kettenis@, deraadt@

diff --git a/sys/dev/fdt/sxiccmu.c b/sys/dev/fdt/sxiccmu.c
index e7047d3..f48378c 100644 (file)
--- a/sys/dev/fdt/sxiccmu.c
+++ b/sys/dev/fdt/sxiccmu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: sxiccmu.c,v 1.37 2024/03/04 04:11:52 deraadt Exp $    */
+/*     $OpenBSD: sxiccmu.c,v 1.38 2024/03/07 01:04:16 kevlo Exp $      */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -1265,12 +1265,15 @@ sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 #define D1_RISCV_CLK_SEL_HOSC          (0 << 24)
 #define D1_RISCV_CLK_SEL_PLL_CPU       (5 << 24)
 #define D1_RISCV_DIV_CFG_FACTOR_M(x)   (((x) >> 0) & 0x1f)
+#define D1_PSI_CLK_REG                 0x0510
+#define D1_PSI_CLK_FACTOR_N(x)         (((x) >> 8) & 0x3)
+#define D1_PSI_CLK_FACTOR_M(x)         (((x) >> 0) & 0x3)
 
 uint32_t
 sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 {
        uint32_t parent;
-       uint32_t reg;
+       uint32_t reg, freq;
        uint32_t m, n;
 
        switch (idx) {
@@ -1301,6 +1304,13 @@ sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
                }
                m = D1_RISCV_DIV_CFG_FACTOR_M(reg) + 1;
                return sxiccmu_ccu_get_frequency(sc, &parent) / m;
+       case D1_CLK_PSI_AHB:
+               reg = SXIREAD4(sc, D1_PSI_CLK_REG);
+               /* assume PLL_PERIPH0 source */
+               freq = sxiccmu_d1_get_frequency(sc, D1_CLK_PLL_PERIPH0);
+               m = D1_PSI_CLK_FACTOR_M(reg) + 1;
+               n = 1 << D1_PSI_CLK_FACTOR_N(reg);
+               return freq / (m * n);
        }
 
        printf("%s: 0x%08x\n", __func__, idx);

diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h
index cce1be6..402ef9d 100644 (file)
--- a/sys/dev/fdt/sxiccmu_clocks.h
+++ b/sys/dev/fdt/sxiccmu_clocks.h
@@ -364,6 +364,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
 
 #define D1_CLK_PLL_CPU         0
 #define D1_CLK_PLL_PERIPH0     5
+#define D1_CLK_PSI_AHB         23
 #define D1_CLK_APB1            25
 #define D1_CLK_MMC0            56
 #define D1_CLK_MMC1            57
@@ -377,6 +378,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
 #define D1_CLK_BUS_UART3       65
 #define D1_CLK_BUS_UART4       66
 #define D1_CLK_BUS_UART5       67
+#define D1_CLK_BUS_EMAC                77
 #define D1_CLK_USB_OHCI0       97
 #define D1_CLK_USB_OHCI1       98
 #define D1_CLK_BUS_OHCI0       99
@@ -400,6 +402,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_gates[] = {
        [D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 },
        [D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 },
        [D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 },
+       [D1_CLK_BUS_EMAC] =  { 0x097c, 0, D1_CLK_PSI_AHB },
        [D1_CLK_USB_OHCI0] = { 0x0a70, 31 },
        [D1_CLK_USB_OHCI1] = { 0x0a74, 31 },
        [D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
@@ -989,6 +992,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
 #define D1_RST_BUS_UART3       21
 #define D1_RST_BUS_UART4       22
 #define D1_RST_BUS_UART5       23
+#define D1_RST_BUS_EMAC                30
 #define D1_RST_USB_PHY0                40
 #define D1_RST_USB_PHY1                41
 #define D1_RST_BUS_OHCI0       42
@@ -1006,6 +1010,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_resets[] = {
        [D1_RST_BUS_UART3] = { 0x090c, 19 },
        [D1_RST_BUS_UART4] = { 0x090c, 20 },
        [D1_RST_BUS_UART5] = { 0x090c, 21 },
+       [D1_RST_BUS_EMAC] =  { 0x097c, 16 },
        [D1_RST_USB_PHY0] =  { 0x0a70, 30 },
        [D1_RST_USB_PHY1] =  { 0x0a74, 30 },
        [D1_RST_BUS_OHCI0] = { 0x0a8c, 16 },