drm/amd/display: Remove FPU guards from the DML folder
authorjsg <jsg@openbsd.org>
Tue, 13 Jun 2023 02:38:27 +0000 (02:38 +0000)
committerjsg <jsg@openbsd.org>
Tue, 13 Jun 2023 02:38:27 +0000 (02:38 +0000)
From Rodrigo Siqueira
0b47019f544fbf1667798085b71374fe4d09e611 in linux-6.1.y/6.1.29
bbfbf09d193ac831c40db50ef4b31d11548a9eef in mainline linux

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

index 990dbd7..4fa6363 100644 (file)
@@ -520,9 +520,7 @@ void dcn30_fpu_calculate_wm_and_dlg(
                pipe_idx++;
        }
 
-       DC_FP_START();
        dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
-       DC_FP_END();
 
        if (!pstate_en)
                /* Restore full p-state latency */
index e22b4b3..d2b184f 100644 (file)
@@ -1200,9 +1200,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
                        }
                } else {
                        // Most populate phantom DLG params before programming hardware / timing for phantom pipe
-                       DC_FP_START();
                        dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
-                       DC_FP_END();
 
                        /* Call validate_apply_pipe_split flags after calling DML getters for
                         * phantom dlg params, or some of the VBA params indicating pipe split
@@ -1503,11 +1501,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,
 
        dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
 
-       if (!fast_validate) {
-               DC_FP_START();
+       if (!fast_validate)
                dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
-               DC_FP_END();
-       }
 
        if (fast_validate ||
                        (dc->debug.dml_disallow_alternate_prefetch_modes &&
@@ -2172,9 +2167,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                entry.fabricclk_mhz = 0;
                entry.dram_speed_mts = 0;
 
-               DC_FP_START();
                insert_entry_into_table_sorted(table, num_entries, &entry);
-               DC_FP_END();
        }
 
        // Insert the max DCFCLK
@@ -2182,9 +2175,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
        entry.fabricclk_mhz = 0;
        entry.dram_speed_mts = 0;
 
-       DC_FP_START();
        insert_entry_into_table_sorted(table, num_entries, &entry);
-       DC_FP_END();
 
        // Insert the UCLK DPMS
        for (i = 0; i < num_uclk_dpms; i++) {
@@ -2192,9 +2183,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                entry.fabricclk_mhz = 0;
                entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
 
-               DC_FP_START();
                insert_entry_into_table_sorted(table, num_entries, &entry);
-               DC_FP_END();
        }
 
        // If FCLK is coarse grained, insert individual DPMs.
@@ -2204,9 +2193,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                        entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
                        entry.dram_speed_mts = 0;
 
-                       DC_FP_START();
                        insert_entry_into_table_sorted(table, num_entries, &entry);
-                       DC_FP_END();
                }
        }
        // If FCLK fine grained, only insert max
@@ -2215,9 +2202,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                entry.fabricclk_mhz = max_fclk_mhz;
                entry.dram_speed_mts = 0;
 
-               DC_FP_START();
                insert_entry_into_table_sorted(table, num_entries, &entry);
-               DC_FP_END();
        }
 
        // At this point, the table contains all "points of interest" based on