Add macros to get the appropriate interrupt target ID for non-UPA CPUs and

use them in cpu_myid().

diff --git a/sys/arch/sparc64/include/ctlreg.h b/sys/arch/sparc64/include/ctlreg.h
index 191b8eb..e033f7e 100644 (file)
--- a/sys/arch/sparc64/include/ctlreg.h
+++ b/sys/arch/sparc64/include/ctlreg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: ctlreg.h,v 1.18 2008/07/05 23:06:06 kettenis Exp $    */
+/*     $OpenBSD: ctlreg.h,v 1.19 2008/07/12 07:37:25 kettenis Exp $    */
 /*     $NetBSD: ctlreg.h,v 1.28 2001/08/06 23:55:34 eeh Exp $ */
 
 /*
@@ -246,10 +246,17 @@
  * The following are 4u control registers
  */
 
+/* Get the CPU's UPA port ID */
+#define        UPA_CR_MID(x)           (((x) >> 17) & 0x1f)
+#define        CPU_UPAID               UPA_CR_MID(ldxa(0, ASI_MID_REG))
 
-/* Get the CPU's UPAID */
-#define        UPA_CR_MID(x)   (((x)>>17)&0x1f)        
-#define        CPU_UPAID       UPA_CR_MID(ldxa(0, ASI_MID_REG))
+/* Get the CPU's Fireplane agent ID */
+#define FIREPLANE_CR_AID(x)    (((x) >> 17) & 0x3ff)
+#define CPU_FIREPLANEID                FIREPLANE_CR_AID(ldxa(0, ASI_MID_REG))
+
+/* Get the CPU's Jupiter Bus interrupt target ID */
+#define JUPITER_CR_ITID(x)     ((x) & 0x3ff)
+#define CPU_JUPITERID          JUPITER_CR_ITID(ldxa(0, ASI_MID_REG))
 
 /*
  * [4u] MMU and Cache Control Register (MCCR)

diff --git a/sys/arch/sparc64/sparc64/cpu.c b/sys/arch/sparc64/sparc64/cpu.c
index 589624f..f4bf09a 100644 (file)
--- a/sys/arch/sparc64/sparc64/cpu.c
+++ b/sys/arch/sparc64/sparc64/cpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cpu.c,v 1.42 2008/07/11 14:23:53 kettenis Exp $       */
+/*     $OpenBSD: cpu.c,v 1.43 2008/07/12 07:37:25 kettenis Exp $       */
 /*     $NetBSD: cpu.c,v 1.13 2001/05/26 21:27:15 chs Exp $ */
 
 /*
@@ -366,6 +366,7 @@ int
 cpu_myid(void)
 {
        char buf[32];
+       int impl;
 
 #ifdef SUN4V
        if (CPU_ISSUN4V) {
@@ -379,8 +380,20 @@ cpu_myid(void)
        if (OF_getprop(findroot(), "name", buf, sizeof(buf)) > 0 &&
            strcmp(buf, "SUNW,Ultra-Enterprise-10000") == 0)
                return lduwa(0x1fff40000d0UL, ASI_PHYS_NON_CACHED);
-       else
+
+       impl = (getver() & VER_IMPL) >> VER_IMPL_SHIFT;
+       switch (impl) {
+       case IMPL_OLYMPUS_C:
+       case IMPL_JUPITER:
+               return CPU_JUPITERID;
+       case IMPL_CHEETAH:
+       case IMPL_CHEETAH_PLUS:
+       case IMPL_JAGUAR:
+       case IMPL_PANTHER:
+               return CPU_FIREPLANEID;
+       default:
                return CPU_UPAID;
+       }
 }
 
 void