+++ /dev/null
-.\" $OpenBSD: elansc.4,v 1.22 2013/08/14 06:32:33 jmc Exp $
-.\" $NetBSD: elansc.4,v 1.1 2002/08/12 03:45:25 thorpej Exp $
-.\"
-.\" Copyright (c) 2002 The NetBSD Foundation, Inc.
-.\" All rights reserved.
-.\"
-.\" This code is derived from software contributed to The NetBSD Foundation
-.\" by Jason R. Thorpe.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\" notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\" notice, this list of conditions and the following disclaimer in the
-.\" documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
-.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
-.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-.\" POSSIBILITY OF SUCH DAMAGE.
-.\"
-.Dd $Mdocdate: August 14 2013 $
-.Dt ELANSC 4 i386
-.Os
-.Sh NAME
-.Nm elansc
-.Nd AMD Elan SC520 System Controller with watchdog timer and GPIO
-.Sh SYNOPSIS
-.Cd "elansc* at pci?"
-.Cd "gpio* at elansc?"
-.Sh DESCRIPTION
-The
-.Nm
-driver supports the system controller of the AMD Elan SC520 microcontroller.
-The SC520 consists of an AMD Am5x86 processor core, integrated PCI host
-controller, and several standard on-chip devices, such as NS16550-compatible
-UARTs, real-time clock, and timers.
-.Pp
-The Elan SC520 also provides several special on-chip devices.
-The following are supported by the
-.Nm
-driver:
-.Bl -bullet
-.It
-Watchdog timer.
-The watchdog timer may be configured for a 1 second, 2 second, 4 second,
-8 second, 16 second, or 32 second expiration period.
-.It
-Programmable Input/Output.
-The SC520 microcontroller supports 32 programmable I/O signals (PIOs)
-that can be used on the system board to monitor signals or control devices
-that are not handled by the other functions in the SC520 microcontroller.
-These signals can be programmed to be inputs or to be driven out
-.Dq high
-or
-.Dq low
-as outputs.
-Pins can be accessed through the
-.Xr gpio 4
-framework.
-The
-.Xr gpioctl 8
-program allows easy manipulation of pins from userland.
-.El
-.Sh SEE ALSO
-.Xr gpio 4 ,
-.Xr intro 4 ,
-.Xr watchdog 4 ,
-.Xr gpioctl 8 ,
-.Xr sysctl 8
-.Sh HISTORY
-Support for the
-.Nm
-was added in
-.Ox 3.3 .
-PIO function support appeared in
-.Ox 3.6 .
-.Sh AUTHORS
-.An -nosplit
-The
-.Nm
-driver was written by
-.An Jason R. Thorpe Aq Mt thorpej@netbsd.org .
-.An Jasper Wallace
-provided the work-around for a hardware bug related to the watchdog timer
-in some steppings of the SC520 CPU.
-.An Alexander Yurchenko Aq Mt grange@openbsd.org
-added support for the PIO function.
+++ /dev/null
-/* $OpenBSD: elan520.c,v 1.23 2022/02/21 10:24:28 mpi Exp $ */
-/* $NetBSD: elan520.c,v 1.4 2002/10/02 05:47:15 thorpej Exp $ */
-
-/*-
- * Copyright (c) 2002 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Device driver for the AMD Elan SC520 System Controller. This attaches
- * where the "pchb" driver might normally attach, and provides support for
- * extra features on the SC520, such as the watchdog timer and GPIO.
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/device.h>
-#include <sys/gpio.h>
-#include <sys/sysctl.h>
-#include <sys/time.h>
-#include <sys/timetc.h>
-
-#include <machine/bus.h>
-
-#include <machine/cpufunc.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcidevs.h>
-
-#include <dev/gpio/gpiovar.h>
-
-#include <arch/i386/pci/elan520reg.h>
-
-struct elansc_softc {
- struct device sc_dev;
- bus_space_tag_t sc_memt;
- bus_space_handle_t sc_memh;
-
- /* GPIO interface */
- struct gpio_chipset_tag sc_gpio_gc;
- gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS];
-
- /* GP timer */
- struct timecounter sc_tc;
-} *elansc;
-
-int elansc_match(struct device *, void *, void *);
-void elansc_attach(struct device *, struct device *, void *);
-int elansc_activate(struct device *, int);
-void elansc_update_cpuspeed(void);
-void elansc_setperf(int);
-int elansc_cpuspeed(int *);
-
-void elansc_wdogctl(struct elansc_softc *, int, uint16_t);
-#define elansc_wdogctl_reset(sc) elansc_wdogctl(sc, 1, 0)
-#define elansc_wdogctl_write(sc, val) elansc_wdogctl(sc, 0, val)
-int elansc_wdogctl_cb(void *, int);
-
-int elansc_gpio_pin_read(void *, int);
-void elansc_gpio_pin_write(void *, int, int);
-void elansc_gpio_pin_ctl(void *, int, int);
-
-u_int elansc_tc_read(struct timecounter *);
-
-const struct cfattach elansc_ca = {
- sizeof(struct elansc_softc), elansc_match, elansc_attach,
- NULL, elansc_activate
-};
-
-struct cfdriver elansc_cd = {
- NULL, "elansc", DV_DULL
-};
-
-int
-elansc_match(struct device *parent, void *match, void *aux)
-{
- struct pci_attach_args *pa = aux;
-
- if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
- PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_ELANSC520)
- return (10); /* beat pchb */
-
- return (0);
-}
-
-static const char *elansc_speeds[] = {
- "(reserved 00)",
- "100MHz",
- "133MHz",
- "(reserved 11)",
-};
-
-#define RSTBITS "\20\x07SCP\x06HRST\x05SRST\x04WDT\x03SD\x02PRGRST\x01PWRGOOD"
-
-void
-elansc_attach(struct device *parent, struct device *self, void *aux)
-{
- struct elansc_softc *sc = (void *) self;
- struct pci_attach_args *pa = aux;
- struct gpiobus_attach_args gba;
- struct timecounter *tc;
- uint16_t rev, data;
- uint8_t ressta, cpuctl, tmr;
- int pin, reg, shift;
-
- sc->sc_memt = pa->pa_memt;
- if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, NBPG, 0,
- &sc->sc_memh) != 0) {
- printf(": unable to map registers\n");
- return;
- }
-
- rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID);
- cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL);
- ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA);
-
- printf(": product %d stepping %d.%d, CPU clock %s, reset %b\n",
- (rev & REVID_PRODID) >> REVID_PRODID_SHIFT,
- (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT,
- (rev & REVID_MINSTEP),
- elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK],
- ressta, RSTBITS);
-
- /*
- * Determine cause of the last reset, and issue a warning if it
- * was due to watchdog expiry.
- */
- if (ressta & RESSTA_WDT_RST_DET)
- printf("%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n",
- sc->sc_dev.dv_xname);
- bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta);
-
- /* Set up the watchdog registers with some defaults. */
- elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
-
- /* ...and clear it. */
- elansc_wdogctl_reset(sc);
-
- wdog_register(elansc_wdogctl_cb, sc);
- elansc = sc;
- cpu_setperf = elansc_setperf;
- cpu_cpuspeed = elansc_cpuspeed;
- elansc_update_cpuspeed();
-
- /* Initialize GPIO pins array */
- for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) {
- sc->sc_gpio_pins[pin].pin_num = pin;
- sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT |
- GPIO_PIN_OUTPUT;
-
- /* Read initial state */
- reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
- shift = pin % 16;
- data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
- if ((data & (1 << shift)) == 0)
- sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT;
- else
- sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT;
- if (elansc_gpio_pin_read(sc, pin) == 0)
- sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW;
- else
- sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH;
- }
-
- /* Create controller tag */
- sc->sc_gpio_gc.gp_cookie = sc;
- sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read;
- sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write;
- sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl;
-
- gba.gba_name = "gpio";
- gba.gba_gc = &sc->sc_gpio_gc;
- gba.gba_pins = sc->sc_gpio_pins;
- gba.gba_npins = ELANSC_PIO_NPINS;
-
- /* Attach GPIO framework */
- config_found(&sc->sc_dev, &gba, gpiobus_print);
-
- /* Disable GP1/2, clear the current count, and set the period to max */
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1CTL,
- GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP |
- GPTMRCTL_PSC_SEL | GPTMRCTL_RTG);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT, 0);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1MAXCMPA, 0);
-
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2CTL,
- GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2CNT, 0);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2MAXCMPA, 0);
-
- tmr = bus_space_read_1(sc->sc_memt, sc->sc_memh, SWTMRCFG);
-
- /* Enable GP1/2 */
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1CTL,
- GPTMRCTL_ENB | GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP |
- GPTMRCTL_PSC_SEL | GPTMRCTL_RTG);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2CTL,
- GPTMRCTL_ENB | GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP);
-
- /* Attach timer */
- tc = &sc->sc_tc;
- tc->tc_get_timecount = elansc_tc_read;
- tc->tc_poll_pps = NULL;
- tc->tc_counter_mask = ~0;
- tc->tc_frequency = (tmr & 1) ? (33000000 / 4) : (33333333 / 4);
- tc->tc_name = sc->sc_dev.dv_xname;
- tc->tc_quality = 1000;
- tc->tc_priv = sc;
- tc_init(tc);
-}
-
-int
-elansc_activate(struct device *self, int act)
-{
- switch (act) {
- case DVACT_POWERDOWN:
- wdog_shutdown(self);
- break;
- }
-
- return (0);
-}
-
-u_int
-elansc_tc_read(struct timecounter *tc)
-{
- struct elansc_softc *sc = tc->tc_priv;
- u_int32_t m1, m2, l;
-
- do {
- m1 = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT);
- l = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR2CNT);
- m2 = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT);
- } while (m1 != m2);
-
- return ((m1 << 16) | l);
-}
-
-void
-elansc_wdogctl(struct elansc_softc *sc, int do_reset, uint16_t val)
-{
- int s;
- uint8_t echo_mode;
-
- s = splhigh();
-
- /* Switch off GP bus echo mode. */
- echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO);
- bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO,
- echo_mode & ~GPECHO_GP_ECHO_ENB);
-
- if (do_reset) {
- /* Reset the watchdog. */
- bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
- WDTMRCTL_RESET1);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
- WDTMRCTL_RESET2);
- } else {
- /* Unlock the register. */
- bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
- WDTMRCTL_UNLOCK1);
- bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
- WDTMRCTL_UNLOCK2);
-
- /* Write the value. */
- bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
- val);
- }
-
- /* Switch GP bus echo mode back. */
- bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, echo_mode);
-
- splx(s);
-}
-
-static const struct {
- int period; /* whole seconds */
- uint16_t exp; /* exponent select */
-} elansc_wdog_periods[] = {
- { 1, WDTMRCTL_EXP_SEL25 },
- { 2, WDTMRCTL_EXP_SEL26 },
- { 4, WDTMRCTL_EXP_SEL27 },
- { 8, WDTMRCTL_EXP_SEL28 },
- { 16, WDTMRCTL_EXP_SEL29 },
- { 32, WDTMRCTL_EXP_SEL30 },
-};
-
-int
-elansc_wdogctl_cb(void *self, int period)
-{
- struct elansc_softc *sc = self;
- int i;
-
- if (period == 0) {
- elansc_wdogctl_write(sc,
- WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
- } else {
- for (i = 0; i < (sizeof(elansc_wdog_periods) /
- sizeof(elansc_wdog_periods[0])) - 1; i++)
- if (elansc_wdog_periods[i].period >= period)
- break;
- period = elansc_wdog_periods[i].period;
- elansc_wdogctl_write(sc, WDTMRCTL_ENB |
- WDTMRCTL_WRST_ENB | elansc_wdog_periods[i].exp);
- elansc_wdogctl_reset(sc);
- }
- return (period);
-}
-
-void
-elansc_update_cpuspeed(void)
-{
- static const int elansc_mhz[] = { 0, 100, 133, 999 };
- uint8_t cpuctl;
-
- cpuctl = bus_space_read_1(elansc->sc_memt, elansc->sc_memh,
- MMCR_CPUCTL);
- cpuspeed = elansc_mhz[cpuctl & CPUCTL_CPU_CLK_SPD_MASK];
-}
-
-void
-elansc_setperf(int level)
-{
- uint8_t cpuctl, speed;
- u_long s;
-
- level = (level > 50) ? 100 : 0;
-
- cpuctl = bus_space_read_1(elansc->sc_memt, elansc->sc_memh,
- MMCR_CPUCTL);
- speed = (level == 100) ? 2 : 1;
- if ((cpuctl & CPUCTL_CPU_CLK_SPD_MASK) == speed)
- return;
-
- s = intr_disable();
- bus_space_write_1(elansc->sc_memt, elansc->sc_memh, MMCR_CPUCTL,
- (cpuctl & ~CPUCTL_CPU_CLK_SPD_MASK) | speed);
- intr_restore(s);
-
- elansc_update_cpuspeed();
-}
-
-int
-elansc_cpuspeed(int *freq)
-{
- *freq = cpuspeed;
- return (0);
-}
-
-int
-elansc_gpio_pin_read(void *arg, int pin)
-{
- struct elansc_softc *sc = arg;
- int reg, shift;
- u_int16_t data;
-
- reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
- shift = pin % 16;
- data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
-
- return ((data >> shift) & 0x1);
-}
-
-void
-elansc_gpio_pin_write(void *arg, int pin, int value)
-{
- struct elansc_softc *sc = arg;
- int reg, shift;
- u_int16_t data;
-
- reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
- shift = pin % 16;
- data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
- if (value == 0)
- data &= ~(1 << shift);
- else if (value == 1)
- data |= (1 << shift);
-
- bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
-}
-
-void
-elansc_gpio_pin_ctl(void *arg, int pin, int flags)
-{
- struct elansc_softc *sc = arg;
- int reg, shift;
- u_int16_t data;
-
- reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
- shift = pin % 16;
- data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
- if (flags & GPIO_PIN_INPUT)
- data &= ~(1 << shift);
- if (flags & GPIO_PIN_OUTPUT)
- data |= (1 << shift);
-
- bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
-}
+++ /dev/null
-/* $OpenBSD: elan520reg.h,v 1.4 2008/06/26 05:42:11 ray Exp $ */
-/* $NetBSD: elan520reg.h,v 1.1 2002/08/12 01:03:14 thorpej Exp $ */
-
-/*-
- * Copyright (c) 2002 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Register definitions for the AMD Elan SC520 System Controller.
- */
-
-#ifndef _I386_PCI_ELAN520REG_H_
-#define _I386_PCI_ELAN520REG_H_
-
-#define MMCR_BASE_ADDR 0xfffef000
-
-/*
- * Am5x86 CPU Registers.
- */
-#define MMCR_REVID 0x0000
-#define MMCR_CPUCTL 0x0002
-
-#define REVID_PRODID 0xff00 /* product ID */
-#define REVID_PRODID_SHIFT 8
-#define REVID_MAJSTEP 0x00f0 /* stepping major */
-#define REVID_MAJSTEP_SHIFT 4
-#define REVID_MINSTEP 0x000f /* stepping minor */
-
-#define PRODID_ELAN_SC520 0x00 /* Elan SC520 */
-
-#define CPUCTL_CPU_CLK_SPD_MASK 0x03 /* CPU clock speed */
-#define CPUCTL_CACHE_WR_MODE 0x10 /* cache mode (0 = wb, 1 = wt) */
-
-/*
- * General Purpose Bus Registers
- */
-#define MMCR_GPECHO 0x0c00 /* GP echo mode */
-#define MMCR_GPCSDW 0x0c01 /* GP chip sel data width */
-#define MMCR_CPCSQUAL 0x0c02 /* GP chip sel qualification */
-#define MMCR_GPCSRT 0x0c08 /* GP chip sel recovery time */
-#define MMCR_GPCSPW 0x0c09 /* GP chip sel pulse width */
-#define MMCR_GPCSOFF 0x0c0a /* GP chip sel offset */
-#define MMCR_GPRDW 0x0c0b /* GP read pulse width */
-#define MMCR_GPRDOFF 0x0c0c /* GP read offset */
-#define MMCR_GPWRW 0x0c0d /* GP write pulse width */
-#define MMCR_GPWROFF 0x0c0e /* GP write offset */
-#define MMCR_GPALEW 0x0c0f /* GPALE pulse width */
-#define MMCR_GPALEOFF 0x0c10 /* GPALE offset */
-
-#define GPECHO_GP_ECHO_ENB 0x01 /* GP bus echo mode enable */
-
-/*
- * Programmable Input/Output Registers
- */
-#define MMCR_PIOPFS15_0 0x0c20 /* PIO15-PIO0 pin func sel */
-#define MMCR_PIOPFS31_16 0x0c22 /* PIO31-PIO16 pin func sel */
-#define MMCR_CSPFS 0x0c24 /* chip sel pin func sel */
-#define MMCR_CLKSEL 0x0c26 /* clock select */
-#define MMCR_DSCTL 0x0c28 /* drive strength control */
-#define MMCR_PIODIR15_0 0x0c2a /* PIO15-PIO0 direction */
-#define MMCR_PIODIR31_16 0x0c2c /* PIO31-PIO16 direction */
-#define MMCR_PIODATA15_0 0x0c30 /* PIO15-PIO0 data */
-#define MMCR_PIODATA31_16 0x0c32 /* PIO31-PIO16 data */
-#define MMCR_PIOSET15_0 0x0c34 /* PIO15-PIO0 set */
-#define MMCR_PIOSET31_16 0x0c36 /* PIO31-PIO16 set */
-#define MMCR_PIOCLR15_0 0x0c38 /* PIO15-PIO0 clear */
-#define MMCR_PIOCLR31_16 0x0c3a /* PIO31-PIO16 clear */
-
-#define ELANSC_PIO_NPINS 32 /* total number of PIO pins */
-
-/*
- * Watchdog Timer Registers.
- */
-#define MMCR_WDTMRCTL 0x0cb0 /* watchdog timer control */
-#define MMCR_WDTMRCNTL 0x0cb2 /* watchdog timer count low */
-#define MMCR_WDTMRCNTH 0x0cb4 /* watchdog timer count high */
-
-#define WDTMRCTL_EXP_SEL_MASK 0x00ff /* exponent select */
-#define WDTMRCTL_EXP_SEL14 0x0001 /* 496us/492us */
-#define WDTMRCTL_EXP_SEL24 0x0002 /* 508ms/503ms */
-#define WDTMRCTL_EXP_SEL25 0x0004 /* 1.02s/1.01s */
-#define WDTMRCTL_EXP_SEL26 0x0008 /* 2.03s/2.01s */
-#define WDTMRCTL_EXP_SEL27 0x0010 /* 4.07s/4.03s */
-#define WDTMRCTL_EXP_SEL28 0x0020 /* 8.13s/8.05s */
-#define WDTMRCTL_EXP_SEL29 0x0040 /* 16.27s/16.11s */
-#define WDTMRCTL_EXP_SEL30 0x0080 /* 32.54s/32.21s */
-#define WDTMRCTL_IRQ_FLG 0x1000 /* interrupt request */
-#define WDTMRCTL_WRST_ENB 0x4000 /* watchdog timer reset enable */
-#define WDTMRCTL_ENB 0x8000 /* watchdog timer enable */
-
-#define WDTMRCTL_UNLOCK1 0x3333
-#define WDTMRCTL_UNLOCK2 0xcccc
-
-#define WDTMRCTL_RESET1 0xaaaa
-#define WDTMRCTL_RESET2 0x5555
-
-/*
- * Reset Generation Registers.
- */
-#define MMCR_SYSINFO 0x0d70 /* system board information */
-#define MMCR_RESCFG 0x0d72 /* reset configuration */
-#define MMCR_RESSTA 0x0d74 /* reset status */
-
-#define RESCFG_SYS_RST 0x01 /* software system reset */
-#define RESCFG_GP_RST 0x02 /* assert GP bus reset */
-#define RESCFG_PRG_RST_ENB 0x04 /* programmable reset enable */
-#define RESCFG_ICE_ON_RST 0x08 /* enter AMDebug(tm) on reset */
-
-#define RESSTA_PWRGOOD_DET 0x01 /* POWERGOOD reset detect */
-#define RESSTA_PRGRST_DET 0x02 /* programmable reset detect */
-#define RESSTA_SD_RST_DET 0x04 /* CPU shutdown reset detect */
-#define RESSTA_WDT_RST_DET 0x08 /* watchdog timer reset detect */
-#define RESSTA_ICE_SRST_DET 0x10 /* AMDebug(tm) soft reset detect */
-#define RESSTA_ICE_HRST_DET 0x20 /* AMDebug(tm) soft reset detect */
-#define RESSTA_SCP_RST 0x40 /* SCP reset detect */
-
-/*
- * General-Purpose Timers
- */
-#define SWTMRCFG 0xc64 /* Software Timer Configuration */
-#define GPTMR0CTL 0xc72 /* GP Timer 0 mode/control */
-#define GPTMR0CNT 0xc74 /* GP Timer 0 current count value */
-#define GPTMR0MAXCMPA 0xc76 /* GP Timer 0 maxcount value A */
-#define GPTMR0MAXCMPB 0xc78 /* GP Timer 0 maxcount value B */
-#define GPTMR1CTL 0xc7a /* GP Timer 1 mode/control */
-#define GPTMR1CNT 0xc7c /* GP Timer 1 current count value */
-#define GPTMR1MAXCMPA 0xc7e /* GP Timer 1 maxcount value A */
-#define GPTMR1MAXCMPB 0xc80 /* GP Timer 1 maxcount value B */
-#define GPTMR2CTL 0xc82 /* GP Timer 2 mode/control */
-#define GPTMR2CNT 0xc84 /* GP Timer 2 current count value */
-#define GPTMR2MAXCMPA 0xc8e /* GP Timer 2 maxcount value A */
-#define GPTMRCTL_CONT_CMP 0x0001 /* GP Timer continuous mode */
-#define GPTMRCTL_RTG 0x0010 /* GP Timer retrigger */
-#define GPTMRCTL_PSC_SEL 0x0008 /* GP Timer prescaler */
-#define GPTMRCTL_ENB 0x8000 /* GP Timer enable */
-#define GPTMRCTL_ENB_WR 0x4000 /* GP Timer enable bit write */
-
-#endif /* _I386_PCI_ELAN520REG_H_ */
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