Make sure that all CPUs end up with the same bits set in SCTLR_EL1.

Do this by clearing all the bits marked RES0 and set all the bits
marked RES1 for the ARMv8.0.

Any optional features introduced in later revisions of the architecture
(such as PAN) will be enabled after SCTLR_EL1 is initialized.

ok patrick@

diff --git a/sys/arch/arm64/arm64/locore.S b/sys/arch/arm64/arm64/locore.S
index 4a37fdc..1c61bbf 100644 (file)
--- a/sys/arch/arm64/arm64/locore.S
+++ b/sys/arch/arm64/arm64/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.36 2021/03/16 10:57:47 kettenis Exp $ */
+/* $OpenBSD: locore.S,v 1.37 2021/03/27 20:03:15 kettenis Exp $ */
 /*-
  * Copyright (c) 2012-2014 Andrew Turner
  * All rights reserved.
@@ -260,11 +260,12 @@ tcr:
 sctlr_set:
        /* Bits to set */
        .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
-           SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M)
+           SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M | \
+           SCTLR_RES1)
 sctlr_clear:
        /* Bits to clear */
        .quad (SCTLR_EE | SCTLR_EOE | SCTLR_WXN | SCTLR_UMA | SCTLR_ITD | \
-           SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A)
+           SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A | SCTLR_RES0)
 
        .align 3
        .globl abort

diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index 7b011e6..fba285f 100644 (file)
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.15 2021/03/27 19:57:19 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.16 2021/03/27 20:03:15 kettenis Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -552,29 +552,29 @@
 #define        PAR_S_MASK              (0x1 << PAR_S_SHIFT)
 
 /* SCTLR_EL1 - System Control Register */
-#define        SCTLR_RES0      0xc8222400      /* Reserved, write 0 */
-#define        SCTLR_RES1      0x30d00800      /* Reserved, write 1 */
-
-#define        SCTLR_M         0x00000001
-#define        SCTLR_A         0x00000002
-#define        SCTLR_C         0x00000004
-#define        SCTLR_SA        0x00000008
-#define        SCTLR_SA0       0x00000010
-#define        SCTLR_CP15BEN   0x00000020
-#define        SCTLR_THEE      0x00000040
-#define        SCTLR_ITD       0x00000080
-#define        SCTLR_SED       0x00000100
-#define        SCTLR_UMA       0x00000200
-#define        SCTLR_I         0x00001000
-#define        SCTLR_DZE       0x00004000
-#define        SCTLR_UCT       0x00008000
-#define        SCTLR_nTWI      0x00010000
-#define        SCTLR_nTWE      0x00040000
-#define        SCTLR_WXN       0x00080000
-#define        SCTLR_SPAN      0x00800000
-#define        SCTLR_EOE       0x01000000
-#define        SCTLR_EE        0x02000000
-#define        SCTLR_UCI       0x04000000
+#define        SCTLR_RES0      0xffffffffc8222400      /* Reserved, write 0 */
+#define        SCTLR_RES1      0x0000000030d00800      /* Reserved, write 1 */
+
+#define        SCTLR_M         0x0000000000000001
+#define        SCTLR_A         0x0000000000000002
+#define        SCTLR_C         0x0000000000000004
+#define        SCTLR_SA        0x0000000000000008
+#define        SCTLR_SA0       0x0000000000000010
+#define        SCTLR_CP15BEN   0x0000000000000020
+#define        SCTLR_THEE      0x0000000000000040
+#define        SCTLR_ITD       0x0000000000000080
+#define        SCTLR_SED       0x0000000000000100
+#define        SCTLR_UMA       0x0000000000000200
+#define        SCTLR_I         0x0000000000001000
+#define        SCTLR_DZE       0x0000000000004000
+#define        SCTLR_UCT       0x0000000000008000
+#define        SCTLR_nTWI      0x0000000000010000
+#define        SCTLR_nTWE      0x0000000000040000
+#define        SCTLR_WXN       0x0000000000080000
+#define        SCTLR_SPAN      0x0000000000800000
+#define        SCTLR_EOE       0x0000000001000000
+#define        SCTLR_EE        0x0000000002000000
+#define        SCTLR_UCI       0x0000000004000000
 
 /* SPSR_EL1 */
 /*