Identify UMIP feature, if available.

ok millert, kettenis, deraadt

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index 777d645..839c4d0 100644 (file)
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: identcpu.c,v 1.72 2016/02/03 03:25:08 guenther Exp $  */
+/*     $OpenBSD: identcpu.c,v 1.73 2016/06/22 07:22:00 mlarkin Exp $   */
 /*     $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $        */
 
 /*
@@ -193,6 +193,7 @@ const struct {
 }, cpu_seff0_ecxfeatures[] = {
        { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" },
        { SEFF0ECX_AVX512VBMI,  "AVX512VBMI" },
+       { SEFF0ECX_UMIP,        "UMIP" },
        { SEFF0ECX_PKU,         "PKU" },
 }, cpu_tpm_eaxfeatures[] = {
        { TPM_SENSOR,           "SENSOR" },

diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index 4316933..c9a6e06 100644 (file)
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: specialreg.h,v 1.43 2016/04/26 15:57:09 mlarkin Exp $ */
+/*     $OpenBSD: specialreg.h,v 1.44 2016/06/22 07:22:00 mlarkin Exp $ */
 /*     $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $      */
 /*     $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $  */
 
@@ -90,6 +90,7 @@
 #define        CR4_PCE 0x00000100      /* enable RDPMC instruction for all cpls */
 #define        CR4_OSFXSR      0x00000200      /* enable fxsave/fxrestor and SSE */
 #define        CR4_OSXMMEXCPT  0x00000400      /* enable unmasked SSE exceptions */
+#define        CR4_UMIP        0x00000800      /* user mode instruction prevention */
 #define        CR4_VMXE        0x00002000      /* enable virtual machine operation */
 #define        CR4_SMXE        0x00004000      /* enable safe mode operation */
 #define        CR4_FSGSBASE    0x00010000      /* enable {RD,WR}{FS,GS}BASE ops */
@@ -210,6 +211,7 @@
 /* SEFF ECX bits */
 #define SEFF0ECX_PREFETCHWT1   0x00000001 /* PREFETCHWT1 instruction */
 #define SEFF0ECX_AVX512VBMI    0x00000002 /* AVX-512 vector bit inst */
+#define SEFF0ECX_UMIP          0x00000004 /* UMIP support */
 #define SEFF0ECX_PKU           0x00000008 /* Page prot keys for user mode */
 
 /*

diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 673d17e..469bc68 100644 (file)
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: machdep.c,v 1.587 2016/05/21 01:06:53 deraadt Exp $   */
+/*     $OpenBSD: machdep.c,v 1.588 2016/06/22 07:22:00 mlarkin Exp $   */
 /*     $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $    */
 
 /*-
@@ -1080,6 +1080,7 @@ const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = {
 
 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = {
        { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" },
+       { SEFF0ECX_UMIP,        "UMIP" },
        { SEFF0ECX_AVX512VBMI,  "AVX512VBMI" },
        { SEFF0ECX_PKU,         "PKU" },
 };

diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 11d2ba3..51f6e9e 100644 (file)
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: specialreg.h,v 1.54 2016/04/26 15:27:32 mlarkin Exp $ */
+/*     $OpenBSD: specialreg.h,v 1.55 2016/06/22 07:22:00 mlarkin Exp $ */
 /*     $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $       */
 
 /*-
@@ -83,6 +83,7 @@
 #define        CR4_PCE 0x00000100      /* enable RDPMC instruction for all cpls */
 #define        CR4_OSFXSR      0x00000200      /* enable fxsave/fxrestor and SSE */
 #define        CR4_OSXMMEXCPT  0x00000400      /* enable unmasked SSE exceptions */
+#define        CR4_UMIP        0x00000800      /* user mode instruction prevention */
 #define        CR4_VMXE        0x00002000      /* enable virtual machine operation */
 #define        CR4_SMXE        0x00004000      /* enable safe mode operation */
 #define        CR4_FSGSBASE    0x00010000      /* enable {RD,WR}{FS,GS}BASE ops */
@@ -195,6 +196,7 @@
 /* SEFF ECX bits */
 #define SEFF0ECX_PREFETCHWT1   0x00000001 /* PREFETCHWT1 instruction */
 #define SEFF0ECX_AVX512VBMI    0x00000002 /* AVX-512 vector bit inst */
+#define SEFF0ECX_UMIP          0x00000004 /* UMIP support */
 #define SEFF0ECX_PKU           0x00000008 /* Page prot keys for user mode */
 
 /*