-/* $OpenBSD: audio.c,v 1.5 1996/03/02 00:29:19 niklas Exp $ */
-/* $NetBSD: audio.c,v 1.20 1996/02/20 11:47:22 mycroft Exp $ */
+/* $OpenBSD: audio.c,v 1.6 1996/04/18 23:46:55 niklas Exp $ */
+/* $NetBSD: audio.c,v 1.22 1996/03/14 19:08:32 christos Exp $ */
/*
* Copyright (c) 1991-1993 Regents of the University of California.
#include <sys/systm.h>
#include <sys/syslog.h>
#include <sys/kernel.h>
+#include <sys/signalvar.h>
#include <sys/audioio.h>
#include <dev/audiovar.h>
void audio_init_play __P((struct audio_softc *));
void audiostartr __P((struct audio_softc *));
void audiostartp __P((struct audio_softc *));
-void audio_rint __P((struct audio_softc *));
-void audio_pint __P((struct audio_softc *));
-void audio_rpint __P((struct audio_softc *));
+void audio_rint __P((void *));
+void audio_pint __P((void *));
+void audio_rpint __P((void *));
int audio_calc_blksize __P((struct audio_softc *));
void audio_silence_fill __P((struct audio_softc *, u_char *, int));
int audio_silence_copyout __P((struct audio_softc *, int, struct uio *));
void audio_alloc_auzero __P((struct audio_softc *, int));
+void audio_printsc __P((struct audio_softc *));
+void audioattach __P((int));
+int audio_hardware_attach __P((struct audio_hw_if *, void *));
+int audioopen __P((dev_t, int, int, struct proc *));
+int audioclose __P((dev_t, int, int, struct proc *));
+int audioread __P((dev_t, struct uio *, int));
+int audiowrite __P((dev_t, struct uio *, int));
+int audioioctl __P((dev_t, int, caddr_t, int, struct proc *));
+int audioselect __P((dev_t, int, struct proc *));
+void audio_init_ring __P((struct audio_buffer *, int));
+void audio_initbufs __P((struct audio_softc *));
+static __inline int audio_sleep_timo __P((int *, char *, int));
+static __inline int audio_sleep __P((int *, char *));
+static __inline void audio_wakeup __P((int *));
+int audio_drain __P((struct audio_softc *));
+void audio_clear __P((struct audio_softc *));
+
#ifdef AUDIO_DEBUG
void
-audio_printsc(struct audio_softc *sc)
+audio_printsc(sc)
+ struct audio_softc *sc;
{
printf("hwhandle %x hw_if %x ", sc->hw_hdl, sc->hw_if);
printf("open %x mode %x\n", sc->sc_open, sc->sc_mode);
struct audio_hw_if *hwp;
void *hdlp;
{
- int *zp, i;
struct audio_softc *sc;
if (naudio >= NAUDIO) {
sc->sc_hiwat = nblk;
}
-static inline int
+static __inline int
audio_sleep_timo(chan, label, timo)
int *chan;
char *label;
return (st);
}
-static inline int
+static __inline int
audio_sleep(chan, label)
int *chan;
char *label;
return audio_sleep_timo(chan, label, 0);
}
-static inline void
+static __inline void
audio_wakeup(chan)
int *chan;
{
int n;
{
struct audio_hw_if *hw = sc->hw_if;
- int i;
u_int auzero;
auzero = hw->get_silence(sc->sc_pencoding);
*p++ = auzero;
}
+int
audio_silence_copyout(sc, n, uio)
struct audio_softc *sc;
int n;
if ((tp + towrite) > cb->ep) {
DPRINTF(("audio_write: overwrite tp=0x%x towrite=%d ep=0x%x bs=%d\n",
tp, towrite, cb->ep, blocksize));
- printf("audio_write: overwrite tp=0x%x towrite=%d ep=0x%x\n",
+ printf("audio_write: overwrite tp=%p towrite=%d ep=%p\n",
tp, towrite, cb->ep);
tp = cb->bp;
}
audiostartr(sc)
struct audio_softc *sc;
{
- int err;
+ int error;
DPRINTF(("audiostartr: tp=0x%x\n", sc->rr.tp));
- if (err = sc->hw_if->start_input(sc->hw_hdl, sc->rr.tp, sc->sc_blksize,
- audio_rint, (void *)sc)) {
- DPRINTF(("audiostartr failed: %d\n", err));
+ error = sc->hw_if->start_input(sc->hw_hdl, sc->rr.tp, sc->sc_blksize,
+ audio_rint, (void *)sc);
+ if (error) {
+ DPRINTF(("audiostartr failed: %d\n", error));
audio_clear(sc);
}
else
audiostartp(sc)
struct audio_softc *sc;
{
- int rval;
+ int error;
DPRINTF(("audiostartp: hp=0x%x nblk=%d\n", sc->pr.hp, sc->pr.nblk));
if (sc->pr.nblk > 0) {
u_char *hp = sc->pr.hp;
- if (rval = sc->hw_if->start_output(sc->hw_hdl, hp, sc->sc_blksize,
- audio_rpint, (void *)sc)) {
- DPRINTF(("audiostartp: failed: %d\n", rval));
+ error = sc->hw_if->start_output(sc->hw_hdl, hp, sc->sc_blksize,
+ audio_rpint, (void *)sc);
+ if (error) {
+ DPRINTF(("audiostartp: failed: %d\n", error));
}
else {
sc->sc_pbus = 1;
* account for user data and silence separately.
*/
void
-audio_rpint(sc)
- struct audio_softc *sc;
+audio_rpint(v)
+ void *v;
{
-
+ struct audio_softc *sc = v;
sc->pr.nblk--;
- audio_pint(sc); /* 'twas a real audio block */
+ audio_pint(v); /* 'twas a real audio block */
}
/*
* Do a wakeup if necessary.
*/
void
-audio_pint(sc)
- struct audio_softc *sc;
+audio_pint(v)
+ void *v;
{
+ struct audio_softc *sc = v;
u_char *hp;
int cc = sc->sc_blksize;
struct audio_hw_if *hw = sc->hw_if;
struct audio_buffer *cb = &sc->pr;
- int err;
+ int error;
/*
* XXX
if (audiodebug > 1)
Dprintf("audio_pint: hp=0x%x cc=%d\n", hp, cc);
#endif
- if (err = hw->start_output(sc->hw_hdl, hp, cc,
- audio_rpint, (void *)sc)) {
- DPRINTF(("audio_pint restart failed: %d\n", err));
+ error = hw->start_output(sc->hw_hdl, hp, cc,
+ audio_rpint, (void *)sc);
+ if (error) {
+ DPRINTF(("audio_pint restart failed: %d\n", error));
audio_clear(sc);
}
else {
Dprintf("audio_pint: drops=%d auzero %d 0x%x\n", cb->cb_drops, cc, *(int *)auzero_block);
#endif
psilence:
- if (err = hw->start_output(sc->hw_hdl,
- auzero_block, cc,
- audio_pint, (void *)sc)) {
- DPRINTF(("audio_pint zero failed: %d\n", err));
+ error = hw->start_output(sc->hw_hdl,
+ auzero_block, cc,
+ audio_pint, (void *)sc);
+ if (error) {
+ DPRINTF(("audio_pint zero failed: %d\n", error));
audio_clear(sc);
} else
++sc->sc_wblks;
* Do a wakeup if necessary.
*/
void
-audio_rint(sc)
- struct audio_softc *sc;
+audio_rint(v)
+ void *v;
{
+ struct audio_softc *sc = v;
u_char *tp;
int cc = sc->sc_blksize;
struct audio_hw_if *hw = sc->hw_if;
struct audio_buffer *cb = &sc->rr;
- int err;
+ int error;
tp = cb->tp;
if (cb->cb_pause) {
if (audiodebug > 1)
Dprintf("audio_rint: tp=0x%x cc=%d\n", tp, cc);
#endif
- if (err = hw->start_input(sc->hw_hdl, tp, cc,
- audio_rint, (void *)sc)) {
- DPRINTF(("audio_rint: start failed: %d\n", err));
+ error = hw->start_input(sc->hw_hdl, tp, cc,
+ audio_rint, (void *)sc);
+ if (error) {
+ DPRINTF(("audio_rint: start failed: %d\n",
+ error));
audio_clear(sc);
}
cb->au_stamp += sc->sc_smpl_in_blk;
-/* $OpenBSD: audio_if.h,v 1.3 1996/03/02 00:29:20 niklas Exp $ */
-/* $NetBSD: audio_if.h,v 1.6 1995/12/24 02:30:58 mycroft Exp $ */
+/* $OpenBSD: audio_if.h,v 1.4 1996/04/18 23:46:58 niklas Exp $ */
+/* $NetBSD: audio_if.h,v 1.7 1996/03/07 15:00:10 christos Exp $ */
/*
* Copyright (c) 1994 Havard Eidnes.
* Generic interface to hardware driver.
*/
+struct audio_softc;
+
struct audio_hw_if {
int (*open)__P((dev_t, int)); /* open hardware */
void (*close)__P((void *)); /* close hardware */
void (*sw_decode)__P((void *, int, u_char *, int));
/* Start input/output routines. These usually control DMA. */
- int (*start_output)__P((void *, void *, int, void (*)(), void *));
- int (*start_input)__P((void *, void *, int, void (*)(), void *));
+ int (*start_output)__P((void *, void *, int,
+ void (*)(void *), void *));
+ int (*start_input)__P((void *, void *, int,
+ void (*)(void *), void *));
int (*halt_output)__P((void *));
int (*halt_input)__P((void *));
int (*cont_output)__P((void *));
-/* $OpenBSD: ccd.c,v 1.7 1996/03/02 00:29:21 niklas Exp $ */
-/* $NetBSD: ccd.c,v 1.28 1996/02/28 01:08:28 thorpej Exp $ */
+/* $OpenBSD: ccd.c,v 1.8 1996/04/18 23:47:00 niklas Exp $ */
+/* $NetBSD: ccd.c,v 1.29 1996/03/07 15:00:11 christos Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
#include <sys/buf.h>
#include <sys/malloc.h>
#include <sys/namei.h>
-#include <sys/conf.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/disklabel.h>
#include <sys/syslog.h>
#include <sys/fcntl.h>
#include <sys/vnode.h>
+#include <sys/cpu.h>
+#include <dev/dev_conf.h>
#include <dev/ccdvar.h>
#if defined(CCDDEBUG) && !defined(DEBUG)
#define CCDLABELDEV(dev) \
(MAKEDISKDEV(major((dev)), ccdunit((dev)), RAW_PART))
-/* {b,c}devsw[] function prototypes */
-dev_type_open(ccdopen);
-dev_type_close(ccdclose);
-dev_type_strategy(ccdstrategy);
-dev_type_ioctl(ccdioctl);
-dev_type_read(ccdread);
-dev_type_write(ccdwrite);
-
/* called by main() at boot time */
void ccdattach __P((int));
/* called by biodone() at interrupt time */
-void ccdiodone __P((struct ccdbuf *cbp));
+void ccdiodone __P((struct buf *));
+int ccdsize __P((dev_t));
static void ccdstart __P((struct ccd_softc *, struct buf *));
static void ccdinterleave __P((struct ccd_softc *, int));
ccdattach(num)
int num;
{
- int i;
-
if (num <= 0) {
#ifdef DIAGNOSTIC
panic("ccdattach: count <= 0");
struct proc *p;
{
register struct ccd_softc *cs = &ccd_softc[ccd->ccd_unit];
- register struct ccdcinfo *ci;
+ register struct ccdcinfo *ci = NULL;
register size_t size;
register int ix;
struct vnode *vp;
* Copy in the pathname of the component.
*/
bzero(tmppath, sizeof(tmppath)); /* sanity */
- if (error = copyinstr(cpaths[ix], tmppath,
- MAXPATHLEN, &ci->ci_pathlen)) {
+ error = copyinstr(cpaths[ix], tmppath,
+ MAXPATHLEN, &ci->ci_pathlen);
+ if (error) {
#ifdef DEBUG
if (ccddebug & (CCDB_FOLLOW|CCDB_INIT))
printf("%s: can't copy path, error = %d\n",
/*
* XXX: Cache the component's dev_t.
*/
- if (error = VOP_GETATTR(vp, &va, p->p_ucred, p)) {
+ if ((error = VOP_GETATTR(vp, &va, p->p_ucred, p)) != 0) {
#ifdef DEBUG
if (ccddebug & (CCDB_FOLLOW|CCDB_INIT))
printf("%s: %s: getattr failed %s = %d\n",
/*
* Get partition information for the component.
*/
- if (error = VOP_IOCTL(vp, DIOCGPART, (caddr_t)&dpart,
- FREAD, p->p_ucred, p)) {
+ error = VOP_IOCTL(vp, DIOCGPART, (caddr_t)&dpart,
+ FREAD, p->p_ucred, p);
+ if (error) {
#ifdef DEBUG
if (ccddebug & (CCDB_FOLLOW|CCDB_INIT))
printf("%s: %s: ioctl failed, error = %d\n",
* Calculate the size, truncating to an interleave
* boundary if necessary.
*/
- if (size < 0)
- size = 0;
-
if (cs->sc_ileave > 1)
size -= size % cs->sc_ileave;
#ifdef DEBUG
if (ccddebug & CCDB_INIT)
- printf("ccdinterleave(%x): ileave %d\n", cs, cs->sc_ileave);
+ printf("ccdinterleave(%p): ileave %d\n", cs, cs->sc_ileave);
#endif
/*
* Allocate an interleave table.
return (ENXIO);
cs = &ccd_softc[unit];
- if (error = ccdlock(cs))
+ if ((error = ccdlock(cs)) != 0)
return (error);
lp = cs->sc_dkdev.dk_label;
return (ENXIO);
cs = &ccd_softc[unit];
- if (error = ccdlock(cs))
+ if ((error = ccdlock(cs)) != 0)
return (error);
part = DISKPART(dev);
{
register int unit = ccdunit(bp->b_dev);
register struct ccd_softc *cs = &ccd_softc[unit];
- register daddr_t bn;
- register int sz, s;
+ register int s;
int wlabel;
struct disklabel *lp;
#ifdef DEBUG
if (ccddebug & CCDB_FOLLOW)
- printf("ccdstrategy(%x): unit %d\n", bp, unit);
+ printf("ccdstrategy(%p): unit %d\n", bp, unit);
#endif
if ((cs->sc_flags & CCDF_INITED) == 0) {
bp->b_error = ENXIO;
#ifdef DEBUG
if (ccddebug & CCDB_FOLLOW)
- printf("ccdstart(%x, %x)\n", cs, bp);
+ printf("ccdstart(%p, %p)\n", cs, bp);
#endif
/* Instrumentation. */
long bcount;
struct ccdbuf **cbpp;
{
- register struct ccdcinfo *ci, *ci2;
+ register struct ccdcinfo *ci, *ci2 = NULL;
register struct ccdbuf *cbp;
register daddr_t cbn, cboff;
#ifdef DEBUG
if (ccddebug & CCDB_IO)
- printf("ccdbuffer(%x, %x, %d, %x, %d)\n",
+ printf("ccdbuffer(%p, %p, %d, %p, %d)\n",
cs, bp, bn, addr, bcount);
#endif
/*
cbp = getccdbuf();
cbp->cb_flags = 0;
cbp->cb_buf.b_flags = bp->b_flags | B_CALL;
- cbp->cb_buf.b_iodone = (void (*)())ccdiodone;
+ cbp->cb_buf.b_iodone = ccdiodone;
cbp->cb_buf.b_proc = bp->b_proc;
cbp->cb_buf.b_dev = ci->ci_dev; /* XXX */
cbp->cb_buf.b_blkno = cbn + cboff;
#ifdef DEBUG
if (ccddebug & CCDB_IO)
- printf(" dev %x(u%d): cbp %x bn %d addr %x bcnt %d\n",
+ printf(" dev %x(u%d): cbp %p bn %d addr %p bcnt %d\n",
ci->ci_dev, ci-cs->sc_cinfo, cbp, cbp->cb_buf.b_blkno,
cbp->cb_buf.b_data, cbp->cb_buf.b_bcount);
#endif
#ifdef DEBUG
if (ccddebug & CCDB_FOLLOW)
- printf("ccdintr(%x, %x)\n", cs, bp);
+ printf("ccdintr(%p, %p)\n", cs, bp);
#endif
/*
* Request is done for better or worse, wakeup the top half.
* take a ccd interrupt.
*/
void
-ccdiodone(cbp)
- struct ccdbuf *cbp;
+ccdiodone(vbp)
+ struct buf *vbp;
{
+ struct ccdbuf *cbp = (struct ccdbuf *) vbp;
register struct buf *bp = cbp->cb_obp;
register int unit = cbp->cb_unit;
struct ccd_softc *cs = &ccd_softc[unit];
s = splbio();
#ifdef DEBUG
if (ccddebug & CCDB_FOLLOW)
- printf("ccdiodone(%x)\n", cbp);
+ printf("ccdiodone(%p)\n", cbp);
if (ccddebug & CCDB_IO) {
if (cbp->cb_flags & CBF_MIRROR)
printf("ccdiodone: mirror component\n");
else
- printf("ccdiodone: bp %x bcount %d resid %d\n",
+ printf("ccdiodone: bp %p bcount %d resid %d\n",
bp, bp->b_bcount, bp->b_resid);
- printf(" dev %x(u%d), cbp %x bn %d addr %x bcnt %d\n",
+ printf(" dev %x(u%d), cbp %p bn %d addr %p bcnt %d\n",
cbp->cb_buf.b_dev, cbp->cb_comp, cbp,
cbp->cb_buf.b_blkno, cbp->cb_buf.b_data,
cbp->cb_buf.b_bcount);
#ifdef DEBUG
if (ccddebug & CCDB_FOLLOW)
- printf("ccdread(%x, %x)\n", dev, uio);
+ printf("ccdread(%x, %p)\n", dev, uio);
#endif
if (unit >= numccd)
return (ENXIO);
#ifdef DEBUG
if (ccddebug & CCDB_FOLLOW)
- printf("ccdwrite(%x, %x)\n", dev, uio);
+ printf("ccdwrite(%x, %p)\n", dev, uio);
#endif
if (unit >= numccd)
return (ENXIO);
if ((flag & FWRITE) == 0)
return (EBADF);
- if (error = ccdlock(cs))
+ if ((error = ccdlock(cs)) != 0)
return (error);
/* Fill in some important bits. */
#ifdef DEBUG
if (ccddebug & CCDB_INIT)
for (i = 0; i < ccio->ccio_ndisks; ++i)
- printf("ccdioctl: component %d: 0x%x\n",
+ printf("ccdioctl: component %d: 0x%p\n",
i, cpp[i]);
#endif
if (ccddebug & CCDB_INIT)
printf("ccdioctl: lookedup = %d\n", lookedup);
#endif
- if (error = ccdlookup(cpp[i], p, &vpp[i])) {
+ if ((error = ccdlookup(cpp[i], p, &vpp[i])) != 0) {
for (j = 0; j < lookedup; ++j)
(void)vn_close(vpp[j], FREAD|FWRITE,
p->p_ucred, p);
/*
* Initialize the ccd. Fills in the softc for us.
*/
- if (error = ccdinit(&ccd, cpp, p)) {
+ if ((error = ccdinit(&ccd, cpp, p)) != 0) {
for (j = 0; j < lookedup; ++j)
(void)vn_close(vpp[j], FREAD|FWRITE,
p->p_ucred, p);
if ((flag & FWRITE) == 0)
return (EBADF);
- if (error = ccdlock(cs))
+ if ((error = ccdlock(cs)) != 0)
return (error);
/*
if ((flag & FWRITE) == 0)
return (EBADF);
- if (error = ccdlock(cs))
+ if ((error = ccdlock(cs)) != 0)
return (error);
cs->sc_flags |= CCDF_LABELLING;
int error;
NDINIT(&nd, LOOKUP, FOLLOW, UIO_USERSPACE, path, p);
- if (error = vn_open(&nd, FREAD|FWRITE, 0)) {
+ if ((error = vn_open(&nd, FREAD|FWRITE, 0)) != 0) {
#ifdef DEBUG
- if (ccddebug & CCDB_FOLLOW|CCDB_INIT)
+ if (ccddebug & (CCDB_FOLLOW|CCDB_INIT))
printf("ccdlookup: vn_open error = %d\n", error);
#endif
return (error);
return (EBUSY);
}
- if (error = VOP_GETATTR(vp, &va, p->p_ucred, p)) {
+ if ((error = VOP_GETATTR(vp, &va, p->p_ucred, p)) != 0) {
#ifdef DEBUG
- if (ccddebug & CCDB_FOLLOW|CCDB_INIT)
+ if (ccddebug & (CCDB_FOLLOW|CCDB_INIT))
printf("ccdlookup: getattr error = %d\n", error);
#endif
VOP_UNLOCK(vp);
/*
* Call the generic disklabel extraction routine.
*/
- if (errstring = readdisklabel(CCDLABELDEV(dev), ccdstrategy,
- cs->sc_dkdev.dk_label, cs->sc_dkdev.dk_cpulabel))
+ errstring = readdisklabel(CCDLABELDEV(dev), ccdstrategy,
+ cs->sc_dkdev.dk_label, cs->sc_dkdev.dk_cpulabel);
+ if (errstring)
ccdmakedisklabel(cs);
#ifdef DEBUG
-/* $OpenBSD: cons.h,v 1.4 1996/03/02 00:29:24 niklas Exp $ */
-/* $NetBSD: cons.h,v 1.13 1996/02/04 02:04:17 christos Exp $ */
+/* $OpenBSD: cons.h,v 1.5 1996/04/18 23:47:02 niklas Exp $ */
+/* $NetBSD: cons.h,v 1.14 1996/03/14 19:08:35 christos Exp $ */
/*
* Copyright (c) 1988 University of Utah.
int cnselect __P((dev_t, int, struct proc *));
int cngetc __P((void));
void cnputc __P((int));
+void cnpollc __P((int));
+void cnrint __P((void));
void nullcnpollc __P((dev_t, int));
/* console-specific types */
--- /dev/null
+/* $OpenBSD: dev_conf.h,v 1.1 1996/04/18 23:47:02 niklas Exp $ */
+/* $NetBSD: dev_conf.h,v 1.1 1996/03/07 15:00:13 christos Exp $ */
+
+/*
+ * Copyright (c) 1995 Christos Zoulas. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christos Zoulas.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/conf.h>
+
+#include "audio.h"
+cdev_decl(audio);
+
+cdev_decl(cn);
+
+#include "vnd.h"
+bdev_decl(vnd);
+cdev_decl(vnd);
+
+#include "ccd.h"
+bdev_decl(ccd);
+cdev_decl(ccd);
--- /dev/null
+# $OpenBSD: Makefile,v 1.1 1996/04/18 23:47:08 niklas Exp $
+# $NetBSD: Makefile,v 1.1 1996/02/26 23:46:17 cgd Exp $
+
+AWK= awk
+
+eisadevs.h eisadevs_data.h: eisadevs devlist2h.awk
+ /bin/rm -f eisadevs.h eisadevs_data.h
+ ${AWK} -f devlist2h.awk eisadevs
-/* $NetBSD: aha1742.c,v 1.52 1995/10/04 00:35:10 mycroft Exp $ */
+/* $OpenBSD: aha1742.c,v 1.4 1996/04/18 23:47:09 niklas Exp $ */
+/* $NetBSD: aha1742.c,v 1.57 1996/03/08 22:03:26 cgd Exp $ */
/*
* Copyright (c) 1994 Charles Hannum. All rights reserved.
#include <sys/proc.h>
#include <sys/user.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/eisa/eisareg.h>
#include <dev/eisa/eisavar.h>
+#include <dev/eisa/eisadevs.h>
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
struct device sc_dev;
struct isadev sc_id;
void *sc_ih;
+ bus_chipset_tag_t sc_bc;
+ bus_io_handle_t sc_ioh;
- int sc_iobase;
int sc_irq;
struct ahb_ecb *immed_ecb; /* an outstanding immediete command */
void ahb_free_ecb __P((struct ahb_softc *, struct ahb_ecb *, int));
struct ahb_ecb *ahb_get_ecb __P((struct ahb_softc *, int));
struct ahb_ecb *ahb_ecb_phys_kv __P((struct ahb_softc *, physaddr));
-int ahb_find __P((struct ahb_softc *));
+int ahb_find __P((bus_chipset_tag_t, bus_io_handle_t, struct ahb_softc *));
void ahb_init __P((struct ahb_softc *));
void ahbminphys __P((struct buf *));
int ahb_scsi_cmd __P((struct scsi_xfer *));
NULL, /* Use default 'done' routine */
};
-int ahbprobe();
-int ahbprobe1 __P((struct ahb_softc *, struct isa_attach_args *));
-void ahbattach();
+int ahbmatch __P((struct device *, void *, void *));
+void ahbattach __P((struct device *, struct device *, void *));
struct cfdriver ahbcd = {
- NULL, "ahb", ahbprobe, ahbattach, DV_DULL, sizeof(struct ahb_softc)
+ NULL, "ahb", ahbmatch, ahbattach, DV_DULL, sizeof(struct ahb_softc)
};
/*
int opcode;
struct ahb_ecb *ecb;
{
- int iobase = ahb->sc_iobase;
- int stport = iobase + G2STAT;
+ bus_chipset_tag_t bc = ahb->sc_bc;
+ bus_io_handle_t ioh = ahb->sc_ioh;
int wait = 300; /* 1ms should be enough */
while (--wait) {
- if ((inb(stport) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
+ if ((bus_io_read_1(bc, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
== (G2STAT_MBOX_EMPTY))
break;
delay(10);
Debugger();
}
- outl(iobase + MBOXOUT0, KVTOPHYS(ecb)); /* don't know this will work */
- outb(iobase + ATTN, opcode | ecb->xs->sc_link->target);
+ bus_io_write_4(bc, ioh, MBOXOUT0, KVTOPHYS(ecb)); /* don't know this will work */
+ bus_io_write_1(bc, ioh, ATTN, opcode | ecb->xs->sc_link->target);
}
/*
struct scsi_xfer *xs;
int count;
{ /* in msec */
- int iobase = ahb->sc_iobase;
- int stport = iobase + G2STAT;
+ bus_chipset_tag_t bc = ahb->sc_bc;
+ bus_io_handle_t ioh = ahb->sc_ioh;
while (count) {
/*
* If we had interrupts enabled, would we
* have got an interrupt?
*/
- if (inb(stport) & G2STAT_INT_PEND)
+ if (bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND)
ahbintr(ahb);
if (xs->flags & ITSDONE)
return 0;
int target;
u_long cmd;
{
- int iobase = ahb->sc_iobase;
- int stport = iobase + G2STAT;
+ bus_chipset_tag_t bc = ahb->sc_bc;
+ bus_io_handle_t ioh = ahb->sc_ioh;
int wait = 100; /* 1 ms enough? */
while (--wait) {
- if ((inb(stport) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
+ if ((bus_io_read_1(bc, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
== (G2STAT_MBOX_EMPTY))
break;
delay(10);
Debugger();
}
- outl(iobase + MBOXOUT0, cmd); /* don't know this will work */
- outb(iobase + G2CNTRL, G2CNTRL_SET_HOST_READY);
- outb(iobase + ATTN, OP_IMMED | target);
+ bus_io_write_4(bc, ioh, MBOXOUT0, cmd); /* don't know this will work */
+ bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_SET_HOST_READY);
+ bus_io_write_1(bc, ioh, ATTN, OP_IMMED | target);
}
/*
* the actual probe routine to check it out.
*/
int
-ahbprobe(parent, self, aux)
- struct device *parent, *self;
- void *aux;
+ahbmatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
{
- struct ahb_softc *ahb = (void *)self;
- struct isa_attach_args *ia = aux;
- int iobase;
- u_short vendor, model;
-
-#ifdef NEWCONFIG
- if (ia->ia_iobase != IOBASEUNK)
- return ahbprobe1(ahb, ia);
-#endif
+ struct eisa_attach_args *ea = aux;
+ bus_chipset_tag_t bc = ea->ea_bc;
+ bus_io_handle_t ioh;
+ int rv;
- while (ahb_slot < MAX_SLOTS) {
- ahb_slot++;
- iobase = 0x1000 * ahb_slot;
+ /* must match one of our known ID strings */
+ if (strcmp(ea->ea_idstring, "ADP0000") &&
+ strcmp(ea->ea_idstring, "ADP0001") &&
+ strcmp(ea->ea_idstring, "ADP0002") &&
+ strcmp(ea->ea_idstring, "ADP0400"))
+ return (0);
- vendor = htons(inw(iobase + EISA_VENDOR));
- if (vendor != 0x0490) /* `ADP' */
- continue;
-
- model = htons(inw(iobase + EISA_MODEL));
- if ((model & 0xfff0) != 0x0000 &&
- (model & 0xfff0) != 0x0100) {
-#ifndef trusted
- printf("ahbprobe: ignoring model %04x\n", model);
-#endif
- continue;
- }
+ if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
+ return (0);
#ifdef notyet
- outb(iobase + EISA_CONTROL, EISA_ENABLE | EISA_RESET);
- delay(10);
- outb(iobase + EISA_CONTROL, EISA_ENABLE);
- /* Wait for reset? */
- delay(1000);
+ /* This won't compile as-is, anyway. */
+ bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
+ delay(10);
+ bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE);
+ /* Wait for reset? */
+ delay(1000);
#endif
- ia->ia_iobase = iobase;
- if (ahbprobe1(ahb, ia))
- return 1;
- }
-
- return 0;
-}
-
-/*
- * Check if the device can be found at the port given
- * and if so, set it up ready for further work
- * as an argument, takes the isa_device structure from
- * autoconf.c.
- */
-int
-ahbprobe1(ahb, ia)
- struct ahb_softc *ahb;
- struct isa_attach_args *ia;
-{
-
- ahb->sc_iobase = ia->ia_iobase;
+ rv = !ahb_find(bc, ioh, NULL);
- /*
- * Try initialise a unit at this location
- * sets up dma and bus speed, loads ahb->sc_irq
- */
- if (ahb_find(ahb) != 0)
- return 0;
+ bus_io_unmap(ea->ea_bc, ioh, EISA_SLOT_SIZE);
- if (ia->ia_irq != IRQUNK) {
- if (ia->ia_irq != ahb->sc_irq) {
- printf("%s: irq mismatch; kernel configured %d != board configured %d\n",
- ahb->sc_dev.dv_xname, ia->ia_irq, ahb->sc_irq);
- return 0;
- }
- } else
- ia->ia_irq = ahb->sc_irq;
-
- ia->ia_drq = DRQUNK;
- ia->ia_msize = 0;
- ia->ia_iosize = 0x1000;
- return 1;
+ return (rv);
}
ahbprint()
struct device *parent, *self;
void *aux;
{
- struct isa_attach_args *ia = aux;
+ struct eisa_attach_args *ea = aux;
struct ahb_softc *ahb = (void *)self;
- u_short model;
+ bus_chipset_tag_t bc = ea->ea_bc;
+ bus_io_handle_t ioh;
+ char *model;
+
+ ahb->sc_bc = bc;
+ if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
+ panic("ahbattach: could not map I/O addresses");
+ ahb->sc_ioh = ioh;
+ if (ahb_find(bc, ioh, ahb))
+ panic("ahbattach: ahb_find failed!");
ahb_init(ahb);
TAILQ_INIT(&ahb->free_ecb);
ahb->sc_link.device = &ahb_dev;
ahb->sc_link.openings = 2;
- printf(": ");
- model = htons(inw(ahb->sc_iobase + EISA_MODEL));
- switch (model & 0xfff0) {
- case 0x0000:
- printf("model 1740 or 1742");
- break;
- case 0x0100:
- printf("model 1744");
- break;
- }
- printf(", revision %d\n", model & 0x000f);
+ if (!strcmp(ea->ea_idstring, "ADP0000"))
+ model = EISA_PRODUCT_ADP0000;
+ else if (!strcmp(ea->ea_idstring, "ADP0001"))
+ model = EISA_PRODUCT_ADP0001;
+ else if (!strcmp(ea->ea_idstring, "ADP0002"))
+ model = EISA_PRODUCT_ADP0002;
+ else if (!strcmp(ea->ea_idstring, "ADP0400"))
+ model = EISA_PRODUCT_ADP0400;
+ else
+ model = "unknown model!";
+ printf(" irq %d: %s\n", ahb->sc_irq, model);
#ifdef NEWCONFIG
isa_establish(&ahb->sc_id, &ahb->sc_dev);
#endif
- ahb->sc_ih = eisa_intr_establish(ia->ia_irq, IST_LEVEL, IPL_BIO,
+ ahb->sc_ih = eisa_intr_establish(ahb->sc_irq, IST_LEVEL, IPL_BIO,
ahbintr, ahb, ahb->sc_dev.dv_xname);
/*
void *arg;
{
struct ahb_softc *ahb = arg;
+ bus_chipset_tag_t bc = ahb->sc_bc;
+ bus_io_handle_t ioh = ahb->sc_ioh;
struct ahb_ecb *ecb;
u_char ahbstat;
u_long mboxval;
- int iobase = ahb->sc_iobase;
#ifdef AHBDEBUG
printf("%s: ahbintr ", ahb->sc_dev.dv_xname);
#endif /* AHBDEBUG */
- if ((inb(iobase + G2STAT) & G2STAT_INT_PEND) == 0)
+ if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
return 0;
for (;;) {
* First get all the information and then
* acknowlege the interrupt
*/
- ahbstat = inb(iobase + G2INTST);
- mboxval = inl(iobase + MBOXIN0);
- outb(iobase + G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
+ ahbstat = bus_io_read_1(bc, ioh, G2INTST);
+ mboxval = bus_io_read_4(bc, ioh, MBOXIN0);
+ bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
#ifdef AHBDEBUG
printf("status = 0x%x ", ahbstat);
ahb_done(ahb, ecb);
}
- if ((inb(iobase + G2STAT) & G2STAT_INT_PEND) == 0)
+ if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
return 1;
}
}
* Start the board, ready for normal operation
*/
int
-ahb_find(ahb)
+ahb_find(bc, ioh, ahb)
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
struct ahb_softc *ahb;
{
- int iobase = ahb->sc_iobase;
- int stport = iobase + G2STAT;
u_char intdef;
- int i;
+ int i, irq, busid;
int wait = 1000; /* 1 sec enough? */
- outb(iobase + PORTADDR, PORTADDR_ENHANCED);
+ bus_io_write_1(bc, ioh, PORTADDR, PORTADDR_ENHANCED);
#define NO_NO 1
#ifdef NO_NO
* reset board, If it doesn't respond, assume
* that it's not there.. good for the probe
*/
- outb(iobase + G2CNTRL, G2CNTRL_HARD_RESET);
+ bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_HARD_RESET);
delay(1000);
- outb(iobase + G2CNTRL, 0);
+ bus_io_write_1(bc, ioh, G2CNTRL, 0);
delay(10000);
while (--wait) {
- if ((inb(stport) & G2STAT_BUSY) == 0)
+ if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_BUSY) == 0)
break;
delay(1000);
}
if (!wait) {
-#ifdef AHBDEBUG
+#ifdef AHBDEBUG
if (ahb_debug & AHB_SHOWMISC)
printf("ahb_find: No answer from aha1742 board\n");
#endif /*AHBDEBUG */
return ENXIO;
}
- i = inb(iobase + MBOXIN0);
+ i = bus_io_read_1(bc, ioh, MBOXIN0);
if (i) {
printf("self test failed, val = 0x%x\n", i);
return EIO;
}
/* Set it again, just to be sure. */
- outb(iobase + PORTADDR, PORTADDR_ENHANCED);
+ bus_io_write_1(bc, ioh, PORTADDR, PORTADDR_ENHANCED);
#endif
- while (inb(stport) & G2STAT_INT_PEND) {
+ while (bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) {
printf(".");
- outb(iobase + G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
+ bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
delay(10000);
}
- intdef = inb(iobase + INTDEF);
+ intdef = bus_io_read_1(bc, ioh, INTDEF);
switch (intdef & 0x07) {
case INT9:
- ahb->sc_irq = 9;
+ irq = 9;
break;
case INT10:
- ahb->sc_irq = 10;
+ irq = 10;
break;
case INT11:
- ahb->sc_irq = 11;
+ irq = 11;
break;
case INT12:
- ahb->sc_irq = 12;
+ irq = 12;
break;
case INT14:
- ahb->sc_irq = 14;
+ irq = 14;
break;
case INT15:
- ahb->sc_irq = 15;
+ irq = 15;
break;
default:
printf("illegal int setting %x\n", intdef);
return EIO;
}
- outb(iobase + INTDEF, (intdef | INTEN)); /* make sure we can interrupt */
+ bus_io_write_1(bc, ioh, INTDEF, (intdef | INTEN)); /* make sure we can interrupt */
/* who are we on the scsi bus? */
- ahb->ahb_scsi_dev = (inb(iobase + SCSIDEF) & HSCSIID);
+ busid = (bus_io_read_1(bc, ioh, SCSIDEF) & HSCSIID);
+
+ /* if we want to fill in softc, do so now */
+ if (ahb != NULL) {
+ ahb->sc_irq = irq;
+ ahb->ahb_scsi_dev = busid;
+ }
/*
* Note that we are going and return (to probe)
--- /dev/null
+#! /usr/bin/awk -f
+# $OpenBSD: devlist2h.awk,v 1.1 1996/04/18 23:47:10 niklas Exp $
+# $NetBSD: devlist2h.awk,v 1.1 1996/02/26 23:46:20 cgd Exp $
+#
+# Copyright (c) 1995, 1996 Christopher G. Demetriou
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# 3. All advertising materials mentioning features or use of this software
+# must display the following acknowledgement:
+# This product includes software developed by Christopher G. Demetriou.
+# 4. The name of the author may not be used to endorse or promote products
+# derived from this software without specific prior written permission
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+BEGIN {
+ nproducts = nvendors = 0
+ dfile="eisadevs_data.h"
+ hfile="eisadevs.h"
+}
+NR == 1 {
+ VERSION = $0
+ gsub("\\$", "", VERSION)
+
+ printf("/*\n") > dfile
+ printf(" * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n") \
+ > dfile
+ printf(" *\n") > dfile
+ printf(" * generated from:\n") > dfile
+ printf(" *\t%s\n", VERSION) > dfile
+ printf(" */\n") > dfile
+
+ printf("/*\n") > hfile
+ printf(" * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n") \
+ > hfile
+ printf(" *\n") > hfile
+ printf(" * generated from:\n") > hfile
+ printf(" *\t%s\n", VERSION) > hfile
+ printf(" */\n") > hfile
+
+ next
+}
+$1 == "vendor" {
+ nvendors++
+
+ vendorindex[$2] = nvendors; # record index for this name, for later.
+ vendors[nvendors, 1] = $2; # name/ID
+ i = 2; f = 3;
+
+ # comments
+ ocomment = oparen = 0
+ if (f <= NF) {
+ ocomment = 1;
+ }
+ while (f <= NF) {
+ if ($f == "#") {
+ oparen = 1
+ f++
+ continue
+ }
+ if (oparen) {
+ f++
+ continue
+ }
+ vendors[nvendors, i] = $f
+ i++; f++;
+ }
+
+ next
+}
+$1 == "product" {
+ nproducts++
+
+ products[nproducts, 1] = $2; # vendor name
+ products[nproducts, 2] = $3; # product id
+ printf("#define\tEISA_PRODUCT_%s%s\t\"", products[nproducts, 1],
+ products[nproducts, 2]) > hfile
+
+ i = vendorindex[products[nproducts, 1]]; j = 2;
+ needspace = 0;
+ while (vendors[i, j] != "") {
+ if (needspace)
+ printf(" ") > hfile
+ printf("%s", vendors[i, j]) > hfile
+ needspace = 1
+ j++
+ }
+
+ if (needspace)
+ printf(" ") > hfile
+
+ i=3; f = 4;
+
+ # comments
+ ocomment = oparen = 0
+ if (f <= NF) {
+ ocomment = 1;
+ }
+ while (f <= NF) {
+ if ($f == "#") {
+ printf("(") > hfile
+ oparen = 1
+ f++
+ continue
+ }
+ if (oparen) {
+ printf("%s", $f) > hfile
+ if (f < NF)
+ printf(" ") > hfile
+ f++
+ continue
+ }
+ products[nproducts, i] = $f
+ printf("%s", products[nproducts, i]) > hfile
+ if (f < NF)
+ printf(" ") > hfile
+ i++; f++;
+ }
+ if (oparen)
+ printf(")") > hfile
+ if (ocomment)
+ printf("\"") > hfile
+ printf("\n") > hfile
+
+ next
+}
+{
+ if ($0 == "")
+ blanklines++
+ if (blanklines != 2 && blanklines != 3)
+ print $0 > hfile
+ if (blanklines < 2)
+ print $0 > dfile
+}
+END {
+ # print out the match tables
+
+ printf("\n") > dfile
+
+ printf("struct eisa_knowndev eisa_knowndevs[] = {\n") > dfile
+ for (i = 1; i <= nproducts; i++) {
+ printf("\t{\n") > dfile
+ printf("\t 0,\n") > dfile
+ printf("\t \"%s%s\",\n", products[i, 1], products[i, 2]) \
+ > dfile
+ printf("\t EISA_PRODUCT_%s%s,\n", \
+ products[i, 1], products[i, 2]) \
+ > dfile
+
+ printf("\t},\n") > dfile
+ }
+ for (i = 1; i <= nvendors; i++) {
+ printf("\t{\n") > dfile
+ printf("\t EISA_KNOWNDEV_NOPROD,\n") \
+ > dfile
+ printf("\t \"%s\",\n", vendors[i, 1]) \
+ > dfile
+ printf("\t \"") > dfile
+ j = 2;
+ needspace = 0;
+ while (vendors[i, j] != "") {
+ if (needspace)
+ printf(" ") > dfile
+ printf("%s", vendors[i, j]) > dfile
+ needspace = 1
+ j++
+ }
+ printf("\",\n") > dfile
+ printf("\t},\n") > dfile
+ }
+ printf("\t{ 0, NULL, NULL, }\n") > dfile
+ printf("};\n") > dfile
+}
--- /dev/null
+/* $OpenBSD: eisa.c,v 1.1 1996/04/18 23:47:10 niklas Exp $ */
+/* $NetBSD: eisa.c,v 1.7 1996/03/14 04:02:58 cgd Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * EISA Bus device
+ *
+ * Makes sure an EISA bus is present, and finds and attaches devices
+ * living on it.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+
+#include <dev/eisa/eisareg.h>
+#include <dev/eisa/eisavar.h>
+#include <dev/eisa/eisadevs.h>
+
+int eisamatch __P((struct device *, void *, void *));
+void eisaattach __P((struct device *, struct device *, void *));
+
+struct cfdriver eisacd = {
+ NULL, "eisa", eisamatch, eisaattach, DV_DULL, sizeof(struct device)
+};
+
+int eisasubmatch __P((struct device *, void *, void *));
+int eisaprint __P((void *, char *));
+void eisa_devinfo __P((const char *, char *));
+
+int
+eisamatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct eisabus_attach_args *eba = aux;
+
+ if (strcmp(eba->eba_busname, cf->cf_driver->cd_name))
+ return (0);
+
+ /* XXX check other indicators */
+
+ return (1);
+}
+
+int
+eisaprint(aux, pnp)
+ void *aux;
+ char *pnp;
+{
+ register struct eisa_attach_args *ea = aux;
+ char devinfo[256];
+
+ if (pnp) {
+ eisa_devinfo(ea->ea_idstring, devinfo);
+ printf("%s at %s", devinfo, pnp);
+ }
+ printf(" slot %d", ea->ea_slot);
+ return (UNCONF);
+}
+
+int
+eisasubmatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct eisa_attach_args *ea = aux;
+
+ if (cf->eisacf_slot != EISA_UNKNOWN_SLOT &&
+ cf->eisacf_slot != ea->ea_slot)
+ return 0;
+ return ((*cf->cf_driver->cd_match)(parent, match, aux));
+}
+
+void
+eisaattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct eisabus_attach_args *eba = aux;
+ bus_chipset_tag_t bc;
+ int slot;
+
+ printf("\n");
+
+ bc = eba->eba_bc;
+
+ /*
+ * Search for and attach subdevices.
+ *
+ * Slot 0 is the "motherboard" slot, and the code attaching
+ * the EISA bus should have already attached an ISA bus there.
+ */
+ for (slot = 1; slot < EISA_MAX_SLOT; slot++) {
+ struct eisa_attach_args ea;
+ struct cfdata *cf;
+ u_int slotaddr;
+ bus_io_handle_t slotioh;
+ int i;
+
+ ea.ea_bc = bc;
+ ea.ea_slot = slot;
+ slotaddr = EISA_SLOT_ADDR(slot);
+
+ /*
+ * Get a mapping for the whole slot-specific address
+ * space. If we can't, assume nothing's there but warn
+ * about it.
+ */
+ if (bus_io_map(bc, slotaddr, EISA_SLOT_SIZE, &slotioh)) {
+ printf("%s: can't map I/O space for slot %d\n", slot);
+ continue;
+ }
+
+ /* Get the vendor ID bytes */
+ for (i = 0; i < EISA_NVIDREGS; i++)
+ ea.ea_vid[i] = bus_io_read_1(bc, slotioh,
+ EISA_SLOTOFF_VID + i);
+
+ /* Check for device existence */
+ if (EISA_VENDID_NODEV(ea.ea_vid)) {
+#if 0
+ printf("no device at %s slot %d\n", self->dv_xname,
+ slot);
+ printf("\t(0x%x, 0x%x)\n", ea.ea_vid[0],
+ ea.ea_vid[1]);
+#endif
+ bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
+ continue;
+ }
+
+ /* And check that the firmware didn't biff something badly */
+ if (EISA_VENDID_IDDELAY(ea.ea_vid)) {
+ printf("%s slot %d not configured by BIOS?\n",
+ self->dv_xname, slot);
+ bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
+ continue;
+ }
+
+ /* Get the product ID bytes */
+ for (i = 0; i < EISA_NPIDREGS; i++)
+ ea.ea_pid[i] = bus_io_read_1(bc, slotioh,
+ EISA_SLOTOFF_PID + i);
+
+ /* Create the ID string from the vendor and product IDs */
+ ea.ea_idstring[0] = EISA_VENDID_0(ea.ea_vid);
+ ea.ea_idstring[1] = EISA_VENDID_1(ea.ea_vid);
+ ea.ea_idstring[2] = EISA_VENDID_2(ea.ea_vid);
+ ea.ea_idstring[3] = EISA_PRODID_0(ea.ea_pid);
+ ea.ea_idstring[4] = EISA_PRODID_1(ea.ea_pid);
+ ea.ea_idstring[5] = EISA_PRODID_2(ea.ea_pid);
+ ea.ea_idstring[6] = EISA_PRODID_3(ea.ea_pid);
+ ea.ea_idstring[7] = '\0'; /* sanity */
+
+ /* We no longer need the I/O handle; free it. */
+ bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
+
+ /* Attach matching device. */
+ config_found_sm(self, &ea, eisaprint, eisasubmatch);
+ }
+}
+
+#ifdef EISAVERBOSE
+/*
+ * Descriptions of of known vendors and devices ("products").
+ */
+struct eisa_knowndev {
+ int flags;
+ const char *id, *name;
+};
+#define EISA_KNOWNDEV_NOPROD 0x01 /* match on vendor only */
+
+#include <dev/eisa/eisadevs_data.h>
+#endif /* EISAVERBOSE */
+
+void
+eisa_devinfo(id, cp)
+ const char *id;
+ char *cp;
+{
+ const char *name;
+ int onlyvendor;
+#ifdef EISAVERBOSE
+ struct eisa_knowndev *edp;
+ int match;
+ const char *unmatched = "unknown ";
+#else
+ const char *unmatched = "";
+#endif
+
+ onlyvendor = 0;
+ name = NULL;
+
+#ifdef EISAVERBOSE
+ /* find the device in the table, if possible. */
+ edp = eisa_knowndevs;
+ while (edp->id != NULL) {
+ /* check this entry for a match */
+ if ((edp->flags & EISA_KNOWNDEV_NOPROD) != 0)
+ match = !strncmp(edp->id, id, 3);
+ else
+ match = !strcmp(edp->id, id);
+ if (match) {
+ name = edp->name;
+ onlyvendor = (edp->flags & EISA_KNOWNDEV_NOPROD) != 0;
+ break;
+ }
+ edp++;
+ }
+#endif
+
+ if (name == NULL)
+ cp += sprintf(cp, "%sdevice %s", unmatched, id);
+ else if (onlyvendor) /* never if not EISAVERBOSE */
+ cp += sprintf(cp, "unknown %s device %s", name, id);
+ else
+ cp += sprintf(cp, "%s", name);
+}
--- /dev/null
+$OpenBSD: eisadevs,v 1.1 1996/04/18 23:47:11 niklas Exp $
+/* $NetBSD: eisadevs,v 1.1 1996/02/26 23:46:22 cgd Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * List of known EISA vendors
+ */
+
+vendor ADP Adaptec
+vendor BUS BusLogic
+vendor DEC Digital Equipment
+vendor TCM 3Com
+
+/*
+ * List of known products, grouped by vendor.
+ */
+
+/* Adaptec products */
+product ADP 0000 AHA-1740
+product ADP 0001 AHA-1740A
+product ADP 0002 AHA-1742A
+product ADP 0400 AHA-1744
+product ADP 7770 AIC-7770 (on motherboard)
+product ADP 7771 AHA-274x
+product ADP 7756 AHA-284x (BIOS enabled)
+product ADP 7757 AHA-284x (BIOS disabled)
+
+/* BusLogic products */
+/* XXX */
+
+/* Digital Equipment products */
+product DEC 4250 DE425
+/* ??? DEC DEFEA */
+
+/* 3Com products */
+product TCM 5092 3C579-TP
+product TCM 5093 3C579
--- /dev/null
+/*
+ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * generated from:
+ * OpenBSD
+ */
+/* $NetBSD: eisadevs,v 1.1 1996/02/26 23:46:22 cgd Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * List of known products, grouped by vendor.
+ */
+
+/* Adaptec products */
+#define EISA_PRODUCT_ADP0000 "Adaptec AHA-1740"
+#define EISA_PRODUCT_ADP0001 "Adaptec AHA-1740A"
+#define EISA_PRODUCT_ADP0002 "Adaptec AHA-1742A"
+#define EISA_PRODUCT_ADP0400 "Adaptec AHA-1744"
+#define EISA_PRODUCT_ADP7770 "Adaptec AIC-7770 (on motherboard)"
+#define EISA_PRODUCT_ADP7771 "Adaptec AHA-274x"
+#define EISA_PRODUCT_ADP7756 "Adaptec AHA-284x (BIOS enabled)"
+#define EISA_PRODUCT_ADP7757 "Adaptec AHA-284x (BIOS disabled)"
+
+/* BusLogic products */
+/* XXX */
+
+/* Digital Equipment products */
+#define EISA_PRODUCT_DEC4250 "Digital Equipment DE425"
+/* ??? DEC DEFEA */
+
+/* 3Com products */
+#define EISA_PRODUCT_TCM5092 "3Com 3C579-TP"
+#define EISA_PRODUCT_TCM5093 "3Com 3C579"
--- /dev/null
+/*
+ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * generated from:
+ * OpenBSD
+ */
+/* $NetBSD: eisadevs,v 1.1 1996/02/26 23:46:22 cgd Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+struct eisa_knowndev eisa_knowndevs[] = {
+ {
+ 0,
+ "ADP0000",
+ EISA_PRODUCT_ADP0000,
+ },
+ {
+ 0,
+ "ADP0001",
+ EISA_PRODUCT_ADP0001,
+ },
+ {
+ 0,
+ "ADP0002",
+ EISA_PRODUCT_ADP0002,
+ },
+ {
+ 0,
+ "ADP0400",
+ EISA_PRODUCT_ADP0400,
+ },
+ {
+ 0,
+ "ADP7770",
+ EISA_PRODUCT_ADP7770,
+ },
+ {
+ 0,
+ "ADP7771",
+ EISA_PRODUCT_ADP7771,
+ },
+ {
+ 0,
+ "ADP7756",
+ EISA_PRODUCT_ADP7756,
+ },
+ {
+ 0,
+ "ADP7757",
+ EISA_PRODUCT_ADP7757,
+ },
+ {
+ 0,
+ "DEC4250",
+ EISA_PRODUCT_DEC4250,
+ },
+ {
+ 0,
+ "TCM5092",
+ EISA_PRODUCT_TCM5092,
+ },
+ {
+ 0,
+ "TCM5093",
+ EISA_PRODUCT_TCM5093,
+ },
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "ADP",
+ "Adaptec",
+ },
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "BUS",
+ "BusLogic",
+ },
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "DEC",
+ "Digital Equipment",
+ },
+ {
+ EISA_KNOWNDEV_NOPROD,
+ "TCM",
+ "3Com",
+ },
+ { 0, NULL, NULL, }
+};
-/* $NetBSD: eisareg.h,v 1.1 1995/04/17 12:08:21 cgd Exp $ */
+/* $OpenBSD: eisareg.h,v 1.2 1996/04/18 23:47:12 niklas Exp $ */
+/* $NetBSD: eisareg.h,v 1.2 1996/02/27 00:21:02 cgd Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __DEV_EISA_EISAREG_H__
+#define __DEV_EISA_EISAREG_H__
+
/*
- * XXX something should go here. nothing does, yet.
+ * Register (etc.) descriptions for the EISA bus.
+
+ * Mostly culled from EISA chipset descriptions in:
+ * Intel Peripheral Components Databook (1992)
*/
+
+/*
+ * Max number of EISA slots in a machine. 64K I/O space total.
+ */
+#define EISA_MAX_SLOT 16 /* number of slots. 0 -> 0xf */
+
+/*
+ * Slot I/O space size, and I/O address of a given slot.
+ */
+#define EISA_SLOT_SIZE 0x1000
+#define EISA_SLOT_ADDR(s) ((s) * EISA_SLOT_SIZE)
+
+/*
+ * Slot offsets for important/standard registers.
+ */
+#define EISA_SLOTOFF_VID 0xc80 /* offset of vendor id regs */
+#define EISA_NVIDREGS 2
+#define EISA_SLOTOFF_PID 0xc82 /* offset of product id regs */
+#define EISA_NPIDREGS 2
+
+
+/*
+ * EISA ID functions, used to manipulate and decode EISA ID registers.
+ * ``Somebody was let out without adult supervision.''
+ */
+
+#define EISA_IDSTRINGLEN 8 /* length of ID string, incl. NUL */
+
+/*
+ * Vendor ID: three characters, encoded in 16 bits.
+ *
+ * EISA_VENDID_NODEV returns true if there's no device in the slot.
+ * EISA_VENDID_IDDELAY returns true if there's a device in the slot,
+ * but that device hasn't been configured by system firmware.
+ * EISA_VENDID_n returns the "n"th character of the vendor ID.
+ */
+#define EISA_VENDID_NODEV(vid) \
+ (((vid)[0] & 0x80) != 0)
+#define EISA_VENDID_IDDELAY(vid) \
+ (((vid)[0] & 0xf0) == 0x70)
+#define EISA_VENDID_0(vid) \
+ ((((vid)[0] & 0x7c) >> 2) + '@')
+#define EISA_VENDID_1(vid) \
+ (((((vid)[0] & 0x03) << 3) | (((vid)[1] & 0xe0) >> 5)) + '@')
+#define EISA_VENDID_2(vid) \
+ (((vid)[1] & 0x1f) + '@')
+
+/*
+ * Product ID: four hex digits, encoded in 16 bits (normal, sort of).
+ *
+ * EISA_PRIDID_n returns the "n"th hex digit of the product ID.
+ */
+#define __EISA_HEX_MAP "0123456789ABCDEF"
+#define EISA_PRODID_0(pid) \
+ (__EISA_HEX_MAP[(((pid)[0] >> 4) & 0xf)])
+#define EISA_PRODID_1(pid) \
+ (__EISA_HEX_MAP[(((pid)[0] >> 0) & 0xf)])
+#define EISA_PRODID_2(pid) \
+ (__EISA_HEX_MAP[(((pid)[1] >> 4) & 0xf)])
+#define EISA_PRODID_3(pid) \
+ (__EISA_HEX_MAP[(((pid)[1] >> 0) & 0xf)])
+
+#endif /* !__DEV_EISA_EISAREG_H__ */
-/* $NetBSD: eisavar.h,v 1.1 1995/04/17 12:08:23 cgd Exp $ */
+/* $OpenBSD: eisavar.h,v 1.3 1996/04/18 23:47:13 niklas Exp $ */
+/* $NetBSD: eisavar.h,v 1.4 1996/03/08 20:25:22 cgd Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __DEV_EISA_EISAVAR_H__
+#define __DEV_EISA_EISAVAR_H__
+
/*
- * XXX
- * XXX EISA AUTOCONFIG SHOULD BE SEPERATED FROM ISA AUTOCONFIG!!!
- * XXX
+ * Definitions for EISA autoconfiguration.
+ *
+ * This file describes types, constants, and functions which are used
+ * for EISA autoconfiguration.
*/
+#include <machine/bus.h>
+#include <dev/eisa/eisareg.h> /* For ID register & string info. */
+
+
+typedef int eisa_slot_t; /* really only needs to be 4 bits */
+
+
/*
- * pull in the ISA definitions
+ * EISA bus attach arguments.
*/
-#include <dev/isa/isavar.h>
+struct eisabus_attach_args {
+ char *eba_busname; /* XXX should be common */
+ bus_chipset_tag_t eba_bc; /* XXX should be common */
+};
+
/*
- * and bend them to our twisted ways:
- * map the functions, etc. that are used
+ * EISA device attach arguments.
*/
+struct eisa_attach_args {
+ bus_chipset_tag_t ea_bc;
+
+ eisa_slot_t ea_slot;
+ u_int8_t ea_vid[EISA_NVIDREGS];
+ u_int8_t ea_pid[EISA_NPIDREGS];
+ char ea_idstring[EISA_IDSTRINGLEN];
+};
+
+
+/*
+ * Easy to remember names for EISA device locators.
+ */
+
+#define eisacf_slot cf_loc[0] /* slot */
+
+
+/*
+ * EISA device locator values that mean "unknown" or "unspecified."
+ * Note that not all are supplied by 'config' and should be filled
+ * in by the device if appropriate.
+ */
+
+#define EISA_UNKNOWN_SLOT ((eisa_slot_t)-1)
+
+/*
+ * The EISA bus cfdriver, so that subdevices can more easily tell
+ * what bus they're on.
+ */
+
+extern struct cfdriver eisacd;
+
+/*
+ * XXX interrupt attachment, etc., is done by using the ISA interfaces.
+ * XXX THIS SHOULD CHANGE.
+ */
+
+#include <dev/isa/isavar.h>
-#define eisa_attach_args isa_attach_args /* XXX */
-#define eisadev isadev /* XXX */
#define eisa_intr_establish isa_intr_establish /* XXX */
#define eisa_intr_disestablish isa_intr_disestablish /* XXX */
+
+#endif /* !__DEV_EISA_EISAVAR_H__ */
-# $NetBSD: files.eisa,v 1.2 1995/04/17 17:54:15 cgd Exp $
+# $OpenBSD: files.eisa,v 1.2 1996/04/18 23:47:14 niklas Exp $
+# $NetBSD: files.eisa,v 1.6 1996/03/04 03:29:12 cgd Exp $
#
# Config.new file and device description for machine-independent EISA code.
# Included by ports that need it. Requires that the SCSI files be
# defined first.
-# XXX IN A PERFECT WORLD:
-# ports should define their own "device eisa" line (like the one below,
-# but with the correct bus attachment).
-
-# XXX there should be MI EISA configuration, but not yet.
-#device eisa at root {[slot = -1]}
-#file dev/eisa/eisa.c eisa
+device eisa at eisabus {[slot = -1]}
+file dev/eisa/eisa.c eisa needs-flag
# Adaptec AHA-174x EISA SCSI Host Adapter family
-device ahb at isa: scsi # XXX should be at EISA
-file dev/eisa/aha1742.c ahb
+device ahb at eisa: scsi
+file dev/eisa/aha1742.c ahb
-/* $NetBSD: aic7xxx.c,v 1.2 1996/01/13 02:05:22 thorpej Exp $ */
+/* $OpenBSD: aic7xxx.c,v 1.3 1996/04/18 23:47:15 niklas Exp $ */
+/* $NetBSD: aic7xxx.c,v 1.3 1996/02/25 22:56:30 cgd Exp $ */
/*
* Generic driver for the aic7xxx based adaptec SCSI controllers
#include <machine/pio.h>
-#include <dev/isa/isareg.h>
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
#include <scsi/scsi_all.h>
#include <scsi/scsi_debug.h>
#include <scsi/scsiconf.h>
+/* $OpenBSD: aic7xxxvar.h,v 1.2 1996/04/18 23:47:16 niklas Exp $ */
+/* $NetBSD: aic7xxxvar.h,v 1.2 1996/03/14 02:30:30 cgd Exp $ */
+
/*
* Interface to the generic driver for the aic7xxx based adaptec
* SCSI controllers. This is used to implement product specific
* Justin T. Gibbs.
* 4. Modifications may be freely made to this file if the above conditions
* are met.
- *
- * $Id: aic7xxxvar.h,v 1.1.1.1 1995/10/18 08:52:30 deraadt Exp $
*/
#ifndef _AIC7XXX_H_
-/* $NetBSD: am7990.c,v 1.10 1996/01/02 21:51:56 thorpej Exp $ */
+/* $OpenBSD: am7990.c,v 1.4 1996/04/18 23:47:17 niklas Exp $ */
+/* $NetBSD: am7990.c,v 1.11 1996/03/14 19:05:07 christos Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
#if defined(CCITT) && defined(LLC)
#include <sys/socketvar.h>
#include <netccitt/x25.h>
-extern llc_ctlinput(), cons_rtrequest();
+#include <netccitt/pk.h>
+#include <netccitt/pk_var.h>
+#include <netccitt/pk_extern.h>
#endif
#if NBPFILTER > 0
#if defined(CCITT) && defined(LLC)
case SIOCSIFCONF_X25:
ifp->if_flags |= IFF_UP;
- ifa->ifa_rtrequest = (void (*)())cons_rtrequest; /* XXX */
+ ifa->ifa_rtrequest = cons_rtrequest; /* XXX */
error = x25_llcglue(PRC_IFUP, ifa->ifa_addr);
if (error == 0)
leinit(sc);
-/* $NetBSD: am7990var.h,v 1.3 1995/12/11 19:48:58 mycroft Exp $ */
+/* $OpenBSD: am7990var.h,v 1.3 1996/04/18 23:47:18 niklas Exp $ */
+/* $NetBSD: am7990var.h,v 1.4 1996/03/14 19:05:09 christos Exp $ */
/*
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
void lestop __P((struct le_softc *));
void lewatchdog __P((int));
-integrate u_int16_t lerdcsr __P((/* struct le_softc *, u_int16_t */));
-integrate void lewrcsr __P((/* struct le_softc *, u_int16_t, u_int16_t */));
+integrate u_int16_t lerdcsr __P((struct le_softc *, u_int16_t));
+integrate void lewrcsr __P((struct le_softc *, u_int16_t, u_int16_t));
integrate void lerint __P((struct le_softc *));
integrate void letint __P((struct le_softc *));
-/* $OpenBSD: com.c,v 1.9 1996/03/20 01:00:42 mickey Exp $ */
-/* $NetBSD: com.c,v 1.65 1996/02/10 20:23:18 christos Exp $ */
+/* $OpenBSD: com.c,v 1.10 1996/04/18 23:47:32 niklas Exp $ */
+/* $NetBSD: com.c,v 1.75 1996/03/10 09:01:24 cgd Exp $ */
/*-
- * Copyright (c) 1993, 1994, 1995 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1993, 1994, 1995, 1996
+ * Charles M. Hannum. All rights reserved.
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
#include <sys/device.h>
#include <machine/cpu.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/isa/comreg.h>
+#include <dev/isa/comvar.h>
#include <dev/ic/ns16550reg.h>
#ifdef COM_HAYESP
#include <dev/ic/hayespreg.h>
int sc_floods;
int sc_errors;
+ int sc_halt;
+
int sc_iobase;
#ifdef COM_HAYESP
int sc_hayespbase;
#endif
+
+ bus_chipset_tag_t sc_bc;
+ bus_io_handle_t sc_ioh;
+ bus_io_handle_t sc_hayespioh;
+
u_char sc_hwflags;
#define COM_HW_NOIEN 0x01
#define COM_HW_FIFO 0x02
#define COM_SW_CLOCAL 0x02
#define COM_SW_CRTSCTS 0x04
#define COM_SW_MDMBUF 0x08
- u_char sc_msr, sc_mcr, sc_lcr;
+ u_char sc_msr, sc_mcr, sc_lcr, sc_ier;
u_char sc_dtr;
u_char *sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend;
};
int comprobe __P((struct device *, void *, void *));
+#ifdef COM_HAYESP
+int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc));
+#endif
void comattach __P((struct device *, struct device *, void *));
int comopen __P((dev_t, int, int, struct proc *));
int comclose __P((dev_t, int, int, struct proc *));
int comparam __P((struct tty *, struct termios *));
void comstart __P((struct tty *));
+int cominit __P((bus_chipset_tag_t, bus_io_handle_t, int));
+
struct cfdriver comcd = {
NULL, "com", comprobe, comattach, DV_TTY, sizeof(struct com_softc)
};
-int comdefaultrate = TTYDEF_SPEED;
#ifdef COMCONSOLE
-int comconsole = COMCONSOLE;
+int comdefaultrate = CONSPEED; /* XXX why set default? */
#else
-int comconsole = -1;
+int comdefaultrate = TTYDEF_SPEED;
#endif
+int comconsaddr;
int comconsinit;
+int comconsattached;
+bus_chipset_tag_t comconsbc;
+bus_io_handle_t comconsioh;
+
int commajor;
int comsopen = 0;
int comevents = 0;
}
int
-comprobe1(iobase)
+comprobe1(bc, ioh, iobase)
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
int iobase;
{
int tmp;
int i,k;
/* force access to id reg */
- outb(iobase + com_lcr, 0);
- outb(iobase + com_iir, 0);
- for(i=0;i<32;i++) {
- k=inb(iobase + com_iir);
+ bus_io_write_1(bc, ioh, com_lcr, 0);
+ bus_io_write_1(bc, ioh, com_iir, 0);
+ for (i = 0; i < 32; i++) {
+ k = bus_io_read_1(bc, ioh, com_iir);
if (k & 0x38) {
- inb(iobase + com_data ); /* cleanup */
+ bus_io_read_1(bc, ioh, com_data); /* cleanup */
} else
break;
}
- if(i>=32)
+ if (i >= 32)
return 0;
return 1;
#ifdef COM_HAYESP
int
-comprobeHAYESP(iobase, sc)
- int iobase;
+comprobeHAYESP(hayespioh, sc)
+ bus_io_handle_t hayespioh;
struct com_softc *sc;
{
char val, dips;
int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
+ bus_chipset_tag_t bc = sc->sc_bc;
/*
* Hayes ESP cards have two iobases. One is for compatibility with
*/
/* Test for ESP signature */
- if ((inb(iobase) & 0xf3) == 0)
+ if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0)
return 0;
/*
*/
/* Get the dip-switch configurations */
- outb(iobase + HAYESP_CMD1, HAYESP_GETDIPS);
- dips = inb(iobase + HAYESP_STATUS1);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
+ dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1);
/* Determine which com port this ESP card services: bits 0,1 of */
/* dips is the port # (0-3); combaselist[val] is the com_iobase */
/* Check ESP Self Test bits. */
/* Check for ESP version 2.0: bits 4,5,6 == 010 */
- outb(iobase + HAYESP_CMD1, HAYESP_GETTEST);
- val = inb(iobase + HAYESP_STATUS1); /* Clear reg 1 */
- val = inb(iobase + HAYESP_STATUS2);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
+ val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
+ val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2);
if ((val & 0x70) < 0x20) {
printf("-old (%o)", val & 0x70);
/* we do not support the necessary features */
*/
SET(sc->sc_hwflags, COM_HW_HAYESP);
- printf(", 1024k fifo\n");
+ printf(", 1024 byte fifo\n");
return 1;
}
#endif
struct device *parent;
void *match, *aux;
{
- struct isa_attach_args *ia = aux;
- int iobase = ia->ia_iobase;
+ struct cfdata *cf = match;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ int iobase, needioh;
+ int rv = 1;
+
+ if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) {
+ struct isa_attach_args *ia = aux;
+
+ bc = ia->ia_bc;
+ iobase = ia->ia_iobase;
+ needioh = 1;
+ } else {
+ struct commulti_attach_args *ca = aux;
+
+ if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave)
+ return (0);
- if (!comprobe1(iobase))
- return 0;
+ bc = ca->ca_bc;
+ iobase = ca->ca_iobase;
+ ioh = ca->ca_ioh;
+ needioh = 0;
+ }
- ia->ia_iosize = COM_NPORTS;
- ia->ia_msize = 0;
- return 1;
+ /* if it's in use as console, it's there. */
+ if (iobase == comconsaddr && !comconsattached)
+ goto out;
+
+ if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ rv = comprobe1(bc, ioh, iobase);
+ if (needioh)
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+
+out:
+ if (rv && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) {
+ struct isa_attach_args *ia = aux;
+
+ ia->ia_iosize = COM_NPORTS;
+ ia->ia_msize = 0;
+ }
+ return (rv);
}
void
void *aux;
{
struct com_softc *sc = (void *)self;
- struct isa_attach_args *ia = aux;
struct cfdata *cf = sc->sc_dev.dv_cfdata;
- int iobase = ia->ia_iobase;
+ int iobase, irq;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
struct tty *tp;
#ifdef COM_HAYESP
int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
int *hayespp;
#endif
- sc->sc_iobase = iobase;
- sc->sc_hwflags = ISSET(cf->cf_flags, COM_HW_NOIEN);
+ sc->sc_hwflags = 0;
sc->sc_swflags = 0;
+ if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) {
+ struct isa_attach_args *ia = aux;
- if (sc->sc_dev.dv_unit == comconsole)
- delay(1000);
+ /*
+ * We're living on an isa.
+ */
+ iobase = ia->ia_iobase;
+ bc = ia->ia_bc;
+ if (iobase != comconsaddr) {
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh))
+ panic("comattach: io mapping failed");
+ } else
+ ioh = comconsioh;
+ irq = ia->ia_irq;
+ } else {
+ struct commulti_attach_args *ca = aux;
+
+ /*
+ * We're living on a commulti.
+ */
+ iobase = ca->ca_iobase;
+ bc = ca->ca_bc;
+ ioh = ca->ca_ioh;
+ irq = IRQUNK;
+
+ if (ca->ca_noien)
+ sc->sc_hwflags |= COM_HW_NOIEN;
+ }
+
+ sc->sc_bc = bc;
+ sc->sc_ioh = ioh;
+ sc->sc_iobase = iobase;
+
+ if (iobase == comconsaddr) {
+ comconsattached = 1;
+
+ /*
+ * Need to reset baud rate, etc. of next print so reset
+ * comconsinit. Also make sure console is always "hardwired".
+ */
+ delay(1000); /* wait for output to finish */
+ comconsinit = 0;
+ SET(sc->sc_hwflags, COM_HW_CONSOLE);
+ SET(sc->sc_swflags, COM_SW_SOFTCAR);
+ }
#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
- for (hayespp = hayesp_ports; *hayespp != 0; hayespp++)
- if (comprobeHAYESP(*hayespp, sc)) {
+ for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
+ bus_io_handle_t hayespioh;
+
+#define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */
+ if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh))
+ continue;
+ if (comprobeHAYESP(hayespioh, sc)) {
sc->sc_hayespbase = *hayespp;
+ sc->sc_hayespioh = hayespioh;
break;
}
+ bus_io_unmap(bc, hayespioh, HAYESP_NPORTS);
+ }
/* No ESP; look for other things. */
if (*hayespp == 0) {
#endif
/* look for a NS 16550AF UART with FIFOs */
- outb(iobase + com_fifo,
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
delay(100);
- if (ISSET(inb(iobase + com_iir), IIR_FIFO_MASK) == IIR_FIFO_MASK)
- if (ISSET(inb(iobase + com_fifo), FIFO_TRIGGER_14) == FIFO_TRIGGER_14) {
+ if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) ==
+ IIR_FIFO_MASK)
+ if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) ==
+ FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
printf(": ns16550a, working fifo\n");
} else
printf(": ns16550, broken fifo\n");
else
printf(": ns8250 or ns16450, no fifo\n");
- outb(iobase + com_fifo, 0);
+ bus_io_write_1(bc, ioh, com_fifo, 0);
#ifdef COM_HAYESP
}
#endif
/* disable interrupts */
- outb(iobase + com_ier, 0);
- outb(iobase + com_mcr, 0);
+ bus_io_write_1(bc, ioh, com_ier, 0);
+ bus_io_write_1(bc, ioh, com_mcr, 0);
- if (ia->ia_irq != IRQUNK)
- sc->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_TTY,
+ if (irq != IRQUNK)
+ sc->sc_ih = isa_intr_establish(irq, IST_EDGE, IPL_TTY,
comintr, sc, sc->sc_dev.dv_xname);
#ifdef KGDB
if (kgdb_dev == makedev(commajor, unit)) {
- if (comconsole == unit)
+ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
kgdb_dev = -1; /* can't debug over console port */
else {
- (void) cominit(unit, kgdb_rate);
+ (void) cominit(bc, ioh, kgdb_rate);
if (kgdb_debug_init) {
/*
* Print prefix of device name,
}
#endif
- if (sc->sc_dev.dv_unit == comconsole) {
- /*
- * Need to reset baud rate, etc. of next print so reset
- * comconsinit. Also make sure console is always "hardwired".
- */
- comconsinit = 0;
- SET(sc->sc_hwflags, COM_HW_CONSOLE);
- SET(sc->sc_swflags, COM_SW_SOFTCAR);
- }
+ /* XXX maybe move up some? */
+ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
+ printf("%s: console\n", sc->sc_dev.dv_xname);
}
int
{
int unit = COMUNIT(dev);
struct com_softc *sc;
- int iobase;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
struct tty *tp;
int s;
int error = 0;
sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER;
sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
- iobase = sc->sc_iobase;
+ bc = sc->sc_bc;
+ ioh = sc->sc_ioh;
#ifdef COM_HAYESP
/* Setup the ESP board */
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- int hayespbase = sc->sc_hayespbase;
+ bus_io_handle_t hayespioh = sc->sc_hayespioh;
- outb(iobase + com_fifo,
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_DMA_MODE|FIFO_ENABLE|
FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
/* Set 16550 compatibility mode */
- outb(hayespbase + HAYESP_CMD1, HAYESP_SETMODE);
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
HAYESP_MODE_SCALE);
/* Set RTS/CTS flow control */
- outb(hayespbase + HAYESP_CMD1, HAYESP_SETFLOWTYPE);
- outb(hayespbase + HAYESP_CMD2, HAYESP_FLOW_RTS);
- outb(hayespbase + HAYESP_CMD2, HAYESP_FLOW_CTS);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
/* Set flow control levels */
- outb(hayespbase + HAYESP_CMD1, HAYESP_SETRXFLOW);
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXHIWMARK));
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXHIWMARK));
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXLOWMARK));
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
} else
#endif
if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
/* Set the FIFO threshold based on the receive speed. */
- outb(iobase + com_fifo,
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
(tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
/* flush any pending I/O */
- while (ISSET(inb(iobase + com_lsr), LSR_RXRDY))
- (void) inb(iobase + com_data);
+ while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
+ (void) bus_io_read_1(bc, ioh, com_data);
/* you turn me on, baby */
sc->sc_mcr = MCR_DTR | MCR_RTS;
if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
SET(sc->sc_mcr, MCR_IENABLE);
- outb(iobase + com_mcr, sc->sc_mcr);
- outb(iobase + com_ier,
- IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
+ bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
- sc->sc_msr = inb(iobase + com_msr);
+ sc->sc_msr = bus_io_read_1(bc, ioh, com_msr);
if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) ||
ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF))
SET(tp->t_state, TS_CARR_ON);
int unit = COMUNIT(dev);
struct com_softc *sc = comcd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int s;
/* XXX This is for cons.c. */
(*linesw[tp->t_line].l_close)(tp, flag);
s = spltty();
CLR(sc->sc_lcr, LCR_SBREAK);
- outb(iobase + com_lcr, sc->sc_lcr);
- outb(iobase + com_ier, 0);
+ bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_io_write_1(bc, ioh, com_ier, 0);
if (ISSET(tp->t_cflag, HUPCL) &&
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) {
/* XXX perhaps only clear DTR */
- outb(iobase + com_mcr, 0);
+ bus_io_write_1(bc, ioh, com_mcr, 0);
}
CLR(tp->t_state, TS_BUSY | TS_FLUSH);
if (--comsopen == 0)
splx(s);
ttyclose(tp);
#ifdef notyet /* XXXX */
- if (unit != comconsole) {
+ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
ttyfree(tp);
sc->sc_tty = 0;
}
int unit = COMUNIT(dev);
struct com_softc *sc = comcd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int error;
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
switch (cmd) {
case TIOCSBRK:
SET(sc->sc_lcr, LCR_SBREAK);
- outb(iobase + com_lcr, sc->sc_lcr);
+ bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCCBRK:
CLR(sc->sc_lcr, LCR_SBREAK);
- outb(iobase + com_lcr, sc->sc_lcr);
+ bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCSDTR:
SET(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCCDTR:
CLR(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMSET:
CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
case TIOCMBIS:
SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMBIC:
CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMGET: {
u_char m;
SET(bits, TIOCM_DSR);
if (ISSET(m, MSR_RI | MSR_TERI))
SET(bits, TIOCM_RI);
- if (inb(iobase + com_ier))
+ if (bus_io_read_1(bc, ioh, com_ier))
SET(bits, TIOCM_LE);
*(int *)data = bits;
break;
struct termios *t;
{
struct com_softc *sc = comcd.cd_devs[COMUNIT(tp->t_dev)];
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int ospeed = comspeed(t->c_ospeed);
u_char lcr;
tcflag_t oldcflag;
if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
return EINVAL;
- lcr = sc->sc_lcr & LCR_SBREAK;
+ lcr = ISSET(sc->sc_lcr, LCR_SBREAK);
switch (ISSET(t->c_cflag, CSIZE)) {
case CS5:
if (ospeed == 0) {
CLR(sc->sc_mcr, MCR_DTR);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
/*
* Set the FIFO threshold based on the receive speed, if we are
* changing it.
*/
+#if 1
if (tp->t_ispeed != t->c_ispeed) {
- if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
- outb(iobase + com_fifo,
+#else
+ if (1) {
+#endif
+ if (ospeed != 0) {
+ /*
+ * Make sure the transmit FIFO is empty before
+ * proceeding. If we don't do this, some revisions
+ * of the UART will hang. Interestingly enough,
+ * even if we do this will the last character is
+ * still being pushed out, they don't hang. This
+ * seems good enough.
+ */
+ while (ISSET(tp->t_state, TS_BUSY)) {
+ int error;
+
+ ++sc->sc_halt;
+ error = ttysleep(tp, &tp->t_outq,
+ TTOPRI | PCATCH, "comprm", 0);
+ --sc->sc_halt;
+ if (error) {
+ splx(s);
+ comstart(tp);
+ return (error);
+ }
+ }
+
+ bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB);
+ bus_io_write_1(bc, ioh, com_dlbl, ospeed);
+ bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8);
+ bus_io_write_1(bc, ioh, com_lcr, lcr);
+ SET(sc->sc_mcr, MCR_DTR);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ } else
+ bus_io_write_1(bc, ioh, com_lcr, lcr);
+
+ if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) &&
+ ISSET(sc->sc_hwflags, COM_HW_FIFO))
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_ENABLE |
(t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
- }
-
- if (ospeed != 0) {
- outb(iobase + com_lcr, lcr | LCR_DLAB);
- outb(iobase + com_dlbl, ospeed);
- outb(iobase + com_dlbh, ospeed >> 8);
- outb(iobase + com_lcr, lcr);
- SET(sc->sc_mcr, MCR_DTR);
- outb(iobase + com_mcr, sc->sc_mcr);
} else
- outb(iobase + com_lcr, lcr);
+ bus_io_write_1(bc, ioh, com_lcr, lcr);
/* When not using CRTSCTS, RTS follows DTR. */
if (!ISSET(t->c_cflag, CRTSCTS)) {
if (ISSET(sc->sc_mcr, MCR_DTR)) {
if (!ISSET(sc->sc_mcr, MCR_RTS)) {
SET(sc->sc_mcr, MCR_RTS);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
} else {
if (ISSET(sc->sc_mcr, MCR_RTS)) {
CLR(sc->sc_mcr, MCR_RTS);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
}
sc->sc_dtr = MCR_DTR | MCR_RTS;
ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
+ /* Just to be sure... */
splx(s);
+ comstart(tp);
return 0;
}
struct tty *tp;
{
struct com_softc *sc = comcd.cd_devs[COMUNIT(tp->t_dev)];
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int s;
s = spltty();
- if (ISSET(tp->t_state, TS_TTSTOP | TS_BUSY))
+ if (ISSET(tp->t_state, TS_BUSY))
goto out;
+ if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) ||
+ sc->sc_halt > 0)
+ goto stopped;
if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS))
- goto out;
+ goto stopped;
if (tp->t_outq.c_cc <= tp->t_lowat) {
if (ISSET(tp->t_state, TS_ASLEEP)) {
CLR(tp->t_state, TS_ASLEEP);
wakeup(&tp->t_outq);
}
if (tp->t_outq.c_cc == 0)
- goto out;
+ goto stopped;
selwakeup(&tp->t_wsel);
}
SET(tp->t_state, TS_BUSY);
+ if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
+ SET(sc->sc_ier, IER_ETXRDY);
+ bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ }
#ifdef COM_HAYESP
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
u_char buffer[1024], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do
- outb(iobase + com_data, *cp++);
+ bus_io_write_1(bc, ioh, com_data, *cp++);
while (--n);
}
else
u_char buffer[16], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do {
- outb(iobase + com_data, *cp++);
+ bus_io_write_1(bc, ioh, com_data, *cp++);
} while (--n);
} else
- outb(iobase + com_data, getc(&tp->t_outq));
+ bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq));
out:
splx(s);
+ return;
+stopped:
+ if (ISSET(sc->sc_ier, IER_ETXRDY)) {
+ CLR(sc->sc_ier, IER_ETXRDY);
+ bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ }
+ splx(s);
}
/*
!ISSET(sc->sc_mcr, MCR_RTS)) {
/* XXX */
SET(sc->sc_mcr, MCR_RTS);
- outb(sc->sc_iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr,
+ sc->sc_mcr);
}
splx(s);
void *arg;
{
struct com_softc *sc = arg;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
struct tty *tp;
u_char lsr, data, msr, delta;
+#ifdef COM_DEBUG
+ int n;
+ struct {
+ u_char iir, lsr, msr;
+ } iter[32];
+#endif
- if (ISSET(inb(iobase + com_iir), IIR_NOPEND))
+#ifdef COM_DEBUG
+ n = 0;
+ if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ return (0);
+#else
+ if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
return (0);
+#endif
tp = sc->sc_tty;
for (;;) {
- lsr = inb(iobase + com_lsr);
+#ifdef COM_DEBUG
+ iter[n].lsr =
+#endif
+ lsr = bus_io_read_1(bc, ioh, com_lsr);
- if (ISSET(lsr, LSR_RCV_MASK)) {
+ if (ISSET(lsr, LSR_RXRDY)) {
register u_char *p = sc->sc_ibufp;
comevents = 1;
do {
- data = ISSET(lsr, LSR_RXRDY) ?
- inb(iobase + com_data) : 0;
+ data = bus_io_read_1(bc, ioh, com_data);
if (ISSET(lsr, LSR_BI)) {
+#ifdef notdef
+ printf("break %02x %02x %02x %02x\n",
+ sc->sc_msr, sc->sc_mcr, sc->sc_lcr,
+ sc->sc_dtr);
+#endif
#ifdef DDB
- if (sc->sc_dev.dv_unit == comconsole) {
+ if (ISSET(sc->sc_hwflags,
+ COM_HW_CONSOLE)) {
Debugger();
goto next;
}
#endif
- data = '\0';
}
if (p >= sc->sc_ibufend) {
sc->sc_floods++;
ISSET(tp->t_cflag, CRTSCTS)) {
/* XXX */
CLR(sc->sc_mcr, MCR_RTS);
- outb(iobase + com_mcr,
- sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr,
+ sc->sc_mcr);
}
}
next:
- lsr = inb(iobase + com_lsr);
- } while (ISSET(lsr, LSR_RCV_MASK));
+#ifdef COM_DEBUG
+ if (++n >= 32)
+ goto ohfudge;
+ iter[n].lsr =
+#endif
+ lsr = bus_io_read_1(bc, ioh, com_lsr);
+ } while (ISSET(lsr, LSR_RXRDY));
sc->sc_ibufp = p;
}
-#if 0
+#ifdef COM_DEBUG
else if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE))
printf("weird lsr %02x\n", lsr);
#endif
- msr = inb(iobase + com_msr);
+#ifdef COM_DEBUG
+ iter[n].msr =
+#endif
+ msr = bus_io_read_1(bc, ioh, com_msr);
if (msr != sc->sc_msr) {
delta = msr ^ sc->sc_msr;
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) &&
(*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
if (ISSET(delta & msr, MSR_CTS) &&
ISSET(tp->t_cflag, CRTSCTS)) {
}
if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) {
- CLR(tp->t_state, TS_BUSY);
- if (ISSET(tp->t_state, TS_FLUSH))
- CLR(tp->t_state, TS_FLUSH);
- else
- (*linesw[tp->t_line].l_start)(tp);
+ CLR(tp->t_state, TS_BUSY | TS_FLUSH);
+ if (sc->sc_halt > 0)
+ wakeup(&tp->t_outq);
+ (*linesw[tp->t_line].l_start)(tp);
}
- if (ISSET(inb(iobase + com_iir), IIR_NOPEND))
+#ifdef COM_DEBUG
+ if (++n >= 32)
+ goto ohfudge;
+ if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ return (1);
+#else
+ if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
return (1);
+#endif
+ }
+#ifdef COM_DEBUG
+ohfudge:
+ printf("comintr: too many iterations");
+ for (n = 0; n < 32; n++) {
+ if ((n % 4) == 0)
+ printf("\ncomintr: iter[%02d]", n);
+ printf(" %02x %02x %02x", iter[n].iir, iter[n].lsr, iter[n].msr);
}
+ printf("\n");
+ printf("comintr: msr %02x mcr %02x lcr %02x ier %02x\n",
+ sc->sc_msr, sc->sc_mcr, sc->sc_lcr, sc->sc_ier);
+ printf("comintr: state %08x cc %d\n", sc->sc_tty->t_state,
+ sc->sc_tty->t_outq.c_cc);
+#endif
}
/*
comcnprobe(cp)
struct consdev *cp;
{
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ int found;
- if (!comprobe1(CONADDR)) {
+#if 0
+ XXX NEEDS TO BE FIXED XXX
+ bc = ???;
+#endif
+ if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) {
+ cp->cn_pri = CN_DEAD;
+ return;
+ }
+ found = comprobe1(bc, ioh, CONADDR);
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ if (!found) {
cp->cn_pri = CN_DEAD;
return;
}
struct consdev *cp;
{
- cominit(CONUNIT, comdefaultrate);
- comconsole = CONUNIT;
+#if 0
+ XXX NEEDS TO BE FIXED XXX
+ comconsbc = ???;
+#endif
+ if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh))
+ panic("comcninit: mapping failed");
+
+ cominit(comconsbc, comconsioh, comdefaultrate);
+ comconsaddr = CONADDR;
comconsinit = 0;
}
-cominit(unit, rate)
- int unit, rate;
+cominit(bc, ioh, rate)
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ int rate;
{
int s = splhigh();
- int iobase = CONADDR;
u_char stat;
- outb(iobase + com_lcr, LCR_DLAB);
+ bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB);
rate = comspeed(comdefaultrate);
- outb(iobase + com_dlbl, rate);
- outb(iobase + com_dlbh, rate >> 8);
- outb(iobase + com_lcr, LCR_8BITS);
- outb(iobase + com_ier, IER_ERXRDY | IER_ETXRDY);
- outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
- stat = inb(iobase + com_iir);
+ bus_io_write_1(bc, ioh, com_dlbl, rate);
+ bus_io_write_1(bc, ioh, com_dlbh, rate >> 8);
+ bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS);
+ bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
+ bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
+ stat = bus_io_read_1(bc, ioh, com_iir);
splx(s);
}
dev_t dev;
{
int s = splhigh();
- int iobase = CONADDR;
+ bus_chipset_tag_t bc = comconsbc;
+ bus_io_handle_t ioh = comconsioh;
u_char stat, c;
- while (!ISSET(stat = inb(iobase + com_lsr), LSR_RXRDY))
+ while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
;
- c = inb(iobase + com_data);
- stat = inb(iobase + com_iir);
+ c = bus_io_read_1(bc, ioh, com_data);
+ stat = bus_io_read_1(bc, ioh, com_iir);
splx(s);
return c;
}
int c;
{
int s = splhigh();
- int iobase = CONADDR;
+ bus_chipset_tag_t bc = comconsbc;
+ bus_io_handle_t ioh = comconsioh;
u_char stat;
register int timo;
if (dev != kgdb_dev)
#endif
if (comconsinit == 0) {
- (void) cominit(COMUNIT(dev), comdefaultrate);
+ (void) cominit(bc, ioh, comdefaultrate);
comconsinit = 1;
}
/* wait for any pending transmission to finish */
timo = 50000;
- while (!ISSET(stat = inb(iobase + com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
;
- outb(iobase + com_data, c);
+ bus_io_write_1(bc, ioh, com_data, c);
/* wait for this transmission to complete */
timo = 1500000;
- while (!ISSET(stat = inb(iobase + com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
;
/* clear any interrupts generated by this transmission */
- stat = inb(iobase + com_iir);
+ stat = bus_io_read_1(bc, ioh, com_iir);
splx(s);
}
-/* $NetBSD: i8237reg.h,v 1.4 1994/10/27 04:18:39 cgd Exp $ */
+/* $OpenBSD: i8237reg.h,v 1.2 1996/04/18 23:47:19 niklas Exp $ */
+/* $NetBSD: i8237reg.h,v 1.5 1996/03/01 22:27:09 mycroft Exp $ */
/*
* Intel 8237 DMA Controller
*/
-#define DMA37MD_SINGLE 0x40 /* single pass mode */
-#define DMA37MD_CASCADE 0xc0 /* cascade mode */
#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */
#define DMA37MD_READ 0x08 /* write the device, read memory operation */
+#define DMA37MD_LOOP 0x10 /* auto-initialize mode */
+#define DMA37MD_SINGLE 0x40 /* single pass mode */
+#define DMA37MD_CASCADE 0xc0 /* cascade mode */
#define DMA37SM_CLEAR 0x00 /* clear mask bit */
#define DMA37SM_SET 0x04 /* set mask bit */
-/* $NetBSD: ncr5380sbc.c,v 1.3 1996/02/10 00:11:48 christos Exp $ */
+/* $OpenBSD: ncr5380sbc.c,v 1.4 1996/04/18 23:47:19 niklas Exp $ */
+/* $NetBSD: ncr5380sbc.c,v 1.8 1996/03/07 15:00:17 christos Exp $ */
/*
* Copyright (c) 1995 David Jones, Gordon W. Ross
#include <scsi/scsi_message.h>
#include <scsi/scsiconf.h>
-#ifndef DEBUG
-#define DEBUG XXX
-#endif
-
#include <dev/ic/ncr5380reg.h>
#include <dev/ic/ncr5380var.h>
-static int ncr5380_wait_req __P((struct ncr5380_softc *));
-static int ncr5380_wait_not_req __P((struct ncr5380_softc *));
-
static void ncr5380_sched __P((struct ncr5380_softc *));
static void ncr5380_done __P((struct ncr5380_softc *));
static int ncr5380_status __P((struct ncr5380_softc *));
static void ncr5380_machine __P((struct ncr5380_softc *));
+void ncr5380_abort __P((struct ncr5380_softc *));
+void ncr5380_cmd_timeout __P((void *));
/*
* Action flags returned by the info_tranfer functions:
* (These determine what happens next.)
#define Debugger() printf("Debug: ncr5380.c:%d\n", __LINE__)
#endif
-#ifdef DEBUG
+#ifdef NCR5380_DEBUG
#define NCR_DBG_BREAK 1
#define NCR_DBG_CMDS 2
do { if (ncr5380_debug & NCR_DBG_BREAK) Debugger(); } while (0)
static void ncr5380_show_scsi_cmd __P((struct scsi_xfer *));
static void ncr5380_show_sense __P((struct scsi_xfer *));
-#else /* DEBUG */
+
+#else /* NCR5380_DEBUG */
+
#define NCR_BREAK() /* nada */
#define ncr5380_show_scsi_cmd(xs) /* nada */
#define ncr5380_show_sense(xs) /* nada */
-#endif /* DEBUG */
+
+#endif /* NCR5380_DEBUG */
static char *
phase_names[8] = {
int ncr5380_wait_req_timo = 1000 * 50; /* X2 = 100 mS. */
int ncr5380_wait_nrq_timo = 1000 * 25; /* X2 = 50 mS. */
+static __inline int ncr5380_wait_req __P((struct ncr5380_softc *));
+static __inline int ncr5380_wait_not_req __P((struct ncr5380_softc *));
+static __inline void ncr_sched_msgout __P((struct ncr5380_softc *, int));
+
/* Return zero on success. */
-static __inline__ int ncr5380_wait_req(sc)
+static __inline int ncr5380_wait_req(sc)
struct ncr5380_softc *sc;
{
register int timo = ncr5380_wait_req_timo;
}
/* Return zero on success. */
-static __inline__ int ncr5380_wait_not_req(sc)
+static __inline int ncr5380_wait_not_req(sc)
struct ncr5380_softc *sc;
{
register int timo = ncr5380_wait_nrq_timo;
}
/* Ask the target for a MSG_OUT phase. */
-static __inline__ void
+static __inline void
ncr_sched_msgout(sc, msg_code)
struct ncr5380_softc *sc;
int msg_code;
{
int i, j;
-#ifdef DEBUG
+#ifdef NCR5380_DEBUG
ncr5380_debug_sc = sc;
#endif
switch (sr->sr_status) {
case SCSI_OK: /* 0 */
if (sr->sr_flags & SR_SENSE) {
+#ifdef NCR5380_DEBUG
if (ncr5380_debug & NCR_DBG_CMDS) {
ncr5380_show_sense(xs);
}
+#endif
xs->error = XS_SENSE;
}
break;
{
struct sci_req *sr;
struct scsi_xfer *xs;
- int target, lun;
+ int target = 0, lun = 0;
int error, i;
/* Another hack (Er.. hook!) for the sun3 si: */
target = sc->sc_ring[i].sr_target;
lun = sc->sc_ring[i].sr_lun;
if (sc->sc_matrix[target][lun] == NULL) {
- sc->sc_matrix[target][lun] =
- sr = &sc->sc_ring[i];
- sc->sc_rr = i;
- break;
+ /*
+ * Do not mark the target/LUN busy yet,
+ * because reselect may cause some other
+ * job to become the current one, so we
+ * might not actually start this job.
+ * Instead, set sc_matrix later on.
+ */
+ sc->sc_rr = i;
+ sr = &sc->sc_ring[i];
+ break;
}
}
i++;
goto have_nexus;
}
- /* Normal selection result */
+ /* Normal selection result. Target/LUN is now busy. */
+ sc->sc_matrix[target][lun] = sr;
sc->sc_current = sr; /* connected */
xs = sr->sr_xs;
* Normal commands start in MSG_OUT phase where we will
* send and IDENDIFY message, and then expect CMD phase.
*/
+#ifdef NCR5380_DEBUG
if (ncr5380_debug & NCR_DBG_CMDS) {
printf("ncr5380_sched: begin, target=%d, LUN=%d\n",
xs->sc_link->target, xs->sc_link->lun);
ncr5380_show_scsi_cmd(xs);
}
+#endif
if (xs->flags & SCSI_RESET) {
NCR_TRACE("sched: cmd=reset, sr=0x%x\n", (long)sr);
/* Not an error, so do not set NCR_ABORTING */
#ifdef DIAGNOSTIC
if ((xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) == 0) {
if (sc->sc_dataptr) {
- printf("%s: ptr but no data in/out flags?\n");
+ printf("%s: ptr but no data in/out flags?\n",
+ sc->sc_dev.dv_xname);
NCR_BREAK();
sc->sc_dataptr = NULL;
}
struct ncr5380_softc *sc;
struct sci_req *sr;
{
- int timo;
- u_char bus, data, icmd;
+ int timo, s;
+ u_char data, icmd;
/* Check for reselect */
ncr5380_reselect(sc);
* We then wait for one arbitration delay (2.2uS) and
* check the ICMD_LST bit, which will be set if some
* other target drives SEL during arbitration.
+ *
+ * There is a time-critical section during the period
+ * after we enter arbitration up until we assert SEL.
+ * Avoid long interrupts during this period.
*/
+ s = splimp(); /* XXX: Begin time-critical section */
+
*(sc->sci_odata) = 0x80; /* OUR_ID */
*(sc->sci_mode) = SCI_MODE_ARB;
- /* Wait for ICMD_AIP. */
- timo = ncr5380_wait_req_timo;
+#define WAIT_AIP_USEC 20 /* pleanty of time */
+ /* Wait for the AIP bit to turn on. */
+ timo = WAIT_AIP_USEC;
for (;;) {
if (*(sc->sci_icmd) & SCI_ICMD_AIP)
break;
- if (--timo <= 0) {
- /* Did not see any "bus free" period. */
- *sc->sci_mode = 0;
+ if (timo <= 0) {
+ /*
+ * Did not see any "bus free" period.
+ * The usual reason is a reselection,
+ * so treat this as arbitration loss.
+ */
NCR_TRACE("select: bus busy, rc=%d\n", XS_BUSY);
- return XS_BUSY;
+ goto lost_arb;
}
+ timo -= 2;
delay(2);
}
- NCR_TRACE("select: have AIP after %d loops\n",
- ncr5380_wait_req_timo - timo);
+ NCR_TRACE("select: have AIP after %d uSec.\n",
+ WAIT_AIP_USEC - timo);
/* Got AIP. Wait one arbitration delay (2.2 uS.) */
delay(3);
/* Check for ICMD_LST */
if (*(sc->sci_icmd) & SCI_ICMD_LST) {
/* Some other target asserted SEL. */
- *sc->sci_mode = 0;
NCR_TRACE("select: lost one, rc=%d\n", XS_BUSY);
- ncr5380_reselect(sc); /* XXX */
- return XS_BUSY;
+ goto lost_arb;
}
/*
* We can now declare victory by asserting SEL.
*
* Note that the 5380 is asserting BSY because we
- * asked it to do arbitration. We will now hold
+ * have entered arbitration mode. We will now hold
* BSY directly so we can turn off ARB mode.
*/
icmd = (SCI_ICMD_BSY | SCI_ICMD_SEL);
*/
delay(2);
-#if 1
/*
- * XXX: Check one last time to see if we really
- * XXX: did win arbitration. (too paranoid?)
+ * Check one last time to see if we really did
+ * win arbitration. This might only happen if
+ * there can be a higher selection ID than ours.
+ * Keep this code for reference anyway...
*/
if (*(sc->sci_icmd) & SCI_ICMD_LST) {
+ /* Some other target asserted SEL. */
+ NCR_TRACE("select: lost two, rc=%d\n", XS_BUSY);
+
+ lost_arb:
*sc->sci_icmd = 0;
*sc->sci_mode = 0;
- NCR_TRACE("select: lost two, rc=%d\n", XS_BUSY);
+
+ splx(s); /* XXX: End of time-critical section. */
+
+ /*
+ * When we lose arbitration, it usually means
+ * there is a target trying to reselect us.
+ */
+ ncr5380_reselect(sc);
return XS_BUSY;
}
-#endif
+
/* Leave ARB mode Now that we drive BSY+SEL */
*sc->sci_mode = 0;
*sc->sci_sel_enb = 0;
+ splx(s); /* XXX: End of time-critical section. */
+
/*
* Arbitration is complete. Now do selection:
* Drive the data bus with the ID bits for both
* the host and target. Also set ATN now, to
- * ask the target for a messgae out phase.
+ * ask the target for a message out phase.
*/
data = 0x80 | (1 << sr->sr_target);
*(sc->sci_odata) = data;
register struct ncr5380_softc *sc;
{
struct sci_req *sr = sc->sc_current;
- int n, phase, timo;
+ int n, phase;
int act_flags;
register u_char icmd;
}
if (len != xs->cmdlen) {
-#ifdef DEBUG
+#ifdef NCR5380_DEBUG
printf("ncr5380_command: short transfer: wanted %d got %d.\n",
xs->cmdlen, len);
ncr5380_show_scsi_cmd(xs);
struct sci_req *sr = sc->sc_current;
struct scsi_xfer *xs = sr->sr_xs;
int expected_phase;
- int i, len;
+ int len;
if (sr->sr_flags & SR_SENSE) {
NCR_TRACE("data_xfer: get sense, sr=0x%x\n", (long)sr);
int len;
u_char status;
struct sci_req *sr = sc->sc_current;
- struct scsi_xfer *xs = sr->sr_xs;
/* acknowledge phase change */
*sc->sci_tcmd = PHASE_STATUS;
}
-#ifdef DEBUG
+#ifdef NCR5380_DEBUG
static void
ncr5380_show_scsi_cmd(xs)
}
#endif /* DDB */
-#endif /* DEBUG */
+#endif /* NCR5380_DEBUG */
-/* $NetBSD: ncr5380var.h,v 1.4 1996/01/01 22:24:38 thorpej Exp $ */
+/* $OpenBSD: ncr5380var.h,v 1.3 1996/04/18 23:47:21 niklas Exp $ */
+/* $NetBSD: ncr5380var.h,v 1.5 1996/03/01 01:42:07 gwr Exp $ */
/*
* Copyright (c) 1995 David Jones, Gordon W. Ross
int ncr5380_pio_in __P((struct ncr5380_softc *, int, int, u_char *));
int ncr5380_pio_out __P((struct ncr5380_softc *, int, int, u_char *));
-#ifdef DEBUG
+#ifdef NCR5380_DEBUG
struct ncr5380_softc *ncr5380_debug_sc;
void ncr5380_trace __P((char *msg, long val));
#define NCR_TRACE(msg, val) ncr5380_trace(msg, val)
-#else
+#else /* NCR5380_DEBUG */
#define NCR_TRACE(msg, val) /* nada */
-#endif
+#endif /* NCR5380_DEBUG */
-/* $NetBSD: pdq.c,v 1.2 1995/08/19 04:35:18 cgd Exp $ */
+/* $OpenBSD: pdq.c,v 1.2 1996/04/18 23:47:22 niklas Exp $ */
+/* $NetBSD: pdq.c,v 1.3 1996/03/11 21:41:28 thorpej Exp $ */
/*-
* Copyright (c) 1995 Matt Thomas (matt@lkg.dec.com)
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from Id: pdq.c,v 1.18 1995/08/20 18:59:00 thomas Exp thomas
+ *
+ * Log: pdq.c,v
+ * Revision 1.18 1995/08/20 18:59:00 thomas
+ * Changes for NetBSD
+ *
+ * Revision 1.17 1995/08/16 22:57:28 thomas
+ * Add support for NetBSD
+ *
+ * Revision 1.16 1995/08/04 21:54:56 thomas
+ * Clean IRQ processing under BSD/OS.
+ * A receive tweaks. (print source of MAC CRC errors, etc.)
+ *
+ * Revision 1.15 1995/06/30 23:36:21 thomas
+ * Optimize fix.
+ *
+ * Revision 1.14 1995/06/30 23:35:39 thomas
+ * Fix severe bug in transmit path (corruption of ring).
+ *
+ * Revision 1.13 1995/06/21 18:29:27 thomas
+ * SVR4.2 changes
+ *
+ * Revision 1.12 1995/06/05 23:49:36 thomas
+ * Fix bonehead error. Don't try to queue a command if there
+ * is a command.
+ *
+ * Revision 1.11 1995/06/03 15:43:26 thomas
+ * Fix the command submission logic to only submit one
+ * command at a time no matter what. This simplies the
+ * code significantly thereby allowing us to do some up
+ * front optimizations.
+ *
+ * Revision 1.10 1995/06/02 22:18:34 thomas
+ * Don't know why but on some motherboards, the PDQ just can't
+ * multiple outstanding commands.
+ *
+ * Revision 1.9 1995/04/20 20:17:33 thomas
+ * Add PCI support for BSD/OS.
+ * Fix BSD/OS EISA support.
+ * Set latency timer for DEFPA to recommended value if 0.
+ *
+ * Revision 1.8 1995/03/14 01:52:52 thomas
+ * Update for new FreeBSD PCI Interrupt interface
+ *
+ * Revision 1.7 1995/03/07 23:03:16 thomas
+ * Fix SMT queue processing
+ *
+ * Revision 1.6 1995/03/06 18:03:47 thomas
+ * restart trasmitter once link is available
+ *
+ * Revision 1.5 1995/03/06 17:07:56 thomas
+ * Add copyright/disclaimer
+ * Add error recovery code.
+ * Add BPF SMT support
+ *
+ * Revision 1.3 1995/03/03 13:48:35 thomas
+ * more fixes
+ *
+ *
*/
/*
#define PDQ_HWSUPPORT /* for pdq.h */
#include "pdqreg.h"
-#ifndef __NetBSD__
-#include "pdq_os.h"
-#else
+#if defined(__NetBSD__)
#include "pdqvar.h"
+#else
+#include "pdq_os.h"
#endif
#define PDQ_ROUNDUP(n, x) (((n) + ((x) - 1)) & ~((x) - 1))
*/
p = (pdq_uint8_t *) PDQ_OS_MEMALLOC_CONTIG(contig_bytes);
if (p != NULL) {
- pdq_physaddr_t physaddr = PDQ_OS_VA_TO_PA(p) & 0x1FFF;
+ pdq_physaddr_t physaddr = PDQ_OS_VA_TO_PA(p);
+ /*
+ * Assert that we really got contiguous memory. This isn't really
+ * needed on systems that actually have physical contiguous allocation
+ * routines, but on those systems that don't ...
+ */
+ for (idx = PDQ_OS_PAGESIZE; idx < 0x2000; idx += PDQ_OS_PAGESIZE) {
+ if (PDQ_OS_VA_TO_PA(p + idx) - physaddr != idx)
+ goto cleanup_and_return;
+ }
+ physaddr &= 0x1FFF;
if (physaddr) {
pdq->pdq_unsolicited_info.ui_events = (pdq_unsolicited_event_t *) p;
pdq->pdq_dbp = (pdq_descriptor_block_t *) &p[0x2000 - physaddr];
*/
if (pdq->pdq_dbp == NULL || pdq->pdq_unsolicited_info.ui_events == NULL) {
cleanup_and_return:
- if (pdq->pdq_dbp != NULL)
- PDQ_OS_MEMFREE_CONTIG(pdq->pdq_dbp, contig_bytes);
+ if (p /* pdq->pdq_dbp */ != NULL)
+ PDQ_OS_MEMFREE_CONTIG(p /* pdq->pdq_dbp */, contig_bytes);
if (contig_bytes == sizeof(pdq_descriptor_block_t) && pdq->pdq_unsolicited_info.ui_events != NULL)
PDQ_OS_MEMFREE(pdq->pdq_unsolicited_info.ui_events,
PDQ_NUM_UNSOLICITED_EVENTS * sizeof(pdq_unsolicited_event_t));
*/
state = pdq_stop(pdq);
- /* state = PDQ_PSTS_ADAPTER_STATE(*pdq->pdq_csrs.csr_port_status); */
PDQ_PRINTF(("PDQ Adapter State = %s\n", pdq_adapter_states[state]));
PDQ_ASSERT(state == PDQS_DMA_AVAILABLE);
/*
--- /dev/null
+/* $OpenBSD: pdq_ifsubr.c,v 1.1 1996/04/18 23:47:23 niklas Exp $ */
+/* $NetBSD: pdq_ifsubr.c,v 1.2 1996/03/11 21:41:32 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1995 Matt Thomas (thomas@lkg.dec.com)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software withough specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from Id: pdq_ifsubr.c,v 1.2 1995/08/20 18:59:00 thomas Exp
+ *
+ * Log: pdq_ifsubr.c,v
+ * Revision 1.2 1995/08/20 18:59:00 thomas
+ * Changes for NetBSD
+ *
+ * Revision 1.1 1995/08/20 15:43:49 thomas
+ * Initial revision
+ *
+ * Revision 1.13 1995/08/04 21:54:56 thomas
+ * Clean IRQ processing under BSD/OS.
+ * A receive tweaks. (print source of MAC CRC errors, etc.)
+ *
+ * Revision 1.12 1995/06/02 16:04:22 thomas
+ * Use correct PCI defs for BSDI now that they have fixed them.
+ * Increment the slot number 0x1000, not one! (*duh*)
+ *
+ * Revision 1.11 1995/04/21 13:23:55 thomas
+ * Fix a few pub in the DEFPA BSDI support
+ *
+ * Revision 1.10 1995/04/20 21:46:42 thomas
+ * Why???
+ * ,
+ *
+ * Revision 1.9 1995/04/20 20:17:33 thomas
+ * Add PCI support for BSD/OS.
+ * Fix BSD/OS EISA support.
+ * Set latency timer for DEFPA to recommended value if 0.
+ *
+ * Revision 1.8 1995/04/04 22:54:29 thomas
+ * Fix DEFEA support
+ *
+ * Revision 1.7 1995/03/14 01:52:52 thomas
+ * Update for new FreeBSD PCI Interrupt interface
+ *
+ * Revision 1.6 1995/03/10 17:06:59 thomas
+ * Update for latest version of FreeBSD.
+ * Compensate for the fast that the ifp will not be first thing
+ * in softc on BSDI.
+ *
+ * Revision 1.5 1995/03/07 19:59:42 thomas
+ * First pass at BSDI EISA support
+ *
+ * Revision 1.4 1995/03/06 17:06:03 thomas
+ * Add transmit timeout support.
+ * Add support DEFEA (untested).
+ *
+ * Revision 1.3 1995/03/03 13:48:35 thomas
+ * more fixes
+ *
+ *
+ */
+
+/*
+ * DEC PDQ FDDI Controller; code for BSD derived operating systems
+ *
+ * Written by Matt Thomas
+ *
+ * This driver supports the following FDDI controllers:
+ *
+ * Device: Config file entry:
+ * DEC DEFPA (PCI) device fpa0
+ * DEC DEFEA (EISA) device fea0 at isa0 net irq ? vector feaintr
+ *
+ * Eventually, the following adapters will also be supported:
+ *
+ * DEC DEFTA (TC) device fta0 at tc? slot * vector ftaintr
+ * DEC DEFQA (Q-Bus) device fta0 at uba? csr 0?? vector fqaintr
+ * DEC DEFAA (FB+) device faa0 at fbus? slot * vector faaintr
+ */
+
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/protosw.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#if defined(__FreeBSD__)
+#include <sys/devconf.h>
+#elif defined(__bsdi__) || defined(__NetBSD__)
+#include <sys/device.h>
+#endif
+
+#include <net/if.h>
+#include <net/if_types.h>
+#include <net/if_dl.h>
+#include <net/route.h>
+
+#include "bpfilter.h"
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+#endif
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+#if defined(__FreeBSD__)
+#include <netinet/if_fddi.h>
+#else
+#include <net/if_fddi.h>
+#endif
+
+#ifdef NS
+#include <netns/ns.h>
+#include <netns/ns_if.h>
+#endif
+
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_param.h>
+
+#include "pdqreg.h"
+#if defined(__NetBSD__)
+#include "pdqvar.h"
+#else
+#include "pdq_os.h"
+#endif
+
+void
+pdq_ifinit(
+ pdq_softc_t *sc)
+{
+ if (sc->sc_if.if_flags & IFF_UP) {
+ sc->sc_if.if_flags |= IFF_RUNNING;
+ if (sc->sc_if.if_flags & IFF_PROMISC) {
+ sc->sc_pdq->pdq_flags |= PDQ_PROMISC;
+ } else {
+ sc->sc_pdq->pdq_flags &= ~PDQ_PROMISC;
+ }
+ if (sc->sc_if.if_flags & IFF_ALLMULTI) {
+ sc->sc_pdq->pdq_flags |= PDQ_ALLMULTI;
+ } else {
+ sc->sc_pdq->pdq_flags &= ~PDQ_ALLMULTI;
+ }
+ if (sc->sc_if.if_flags & IFF_LINK1) {
+ sc->sc_pdq->pdq_flags |= PDQ_PASS_SMT;
+ } else {
+ sc->sc_pdq->pdq_flags &= ~PDQ_PASS_SMT;
+ }
+ sc->sc_pdq->pdq_flags |= PDQ_RUNNING;
+ pdq_run(sc->sc_pdq);
+ } else {
+ sc->sc_if.if_flags &= ~IFF_RUNNING;
+ sc->sc_pdq->pdq_flags &= ~PDQ_RUNNING;
+ pdq_stop(sc->sc_pdq);
+ }
+}
+\f
+void
+pdq_ifwatchdog(
+ pdq_softc_t *sc)
+{
+ struct mbuf *m;
+ /*
+ * No progress was made on the transmit queue for PDQ_OS_TX_TRANSMIT
+ * seconds. Remove all queued packets.
+ */
+
+ sc->sc_if.if_flags &= ~IFF_OACTIVE;
+ sc->sc_if.if_timer = 0;
+ for (;;) {
+ IF_DEQUEUE(&sc->sc_if.if_snd, m);
+ if (m == NULL)
+ return;
+ m_freem(m);
+ }
+}
+
+ifnet_ret_t
+pdq_ifstart(
+ struct ifnet *ifp)
+{
+ pdq_softc_t *sc = (pdq_softc_t *) ((caddr_t) ifp - offsetof(pdq_softc_t, sc_ac.ac_if));
+ struct ifqueue *ifq = &ifp->if_snd;
+ struct mbuf *m;
+ int tx = 0;
+
+ if ((ifp->if_flags & IFF_RUNNING) == 0)
+ return;
+
+ if (sc->sc_if.if_timer == 0)
+ sc->sc_if.if_timer = PDQ_OS_TX_TIMEOUT;
+
+ if ((sc->sc_pdq->pdq_flags & PDQ_TXOK) == 0) {
+ sc->sc_if.if_flags |= IFF_OACTIVE;
+ return;
+ }
+ for (;; tx = 1) {
+ IF_DEQUEUE(ifq, m);
+ if (m == NULL)
+ break;
+
+ if (pdq_queue_transmit_data(sc->sc_pdq, m) == PDQ_FALSE) {
+ ifp->if_flags |= IFF_OACTIVE;
+ IF_PREPEND(ifq, m);
+ break;
+ }
+ }
+ if (tx)
+ PDQ_DO_TYPE2_PRODUCER(sc->sc_pdq);
+}
+\f
+void
+pdq_os_receive_pdu(
+ pdq_t *pdq,
+ struct mbuf *m,
+ size_t pktlen)
+{
+ pdq_softc_t *sc = (pdq_softc_t *) pdq->pdq_os_ctx;
+ struct fddi_header *fh = mtod(m, struct fddi_header *);
+
+ sc->sc_if.if_ipackets++;
+#if NBPFILTER > 0
+ if (sc->sc_bpf != NULL)
+ bpf_mtap(sc->sc_bpf, m);
+ if ((fh->fddi_fc & (FDDIFC_L|FDDIFC_F)) != FDDIFC_LLC_ASYNC) {
+ m_freem(m);
+ return;
+ }
+#endif
+
+ m->m_data += sizeof(struct fddi_header);
+ m->m_len -= sizeof(struct fddi_header);
+ m->m_pkthdr.len = pktlen - sizeof(struct fddi_header);
+ m->m_pkthdr.rcvif = &sc->sc_if;
+ fddi_input(&sc->sc_if, fh, m);
+}
+
+void
+pdq_os_restart_transmitter(
+ pdq_t *pdq)
+{
+ pdq_softc_t *sc = (pdq_softc_t *) pdq->pdq_os_ctx;
+ sc->sc_if.if_flags &= ~IFF_OACTIVE;
+ if (sc->sc_if.if_snd.ifq_head != NULL) {
+ sc->sc_if.if_timer = PDQ_OS_TX_TIMEOUT;
+ pdq_ifstart(&sc->sc_if);
+ } else {
+ sc->sc_if.if_timer = 0;
+ }
+}
+
+void
+pdq_os_transmit_done(
+ pdq_t *pdq,
+ struct mbuf *m)
+{
+ pdq_softc_t *sc = (pdq_softc_t *) pdq->pdq_os_ctx;
+#if NBPFILTER > 0
+ if (sc->sc_bpf != NULL)
+ bpf_mtap(sc->sc_bpf, m);
+#endif
+ m_freem(m);
+ sc->sc_if.if_opackets++;
+}
+\f
+void
+pdq_os_addr_fill(
+ pdq_t *pdq,
+ pdq_lanaddr_t *addr,
+ size_t num_addrs)
+{
+ pdq_softc_t *sc = (pdq_softc_t *) pdq->pdq_os_ctx;
+ struct ether_multistep step;
+ struct ether_multi *enm;
+
+ ETHER_FIRST_MULTI(step, &sc->sc_ac, enm);
+ while (enm != NULL && num_addrs > 0) {
+ ((u_short *) addr->lanaddr_bytes)[0] = ((u_short *) enm->enm_addrlo)[0];
+ ((u_short *) addr->lanaddr_bytes)[1] = ((u_short *) enm->enm_addrlo)[1];
+ ((u_short *) addr->lanaddr_bytes)[2] = ((u_short *) enm->enm_addrlo)[2];
+ ETHER_NEXT_MULTI(step, enm);
+ addr++;
+ num_addrs--;
+ }
+}
+\f
+int
+pdq_ifioctl(
+ struct ifnet *ifp,
+ ioctl_cmd_t cmd,
+ caddr_t data)
+{
+ pdq_softc_t *sc = (pdq_softc_t *) ((caddr_t) ifp - offsetof(pdq_softc_t, sc_ac.ac_if));
+ int s, error = 0;
+
+ s = splimp();
+
+ switch (cmd) {
+ case SIOCSIFADDR: {
+ struct ifaddr *ifa = (struct ifaddr *)data;
+
+ ifp->if_flags |= IFF_UP;
+ switch(ifa->ifa_addr->sa_family) {
+#ifdef INET
+ case AF_INET: {
+ sc->sc_ac.ac_ipaddr = IA_SIN(ifa)->sin_addr;
+ pdq_ifinit(sc);
+#if !defined(__bsdi__)
+ arp_ifinit(&sc->sc_ac, ifa);
+#else
+ arpwhohas(&sc->sc_ac, &IA_SIN(ifa)->sin_addr);
+ ifa->ifa_rtrequest = arp_rtrequest;
+ ifa->ifa_flags |= RTF_CLONING;
+#endif
+ break;
+ }
+#endif /* INET */
+
+#ifdef NS
+ /* This magic copied from if_is.c; I don't use XNS,
+ * so I have no way of telling if this actually
+ * works or not.
+ */
+ case AF_NS: {
+ struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
+ if (ns_nullhost(*ina)) {
+ ina->x_host = *(union ns_host *)(sc->sc_ac.ac_enaddr);
+ } else {
+ ifp->if_flags &= ~IFF_RUNNING;
+ bcopy((caddr_t)ina->x_host.c_host,
+ (caddr_t)sc->sc_ac.ac_enaddr,
+ sizeof sc->sc_ac.ac_enaddr);
+ }
+
+ pdq_ifinit(sc);
+ break;
+ }
+#endif /* NS */
+
+ default: {
+ pdq_ifinit(sc);
+ break;
+ }
+ }
+ break;
+ }
+
+ case SIOCSIFFLAGS: {
+ pdq_ifinit(sc);
+ break;
+ }
+
+ case SIOCADDMULTI:
+ case SIOCDELMULTI: {
+ /*
+ * Update multicast listeners
+ */
+ if (cmd == SIOCADDMULTI)
+ error = ether_addmulti((struct ifreq *)data, &sc->sc_ac);
+ else
+ error = ether_delmulti((struct ifreq *)data, &sc->sc_ac);
+
+ if (error == ENETRESET) {
+ if (sc->sc_if.if_flags & IFF_RUNNING)
+ pdq_run(sc->sc_pdq);
+ error = 0;
+ }
+ break;
+ }
+
+ default: {
+ error = EINVAL;
+ break;
+ }
+ }
+
+ splx(s);
+ return error;
+}
+\f
+void
+pdq_ifattach(
+ pdq_softc_t *sc,
+ ifnet_ret_t (*ifinit)(int unit),
+ ifnet_ret_t (*ifwatchdog)(int unit))
+{
+ struct ifnet *ifp = &sc->sc_if;
+
+ ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
+
+#if !defined(__NetBSD__)
+ ifp->if_init = ifinit;
+#endif
+ ifp->if_watchdog = ifwatchdog;
+
+ ifp->if_ioctl = pdq_ifioctl;
+ ifp->if_output = fddi_output;
+ ifp->if_start = pdq_ifstart;
+
+ if_attach(ifp);
+ fddi_ifattach(ifp);
+#if NBPFILTER > 0
+ bpfattach(&sc->sc_bpf, ifp, DLT_FDDI, sizeof(struct fddi_header));
+#endif
+}
-/* $NetBSD: pdqreg.h,v 1.2 1995/08/19 04:35:21 cgd Exp $ */
+/* $OpenBSD: pdqreg.h,v 1.2 1996/04/18 23:47:24 niklas Exp $ */
+/* $NetBSD: pdqreg.h,v 1.3 1996/03/11 21:41:33 thorpej Exp $ */
/*-
* Copyright (c) 1995 Matt Thomas (thomas@lkg.dec.com)
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Id: pdqreg.h,v 1.6 1995/06/03 15:43:26 thomas Exp
+ *
+ * Log: pdqreg.h,v
+ * Revision 1.6 1995/06/03 15:43:26 thomas
+ * Fix the command submission logic to only submit one
+ * command at a time no matter what. This simplies the
+ * code significantly thereby allowing us to do some up
+ * front optimizations.
+ *
+ * Revision 1.5 1995/03/10 17:41:55 thomas
+ * Add DEFTA, DEFQA, and DEFAA
+ *
+ * Revision 1.4 1995/03/06 17:07:05 thomas
+ * Add copyright/disclaimer
+ * Add EISA register definitions
+ *
+ * Revision 1.3 1995/03/03 13:48:35 thomas
+ * more fixes
+ *
+ *
*/
/*
* DEC PDQ FDDI Controller; PDQ port driver definitions
*
* Written by Matt Thomas
+ *
*/
#ifndef _PDQREG_H
-/* $NetBSD: pdqvar.h,v 1.2 1995/08/19 04:35:22 cgd Exp $ */
+/* $OpenBSD: pdqvar.h,v 1.2 1996/04/18 23:47:25 niklas Exp $ */
+/* $NetBSD: pdqvar.h,v 1.4 1996/03/11 21:41:35 thorpej Exp $ */
/*-
* Copyright (c) 1995 Matt Thomas (thomas@lkg.dec.com)
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from Id: pdq_os.h,v 1.11 1995/08/20 18:59:00 thomas Exp
+ *
+ * Log: pdq_os.h,v
+ * Revision 1.11 1995/08/20 18:59:00 thomas
+ * Changes for NetBSD
+ *
+ * Revision 1.10 1995/08/16 22:57:28 thomas
+ * Add support for NetBSD
+ *
+ * Revision 1.9 1995/06/21 18:29:27 thomas
+ * SVR4.2 changes
+ *
+ * Revision 1.8 1995/06/12 17:49:37 thomas
+ * Add SVR4.2 support
+ *
+ * Revision 1.7 1995/04/20 20:17:33 thomas
+ * Add PCI support for BSD/OS.
+ * Fix BSD/OS EISA support.
+ * Set latency timer for DEFPA to recommended value if 0.
+ *
+ * Revision 1.6 1995/03/14 01:52:52 thomas
+ * Update for new FreeBSD PCI Interrupt interface
+ * Use inl/inb/... inline macros provided by FreeBSD and BSDI
+ *
+ * Revision 1.5 1995/03/10 17:42:24 thomas
+ * More changes for BSDI
+ *
+ * Revision 1.4 1995/03/06 17:08:56 thomas
+ * Add copyright/disclaimer
+ * Add inx/outx macros
+ *
+ * Revision 1.3 1995/03/03 13:48:35 thomas
+ * more fixes
+ *
+ *
*/
/*
* DEC PDQ FDDI Controller; PDQ O/S dependent definitions
*
* Written by Matt Thomas
+ *
*/
#ifndef _PDQ_OS_H
#define PDQ_OS_MEMFREE_CONTIG(p, n) kmem_free(kernel_map, (vm_offset_t) p, n)
#endif /* __FreeBSD__ */
-#if !defined(PDQ_HWSUPPORT)
#if defined(__FreeBSD__)
#include <machine/cpufunc.h>
+#include <machine/clock.h>
typedef void ifnet_ret_t;
typedef int ioctl_cmd_t;
#elif defined(__bsdi__)
typedef void ifnet_ret_t;
typedef u_long ioctl_cmd_t;
#endif
+
+#if !defined(PDQ_HWSUPPORT)
#define PDQ_OS_IORD_32(port) inl(port)
#define PDQ_OS_IOWR_32(port, data) outl(port, data)
#define PDQ_OS_IORD_8(port) inb(port)
#ifdef __bsdi__
struct device sc_dev; /* base device */
struct isadev sc_id; /* ISA device */
- struct intrhand sc_ih; /* intrrupt vectoring */
+ struct intrhand sc_ih; /* interrupt vectoring */
struct atshutdown sc_ats; /* shutdown routine */
#elif defined(__NetBSD__)
struct device sc_dev; /* base device */
- void *sc_ih; /* intrrupt vectoring */
+ void *sc_ih; /* interrupt vectoring */
void *sc_ats; /* shutdown hook */
#endif
struct arpcom sc_ac;
extern int pdq_interrupt(pdq_t *pdq);
extern pdq_t *pdq_initialize(void *csr_va, const char *name, int unit, void *ctx, pdq_type_t type);
+
#endif /* _PDQ_OS_H */
+/* $OpenBSD: z8530tty.c,v 1.2 1996/04/18 23:47:26 niklas Exp $ */
/* $NetBSD: z8530tty.c,v 1.1 1996/01/24 01:07:25 gwr Exp $ */
/*
dev_t dev;
cf = zst->zst_dev.dv_cfdata;
- tty_unit = cf->cf_unit;
+ tty_unit = zst->zst_dev.dv_unit;
channel = args->channel;
cs = &zsc->zsc_cs[channel];
cs->cs_private = zst;
tp->t_dev = dev;
tp->t_oproc = zsstart;
tp->t_param = zsparam;
- tp->t_sc = zst; /* XXX - Quick access! */
/*
* Hardware init
register struct zs_chanstate *cs;
register int s, nch;
- zst = tp->t_sc;
+ zst = zsttycd.cd_devs[minor(tp->t_dev)];
cs = zst->zst_cs;
s = spltty();
register struct zs_chanstate *cs;
register int s;
- zst = tp->t_sc;
+ zst = zsttycd.cd_devs[minor(tp->t_dev)];
cs = zst->zst_cs;
s = splzs();
register int s, bps, cflag, tconst;
u_char tmp3, tmp4, tmp5, reset;
- zst = tp->t_sc;
+ zst = zsttycd.cd_devs[minor(tp->t_dev)];
cs = zst->zst_cs;
/*
* Interface to the lower layer (zscc)
****************************************************************/
+/*
+ * XXX: need to do input flow-control to avoid ring overrun.
+ */
+
static int
zstty_rxint(cs)
register struct zs_chanstate *cs;
zstty_txint, /* xmit buffer empty */
zstty_softint, /* process software interrupt */
};
-
-/* $OpenBSD: ad1848.c,v 1.3 1996/03/08 16:42:45 niklas Exp $ */
-/* $NetBSD: ad1848.c,v 1.8 1996/02/05 21:32:26 scottr Exp $ */
+/* $OpenBSD: ad1848.c,v 1.4 1996/04/18 23:47:28 niklas Exp $ */
+/* $NetBSD: ad1848.c,v 1.9 1996/03/01 04:08:24 mycroft Exp $ */
/*
* Copyright (c) 1994 John Brezak
* it is needed (and you pay the latency). Also, you might
* never need the buffer anyway.)
*/
- isa_dmastart(B_READ, &dmabuf, 1, sc->sc_drq);
+ isa_dmastart(DMAMODE_READ, &dmabuf, 1, sc->sc_drq);
ad_write(sc, SP_LOWER_BASE_COUNT, 0);
ad_write(sc, SP_UPPER_BASE_COUNT, 0);
sc->sc_locked = 1;
sc->sc_intr = intr;
sc->sc_arg = arg;
- sc->sc_dma_flags = B_READ;
+ sc->sc_dma_flags = DMAMODE_READ;
sc->sc_dma_bp = p;
sc->sc_dma_cnt = cc;
- isa_dmastart(B_READ, p, cc, sc->sc_recdrq);
+ isa_dmastart(DMAMODE_READ, p, cc, sc->sc_recdrq);
if (sc->precision == 16)
cc >>= 1;
sc->sc_locked = 1;
sc->sc_intr = intr;
sc->sc_arg = arg;
- sc->sc_dma_flags = B_WRITE;
+ sc->sc_dma_flags = DMAMODE_WRITE;
sc->sc_dma_bp = p;
sc->sc_dma_cnt = cc;
- isa_dmastart(B_WRITE, p, cc, sc->sc_drq);
+ isa_dmastart(DMAMODE_WRITE, p, cc, sc->sc_drq);
if (sc->precision == 16)
cc >>= 1;
if (sc->sc_intr && (status & INTERRUPT_STATUS)) {
/* ACK DMA read because it may be in a bounce buffer */
/* XXX Do write to mask DMA ? */
- if (sc->sc_dma_flags & B_READ)
+ if (sc->sc_dma_flags & DMAMODE_READ)
isa_dmadone(sc->sc_dma_flags, sc->sc_dma_bp, sc->sc_dma_cnt - 1, sc->sc_recdrq);
(*sc->sc_intr)(sc->sc_arg);
retval = 1;
-/* $OpenBSD: ast.c,v 1.6 1996/03/20 01:00:39 mickey Exp $ */
-/* $NetBSD: ast.c,v 1.18 1995/06/26 04:08:04 cgd Exp $ */
+/* $OpenBSD: ast.c,v 1.7 1996/04/18 23:47:29 niklas Exp $ */
+/* $NetBSD: ast.c,v 1.22 1996/03/10 09:01:20 cgd Exp $ */
/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1995 Charles Hannum. All rights reserved.
*
* This code is derived from public-domain software written by
#include <sys/param.h>
#include <sys/device.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
+#include <dev/isa/comreg.h>
+#include <dev/isa/comvar.h>
+
+#define NSLAVES 4
struct ast_softc {
struct device sc_dev;
void *sc_ih;
+ bus_chipset_tag_t sc_bc;
int sc_iobase;
- int sc_alive; /* mask of slave units attached */
- void *sc_slaves[4]; /* com device unit numbers */
+
+ int sc_alive; /* mask of slave units attached */
+ void *sc_slaves[NSLAVES]; /* com device unit numbers */
+ bus_io_handle_t sc_slaveioh[NSLAVES];
};
int astprobe();
void *aux;
{
struct isa_attach_args *ia = aux;
+ int iobase = ia->ia_iobase;
+ bus_chipset_tag_t bc = ia->ia_bc;
+ bus_io_handle_t ioh;
+ int i, rv = 1;
/*
* Do the normal com probe for the first UART and assume
- * its presence means there is a multiport board there.
+ * its presence, and the ability to map the other UARTS,
+ * means there is a multiport board there.
* XXX Needs more robustness.
*/
- ia->ia_iosize = 4 * 8;
- return (comprobe1(ia->ia_iobase));
-}
-struct ast_attach_args {
- int aa_slave;
-};
+ /* if the first port is in use as console, then it. */
+ if (iobase == comconsaddr && !comconsattached)
+ goto checkmappings;
-int
-astsubmatch(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- struct ast_softc *sc = (void *)parent;
- struct cfdata *cf = match;
- struct isa_attach_args *ia = aux;
- struct ast_attach_args *aa = ia->ia_aux;
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ rv = comprobe1(bc, ioh, iobase);
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ if (rv == 0)
+ goto out;
- if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != aa->aa_slave)
- return (0);
- return ((*cf->cf_driver->cd_match)(parent, match, ia));
+checkmappings:
+ for (i = 1; i < NSLAVES; i++) {
+ iobase += COM_NPORTS;
+
+ if (iobase == comconsaddr && !comconsattached)
+ continue;
+
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ }
+
+out:
+ if (rv)
+ ia->ia_iosize = NSLAVES * COM_NPORTS;
+ return (rv);
}
int
-astprint(aux, ast)
+astprint(aux, pnp)
void *aux;
- char *ast;
+ char *pnp;
{
- struct isa_attach_args *ia = aux;
- struct ast_attach_args *aa = ia->ia_aux;
+ struct commulti_attach_args *ca = aux;
- printf(" slave %d", aa->aa_slave);
+ if (pnp)
+ printf("com at %s", pnp);
+ printf(" slave %d", ca->ca_slave);
+ return (UNCONF);
}
void
{
struct ast_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- struct ast_attach_args aa;
- struct isa_attach_args isa;
- int subunit;
+ struct commulti_attach_args ca;
+ int i, subunit;
+ sc->sc_bc = ia->ia_bc;
sc->sc_iobase = ia->ia_iobase;
+ for (i = 0; i < NSLAVES; i++)
+ if (bus_io_map(bc, sc->sc_iobase + i * COM_NPORTS, COM_NPORTS,
+ &sc->sc_slaveioh[i]))
+ panic("astattach: couldn't map slave %d", i);
+
/*
* Enable the master interrupt.
*/
- outb(sc->sc_iobase | 0x1f, 0x80);
+ bus_io_write_1(bc, sc->sc_slaveioh[3], 7, 0x80);
printf("\n");
- isa.ia_aux = &aa;
- for (aa.aa_slave = 0; aa.aa_slave < 4; aa.aa_slave++) {
- struct cfdata *cf;
- isa.ia_iobase = sc->sc_iobase + 8 * aa.aa_slave;
- isa.ia_iosize = 0x666;
- isa.ia_irq = IRQUNK;
- isa.ia_drq = DRQUNK;
- isa.ia_msize = 0;
- if ((cf = config_search(astsubmatch, self, &isa)) != 0) {
- subunit = cf->cf_unit; /* can change if unit == * */
- config_attach(self, cf, &isa, astprint);
- sc->sc_slaves[aa.aa_slave] =
- cf->cf_driver->cd_devs[subunit];
- sc->sc_alive |= 1 << aa.aa_slave;
+ for (i = 0; i < NSLAVES; i++) {
+ struct cfdata *match;
+
+ ca.ca_slave = i;
+ ca.ca_bc = sc->sc_bc;
+ ca.ca_ioh = sc->sc_slaveioh[i];
+ ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
+ ca.ca_noien = 1;
+
+ /* mimic config_found(), but with special functionality */
+ if ((match = config_search(NULL, self, &ca)) != NULL) {
+ subunit = match->cf_unit; /* can change if unit == * */
+ config_attach(self, match, &ca, astprint);
+ sc->sc_slaves[i] = match->cf_driver->cd_devs[subunit];
+ sc->sc_alive |= 1 << i;
+ } else {
+ astprint(&ca, self->dv_xname);
+ printf(" not configured\n");
}
}
void *arg;
{
struct ast_softc *sc = arg;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
int alive = sc->sc_alive;
int bits;
- bits = ~inb(iobase | 0x1f) & alive;
+ bits = ~bus_io_read_1(bc, sc->sc_slaveioh[3], 7) & alive;
if (bits == 0)
return (0);
TRY(2);
TRY(3);
#undef TRY
- bits = ~inb(iobase | 0x1f) & alive;
+ bits = ~bus_io_read_1(bc, sc->sc_slaveioh[3], 7) & alive;
if (bits == 0)
return (1);
}
-/* $OpenBSD: boca.c,v 1.6 1996/03/20 01:00:40 mickey Exp $ */
-/* $NetBSD: boca.c,v 1.6 1995/12/24 02:31:11 mycroft Exp $ */
+/* $OpenBSD: boca.c,v 1.7 1996/04/18 23:47:30 niklas Exp $ */
+/* $NetBSD: boca.c,v 1.9 1996/03/10 09:01:22 cgd Exp $ */
/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1995 Charles Hannum. All rights reserved.
*
* This code is derived from public-domain software written by
#include <sys/param.h>
#include <sys/device.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
+#include <dev/isa/comreg.h>
+#include <dev/isa/comvar.h>
+
+#define NSLAVES 8
struct boca_softc {
struct device sc_dev;
void *sc_ih;
+ bus_chipset_tag_t sc_bc;
int sc_iobase;
- int sc_alive; /* mask of slave units attached */
- void *sc_slaves[8]; /* com device unit numbers */
+
+ int sc_alive; /* mask of slave units attached */
+ void *sc_slaves[NSLAVES]; /* com device unit numbers */
+ bus_io_handle_t sc_slaveioh[NSLAVES];
};
int bocaprobe();
void *aux;
{
struct isa_attach_args *ia = aux;
+ int iobase = ia->ia_iobase;
+ bus_chipset_tag_t bc = ia->ia_bc;
+ bus_io_handle_t ioh;
+ int i, rv = 1;
/*
* Do the normal com probe for the first UART and assume
- * its presence means there is a multiport board there.
+ * its presence, and the ability to map the other UARTS,
+ * means there is a multiport board there.
* XXX Needs more robustness.
*/
- ia->ia_iosize = 8 * 8;
- return (comprobe1(ia->ia_iobase));
-}
-struct boca_attach_args {
- int ba_slave;
-};
+ /* if the first port is in use as console, then it. */
+ if (iobase == comconsaddr && !comconsattached)
+ goto checkmappings;
-int
-bocasubmatch(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- struct boca_softc *sc = (void *)parent;
- struct cfdata *cf = match;
- struct isa_attach_args *ia = aux;
- struct boca_attach_args *ba = ia->ia_aux;
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ rv = comprobe1(bc, ioh, iobase);
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ if (rv == 0)
+ goto out;
- if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ba->ba_slave)
- return (0);
- return ((*cf->cf_driver->cd_match)(parent, match, ia));
+checkmappings:
+ for (i = 1; i < NSLAVES; i++) {
+ iobase += COM_NPORTS;
+
+ if (iobase == comconsaddr && !comconsattached)
+ continue;
+
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ }
+
+out:
+ if (rv)
+ ia->ia_iosize = NSLAVES * COM_NPORTS;
+ return (rv);
}
int
-bocaprint(aux, boca)
+bocaprint(aux, pnp)
void *aux;
- char *boca;
+ char *pnp;
{
- struct isa_attach_args *ia = aux;
- struct boca_attach_args *ba = ia->ia_aux;
+ struct commulti_attach_args *ca = aux;
- printf(" slave %d", ba->ba_slave);
+ if (pnp)
+ printf("com at %s", pnp);
+ printf(" slave %d", ca->ca_slave);
+ return (UNCONF);
}
void
{
struct boca_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- struct boca_attach_args ba;
- struct isa_attach_args isa;
- int subunit;
+ struct commulti_attach_args ca;
+ int i, subunit;
+ sc->sc_bc = ia->ia_bc;
sc->sc_iobase = ia->ia_iobase;
+ for (i = 0; i < NSLAVES; i++)
+ if (bus_io_map(bc, sc->sc_iobase + i * COM_NPORTS, COM_NPORTS,
+ &sc->sc_slaveioh[i]))
+ panic("bocaattach: couldn't map slave %d", i);
+
printf("\n");
- isa.ia_aux = &ba;
- for (ba.ba_slave = 0; ba.ba_slave < 8; ba.ba_slave++) {
- struct cfdata *cf;
- isa.ia_iobase = sc->sc_iobase + 8 * ba.ba_slave;
- isa.ia_iosize = 0x666;
- isa.ia_irq = IRQUNK;
- isa.ia_drq = DRQUNK;
- isa.ia_msize = 0;
- if ((cf = config_search(bocasubmatch, self, &isa)) != 0) {
- subunit = cf->cf_unit; /* can change if unit == * */
- config_attach(self, cf, &isa, bocaprint);
- sc->sc_slaves[ba.ba_slave] =
- cf->cf_driver->cd_devs[subunit];
- sc->sc_alive |= 1 << ba.ba_slave;
+ for (i = 0; i < NSLAVES; i++) {
+ struct cfdata *match;
+
+ ca.ca_slave = i;
+ ca.ca_bc = sc->sc_bc;
+ ca.ca_ioh = sc->sc_slaveioh[i];
+ ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
+ ca.ca_noien = 0;
+
+ /* mimic config_found(), but with special functionality */
+ if ((match = config_search(NULL, self, &ca)) != NULL) {
+ subunit = match->cf_unit; /* can change if unit == * */
+ config_attach(self, match, &ca, bocaprint);
+ sc->sc_slaves[i] = match->cf_driver->cd_devs[subunit];
+ sc->sc_alive |= 1 << i;
+ } else {
+ bocaprint(&ca, self->dv_xname);
+ printf(" not configured\n");
}
}
void *arg;
{
struct boca_softc *sc = arg;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
int alive = sc->sc_alive;
int bits;
- bits = inb(iobase | 0x07) & alive;
+ bits = bus_io_read_1(bc, sc->sc_slaveioh[0], 7) & alive;
if (bits == 0)
return (0);
TRY(6);
TRY(7);
#undef TRY
- bits = inb(iobase | 0x07) & alive;
+ bits = bus_io_read_1(bc, sc->sc_slaveioh[0], 7) & alive;
if (bits == 0)
return (1);
}
-/* $OpenBSD: bt.c,v 1.6 1996/03/20 01:00:41 mickey Exp $ */
-/* $NetBSD: bt742a.c,v 1.50 1995/12/24 02:31:13 mycroft Exp $ */
+/* $OpenBSD: bt.c,v 1.7 1996/04/18 23:47:31 niklas Exp $ */
+/* $NetBSD: bt742a.c,v 1.55 1996/03/16 05:33:28 cgd Exp $ */
/*
* Copyright (c) 1994 Charles Hannum. All rights reserved.
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
+/*
+ * Note that stdarg.h and the ANSI style va_start macro is used for both
+ * ANSI and traditional C compilers.
+ */
+#include <machine/stdarg.h>
+
#ifndef DDB
#define Debugger() panic("should call debugger here (bt742a.c)")
#endif /* ! DDB */
/*
* I/O Port Interface
*/
-#define BT_BASE bt->sc_iobase
-#define BT_CTRL_STAT_PORT (BT_BASE + 0x0) /* control & status */
-#define BT_CMD_DATA_PORT (BT_BASE + 0x1) /* cmds and datas */
-#define BT_INTR_PORT (BT_BASE + 0x2) /* Intr. stat */
+#define BT_CTRL_STAT_PORT 0x0 /* control & status */
+#define BT_CMD_DATA_PORT 0x1 /* cmds and datas */
+#define BT_INTR_PORT 0x2 /* Intr. stat */
/*
* BT_CTRL_STAT bits (write)
#define BT_READ_FIFO 0x1d /* read fifo buffer */
#define BT_ECHO 0x1e /* Echo command data */
#define BT_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */
-#define BT_INQUIRE_EXTENDED 0x8D /* Adapter Setup Inquiry */
+#define BT_INQUIRE_REV_THIRD 0x84 /* Get 3rd firmware version byte */
+#define BT_INQUIRE_REV_FOURTH 0x85 /* Get 4th firmware version byte */
+#define BT_GET_BOARD_INFO 0x8b /* Get hardware ID and revision */
+#define BT_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */
-/* Follows command appeared at FirmWare 3.31 */
+/* Follows command appeared at firmware 3.31 */
#define BT_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */
#define BT_DISABLE 0x00 /* Parameter value for Disable */
#define BT_ENABLE 0x01 /* Parameter value for Enable */
u_char firm_version;
};
+struct bt_board_info {
+ u_char id[4]; /* i.e bt742a -> '7','4','2','A' */
+ u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */
+};
+
struct bt_setup {
u_char sync_neg:1;
u_char parity:1;
#define KVTOPHYS(x) vtophys(x)
struct bt_softc {
- struct device sc_dev;
- struct isadev sc_id;
- void *sc_ih;
+ struct device sc_dev;
+ struct isadev sc_id;
+ void *sc_ih;
int sc_iobase;
- int sc_irq, bt_drq;
+ int sc_irq, sc_drq;
- struct bt_mbx bt_mbx; /* all our mailboxes */
- struct bt_ccb *ccbhash[CCB_HASH_SIZE];
- TAILQ_HEAD(, bt_ccb) free_ccb;
- int numccbs;
- int bt_scsi_dev; /* adapters scsi id */
+ struct bt_mbx sc_mbx; /* all our mailboxes */
+ struct bt_ccb *sc_ccbhash[CCB_HASH_SIZE];
+ TAILQ_HEAD(, bt_ccb) sc_free_ccb;
+ int sc_numccbs;
+ int sc_scsi_dev; /* adapters scsi id */
struct scsi_link sc_link; /* prototype for devs */
};
#define BT_SHOWMISC 0x08
int bt_debug = 0;
-int bt_cmd(); /* XXX must be varargs to prototype */
+int bt_cmd __P((int, struct bt_softc *, int, int, int, u_char *,
+ unsigned, ...));
int btintr __P((void *));
void bt_free_ccb __P((struct bt_softc *, struct bt_ccb *, int));
struct bt_ccb *bt_get_ccb __P((struct bt_softc *, int));
struct bt_ccb *bt_ccb_phys_kv __P((struct bt_softc *, u_long));
struct bt_mbx_out *bt_send_mbo __P((struct bt_softc *, int, struct bt_ccb *));
void bt_done __P((struct bt_softc *, struct bt_ccb *));
-int bt_find __P((struct bt_softc *));
+int bt_find __P((struct isa_attach_args *, struct bt_softc *));
void bt_init __P((struct bt_softc *));
void bt_inquire_setup_information __P((struct bt_softc *));
void btminphys __P((struct buf *));
#define BT_RESET_TIMEOUT 1000
/*
- * bt_cmd(bt, icnt, ocnt,wait, retval, opcode, args)
+ * bt_cmd(iobase, sc, icnt, ocnt, wait, retval, opcode, ... args ...)
*
* Activate Adapter command
* icnt: number of args (outbound bytes written after opcode)
* wait: number of seconds to wait for response
* retval: buffer where to place returned bytes
* opcode: opcode BT_NOP, BT_MBX_INIT, BT_START_SCSI ...
- * args: parameters
+ * args: variable number of parameters
*
* Performs an adapter command through the ports. Not to be confused with a
* scsi command, which is read in via the dma; one of the adapter commands
* tells it to read in a scsi command.
*/
int
-bt_cmd(bt, icnt, ocnt, wait, retval, opcode, args)
- struct bt_softc *bt;
+#ifdef __STDC__
+bt_cmd(int iobase, struct bt_softc *sc, int icnt, int ocnt, int wait,
+ u_char *retval, unsigned opcode, ...)
+#else
+bt_cmd(iobase, sc, icnt, ocnt, wait, retval, opcode, va_alist)
+ int iobase;
+ struct bt_softc *sc;
int icnt, ocnt, wait;
u_char *retval;
unsigned opcode;
- u_char args;
+ va_dcl
+#endif
{
- unsigned *ic = &opcode;
+ va_list ap;
+ unsigned data;
+ const char *name;
u_char oc;
register i;
int sts;
+ if (sc == NULL)
+ name = sc->sc_dev.dv_xname;
+ else
+ name = "(probe)";
+
/*
* multiply the wait argument by a big constant
* zero defaults to 1
if (opcode != BT_MBX_INIT && opcode != BT_START_SCSI) {
i = 100000; /* 1 sec? */
while (--i) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (sts & BT_IDLE) {
break;
}
}
if (!i) {
printf("%s: bt_cmd, host not idle(0x%x)\n",
- bt->sc_dev.dv_xname, sts);
+ name, sts);
return ENXIO;
}
}
* queue feeding to us.
*/
if (ocnt) {
- while ((inb(BT_CTRL_STAT_PORT)) & BT_DF)
- inb(BT_CMD_DATA_PORT);
+ while ((inb(iobase + BT_CTRL_STAT_PORT)) & BT_DF)
+ inb(iobase + BT_CMD_DATA_PORT);
}
/*
* Output the command and the number of arguments given
* for each byte, first check the port is empty.
*/
- icnt++;
- /* include the command */
- while (icnt--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ va_start(ap, opcode);
+ /* test icnt >= 0, to include the command in data sent */
+ for (data = opcode; icnt >= 0; icnt--, data = va_arg(ap, u_char)) {
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
for (i = wait; i; i--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (!(sts & BT_CDF))
break;
delay(10);
}
if (!i) {
- printf("%s: bt_cmd, cmd/data port full\n",
- bt->sc_dev.dv_xname);
- outb(BT_CTRL_STAT_PORT, BT_SRST);
+ printf("%s: bt_cmd, cmd/data port full\n", name);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_SRST);
+ va_end(ap);
return ENXIO;
}
- outb(BT_CMD_DATA_PORT, (u_char) (*ic++));
+ outb(iobase + BT_CMD_DATA_PORT, data);
}
+ va_end(ap);
/*
* If we expect input, loop that many times, each time,
* looking for the data register to have valid data
*/
while (ocnt--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
for (i = wait; i; i--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (sts & BT_DF)
break;
delay(10);
}
if (!i) {
printf("bt%d: bt_cmd, cmd/data port empty %d\n",
- bt->sc_dev.dv_xname, ocnt);
+ name, ocnt);
return ENXIO;
}
- oc = inb(BT_CMD_DATA_PORT);
+ oc = inb(iobase + BT_CMD_DATA_PORT);
if (retval)
*retval++ = oc;
}
*/
i = 100000; /* 1 sec? */
while (--i) {
- sts = inb(BT_INTR_PORT);
+ sts = inb(iobase + BT_INTR_PORT);
if (sts & BT_HACC)
break;
delay(10);
}
if (!i) {
printf("%s: bt_cmd, host not finished(0x%x)\n",
- bt->sc_dev.dv_xname, sts);
+ name, sts);
return ENXIO;
}
- outb(BT_CTRL_STAT_PORT, BT_IRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_IRST);
return 0;
}
*/
int
btprobe(parent, match, aux)
- struct device *parent;
- void *match, *aux;
+ struct device *parent;
+ void *match, *aux;
{
- struct bt_softc *bt = match;
- register struct isa_attach_args *ia = aux;
+ struct bt_softc *sc = match;
+ register struct isa_attach_args *ia = aux;
#ifdef NEWCONFIG
- if (ia->ia_iobase == IOBASEUNK)
- return 0;
+ if (ia->ia_iobase == IOBASEUNK)
+ return 0;
#endif
- bt->sc_iobase = ia->ia_iobase;
-
/*
* Try initialise a unit at this location
- * sets up dma and bus speed, loads bt->sc_irq
+ * sets up dma and bus speed, loads sc->sc_irq
*/
- if (bt_find(bt) != 0)
+ if (bt_find(ia, NULL) != 0)
return 0;
- if (ia->ia_irq != IRQUNK) {
- if (ia->ia_irq != bt->sc_irq) {
- printf("%s: irq mismatch; kernel configured %d != board configured %d\n",
- bt->sc_dev.dv_xname, ia->ia_irq, bt->sc_irq);
- return 0;
- }
- } else
- ia->ia_irq = bt->sc_irq;
-
- if (ia->ia_drq != DRQUNK) {
- if (ia->ia_drq != bt->bt_drq) {
- printf("%s: drq mismatch; kernel configured %d != board configured %d\n",
- bt->sc_dev.dv_xname, ia->ia_drq, bt->bt_drq);
- return 0;
- }
- } else
- ia->ia_drq = bt->bt_drq;
-
ia->ia_msize = 0;
ia->ia_iosize = 4;
+ /* IRQ and DRQ set by bt_find() */
return 1;
}
void *aux;
char *name;
{
- if (name != NULL)
+ if (name != NULL)
printf("%s: scsibus ", name);
return UNCONF;
}
*/
void
btattach(parent, self, aux)
- struct device *parent, *self;
- void *aux;
+ struct device *parent, *self;
+ void *aux;
{
- struct isa_attach_args *ia = aux;
- struct bt_softc *bt = (void *)self;
+ struct isa_attach_args *ia = aux;
+ struct bt_softc *sc = (struct bt_softc *)self;
- if (ia->ia_drq != DRQUNK)
- isa_dmacascade(ia->ia_drq);
+ if (bt_find(ia, sc) != 0)
+ panic("btattach: bt_find of %s failed", self->dv_xname);
+ sc->sc_iobase = ia->ia_iobase;
- bt_init(bt);
- TAILQ_INIT(&bt->free_ccb);
+ if (sc->sc_drq != DRQUNK)
+ isa_dmacascade(sc->sc_drq);
+
+ bt_init(sc);
+ TAILQ_INIT(&sc->sc_free_ccb);
/*
* fill in the prototype scsi_link.
*/
- bt->sc_link.adapter_softc = bt;
- bt->sc_link.adapter_target = bt->bt_scsi_dev;
- bt->sc_link.adapter = &bt_switch;
- bt->sc_link.device = &bt_dev;
- bt->sc_link.openings = 2;
+ sc->sc_link.adapter_softc = sc;
+ sc->sc_link.adapter_target = sc->sc_scsi_dev;
+ sc->sc_link.adapter = &bt_switch;
+ sc->sc_link.device = &bt_dev;
+ sc->sc_link.openings = 2;
printf("\n");
#ifdef NEWCONFIG
- isa_establish(&bt->sc_id, &bt->sc_dev);
+ isa_establish(&sc->sc_id, &sc->sc_dev);
#endif
- bt->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_BIO, btintr,
- bt, bt->sc_dev.dv_xname);
+ sc->sc_ih = isa_intr_establish(sc->sc_irq, IST_EDGE, IPL_BIO, btintr,
+ sc, sc->sc_dev.dv_xname);
/*
* ask the adapter what subunits are present
*/
- config_found(self, &bt->sc_link, btprint);
+ config_found(self, &sc->sc_link, btprint);
}
/*
btintr(arg)
void *arg;
{
- struct bt_softc *bt = arg;
+ struct bt_softc *sc = arg;
+ int iobase = sc->sc_iobase;
struct bt_mbx_in *wmbi;
struct bt_mbx *wmbx;
struct bt_ccb *ccb;
int found = 0;
#ifdef BTDEBUG
- printf("%s: btintr ", bt->sc_dev.dv_xname);
+ printf("%s: btintr ", sc->sc_dev.dv_xname);
#endif /* BTDEBUG */
/*
* not telling about a completed operation
* just return.
*/
- stat = inb(BT_INTR_PORT);
+ stat = inb(iobase + BT_INTR_PORT);
if ((stat & (BT_MBOA | BT_MBIF)) == 0) {
- outb(BT_CTRL_STAT_PORT, BT_IRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_IRST);
return -1; /* XXX */
}
/* Mail box out empty? */
if (stat & BT_MBOA) {
/* Disable MBO available interrupt. */
- outb(BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
+ outb(iobase + BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
for (i = 100000; i; i--) {
- if (!(inb(BT_CTRL_STAT_PORT) & BT_CDF))
+ if (!(inb(iobase + BT_CTRL_STAT_PORT) & BT_CDF))
break;
delay(10);
}
if (!i) {
printf("%s: btintr, cmd/data port full\n",
- bt->sc_dev.dv_xname);
- outb(BT_CTRL_STAT_PORT, BT_SRST);
+ sc->sc_dev.dv_xname);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_SRST);
return 1;
}
- outb(BT_CMD_DATA_PORT, 0x00); /* Disable */
- wakeup(&bt->bt_mbx);
+ outb(iobase + BT_CMD_DATA_PORT, 0x00); /* Disable */
+ wakeup(&sc->sc_mbx);
}
/* Mail box in full? */
if ((stat & BT_MBIF) == 0)
return 1;
- wmbx = &bt->bt_mbx;
+ wmbx = &sc->sc_mbx;
wmbi = wmbx->tmbi;
AGAIN:
while (wmbi->stat != BT_MBI_FREE) {
- ccb = bt_ccb_phys_kv(bt, wmbi->ccb_addr);
+ ccb = bt_ccb_phys_kv(sc, wmbi->ccb_addr);
if (!ccb) {
wmbi->stat = BT_MBI_FREE;
- printf("%s: BAD CCB ADDR!\n", bt->sc_dev.dv_xname);
+ printf("%s: BAD CCB ADDR!\n", sc->sc_dev.dv_xname);
continue;
}
found++;
wmbi->stat = BT_MBI_FREE;
if (ccb) {
untimeout(bt_timeout, ccb);
- bt_done(bt, ccb);
+ bt_done(sc, ccb);
}
bt_nextmbx(wmbi, wmbx, mbi);
}
if (!found) {
#if 0
printf("%s: mbi interrupt with no full mailboxes\n",
- bt->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
#endif
} else {
found = 0;
}
}
wmbx->tmbi = wmbi;
- outb(BT_CTRL_STAT_PORT, BT_IRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_IRST);
return 1;
}
* A ccb is put onto the free list.
*/
void
-bt_free_ccb(bt, ccb, flags)
- struct bt_softc *bt;
+bt_free_ccb(sc, ccb, flags)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
int flags;
{
s = splbio();
ccb->flags = CCB_FREE;
- TAILQ_INSERT_HEAD(&bt->free_ccb, ccb, chain);
+ TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
/*
* If there were none, wake anybody waiting for one to come free,
* starting with queued entries.
*/
if (ccb->chain.tqe_next == 0)
- wakeup(&bt->free_ccb);
+ wakeup(&sc->sc_free_ccb);
splx(s);
}
static inline void
-bt_init_ccb(bt, ccb)
- struct bt_softc *bt;
+bt_init_ccb(sc, ccb)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
{
int hashnum;
*/
ccb->hashkey = KVTOPHYS(ccb);
hashnum = CCB_HASH(ccb->hashkey);
- ccb->nexthash = bt->ccbhash[hashnum];
- bt->ccbhash[hashnum] = ccb;
+ ccb->nexthash = sc->sc_ccbhash[hashnum];
+ sc->sc_ccbhash[hashnum] = ccb;
}
static inline void
-bt_reset_ccb(bt, ccb)
- struct bt_softc *bt;
+bt_reset_ccb(sc, ccb)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
{
* the hash table too otherwise either return an error or sleep.
*/
struct bt_ccb *
-bt_get_ccb(bt, flags)
- struct bt_softc *bt;
+bt_get_ccb(sc, flags)
+ struct bt_softc *sc;
int flags;
{
struct bt_ccb *ccb;
* but only if we can't allocate a new one.
*/
for (;;) {
- ccb = bt->free_ccb.tqh_first;
+ ccb = sc->sc_free_ccb.tqh_first;
if (ccb) {
- TAILQ_REMOVE(&bt->free_ccb, ccb, chain);
+ TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
break;
}
- if (bt->numccbs < BT_CCB_MAX) {
+ if (sc->sc_numccbs < BT_CCB_MAX) {
if (ccb = (struct bt_ccb *) malloc(sizeof(struct bt_ccb),
M_TEMP, M_NOWAIT)) {
- bt_init_ccb(bt, ccb);
- bt->numccbs++;
+ bt_init_ccb(sc, ccb);
+ sc->sc_numccbs++;
} else {
printf("%s: can't malloc ccb\n",
- bt->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
goto out;
}
break;
}
if ((flags & SCSI_NOSLEEP) != 0)
goto out;
- tsleep(&bt->free_ccb, PRIBIO, "btccb", 0);
+ tsleep(&sc->sc_free_ccb, PRIBIO, "btccb", 0);
}
- bt_reset_ccb(bt, ccb);
+ bt_reset_ccb(sc, ccb);
ccb->flags = CCB_ACTIVE;
out:
* it corresponds to:
*/
struct bt_ccb *
-bt_ccb_phys_kv(bt, ccb_phys)
- struct bt_softc *bt;
+bt_ccb_phys_kv(sc, ccb_phys)
+ struct bt_softc *sc;
u_long ccb_phys;
{
int hashnum = CCB_HASH(ccb_phys);
- struct bt_ccb *ccb = bt->ccbhash[hashnum];
+ struct bt_ccb *ccb = sc->sc_ccbhash[hashnum];
while (ccb) {
if (ccb->hashkey == ccb_phys)
* Get a mbo and send the ccb.
*/
struct bt_mbx_out *
-bt_send_mbo(bt, cmd, ccb)
- struct bt_softc *bt;
+bt_send_mbo(sc, cmd, ccb)
+ struct bt_softc *sc;
int cmd;
struct bt_ccb *ccb;
{
+ int iobase = sc->sc_iobase;
struct bt_mbx_out *wmbo; /* Mail Box Out pointer */
struct bt_mbx *wmbx; /* Mail Box pointer specified unit */
int i;
/* Get the target out mail box pointer and increment. */
- wmbx = &bt->bt_mbx;
+ wmbx = &sc->sc_mbx;
wmbo = wmbx->tmbo;
bt_nextmbx(wmbx->tmbo, wmbx, mbo);
*/
while (wmbo->cmd != BT_MBO_FREE) {
/* Enable mbo available interrupt. */
- outb(BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
+ outb(iobase + BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
for (i = 100000; i; i--) {
- if (!(inb(BT_CTRL_STAT_PORT) & BT_CDF))
+ if (!(inb(iobase + BT_CTRL_STAT_PORT) & BT_CDF))
break;
delay(10);
}
if (!i) {
printf("%s: bt_send_mbo, cmd/data port full\n",
- bt->sc_dev.dv_xname);
- outb(BT_CTRL_STAT_PORT, BT_SRST);
+ sc->sc_dev.dv_xname);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_SRST);
return NULL;
}
- outb(BT_CMD_DATA_PORT, 0x01); /* Enable */
+ outb(iobase + BT_CMD_DATA_PORT, 0x01); /* Enable */
tsleep(wmbx, PRIBIO, "btsnd", 0);/*XXX can't do this */
}
wmbo->cmd = cmd;
/* Send it! */
- outb(BT_CMD_DATA_PORT, BT_START_SCSI);
+ outb(iobase + BT_CMD_DATA_PORT, BT_START_SCSI);
return wmbo;
}
* went. Wake up the owner if waiting
*/
void
-bt_done(bt, ccb)
- struct bt_softc *bt;
+bt_done(sc, ccb)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
{
struct scsi_sense_data *s1, *s2;
* into the xfer and call whoever started it
*/
if ((xs->flags & INUSE) == 0) {
- printf("%s: exiting but not in use!\n", bt->sc_dev.dv_xname);
+ printf("%s: exiting but not in use!\n", sc->sc_dev.dv_xname);
Debugger();
}
if (xs->error == XS_NOERROR) {
break;
default: /* Other scsi protocol messes */
printf("%s: host_stat %x\n",
- bt->sc_dev.dv_xname, ccb->host_stat);
+ sc->sc_dev.dv_xname, ccb->host_stat);
xs->error = XS_DRIVER_STUFFUP;
}
} else if (ccb->target_stat != SCSI_OK) {
break;
default:
printf("%s: target_stat %x\n",
- bt->sc_dev.dv_xname, ccb->target_stat);
+ sc->sc_dev.dv_xname, ccb->target_stat);
xs->error = XS_DRIVER_STUFFUP;
}
} else
xs->resid = 0;
}
xs->flags |= ITSDONE;
- bt_free_ccb(bt, ccb, xs->flags);
+ bt_free_ccb(sc, ccb, xs->flags);
scsi_done(xs);
}
* Find the board and find it's irq/drq
*/
int
-bt_find(bt)
- struct bt_softc *bt;
+bt_find(ia, sc)
+ struct isa_attach_args *ia;
+ struct bt_softc *sc;
{
+ int iobase = ia->ia_iobase;
u_char ad[4];
volatile int i, sts;
struct bt_extended_inquire info;
struct bt_config conf;
+ int irq, drq;
/*
* reset board, If it doesn't respond, assume
* that it's not there.. good for the probe
*/
- outb(BT_CTRL_STAT_PORT, BT_HRST | BT_SRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_HRST | BT_SRST);
for (i = BT_RESET_TIMEOUT; i; i--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (sts == (BT_IDLE | BT_INIT))
break;
delay(1000);
#ifdef UTEST
printf("bt_find: No answer from bt742a board\n");
#endif
- return ENXIO;
+ return 1;
}
/*
* Check that we actually know how to use this board.
*/
delay(1000);
- bt_cmd(bt, 1, sizeof(info), 0, &info, BT_INQUIRE_EXTENDED, sizeof(info));
+ bt_cmd(iobase, sc, 1, sizeof(info), 0, (u_char *)&info,
+ BT_INQUIRE_EXTENDED, sizeof(info));
switch (info.bus_type) {
case BT_BUS_TYPE_24BIT:
/* XXXX How do we avoid conflicting with the aha1542 probe? */
break;
case BT_BUS_TYPE_MCA:
/* We don't grok MicroChannel (yet). */
- return EINVAL;
+ return 1;
default:
- printf("%s: illegal bus type %c\n", bt->sc_dev.dv_xname,
- info.bus_type);
- return EINVAL;
+ printf("bt_find: illegal bus type %c\n", info.bus_type);
+ return 1;
}
/*
* jumpers and save int level
*/
delay(1000);
- bt_cmd(bt, 0, sizeof(conf), 0, &conf, BT_CONF_GET);
+ bt_cmd(iobase, sc, 0, sizeof(conf), 0, (u_char *)&conf, BT_CONF_GET);
switch (conf.chan) {
case EISADMA:
- bt->bt_drq = DRQUNK;
+ drq = DRQUNK;
break;
case CHAN0:
- bt->bt_drq = 0;
+ drq = 0;
break;
case CHAN5:
- bt->bt_drq = 5;
+ drq = 5;
break;
case CHAN6:
- bt->bt_drq = 6;
+ drq = 6;
break;
case CHAN7:
- bt->bt_drq = 7;
+ drq = 7;
break;
default:
- printf("%s: illegal dma setting %x\n", bt->sc_dev.dv_xname,
- conf.chan);
- return EIO;
+ printf("bt_find: illegal dma setting %x\n", conf.chan);
+ return 1;
}
switch (conf.intr) {
case INT9:
- bt->sc_irq = 9;
+ irq = 9;
break;
case INT10:
- bt->sc_irq = 10;
+ irq = 10;
break;
case INT11:
- bt->sc_irq = 11;
+ irq = 11;
break;
case INT12:
- bt->sc_irq = 12;
+ irq = 12;
break;
case INT14:
- bt->sc_irq = 14;
+ irq = 14;
break;
case INT15:
- bt->sc_irq = 15;
+ irq = 15;
break;
default:
- printf("%s: illegal int setting %x\n", bt->sc_dev.dv_xname,
- conf.intr);
- return EIO;
+ printf("bt_find: illegal int setting %x\n", conf.intr);
+ return 1;
}
- /* who are we on the scsi bus? */
- bt->bt_scsi_dev = conf.scsi_dev;
+ if (sc != NULL) {
+ /* who are we on the scsi bus? */
+ sc->sc_scsi_dev = conf.scsi_dev;
+
+ sc->sc_iobase = iobase;
+ sc->sc_irq = irq;
+ sc->sc_drq = drq;
+ } else {
+ if (ia->ia_irq == IRQUNK)
+ ia->ia_irq = irq;
+ else if (ia->ia_irq != irq)
+ return 1;
+ if (ia->ia_drq == DRQUNK)
+ ia->ia_drq = drq;
+ else if (ia->ia_drq != drq)
+ return 1;
+ }
return 0;
}
* Start the board, ready for normal operation
*/
void
-bt_init(bt)
- struct bt_softc *bt;
+bt_init(sc)
+ struct bt_softc *sc;
{
+ int iobase = sc->sc_iobase;
u_char ad[4];
int i;
/*
* Initialize mail box
*/
- *((physaddr *)ad) = KVTOPHYS(&bt->bt_mbx);
+ *((physaddr *)ad) = KVTOPHYS(&sc->sc_mbx);
- bt_cmd(bt, 5, 0, 0, 0, BT_MBX_INIT_EXTENDED, BT_MBX_SIZE,
+ bt_cmd(iobase, sc, 5, 0, 0, 0, BT_MBX_INIT_EXTENDED, BT_MBX_SIZE,
ad[0], ad[1], ad[2], ad[3]);
for (i = 0; i < BT_MBX_SIZE; i++) {
- bt->bt_mbx.mbo[i].cmd = BT_MBO_FREE;
- bt->bt_mbx.mbi[i].stat = BT_MBI_FREE;
+ sc->sc_mbx.mbo[i].cmd = BT_MBO_FREE;
+ sc->sc_mbx.mbi[i].stat = BT_MBI_FREE;
}
/*
* Set up initial mail box for round-robin operation.
*/
- bt->bt_mbx.tmbo = &bt->bt_mbx.mbo[0];
- bt->bt_mbx.tmbi = &bt->bt_mbx.mbi[0];
+ sc->sc_mbx.tmbo = &sc->sc_mbx.mbo[0];
+ sc->sc_mbx.tmbi = &sc->sc_mbx.mbi[0];
- bt_inquire_setup_information(bt);
+ bt_inquire_setup_information(sc);
}
void
-bt_inquire_setup_information(bt)
- struct bt_softc *bt;
+bt_inquire_setup_information(sc)
+ struct bt_softc *sc;
{
+ int iobase = sc->sc_iobase;
struct bt_boardID bID;
- char dummy[8];
+ struct bt_board_info binfo;
+ char dummy[8], sub_ver[3];
struct bt_setup setup;
- int i;
+ int i, ver;
- /* Inquire Board ID to Bt742 for firmware version */
- bt_cmd(bt, 0, sizeof(bID), 0, &bID, BT_INQUIRE);
- printf(": version %c.%c, ", bID.firm_revision, bID.firm_version);
+ /*
+ * Get and print board hardware information.
+ */
+ bt_cmd(iobase, sc, 1, sizeof(binfo), 0, (u_char *)&binfo,
+ BT_GET_BOARD_INFO, sizeof(binfo));
+ printf(": Bt%c%c%c", binfo.id[0], binfo.id[1], binfo.id[2]);
+ if (binfo.id[3] != ' ')
+ printf("%c", binfo.id[3]);
+ if (binfo.version[0] != ' ')
+ printf("%c%s", binfo.version[0], binfo.version[1]);
+ printf("\n");
+
+ /*
+ * Inquire Board ID to Bt742 for board type and firmware version.
+ */
+ bt_cmd(iobase, sc, 0, sizeof(bID), 0, (u_char *)&bID, BT_INQUIRE);
+ ver = (bID.firm_revision - '0') * 10 + (bID.firm_version - '0');
- if (bID.firm_revision != '2') { /* XXXX */
- /* Enable round-robin scheme - appeared at firmware rev. 3.31 */
- bt_cmd(bt, 1, 0, 0, 0, BT_ROUND_ROBIN, BT_ENABLE);
+ /*
+ * Get the rest of the firmware version. Firmware revisions
+ * before 3.3 apparently don't accept the BT_INQUIRE_REV_FOURTH
+ * command.
+ */
+ i = 0;
+ bt_cmd(iobase, sc, 0, 1, 0, &sub_ver[i++], BT_INQUIRE_REV_THIRD);
+ if (ver >= 33)
+ bt_cmd(iobase, sc, 0, 1, 0, &sub_ver[i++],
+ BT_INQUIRE_REV_FOURTH);
+ if (sub_ver[i - 1] == ' ')
+ i--;
+ sub_ver[i] = '\0';
+
+ printf("%s: firmware version %c.%c%s, ", sc->sc_dev.dv_xname,
+ bID.firm_revision, bID.firm_version, sub_ver);
+
+ /* Enable round-robin scheme - appeared at firmware rev. 3.31 */
+ if (ver > 33 || (ver == 33 && sub_ver[0] >= 1)) {
+ bt_cmd(iobase, sc, 1, 0, 0, 0, BT_ROUND_ROBIN, BT_ENABLE);
}
/* Inquire Installed Devices (to force synchronous negotiation) */
- bt_cmd(bt, 0, sizeof(dummy), 10, dummy, BT_DEV_GET);
+ bt_cmd(iobase, sc, 0, sizeof(dummy), 10, dummy, BT_DEV_GET);
/* Obtain setup information from Bt742. */
- bt_cmd(bt, 1, sizeof(setup), 0, &setup, BT_SETUP_GET, sizeof(setup));
+ bt_cmd(iobase, sc, 1, sizeof(setup), 0, (u_char *)&setup, BT_SETUP_GET,
+ sizeof(setup));
- printf("%s, %s, %d mbxs",
+ printf("%s, %s, %d mailboxes",
setup.sync_neg ? "sync" : "async",
setup.parity ? "parity" : "no parity",
setup.num_mbx);
(!setup.sync[i].offset && !setup.sync[i].period))
continue;
printf("\n%s targ %d: sync, offset %d, period %dnsec",
- bt->sc_dev.dv_xname, i,
+ sc->sc_dev.dv_xname, i,
setup.sync[i].offset, setup.sync[i].period * 50 + 200);
}
}
struct scsi_xfer *xs;
{
struct scsi_link *sc_link = xs->sc_link;
- struct bt_softc *bt = sc_link->adapter_softc;
+ struct bt_softc *sc = sc_link->adapter_softc;
struct bt_ccb *ccb;
struct bt_scat_gath *sg;
int seg; /* scatter gather seg being worked on */
*/
flags = xs->flags;
if ((flags & (ITSDONE|INUSE)) != INUSE) {
- printf("%s: done or not in use?\n", bt->sc_dev.dv_xname);
+ printf("%s: done or not in use?\n", sc->sc_dev.dv_xname);
xs->flags &= ~ITSDONE;
xs->flags |= INUSE;
}
- if ((ccb = bt_get_ccb(bt, flags)) == NULL) {
+ if ((ccb = bt_get_ccb(sc, flags)) == NULL) {
xs->error = XS_DRIVER_STUFFUP;
return TRY_AGAIN_LATER;
}
* there's still data, must have run out of segs!
*/
printf("%s: bt_scsi_cmd, more than %d dma segs\n",
- bt->sc_dev.dv_xname, BT_NSEG);
+ sc->sc_dev.dv_xname, BT_NSEG);
xs->error = XS_DRIVER_STUFFUP;
- bt_free_ccb(bt, ccb, flags);
+ bt_free_ccb(sc, ccb, flags);
return COMPLETE;
}
} else { /* No data xfer, use non S/G values */
s = splbio();
- if (bt_send_mbo(bt, BT_MBO_START, ccb) == NULL) {
+ if (bt_send_mbo(sc, BT_MBO_START, ccb) == NULL) {
splx(s);
xs->error = XS_DRIVER_STUFFUP;
- bt_free_ccb(bt, ccb, flags);
+ bt_free_ccb(sc, ccb, flags);
return TRY_AGAIN_LATER;
}
/*
* If we can't use interrupts, poll on completion
*/
- if (bt_poll(bt, xs, xs->timeout)) {
+ if (bt_poll(sc, xs, xs->timeout)) {
bt_timeout(ccb);
- if (bt_poll(bt, xs, 2000))
+ if (bt_poll(sc, xs, 2000))
bt_timeout(ccb);
}
return COMPLETE;
* Poll a particular unit, looking for a particular xs
*/
int
-bt_poll(bt, xs, count)
- struct bt_softc *bt;
+bt_poll(sc, xs, count)
+ struct bt_softc *sc;
struct scsi_xfer *xs;
int count;
{
+ int iobase = sc->sc_iobase;
/* timeouts are in msec, so we loop in 1000 usec cycles */
while (count) {
* If we had interrupts enabled, would we
* have got an interrupt?
*/
- if (inb(BT_INTR_PORT) & BT_ANY_INTR)
- btintr(bt);
+ if (inb(iobase + BT_INTR_PORT) & BT_ANY_INTR)
+ btintr(sc);
if (xs->flags & ITSDONE)
return 0;
delay(1000); /* only happens in boot so ok */
struct bt_ccb *ccb = arg;
struct scsi_xfer *xs = ccb->xs;
struct scsi_link *sc_link = xs->sc_link;
- struct bt_softc *bt = sc_link->adapter_softc;
+ struct bt_softc *sc = sc_link->adapter_softc;
int s;
sc_print_addr(sc_link);
/*
* If the ccb's mbx is not free, then the board has gone Far East?
*/
- if (bt_ccb_phys_kv(bt, ccb->mbx->ccb_addr) == ccb &&
+ if (bt_ccb_phys_kv(sc, ccb->mbx->ccb_addr) == ccb &&
ccb->mbx->cmd != BT_MBO_FREE) {
- printf("%s: not taking commands!\n", bt->sc_dev.dv_xname);
+ printf("%s: not taking commands!\n", sc->sc_dev.dv_xname);
Debugger();
}
/* abort timed out */
printf(" AGAIN\n");
ccb->xs->retries = 0;
- bt_done(bt, ccb);
+ bt_done(sc, ccb);
} else {
/* abort the operation that has timed out */
printf("\n");
ccb->xs->error = XS_TIMEOUT;
ccb->flags = CCB_ABORTED;
- bt_send_mbo(bt, BT_MBO_ABORT, ccb);
+ bt_send_mbo(sc, BT_MBO_ABORT, ccb);
/* 2 secs for the abort */
if ((xs->flags & SCSI_POLL) == 0)
timeout(bt_timeout, ccb, 2 * hz);
}
void
-bt_print_active_ccbs(bt)
- struct bt_softc *bt;
+bt_print_active_ccbs(sc)
+ struct bt_softc *sc;
{
struct bt_ccb *ccb;
int i = 0;
while (i < CCB_HASH_SIZE) {
- ccb = bt->ccbhash[i];
+ ccb = sc->sc_ccbhash[i];
while (ccb) {
if (ccb->flags != CCB_FREE)
bt_print_ccb(ccb);
-/* $OpenBSD: bt742a.c,v 1.6 1996/03/20 01:00:41 mickey Exp $ */
-/* $NetBSD: bt742a.c,v 1.50 1995/12/24 02:31:13 mycroft Exp $ */
+/* $OpenBSD: bt742a.c,v 1.7 1996/04/18 23:47:31 niklas Exp $ */
+/* $NetBSD: bt742a.c,v 1.55 1996/03/16 05:33:28 cgd Exp $ */
/*
* Copyright (c) 1994 Charles Hannum. All rights reserved.
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
+/*
+ * Note that stdarg.h and the ANSI style va_start macro is used for both
+ * ANSI and traditional C compilers.
+ */
+#include <machine/stdarg.h>
+
#ifndef DDB
#define Debugger() panic("should call debugger here (bt742a.c)")
#endif /* ! DDB */
/*
* I/O Port Interface
*/
-#define BT_BASE bt->sc_iobase
-#define BT_CTRL_STAT_PORT (BT_BASE + 0x0) /* control & status */
-#define BT_CMD_DATA_PORT (BT_BASE + 0x1) /* cmds and datas */
-#define BT_INTR_PORT (BT_BASE + 0x2) /* Intr. stat */
+#define BT_CTRL_STAT_PORT 0x0 /* control & status */
+#define BT_CMD_DATA_PORT 0x1 /* cmds and datas */
+#define BT_INTR_PORT 0x2 /* Intr. stat */
/*
* BT_CTRL_STAT bits (write)
#define BT_READ_FIFO 0x1d /* read fifo buffer */
#define BT_ECHO 0x1e /* Echo command data */
#define BT_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */
-#define BT_INQUIRE_EXTENDED 0x8D /* Adapter Setup Inquiry */
+#define BT_INQUIRE_REV_THIRD 0x84 /* Get 3rd firmware version byte */
+#define BT_INQUIRE_REV_FOURTH 0x85 /* Get 4th firmware version byte */
+#define BT_GET_BOARD_INFO 0x8b /* Get hardware ID and revision */
+#define BT_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */
-/* Follows command appeared at FirmWare 3.31 */
+/* Follows command appeared at firmware 3.31 */
#define BT_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */
#define BT_DISABLE 0x00 /* Parameter value for Disable */
#define BT_ENABLE 0x01 /* Parameter value for Enable */
u_char firm_version;
};
+struct bt_board_info {
+ u_char id[4]; /* i.e bt742a -> '7','4','2','A' */
+ u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */
+};
+
struct bt_setup {
u_char sync_neg:1;
u_char parity:1;
#define KVTOPHYS(x) vtophys(x)
struct bt_softc {
- struct device sc_dev;
- struct isadev sc_id;
- void *sc_ih;
+ struct device sc_dev;
+ struct isadev sc_id;
+ void *sc_ih;
int sc_iobase;
- int sc_irq, bt_drq;
+ int sc_irq, sc_drq;
- struct bt_mbx bt_mbx; /* all our mailboxes */
- struct bt_ccb *ccbhash[CCB_HASH_SIZE];
- TAILQ_HEAD(, bt_ccb) free_ccb;
- int numccbs;
- int bt_scsi_dev; /* adapters scsi id */
+ struct bt_mbx sc_mbx; /* all our mailboxes */
+ struct bt_ccb *sc_ccbhash[CCB_HASH_SIZE];
+ TAILQ_HEAD(, bt_ccb) sc_free_ccb;
+ int sc_numccbs;
+ int sc_scsi_dev; /* adapters scsi id */
struct scsi_link sc_link; /* prototype for devs */
};
#define BT_SHOWMISC 0x08
int bt_debug = 0;
-int bt_cmd(); /* XXX must be varargs to prototype */
+int bt_cmd __P((int, struct bt_softc *, int, int, int, u_char *,
+ unsigned, ...));
int btintr __P((void *));
void bt_free_ccb __P((struct bt_softc *, struct bt_ccb *, int));
struct bt_ccb *bt_get_ccb __P((struct bt_softc *, int));
struct bt_ccb *bt_ccb_phys_kv __P((struct bt_softc *, u_long));
struct bt_mbx_out *bt_send_mbo __P((struct bt_softc *, int, struct bt_ccb *));
void bt_done __P((struct bt_softc *, struct bt_ccb *));
-int bt_find __P((struct bt_softc *));
+int bt_find __P((struct isa_attach_args *, struct bt_softc *));
void bt_init __P((struct bt_softc *));
void bt_inquire_setup_information __P((struct bt_softc *));
void btminphys __P((struct buf *));
#define BT_RESET_TIMEOUT 1000
/*
- * bt_cmd(bt, icnt, ocnt,wait, retval, opcode, args)
+ * bt_cmd(iobase, sc, icnt, ocnt, wait, retval, opcode, ... args ...)
*
* Activate Adapter command
* icnt: number of args (outbound bytes written after opcode)
* wait: number of seconds to wait for response
* retval: buffer where to place returned bytes
* opcode: opcode BT_NOP, BT_MBX_INIT, BT_START_SCSI ...
- * args: parameters
+ * args: variable number of parameters
*
* Performs an adapter command through the ports. Not to be confused with a
* scsi command, which is read in via the dma; one of the adapter commands
* tells it to read in a scsi command.
*/
int
-bt_cmd(bt, icnt, ocnt, wait, retval, opcode, args)
- struct bt_softc *bt;
+#ifdef __STDC__
+bt_cmd(int iobase, struct bt_softc *sc, int icnt, int ocnt, int wait,
+ u_char *retval, unsigned opcode, ...)
+#else
+bt_cmd(iobase, sc, icnt, ocnt, wait, retval, opcode, va_alist)
+ int iobase;
+ struct bt_softc *sc;
int icnt, ocnt, wait;
u_char *retval;
unsigned opcode;
- u_char args;
+ va_dcl
+#endif
{
- unsigned *ic = &opcode;
+ va_list ap;
+ unsigned data;
+ const char *name;
u_char oc;
register i;
int sts;
+ if (sc == NULL)
+ name = sc->sc_dev.dv_xname;
+ else
+ name = "(probe)";
+
/*
* multiply the wait argument by a big constant
* zero defaults to 1
if (opcode != BT_MBX_INIT && opcode != BT_START_SCSI) {
i = 100000; /* 1 sec? */
while (--i) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (sts & BT_IDLE) {
break;
}
}
if (!i) {
printf("%s: bt_cmd, host not idle(0x%x)\n",
- bt->sc_dev.dv_xname, sts);
+ name, sts);
return ENXIO;
}
}
* queue feeding to us.
*/
if (ocnt) {
- while ((inb(BT_CTRL_STAT_PORT)) & BT_DF)
- inb(BT_CMD_DATA_PORT);
+ while ((inb(iobase + BT_CTRL_STAT_PORT)) & BT_DF)
+ inb(iobase + BT_CMD_DATA_PORT);
}
/*
* Output the command and the number of arguments given
* for each byte, first check the port is empty.
*/
- icnt++;
- /* include the command */
- while (icnt--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ va_start(ap, opcode);
+ /* test icnt >= 0, to include the command in data sent */
+ for (data = opcode; icnt >= 0; icnt--, data = va_arg(ap, u_char)) {
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
for (i = wait; i; i--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (!(sts & BT_CDF))
break;
delay(10);
}
if (!i) {
- printf("%s: bt_cmd, cmd/data port full\n",
- bt->sc_dev.dv_xname);
- outb(BT_CTRL_STAT_PORT, BT_SRST);
+ printf("%s: bt_cmd, cmd/data port full\n", name);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_SRST);
+ va_end(ap);
return ENXIO;
}
- outb(BT_CMD_DATA_PORT, (u_char) (*ic++));
+ outb(iobase + BT_CMD_DATA_PORT, data);
}
+ va_end(ap);
/*
* If we expect input, loop that many times, each time,
* looking for the data register to have valid data
*/
while (ocnt--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
for (i = wait; i; i--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (sts & BT_DF)
break;
delay(10);
}
if (!i) {
printf("bt%d: bt_cmd, cmd/data port empty %d\n",
- bt->sc_dev.dv_xname, ocnt);
+ name, ocnt);
return ENXIO;
}
- oc = inb(BT_CMD_DATA_PORT);
+ oc = inb(iobase + BT_CMD_DATA_PORT);
if (retval)
*retval++ = oc;
}
*/
i = 100000; /* 1 sec? */
while (--i) {
- sts = inb(BT_INTR_PORT);
+ sts = inb(iobase + BT_INTR_PORT);
if (sts & BT_HACC)
break;
delay(10);
}
if (!i) {
printf("%s: bt_cmd, host not finished(0x%x)\n",
- bt->sc_dev.dv_xname, sts);
+ name, sts);
return ENXIO;
}
- outb(BT_CTRL_STAT_PORT, BT_IRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_IRST);
return 0;
}
*/
int
btprobe(parent, match, aux)
- struct device *parent;
- void *match, *aux;
+ struct device *parent;
+ void *match, *aux;
{
- struct bt_softc *bt = match;
- register struct isa_attach_args *ia = aux;
+ struct bt_softc *sc = match;
+ register struct isa_attach_args *ia = aux;
#ifdef NEWCONFIG
- if (ia->ia_iobase == IOBASEUNK)
- return 0;
+ if (ia->ia_iobase == IOBASEUNK)
+ return 0;
#endif
- bt->sc_iobase = ia->ia_iobase;
-
/*
* Try initialise a unit at this location
- * sets up dma and bus speed, loads bt->sc_irq
+ * sets up dma and bus speed, loads sc->sc_irq
*/
- if (bt_find(bt) != 0)
+ if (bt_find(ia, NULL) != 0)
return 0;
- if (ia->ia_irq != IRQUNK) {
- if (ia->ia_irq != bt->sc_irq) {
- printf("%s: irq mismatch; kernel configured %d != board configured %d\n",
- bt->sc_dev.dv_xname, ia->ia_irq, bt->sc_irq);
- return 0;
- }
- } else
- ia->ia_irq = bt->sc_irq;
-
- if (ia->ia_drq != DRQUNK) {
- if (ia->ia_drq != bt->bt_drq) {
- printf("%s: drq mismatch; kernel configured %d != board configured %d\n",
- bt->sc_dev.dv_xname, ia->ia_drq, bt->bt_drq);
- return 0;
- }
- } else
- ia->ia_drq = bt->bt_drq;
-
ia->ia_msize = 0;
ia->ia_iosize = 4;
+ /* IRQ and DRQ set by bt_find() */
return 1;
}
void *aux;
char *name;
{
- if (name != NULL)
+ if (name != NULL)
printf("%s: scsibus ", name);
return UNCONF;
}
*/
void
btattach(parent, self, aux)
- struct device *parent, *self;
- void *aux;
+ struct device *parent, *self;
+ void *aux;
{
- struct isa_attach_args *ia = aux;
- struct bt_softc *bt = (void *)self;
+ struct isa_attach_args *ia = aux;
+ struct bt_softc *sc = (struct bt_softc *)self;
- if (ia->ia_drq != DRQUNK)
- isa_dmacascade(ia->ia_drq);
+ if (bt_find(ia, sc) != 0)
+ panic("btattach: bt_find of %s failed", self->dv_xname);
+ sc->sc_iobase = ia->ia_iobase;
- bt_init(bt);
- TAILQ_INIT(&bt->free_ccb);
+ if (sc->sc_drq != DRQUNK)
+ isa_dmacascade(sc->sc_drq);
+
+ bt_init(sc);
+ TAILQ_INIT(&sc->sc_free_ccb);
/*
* fill in the prototype scsi_link.
*/
- bt->sc_link.adapter_softc = bt;
- bt->sc_link.adapter_target = bt->bt_scsi_dev;
- bt->sc_link.adapter = &bt_switch;
- bt->sc_link.device = &bt_dev;
- bt->sc_link.openings = 2;
+ sc->sc_link.adapter_softc = sc;
+ sc->sc_link.adapter_target = sc->sc_scsi_dev;
+ sc->sc_link.adapter = &bt_switch;
+ sc->sc_link.device = &bt_dev;
+ sc->sc_link.openings = 2;
printf("\n");
#ifdef NEWCONFIG
- isa_establish(&bt->sc_id, &bt->sc_dev);
+ isa_establish(&sc->sc_id, &sc->sc_dev);
#endif
- bt->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_BIO, btintr,
- bt, bt->sc_dev.dv_xname);
+ sc->sc_ih = isa_intr_establish(sc->sc_irq, IST_EDGE, IPL_BIO, btintr,
+ sc, sc->sc_dev.dv_xname);
/*
* ask the adapter what subunits are present
*/
- config_found(self, &bt->sc_link, btprint);
+ config_found(self, &sc->sc_link, btprint);
}
/*
btintr(arg)
void *arg;
{
- struct bt_softc *bt = arg;
+ struct bt_softc *sc = arg;
+ int iobase = sc->sc_iobase;
struct bt_mbx_in *wmbi;
struct bt_mbx *wmbx;
struct bt_ccb *ccb;
int found = 0;
#ifdef BTDEBUG
- printf("%s: btintr ", bt->sc_dev.dv_xname);
+ printf("%s: btintr ", sc->sc_dev.dv_xname);
#endif /* BTDEBUG */
/*
* not telling about a completed operation
* just return.
*/
- stat = inb(BT_INTR_PORT);
+ stat = inb(iobase + BT_INTR_PORT);
if ((stat & (BT_MBOA | BT_MBIF)) == 0) {
- outb(BT_CTRL_STAT_PORT, BT_IRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_IRST);
return -1; /* XXX */
}
/* Mail box out empty? */
if (stat & BT_MBOA) {
/* Disable MBO available interrupt. */
- outb(BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
+ outb(iobase + BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
for (i = 100000; i; i--) {
- if (!(inb(BT_CTRL_STAT_PORT) & BT_CDF))
+ if (!(inb(iobase + BT_CTRL_STAT_PORT) & BT_CDF))
break;
delay(10);
}
if (!i) {
printf("%s: btintr, cmd/data port full\n",
- bt->sc_dev.dv_xname);
- outb(BT_CTRL_STAT_PORT, BT_SRST);
+ sc->sc_dev.dv_xname);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_SRST);
return 1;
}
- outb(BT_CMD_DATA_PORT, 0x00); /* Disable */
- wakeup(&bt->bt_mbx);
+ outb(iobase + BT_CMD_DATA_PORT, 0x00); /* Disable */
+ wakeup(&sc->sc_mbx);
}
/* Mail box in full? */
if ((stat & BT_MBIF) == 0)
return 1;
- wmbx = &bt->bt_mbx;
+ wmbx = &sc->sc_mbx;
wmbi = wmbx->tmbi;
AGAIN:
while (wmbi->stat != BT_MBI_FREE) {
- ccb = bt_ccb_phys_kv(bt, wmbi->ccb_addr);
+ ccb = bt_ccb_phys_kv(sc, wmbi->ccb_addr);
if (!ccb) {
wmbi->stat = BT_MBI_FREE;
- printf("%s: BAD CCB ADDR!\n", bt->sc_dev.dv_xname);
+ printf("%s: BAD CCB ADDR!\n", sc->sc_dev.dv_xname);
continue;
}
found++;
wmbi->stat = BT_MBI_FREE;
if (ccb) {
untimeout(bt_timeout, ccb);
- bt_done(bt, ccb);
+ bt_done(sc, ccb);
}
bt_nextmbx(wmbi, wmbx, mbi);
}
if (!found) {
#if 0
printf("%s: mbi interrupt with no full mailboxes\n",
- bt->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
#endif
} else {
found = 0;
}
}
wmbx->tmbi = wmbi;
- outb(BT_CTRL_STAT_PORT, BT_IRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_IRST);
return 1;
}
* A ccb is put onto the free list.
*/
void
-bt_free_ccb(bt, ccb, flags)
- struct bt_softc *bt;
+bt_free_ccb(sc, ccb, flags)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
int flags;
{
s = splbio();
ccb->flags = CCB_FREE;
- TAILQ_INSERT_HEAD(&bt->free_ccb, ccb, chain);
+ TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
/*
* If there were none, wake anybody waiting for one to come free,
* starting with queued entries.
*/
if (ccb->chain.tqe_next == 0)
- wakeup(&bt->free_ccb);
+ wakeup(&sc->sc_free_ccb);
splx(s);
}
static inline void
-bt_init_ccb(bt, ccb)
- struct bt_softc *bt;
+bt_init_ccb(sc, ccb)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
{
int hashnum;
*/
ccb->hashkey = KVTOPHYS(ccb);
hashnum = CCB_HASH(ccb->hashkey);
- ccb->nexthash = bt->ccbhash[hashnum];
- bt->ccbhash[hashnum] = ccb;
+ ccb->nexthash = sc->sc_ccbhash[hashnum];
+ sc->sc_ccbhash[hashnum] = ccb;
}
static inline void
-bt_reset_ccb(bt, ccb)
- struct bt_softc *bt;
+bt_reset_ccb(sc, ccb)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
{
* the hash table too otherwise either return an error or sleep.
*/
struct bt_ccb *
-bt_get_ccb(bt, flags)
- struct bt_softc *bt;
+bt_get_ccb(sc, flags)
+ struct bt_softc *sc;
int flags;
{
struct bt_ccb *ccb;
* but only if we can't allocate a new one.
*/
for (;;) {
- ccb = bt->free_ccb.tqh_first;
+ ccb = sc->sc_free_ccb.tqh_first;
if (ccb) {
- TAILQ_REMOVE(&bt->free_ccb, ccb, chain);
+ TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
break;
}
- if (bt->numccbs < BT_CCB_MAX) {
+ if (sc->sc_numccbs < BT_CCB_MAX) {
if (ccb = (struct bt_ccb *) malloc(sizeof(struct bt_ccb),
M_TEMP, M_NOWAIT)) {
- bt_init_ccb(bt, ccb);
- bt->numccbs++;
+ bt_init_ccb(sc, ccb);
+ sc->sc_numccbs++;
} else {
printf("%s: can't malloc ccb\n",
- bt->sc_dev.dv_xname);
+ sc->sc_dev.dv_xname);
goto out;
}
break;
}
if ((flags & SCSI_NOSLEEP) != 0)
goto out;
- tsleep(&bt->free_ccb, PRIBIO, "btccb", 0);
+ tsleep(&sc->sc_free_ccb, PRIBIO, "btccb", 0);
}
- bt_reset_ccb(bt, ccb);
+ bt_reset_ccb(sc, ccb);
ccb->flags = CCB_ACTIVE;
out:
* it corresponds to:
*/
struct bt_ccb *
-bt_ccb_phys_kv(bt, ccb_phys)
- struct bt_softc *bt;
+bt_ccb_phys_kv(sc, ccb_phys)
+ struct bt_softc *sc;
u_long ccb_phys;
{
int hashnum = CCB_HASH(ccb_phys);
- struct bt_ccb *ccb = bt->ccbhash[hashnum];
+ struct bt_ccb *ccb = sc->sc_ccbhash[hashnum];
while (ccb) {
if (ccb->hashkey == ccb_phys)
* Get a mbo and send the ccb.
*/
struct bt_mbx_out *
-bt_send_mbo(bt, cmd, ccb)
- struct bt_softc *bt;
+bt_send_mbo(sc, cmd, ccb)
+ struct bt_softc *sc;
int cmd;
struct bt_ccb *ccb;
{
+ int iobase = sc->sc_iobase;
struct bt_mbx_out *wmbo; /* Mail Box Out pointer */
struct bt_mbx *wmbx; /* Mail Box pointer specified unit */
int i;
/* Get the target out mail box pointer and increment. */
- wmbx = &bt->bt_mbx;
+ wmbx = &sc->sc_mbx;
wmbo = wmbx->tmbo;
bt_nextmbx(wmbx->tmbo, wmbx, mbo);
*/
while (wmbo->cmd != BT_MBO_FREE) {
/* Enable mbo available interrupt. */
- outb(BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
+ outb(iobase + BT_CMD_DATA_PORT, BT_MBO_INTR_EN);
for (i = 100000; i; i--) {
- if (!(inb(BT_CTRL_STAT_PORT) & BT_CDF))
+ if (!(inb(iobase + BT_CTRL_STAT_PORT) & BT_CDF))
break;
delay(10);
}
if (!i) {
printf("%s: bt_send_mbo, cmd/data port full\n",
- bt->sc_dev.dv_xname);
- outb(BT_CTRL_STAT_PORT, BT_SRST);
+ sc->sc_dev.dv_xname);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_SRST);
return NULL;
}
- outb(BT_CMD_DATA_PORT, 0x01); /* Enable */
+ outb(iobase + BT_CMD_DATA_PORT, 0x01); /* Enable */
tsleep(wmbx, PRIBIO, "btsnd", 0);/*XXX can't do this */
}
wmbo->cmd = cmd;
/* Send it! */
- outb(BT_CMD_DATA_PORT, BT_START_SCSI);
+ outb(iobase + BT_CMD_DATA_PORT, BT_START_SCSI);
return wmbo;
}
* went. Wake up the owner if waiting
*/
void
-bt_done(bt, ccb)
- struct bt_softc *bt;
+bt_done(sc, ccb)
+ struct bt_softc *sc;
struct bt_ccb *ccb;
{
struct scsi_sense_data *s1, *s2;
* into the xfer and call whoever started it
*/
if ((xs->flags & INUSE) == 0) {
- printf("%s: exiting but not in use!\n", bt->sc_dev.dv_xname);
+ printf("%s: exiting but not in use!\n", sc->sc_dev.dv_xname);
Debugger();
}
if (xs->error == XS_NOERROR) {
break;
default: /* Other scsi protocol messes */
printf("%s: host_stat %x\n",
- bt->sc_dev.dv_xname, ccb->host_stat);
+ sc->sc_dev.dv_xname, ccb->host_stat);
xs->error = XS_DRIVER_STUFFUP;
}
} else if (ccb->target_stat != SCSI_OK) {
break;
default:
printf("%s: target_stat %x\n",
- bt->sc_dev.dv_xname, ccb->target_stat);
+ sc->sc_dev.dv_xname, ccb->target_stat);
xs->error = XS_DRIVER_STUFFUP;
}
} else
xs->resid = 0;
}
xs->flags |= ITSDONE;
- bt_free_ccb(bt, ccb, xs->flags);
+ bt_free_ccb(sc, ccb, xs->flags);
scsi_done(xs);
}
* Find the board and find it's irq/drq
*/
int
-bt_find(bt)
- struct bt_softc *bt;
+bt_find(ia, sc)
+ struct isa_attach_args *ia;
+ struct bt_softc *sc;
{
+ int iobase = ia->ia_iobase;
u_char ad[4];
volatile int i, sts;
struct bt_extended_inquire info;
struct bt_config conf;
+ int irq, drq;
/*
* reset board, If it doesn't respond, assume
* that it's not there.. good for the probe
*/
- outb(BT_CTRL_STAT_PORT, BT_HRST | BT_SRST);
+ outb(iobase + BT_CTRL_STAT_PORT, BT_HRST | BT_SRST);
for (i = BT_RESET_TIMEOUT; i; i--) {
- sts = inb(BT_CTRL_STAT_PORT);
+ sts = inb(iobase + BT_CTRL_STAT_PORT);
if (sts == (BT_IDLE | BT_INIT))
break;
delay(1000);
#ifdef UTEST
printf("bt_find: No answer from bt742a board\n");
#endif
- return ENXIO;
+ return 1;
}
/*
* Check that we actually know how to use this board.
*/
delay(1000);
- bt_cmd(bt, 1, sizeof(info), 0, &info, BT_INQUIRE_EXTENDED, sizeof(info));
+ bt_cmd(iobase, sc, 1, sizeof(info), 0, (u_char *)&info,
+ BT_INQUIRE_EXTENDED, sizeof(info));
switch (info.bus_type) {
case BT_BUS_TYPE_24BIT:
/* XXXX How do we avoid conflicting with the aha1542 probe? */
break;
case BT_BUS_TYPE_MCA:
/* We don't grok MicroChannel (yet). */
- return EINVAL;
+ return 1;
default:
- printf("%s: illegal bus type %c\n", bt->sc_dev.dv_xname,
- info.bus_type);
- return EINVAL;
+ printf("bt_find: illegal bus type %c\n", info.bus_type);
+ return 1;
}
/*
* jumpers and save int level
*/
delay(1000);
- bt_cmd(bt, 0, sizeof(conf), 0, &conf, BT_CONF_GET);
+ bt_cmd(iobase, sc, 0, sizeof(conf), 0, (u_char *)&conf, BT_CONF_GET);
switch (conf.chan) {
case EISADMA:
- bt->bt_drq = DRQUNK;
+ drq = DRQUNK;
break;
case CHAN0:
- bt->bt_drq = 0;
+ drq = 0;
break;
case CHAN5:
- bt->bt_drq = 5;
+ drq = 5;
break;
case CHAN6:
- bt->bt_drq = 6;
+ drq = 6;
break;
case CHAN7:
- bt->bt_drq = 7;
+ drq = 7;
break;
default:
- printf("%s: illegal dma setting %x\n", bt->sc_dev.dv_xname,
- conf.chan);
- return EIO;
+ printf("bt_find: illegal dma setting %x\n", conf.chan);
+ return 1;
}
switch (conf.intr) {
case INT9:
- bt->sc_irq = 9;
+ irq = 9;
break;
case INT10:
- bt->sc_irq = 10;
+ irq = 10;
break;
case INT11:
- bt->sc_irq = 11;
+ irq = 11;
break;
case INT12:
- bt->sc_irq = 12;
+ irq = 12;
break;
case INT14:
- bt->sc_irq = 14;
+ irq = 14;
break;
case INT15:
- bt->sc_irq = 15;
+ irq = 15;
break;
default:
- printf("%s: illegal int setting %x\n", bt->sc_dev.dv_xname,
- conf.intr);
- return EIO;
+ printf("bt_find: illegal int setting %x\n", conf.intr);
+ return 1;
}
- /* who are we on the scsi bus? */
- bt->bt_scsi_dev = conf.scsi_dev;
+ if (sc != NULL) {
+ /* who are we on the scsi bus? */
+ sc->sc_scsi_dev = conf.scsi_dev;
+
+ sc->sc_iobase = iobase;
+ sc->sc_irq = irq;
+ sc->sc_drq = drq;
+ } else {
+ if (ia->ia_irq == IRQUNK)
+ ia->ia_irq = irq;
+ else if (ia->ia_irq != irq)
+ return 1;
+ if (ia->ia_drq == DRQUNK)
+ ia->ia_drq = drq;
+ else if (ia->ia_drq != drq)
+ return 1;
+ }
return 0;
}
* Start the board, ready for normal operation
*/
void
-bt_init(bt)
- struct bt_softc *bt;
+bt_init(sc)
+ struct bt_softc *sc;
{
+ int iobase = sc->sc_iobase;
u_char ad[4];
int i;
/*
* Initialize mail box
*/
- *((physaddr *)ad) = KVTOPHYS(&bt->bt_mbx);
+ *((physaddr *)ad) = KVTOPHYS(&sc->sc_mbx);
- bt_cmd(bt, 5, 0, 0, 0, BT_MBX_INIT_EXTENDED, BT_MBX_SIZE,
+ bt_cmd(iobase, sc, 5, 0, 0, 0, BT_MBX_INIT_EXTENDED, BT_MBX_SIZE,
ad[0], ad[1], ad[2], ad[3]);
for (i = 0; i < BT_MBX_SIZE; i++) {
- bt->bt_mbx.mbo[i].cmd = BT_MBO_FREE;
- bt->bt_mbx.mbi[i].stat = BT_MBI_FREE;
+ sc->sc_mbx.mbo[i].cmd = BT_MBO_FREE;
+ sc->sc_mbx.mbi[i].stat = BT_MBI_FREE;
}
/*
* Set up initial mail box for round-robin operation.
*/
- bt->bt_mbx.tmbo = &bt->bt_mbx.mbo[0];
- bt->bt_mbx.tmbi = &bt->bt_mbx.mbi[0];
+ sc->sc_mbx.tmbo = &sc->sc_mbx.mbo[0];
+ sc->sc_mbx.tmbi = &sc->sc_mbx.mbi[0];
- bt_inquire_setup_information(bt);
+ bt_inquire_setup_information(sc);
}
void
-bt_inquire_setup_information(bt)
- struct bt_softc *bt;
+bt_inquire_setup_information(sc)
+ struct bt_softc *sc;
{
+ int iobase = sc->sc_iobase;
struct bt_boardID bID;
- char dummy[8];
+ struct bt_board_info binfo;
+ char dummy[8], sub_ver[3];
struct bt_setup setup;
- int i;
+ int i, ver;
- /* Inquire Board ID to Bt742 for firmware version */
- bt_cmd(bt, 0, sizeof(bID), 0, &bID, BT_INQUIRE);
- printf(": version %c.%c, ", bID.firm_revision, bID.firm_version);
+ /*
+ * Get and print board hardware information.
+ */
+ bt_cmd(iobase, sc, 1, sizeof(binfo), 0, (u_char *)&binfo,
+ BT_GET_BOARD_INFO, sizeof(binfo));
+ printf(": Bt%c%c%c", binfo.id[0], binfo.id[1], binfo.id[2]);
+ if (binfo.id[3] != ' ')
+ printf("%c", binfo.id[3]);
+ if (binfo.version[0] != ' ')
+ printf("%c%s", binfo.version[0], binfo.version[1]);
+ printf("\n");
+
+ /*
+ * Inquire Board ID to Bt742 for board type and firmware version.
+ */
+ bt_cmd(iobase, sc, 0, sizeof(bID), 0, (u_char *)&bID, BT_INQUIRE);
+ ver = (bID.firm_revision - '0') * 10 + (bID.firm_version - '0');
- if (bID.firm_revision != '2') { /* XXXX */
- /* Enable round-robin scheme - appeared at firmware rev. 3.31 */
- bt_cmd(bt, 1, 0, 0, 0, BT_ROUND_ROBIN, BT_ENABLE);
+ /*
+ * Get the rest of the firmware version. Firmware revisions
+ * before 3.3 apparently don't accept the BT_INQUIRE_REV_FOURTH
+ * command.
+ */
+ i = 0;
+ bt_cmd(iobase, sc, 0, 1, 0, &sub_ver[i++], BT_INQUIRE_REV_THIRD);
+ if (ver >= 33)
+ bt_cmd(iobase, sc, 0, 1, 0, &sub_ver[i++],
+ BT_INQUIRE_REV_FOURTH);
+ if (sub_ver[i - 1] == ' ')
+ i--;
+ sub_ver[i] = '\0';
+
+ printf("%s: firmware version %c.%c%s, ", sc->sc_dev.dv_xname,
+ bID.firm_revision, bID.firm_version, sub_ver);
+
+ /* Enable round-robin scheme - appeared at firmware rev. 3.31 */
+ if (ver > 33 || (ver == 33 && sub_ver[0] >= 1)) {
+ bt_cmd(iobase, sc, 1, 0, 0, 0, BT_ROUND_ROBIN, BT_ENABLE);
}
/* Inquire Installed Devices (to force synchronous negotiation) */
- bt_cmd(bt, 0, sizeof(dummy), 10, dummy, BT_DEV_GET);
+ bt_cmd(iobase, sc, 0, sizeof(dummy), 10, dummy, BT_DEV_GET);
/* Obtain setup information from Bt742. */
- bt_cmd(bt, 1, sizeof(setup), 0, &setup, BT_SETUP_GET, sizeof(setup));
+ bt_cmd(iobase, sc, 1, sizeof(setup), 0, (u_char *)&setup, BT_SETUP_GET,
+ sizeof(setup));
- printf("%s, %s, %d mbxs",
+ printf("%s, %s, %d mailboxes",
setup.sync_neg ? "sync" : "async",
setup.parity ? "parity" : "no parity",
setup.num_mbx);
(!setup.sync[i].offset && !setup.sync[i].period))
continue;
printf("\n%s targ %d: sync, offset %d, period %dnsec",
- bt->sc_dev.dv_xname, i,
+ sc->sc_dev.dv_xname, i,
setup.sync[i].offset, setup.sync[i].period * 50 + 200);
}
}
struct scsi_xfer *xs;
{
struct scsi_link *sc_link = xs->sc_link;
- struct bt_softc *bt = sc_link->adapter_softc;
+ struct bt_softc *sc = sc_link->adapter_softc;
struct bt_ccb *ccb;
struct bt_scat_gath *sg;
int seg; /* scatter gather seg being worked on */
*/
flags = xs->flags;
if ((flags & (ITSDONE|INUSE)) != INUSE) {
- printf("%s: done or not in use?\n", bt->sc_dev.dv_xname);
+ printf("%s: done or not in use?\n", sc->sc_dev.dv_xname);
xs->flags &= ~ITSDONE;
xs->flags |= INUSE;
}
- if ((ccb = bt_get_ccb(bt, flags)) == NULL) {
+ if ((ccb = bt_get_ccb(sc, flags)) == NULL) {
xs->error = XS_DRIVER_STUFFUP;
return TRY_AGAIN_LATER;
}
* there's still data, must have run out of segs!
*/
printf("%s: bt_scsi_cmd, more than %d dma segs\n",
- bt->sc_dev.dv_xname, BT_NSEG);
+ sc->sc_dev.dv_xname, BT_NSEG);
xs->error = XS_DRIVER_STUFFUP;
- bt_free_ccb(bt, ccb, flags);
+ bt_free_ccb(sc, ccb, flags);
return COMPLETE;
}
} else { /* No data xfer, use non S/G values */
s = splbio();
- if (bt_send_mbo(bt, BT_MBO_START, ccb) == NULL) {
+ if (bt_send_mbo(sc, BT_MBO_START, ccb) == NULL) {
splx(s);
xs->error = XS_DRIVER_STUFFUP;
- bt_free_ccb(bt, ccb, flags);
+ bt_free_ccb(sc, ccb, flags);
return TRY_AGAIN_LATER;
}
/*
* If we can't use interrupts, poll on completion
*/
- if (bt_poll(bt, xs, xs->timeout)) {
+ if (bt_poll(sc, xs, xs->timeout)) {
bt_timeout(ccb);
- if (bt_poll(bt, xs, 2000))
+ if (bt_poll(sc, xs, 2000))
bt_timeout(ccb);
}
return COMPLETE;
* Poll a particular unit, looking for a particular xs
*/
int
-bt_poll(bt, xs, count)
- struct bt_softc *bt;
+bt_poll(sc, xs, count)
+ struct bt_softc *sc;
struct scsi_xfer *xs;
int count;
{
+ int iobase = sc->sc_iobase;
/* timeouts are in msec, so we loop in 1000 usec cycles */
while (count) {
* If we had interrupts enabled, would we
* have got an interrupt?
*/
- if (inb(BT_INTR_PORT) & BT_ANY_INTR)
- btintr(bt);
+ if (inb(iobase + BT_INTR_PORT) & BT_ANY_INTR)
+ btintr(sc);
if (xs->flags & ITSDONE)
return 0;
delay(1000); /* only happens in boot so ok */
struct bt_ccb *ccb = arg;
struct scsi_xfer *xs = ccb->xs;
struct scsi_link *sc_link = xs->sc_link;
- struct bt_softc *bt = sc_link->adapter_softc;
+ struct bt_softc *sc = sc_link->adapter_softc;
int s;
sc_print_addr(sc_link);
/*
* If the ccb's mbx is not free, then the board has gone Far East?
*/
- if (bt_ccb_phys_kv(bt, ccb->mbx->ccb_addr) == ccb &&
+ if (bt_ccb_phys_kv(sc, ccb->mbx->ccb_addr) == ccb &&
ccb->mbx->cmd != BT_MBO_FREE) {
- printf("%s: not taking commands!\n", bt->sc_dev.dv_xname);
+ printf("%s: not taking commands!\n", sc->sc_dev.dv_xname);
Debugger();
}
/* abort timed out */
printf(" AGAIN\n");
ccb->xs->retries = 0;
- bt_done(bt, ccb);
+ bt_done(sc, ccb);
} else {
/* abort the operation that has timed out */
printf("\n");
ccb->xs->error = XS_TIMEOUT;
ccb->flags = CCB_ABORTED;
- bt_send_mbo(bt, BT_MBO_ABORT, ccb);
+ bt_send_mbo(sc, BT_MBO_ABORT, ccb);
/* 2 secs for the abort */
if ((xs->flags & SCSI_POLL) == 0)
timeout(bt_timeout, ccb, 2 * hz);
}
void
-bt_print_active_ccbs(bt)
- struct bt_softc *bt;
+bt_print_active_ccbs(sc)
+ struct bt_softc *sc;
{
struct bt_ccb *ccb;
int i = 0;
while (i < CCB_HASH_SIZE) {
- ccb = bt->ccbhash[i];
+ ccb = sc->sc_ccbhash[i];
while (ccb) {
if (ccb->flags != CCB_FREE)
bt_print_ccb(ccb);
-/* $OpenBSD: com.c,v 1.9 1996/03/20 01:00:42 mickey Exp $ */
-/* $NetBSD: com.c,v 1.65 1996/02/10 20:23:18 christos Exp $ */
+/* $OpenBSD: com.c,v 1.10 1996/04/18 23:47:32 niklas Exp $ */
+/* $NetBSD: com.c,v 1.75 1996/03/10 09:01:24 cgd Exp $ */
/*-
- * Copyright (c) 1993, 1994, 1995 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1993, 1994, 1995, 1996
+ * Charles M. Hannum. All rights reserved.
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
#include <sys/device.h>
#include <machine/cpu.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/isa/comreg.h>
+#include <dev/isa/comvar.h>
#include <dev/ic/ns16550reg.h>
#ifdef COM_HAYESP
#include <dev/ic/hayespreg.h>
int sc_floods;
int sc_errors;
+ int sc_halt;
+
int sc_iobase;
#ifdef COM_HAYESP
int sc_hayespbase;
#endif
+
+ bus_chipset_tag_t sc_bc;
+ bus_io_handle_t sc_ioh;
+ bus_io_handle_t sc_hayespioh;
+
u_char sc_hwflags;
#define COM_HW_NOIEN 0x01
#define COM_HW_FIFO 0x02
#define COM_SW_CLOCAL 0x02
#define COM_SW_CRTSCTS 0x04
#define COM_SW_MDMBUF 0x08
- u_char sc_msr, sc_mcr, sc_lcr;
+ u_char sc_msr, sc_mcr, sc_lcr, sc_ier;
u_char sc_dtr;
u_char *sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend;
};
int comprobe __P((struct device *, void *, void *));
+#ifdef COM_HAYESP
+int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc));
+#endif
void comattach __P((struct device *, struct device *, void *));
int comopen __P((dev_t, int, int, struct proc *));
int comclose __P((dev_t, int, int, struct proc *));
int comparam __P((struct tty *, struct termios *));
void comstart __P((struct tty *));
+int cominit __P((bus_chipset_tag_t, bus_io_handle_t, int));
+
struct cfdriver comcd = {
NULL, "com", comprobe, comattach, DV_TTY, sizeof(struct com_softc)
};
-int comdefaultrate = TTYDEF_SPEED;
#ifdef COMCONSOLE
-int comconsole = COMCONSOLE;
+int comdefaultrate = CONSPEED; /* XXX why set default? */
#else
-int comconsole = -1;
+int comdefaultrate = TTYDEF_SPEED;
#endif
+int comconsaddr;
int comconsinit;
+int comconsattached;
+bus_chipset_tag_t comconsbc;
+bus_io_handle_t comconsioh;
+
int commajor;
int comsopen = 0;
int comevents = 0;
}
int
-comprobe1(iobase)
+comprobe1(bc, ioh, iobase)
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
int iobase;
{
int tmp;
int i,k;
/* force access to id reg */
- outb(iobase + com_lcr, 0);
- outb(iobase + com_iir, 0);
- for(i=0;i<32;i++) {
- k=inb(iobase + com_iir);
+ bus_io_write_1(bc, ioh, com_lcr, 0);
+ bus_io_write_1(bc, ioh, com_iir, 0);
+ for (i = 0; i < 32; i++) {
+ k = bus_io_read_1(bc, ioh, com_iir);
if (k & 0x38) {
- inb(iobase + com_data ); /* cleanup */
+ bus_io_read_1(bc, ioh, com_data); /* cleanup */
} else
break;
}
- if(i>=32)
+ if (i >= 32)
return 0;
return 1;
#ifdef COM_HAYESP
int
-comprobeHAYESP(iobase, sc)
- int iobase;
+comprobeHAYESP(hayespioh, sc)
+ bus_io_handle_t hayespioh;
struct com_softc *sc;
{
char val, dips;
int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
+ bus_chipset_tag_t bc = sc->sc_bc;
/*
* Hayes ESP cards have two iobases. One is for compatibility with
*/
/* Test for ESP signature */
- if ((inb(iobase) & 0xf3) == 0)
+ if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0)
return 0;
/*
*/
/* Get the dip-switch configurations */
- outb(iobase + HAYESP_CMD1, HAYESP_GETDIPS);
- dips = inb(iobase + HAYESP_STATUS1);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS);
+ dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1);
/* Determine which com port this ESP card services: bits 0,1 of */
/* dips is the port # (0-3); combaselist[val] is the com_iobase */
/* Check ESP Self Test bits. */
/* Check for ESP version 2.0: bits 4,5,6 == 010 */
- outb(iobase + HAYESP_CMD1, HAYESP_GETTEST);
- val = inb(iobase + HAYESP_STATUS1); /* Clear reg 1 */
- val = inb(iobase + HAYESP_STATUS2);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST);
+ val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */
+ val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2);
if ((val & 0x70) < 0x20) {
printf("-old (%o)", val & 0x70);
/* we do not support the necessary features */
*/
SET(sc->sc_hwflags, COM_HW_HAYESP);
- printf(", 1024k fifo\n");
+ printf(", 1024 byte fifo\n");
return 1;
}
#endif
struct device *parent;
void *match, *aux;
{
- struct isa_attach_args *ia = aux;
- int iobase = ia->ia_iobase;
+ struct cfdata *cf = match;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ int iobase, needioh;
+ int rv = 1;
+
+ if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) {
+ struct isa_attach_args *ia = aux;
+
+ bc = ia->ia_bc;
+ iobase = ia->ia_iobase;
+ needioh = 1;
+ } else {
+ struct commulti_attach_args *ca = aux;
+
+ if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave)
+ return (0);
- if (!comprobe1(iobase))
- return 0;
+ bc = ca->ca_bc;
+ iobase = ca->ca_iobase;
+ ioh = ca->ca_ioh;
+ needioh = 0;
+ }
- ia->ia_iosize = COM_NPORTS;
- ia->ia_msize = 0;
- return 1;
+ /* if it's in use as console, it's there. */
+ if (iobase == comconsaddr && !comconsattached)
+ goto out;
+
+ if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ rv = comprobe1(bc, ioh, iobase);
+ if (needioh)
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+
+out:
+ if (rv && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) {
+ struct isa_attach_args *ia = aux;
+
+ ia->ia_iosize = COM_NPORTS;
+ ia->ia_msize = 0;
+ }
+ return (rv);
}
void
void *aux;
{
struct com_softc *sc = (void *)self;
- struct isa_attach_args *ia = aux;
struct cfdata *cf = sc->sc_dev.dv_cfdata;
- int iobase = ia->ia_iobase;
+ int iobase, irq;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
struct tty *tp;
#ifdef COM_HAYESP
int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };
int *hayespp;
#endif
- sc->sc_iobase = iobase;
- sc->sc_hwflags = ISSET(cf->cf_flags, COM_HW_NOIEN);
+ sc->sc_hwflags = 0;
sc->sc_swflags = 0;
+ if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) {
+ struct isa_attach_args *ia = aux;
- if (sc->sc_dev.dv_unit == comconsole)
- delay(1000);
+ /*
+ * We're living on an isa.
+ */
+ iobase = ia->ia_iobase;
+ bc = ia->ia_bc;
+ if (iobase != comconsaddr) {
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh))
+ panic("comattach: io mapping failed");
+ } else
+ ioh = comconsioh;
+ irq = ia->ia_irq;
+ } else {
+ struct commulti_attach_args *ca = aux;
+
+ /*
+ * We're living on a commulti.
+ */
+ iobase = ca->ca_iobase;
+ bc = ca->ca_bc;
+ ioh = ca->ca_ioh;
+ irq = IRQUNK;
+
+ if (ca->ca_noien)
+ sc->sc_hwflags |= COM_HW_NOIEN;
+ }
+
+ sc->sc_bc = bc;
+ sc->sc_ioh = ioh;
+ sc->sc_iobase = iobase;
+
+ if (iobase == comconsaddr) {
+ comconsattached = 1;
+
+ /*
+ * Need to reset baud rate, etc. of next print so reset
+ * comconsinit. Also make sure console is always "hardwired".
+ */
+ delay(1000); /* wait for output to finish */
+ comconsinit = 0;
+ SET(sc->sc_hwflags, COM_HW_CONSOLE);
+ SET(sc->sc_swflags, COM_SW_SOFTCAR);
+ }
#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
- for (hayespp = hayesp_ports; *hayespp != 0; hayespp++)
- if (comprobeHAYESP(*hayespp, sc)) {
+ for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) {
+ bus_io_handle_t hayespioh;
+
+#define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */
+ if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh))
+ continue;
+ if (comprobeHAYESP(hayespioh, sc)) {
sc->sc_hayespbase = *hayespp;
+ sc->sc_hayespioh = hayespioh;
break;
}
+ bus_io_unmap(bc, hayespioh, HAYESP_NPORTS);
+ }
/* No ESP; look for other things. */
if (*hayespp == 0) {
#endif
/* look for a NS 16550AF UART with FIFOs */
- outb(iobase + com_fifo,
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
delay(100);
- if (ISSET(inb(iobase + com_iir), IIR_FIFO_MASK) == IIR_FIFO_MASK)
- if (ISSET(inb(iobase + com_fifo), FIFO_TRIGGER_14) == FIFO_TRIGGER_14) {
+ if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) ==
+ IIR_FIFO_MASK)
+ if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) ==
+ FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
printf(": ns16550a, working fifo\n");
} else
printf(": ns16550, broken fifo\n");
else
printf(": ns8250 or ns16450, no fifo\n");
- outb(iobase + com_fifo, 0);
+ bus_io_write_1(bc, ioh, com_fifo, 0);
#ifdef COM_HAYESP
}
#endif
/* disable interrupts */
- outb(iobase + com_ier, 0);
- outb(iobase + com_mcr, 0);
+ bus_io_write_1(bc, ioh, com_ier, 0);
+ bus_io_write_1(bc, ioh, com_mcr, 0);
- if (ia->ia_irq != IRQUNK)
- sc->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_TTY,
+ if (irq != IRQUNK)
+ sc->sc_ih = isa_intr_establish(irq, IST_EDGE, IPL_TTY,
comintr, sc, sc->sc_dev.dv_xname);
#ifdef KGDB
if (kgdb_dev == makedev(commajor, unit)) {
- if (comconsole == unit)
+ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
kgdb_dev = -1; /* can't debug over console port */
else {
- (void) cominit(unit, kgdb_rate);
+ (void) cominit(bc, ioh, kgdb_rate);
if (kgdb_debug_init) {
/*
* Print prefix of device name,
}
#endif
- if (sc->sc_dev.dv_unit == comconsole) {
- /*
- * Need to reset baud rate, etc. of next print so reset
- * comconsinit. Also make sure console is always "hardwired".
- */
- comconsinit = 0;
- SET(sc->sc_hwflags, COM_HW_CONSOLE);
- SET(sc->sc_swflags, COM_SW_SOFTCAR);
- }
+ /* XXX maybe move up some? */
+ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
+ printf("%s: console\n", sc->sc_dev.dv_xname);
}
int
{
int unit = COMUNIT(dev);
struct com_softc *sc;
- int iobase;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
struct tty *tp;
int s;
int error = 0;
sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER;
sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
- iobase = sc->sc_iobase;
+ bc = sc->sc_bc;
+ ioh = sc->sc_ioh;
#ifdef COM_HAYESP
/* Setup the ESP board */
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
- int hayespbase = sc->sc_hayespbase;
+ bus_io_handle_t hayespioh = sc->sc_hayespioh;
- outb(iobase + com_fifo,
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_DMA_MODE|FIFO_ENABLE|
FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8);
/* Set 16550 compatibility mode */
- outb(hayespbase + HAYESP_CMD1, HAYESP_SETMODE);
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
HAYESP_MODE_SCALE);
/* Set RTS/CTS flow control */
- outb(hayespbase + HAYESP_CMD1, HAYESP_SETFLOWTYPE);
- outb(hayespbase + HAYESP_CMD2, HAYESP_FLOW_RTS);
- outb(hayespbase + HAYESP_CMD2, HAYESP_FLOW_CTS);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS);
/* Set flow control levels */
- outb(hayespbase + HAYESP_CMD1, HAYESP_SETRXFLOW);
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW);
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXHIWMARK));
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXHIWMARK));
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_HIBYTE(HAYESP_RXLOWMARK));
- outb(hayespbase + HAYESP_CMD2,
+ bus_io_write_1(bc, hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
} else
#endif
if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
/* Set the FIFO threshold based on the receive speed. */
- outb(iobase + com_fifo,
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
(tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
/* flush any pending I/O */
- while (ISSET(inb(iobase + com_lsr), LSR_RXRDY))
- (void) inb(iobase + com_data);
+ while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
+ (void) bus_io_read_1(bc, ioh, com_data);
/* you turn me on, baby */
sc->sc_mcr = MCR_DTR | MCR_RTS;
if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
SET(sc->sc_mcr, MCR_IENABLE);
- outb(iobase + com_mcr, sc->sc_mcr);
- outb(iobase + com_ier,
- IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
+ bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
- sc->sc_msr = inb(iobase + com_msr);
+ sc->sc_msr = bus_io_read_1(bc, ioh, com_msr);
if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) ||
ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF))
SET(tp->t_state, TS_CARR_ON);
int unit = COMUNIT(dev);
struct com_softc *sc = comcd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int s;
/* XXX This is for cons.c. */
(*linesw[tp->t_line].l_close)(tp, flag);
s = spltty();
CLR(sc->sc_lcr, LCR_SBREAK);
- outb(iobase + com_lcr, sc->sc_lcr);
- outb(iobase + com_ier, 0);
+ bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
+ bus_io_write_1(bc, ioh, com_ier, 0);
if (ISSET(tp->t_cflag, HUPCL) &&
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) {
/* XXX perhaps only clear DTR */
- outb(iobase + com_mcr, 0);
+ bus_io_write_1(bc, ioh, com_mcr, 0);
}
CLR(tp->t_state, TS_BUSY | TS_FLUSH);
if (--comsopen == 0)
splx(s);
ttyclose(tp);
#ifdef notyet /* XXXX */
- if (unit != comconsole) {
+ if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
ttyfree(tp);
sc->sc_tty = 0;
}
int unit = COMUNIT(dev);
struct com_softc *sc = comcd.cd_devs[unit];
struct tty *tp = sc->sc_tty;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int error;
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
switch (cmd) {
case TIOCSBRK:
SET(sc->sc_lcr, LCR_SBREAK);
- outb(iobase + com_lcr, sc->sc_lcr);
+ bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCCBRK:
CLR(sc->sc_lcr, LCR_SBREAK);
- outb(iobase + com_lcr, sc->sc_lcr);
+ bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr);
break;
case TIOCSDTR:
SET(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCCDTR:
CLR(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMSET:
CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
case TIOCMBIS:
SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMBIC:
CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
break;
case TIOCMGET: {
u_char m;
SET(bits, TIOCM_DSR);
if (ISSET(m, MSR_RI | MSR_TERI))
SET(bits, TIOCM_RI);
- if (inb(iobase + com_ier))
+ if (bus_io_read_1(bc, ioh, com_ier))
SET(bits, TIOCM_LE);
*(int *)data = bits;
break;
struct termios *t;
{
struct com_softc *sc = comcd.cd_devs[COMUNIT(tp->t_dev)];
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int ospeed = comspeed(t->c_ospeed);
u_char lcr;
tcflag_t oldcflag;
if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
return EINVAL;
- lcr = sc->sc_lcr & LCR_SBREAK;
+ lcr = ISSET(sc->sc_lcr, LCR_SBREAK);
switch (ISSET(t->c_cflag, CSIZE)) {
case CS5:
if (ospeed == 0) {
CLR(sc->sc_mcr, MCR_DTR);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
/*
* Set the FIFO threshold based on the receive speed, if we are
* changing it.
*/
+#if 1
if (tp->t_ispeed != t->c_ispeed) {
- if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
- outb(iobase + com_fifo,
+#else
+ if (1) {
+#endif
+ if (ospeed != 0) {
+ /*
+ * Make sure the transmit FIFO is empty before
+ * proceeding. If we don't do this, some revisions
+ * of the UART will hang. Interestingly enough,
+ * even if we do this will the last character is
+ * still being pushed out, they don't hang. This
+ * seems good enough.
+ */
+ while (ISSET(tp->t_state, TS_BUSY)) {
+ int error;
+
+ ++sc->sc_halt;
+ error = ttysleep(tp, &tp->t_outq,
+ TTOPRI | PCATCH, "comprm", 0);
+ --sc->sc_halt;
+ if (error) {
+ splx(s);
+ comstart(tp);
+ return (error);
+ }
+ }
+
+ bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB);
+ bus_io_write_1(bc, ioh, com_dlbl, ospeed);
+ bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8);
+ bus_io_write_1(bc, ioh, com_lcr, lcr);
+ SET(sc->sc_mcr, MCR_DTR);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
+ } else
+ bus_io_write_1(bc, ioh, com_lcr, lcr);
+
+ if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) &&
+ ISSET(sc->sc_hwflags, COM_HW_FIFO))
+ bus_io_write_1(bc, ioh, com_fifo,
FIFO_ENABLE |
(t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
- }
-
- if (ospeed != 0) {
- outb(iobase + com_lcr, lcr | LCR_DLAB);
- outb(iobase + com_dlbl, ospeed);
- outb(iobase + com_dlbh, ospeed >> 8);
- outb(iobase + com_lcr, lcr);
- SET(sc->sc_mcr, MCR_DTR);
- outb(iobase + com_mcr, sc->sc_mcr);
} else
- outb(iobase + com_lcr, lcr);
+ bus_io_write_1(bc, ioh, com_lcr, lcr);
/* When not using CRTSCTS, RTS follows DTR. */
if (!ISSET(t->c_cflag, CRTSCTS)) {
if (ISSET(sc->sc_mcr, MCR_DTR)) {
if (!ISSET(sc->sc_mcr, MCR_RTS)) {
SET(sc->sc_mcr, MCR_RTS);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
} else {
if (ISSET(sc->sc_mcr, MCR_RTS)) {
CLR(sc->sc_mcr, MCR_RTS);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
}
sc->sc_dtr = MCR_DTR | MCR_RTS;
ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
+ /* Just to be sure... */
splx(s);
+ comstart(tp);
return 0;
}
struct tty *tp;
{
struct com_softc *sc = comcd.cd_devs[COMUNIT(tp->t_dev)];
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int s;
s = spltty();
- if (ISSET(tp->t_state, TS_TTSTOP | TS_BUSY))
+ if (ISSET(tp->t_state, TS_BUSY))
goto out;
+ if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) ||
+ sc->sc_halt > 0)
+ goto stopped;
if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS))
- goto out;
+ goto stopped;
if (tp->t_outq.c_cc <= tp->t_lowat) {
if (ISSET(tp->t_state, TS_ASLEEP)) {
CLR(tp->t_state, TS_ASLEEP);
wakeup(&tp->t_outq);
}
if (tp->t_outq.c_cc == 0)
- goto out;
+ goto stopped;
selwakeup(&tp->t_wsel);
}
SET(tp->t_state, TS_BUSY);
+ if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
+ SET(sc->sc_ier, IER_ETXRDY);
+ bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ }
#ifdef COM_HAYESP
if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) {
u_char buffer[1024], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do
- outb(iobase + com_data, *cp++);
+ bus_io_write_1(bc, ioh, com_data, *cp++);
while (--n);
}
else
u_char buffer[16], *cp = buffer;
int n = q_to_b(&tp->t_outq, cp, sizeof buffer);
do {
- outb(iobase + com_data, *cp++);
+ bus_io_write_1(bc, ioh, com_data, *cp++);
} while (--n);
} else
- outb(iobase + com_data, getc(&tp->t_outq));
+ bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq));
out:
splx(s);
+ return;
+stopped:
+ if (ISSET(sc->sc_ier, IER_ETXRDY)) {
+ CLR(sc->sc_ier, IER_ETXRDY);
+ bus_io_write_1(bc, ioh, com_ier, sc->sc_ier);
+ }
+ splx(s);
}
/*
!ISSET(sc->sc_mcr, MCR_RTS)) {
/* XXX */
SET(sc->sc_mcr, MCR_RTS);
- outb(sc->sc_iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr,
+ sc->sc_mcr);
}
splx(s);
void *arg;
{
struct com_softc *sc = arg;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
struct tty *tp;
u_char lsr, data, msr, delta;
+#ifdef COM_DEBUG
+ int n;
+ struct {
+ u_char iir, lsr, msr;
+ } iter[32];
+#endif
- if (ISSET(inb(iobase + com_iir), IIR_NOPEND))
+#ifdef COM_DEBUG
+ n = 0;
+ if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ return (0);
+#else
+ if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
return (0);
+#endif
tp = sc->sc_tty;
for (;;) {
- lsr = inb(iobase + com_lsr);
+#ifdef COM_DEBUG
+ iter[n].lsr =
+#endif
+ lsr = bus_io_read_1(bc, ioh, com_lsr);
- if (ISSET(lsr, LSR_RCV_MASK)) {
+ if (ISSET(lsr, LSR_RXRDY)) {
register u_char *p = sc->sc_ibufp;
comevents = 1;
do {
- data = ISSET(lsr, LSR_RXRDY) ?
- inb(iobase + com_data) : 0;
+ data = bus_io_read_1(bc, ioh, com_data);
if (ISSET(lsr, LSR_BI)) {
+#ifdef notdef
+ printf("break %02x %02x %02x %02x\n",
+ sc->sc_msr, sc->sc_mcr, sc->sc_lcr,
+ sc->sc_dtr);
+#endif
#ifdef DDB
- if (sc->sc_dev.dv_unit == comconsole) {
+ if (ISSET(sc->sc_hwflags,
+ COM_HW_CONSOLE)) {
Debugger();
goto next;
}
#endif
- data = '\0';
}
if (p >= sc->sc_ibufend) {
sc->sc_floods++;
ISSET(tp->t_cflag, CRTSCTS)) {
/* XXX */
CLR(sc->sc_mcr, MCR_RTS);
- outb(iobase + com_mcr,
- sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr,
+ sc->sc_mcr);
}
}
next:
- lsr = inb(iobase + com_lsr);
- } while (ISSET(lsr, LSR_RCV_MASK));
+#ifdef COM_DEBUG
+ if (++n >= 32)
+ goto ohfudge;
+ iter[n].lsr =
+#endif
+ lsr = bus_io_read_1(bc, ioh, com_lsr);
+ } while (ISSET(lsr, LSR_RXRDY));
sc->sc_ibufp = p;
}
-#if 0
+#ifdef COM_DEBUG
else if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE))
printf("weird lsr %02x\n", lsr);
#endif
- msr = inb(iobase + com_msr);
+#ifdef COM_DEBUG
+ iter[n].msr =
+#endif
+ msr = bus_io_read_1(bc, ioh, com_msr);
if (msr != sc->sc_msr) {
delta = msr ^ sc->sc_msr;
!ISSET(sc->sc_swflags, COM_SW_SOFTCAR) &&
(*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) {
CLR(sc->sc_mcr, sc->sc_dtr);
- outb(iobase + com_mcr, sc->sc_mcr);
+ bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr);
}
if (ISSET(delta & msr, MSR_CTS) &&
ISSET(tp->t_cflag, CRTSCTS)) {
}
if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) {
- CLR(tp->t_state, TS_BUSY);
- if (ISSET(tp->t_state, TS_FLUSH))
- CLR(tp->t_state, TS_FLUSH);
- else
- (*linesw[tp->t_line].l_start)(tp);
+ CLR(tp->t_state, TS_BUSY | TS_FLUSH);
+ if (sc->sc_halt > 0)
+ wakeup(&tp->t_outq);
+ (*linesw[tp->t_line].l_start)(tp);
}
- if (ISSET(inb(iobase + com_iir), IIR_NOPEND))
+#ifdef COM_DEBUG
+ if (++n >= 32)
+ goto ohfudge;
+ if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
+ return (1);
+#else
+ if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND))
return (1);
+#endif
+ }
+#ifdef COM_DEBUG
+ohfudge:
+ printf("comintr: too many iterations");
+ for (n = 0; n < 32; n++) {
+ if ((n % 4) == 0)
+ printf("\ncomintr: iter[%02d]", n);
+ printf(" %02x %02x %02x", iter[n].iir, iter[n].lsr, iter[n].msr);
}
+ printf("\n");
+ printf("comintr: msr %02x mcr %02x lcr %02x ier %02x\n",
+ sc->sc_msr, sc->sc_mcr, sc->sc_lcr, sc->sc_ier);
+ printf("comintr: state %08x cc %d\n", sc->sc_tty->t_state,
+ sc->sc_tty->t_outq.c_cc);
+#endif
}
/*
comcnprobe(cp)
struct consdev *cp;
{
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ int found;
- if (!comprobe1(CONADDR)) {
+#if 0
+ XXX NEEDS TO BE FIXED XXX
+ bc = ???;
+#endif
+ if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) {
+ cp->cn_pri = CN_DEAD;
+ return;
+ }
+ found = comprobe1(bc, ioh, CONADDR);
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ if (!found) {
cp->cn_pri = CN_DEAD;
return;
}
struct consdev *cp;
{
- cominit(CONUNIT, comdefaultrate);
- comconsole = CONUNIT;
+#if 0
+ XXX NEEDS TO BE FIXED XXX
+ comconsbc = ???;
+#endif
+ if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh))
+ panic("comcninit: mapping failed");
+
+ cominit(comconsbc, comconsioh, comdefaultrate);
+ comconsaddr = CONADDR;
comconsinit = 0;
}
-cominit(unit, rate)
- int unit, rate;
+cominit(bc, ioh, rate)
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ int rate;
{
int s = splhigh();
- int iobase = CONADDR;
u_char stat;
- outb(iobase + com_lcr, LCR_DLAB);
+ bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB);
rate = comspeed(comdefaultrate);
- outb(iobase + com_dlbl, rate);
- outb(iobase + com_dlbh, rate >> 8);
- outb(iobase + com_lcr, LCR_8BITS);
- outb(iobase + com_ier, IER_ERXRDY | IER_ETXRDY);
- outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
- stat = inb(iobase + com_iir);
+ bus_io_write_1(bc, ioh, com_dlbl, rate);
+ bus_io_write_1(bc, ioh, com_dlbh, rate >> 8);
+ bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS);
+ bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY);
+ bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4);
+ stat = bus_io_read_1(bc, ioh, com_iir);
splx(s);
}
dev_t dev;
{
int s = splhigh();
- int iobase = CONADDR;
+ bus_chipset_tag_t bc = comconsbc;
+ bus_io_handle_t ioh = comconsioh;
u_char stat, c;
- while (!ISSET(stat = inb(iobase + com_lsr), LSR_RXRDY))
+ while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY))
;
- c = inb(iobase + com_data);
- stat = inb(iobase + com_iir);
+ c = bus_io_read_1(bc, ioh, com_data);
+ stat = bus_io_read_1(bc, ioh, com_iir);
splx(s);
return c;
}
int c;
{
int s = splhigh();
- int iobase = CONADDR;
+ bus_chipset_tag_t bc = comconsbc;
+ bus_io_handle_t ioh = comconsioh;
u_char stat;
register int timo;
if (dev != kgdb_dev)
#endif
if (comconsinit == 0) {
- (void) cominit(COMUNIT(dev), comdefaultrate);
+ (void) cominit(bc, ioh, comdefaultrate);
comconsinit = 1;
}
/* wait for any pending transmission to finish */
timo = 50000;
- while (!ISSET(stat = inb(iobase + com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
;
- outb(iobase + com_data, c);
+ bus_io_write_1(bc, ioh, com_data, c);
/* wait for this transmission to complete */
timo = 1500000;
- while (!ISSET(stat = inb(iobase + com_lsr), LSR_TXRDY) && --timo)
+ while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo)
;
/* clear any interrupts generated by this transmission */
- stat = inb(iobase + com_iir);
+ stat = bus_io_read_1(bc, ioh, com_iir);
splx(s);
}
-# $OpenBSD: files.isa,v 1.6 1996/02/27 11:12:56 niklas Exp $
-# $NetBSD: files.isa,v 1.10 1996/01/13 02:05:15 thorpej Exp $
+# $OpenBSD: files.isa,v 1.7 1996/04/18 23:47:33 niklas Exp $
+# $NetBSD: files.isa,v 1.12 1996/03/04 03:29:16 cgd Exp $
#
# Config.new file and device description for machine-independent ISA code.
# Included by ports that need it. Requires that the SCSI files be
# defined first.
-# ports should define their own "device isa" line (like the one below,
-# but with the correct bus attachment). IT MUST USE CONFIGURATION
-# LOCATORS IDENTICAL TO THOSE SPECIFIED BELOW.
-
# ports should specify appropriate major numbers for the following
# devices:
# mcd, scd, wd, wt
-#device isa at root {[port = -1], [size = 0],
-# [iomem = -1], [iosiz = 0],
-# [irq = -1], [drq = -1]}
+define isa {[port = -1], [size = 0],
+ [iomem = -1], [iosiz = 0],
+ [irq = -1], [drq = -1]}
+
+device isa at isabus: isa
file dev/isa/isa.c isa needs-flag
# ISA DMA controller
define isadma
file dev/isa/isadma.c isadma needs-flag
-#pcmcia
+# PCMCIA
+# XXX What is this?
#config problems
#device pcic at isa
#file dev/isa/pcmcia_pcic.c pcic pcmciabus
-file dev/isa/pcmcia_isa.c pcmciabus
+
+define pcicbus {[iomem = -1], [iosiz = 0]}
+
+device pcic at isa: pcicbus
+file dev/isa/pcmcia_pcic.c pcic
+
+file dev/isa/pcmcia_isa.c pcmcia
+
+#
+# PCMCIA-only drivers
+#
+
+include "../../../dev/pcmcia/files.pcmcia"
+
#
# 8250/16[45]50-based multi-port serial boards
#
# 8250/16[45]50-based "com" ports
-device com at isa, commulti, pcmciabus: tty
+device com at isa, commulti: tty
file dev/isa/com.c com needs-flag
# Cyclades Cyclom multiport serial cards
# National Semiconductor DS8390/WD83C690-based boards
# (WD/SMC 80x3 family, SMC Ultra [8216], 3Com 3C503, NE[12]000, and clones)
# XXX conflicts with amiga if_ed.c
-#device ed at isa, pcmciabus: ether, ifnet
+#device ed at isa, pcmcia: ether, ifnet
#file dev/isa/if_ed.c ed needs-flag
# 3Com 3C505
file dev/isa/if_el.c el
# 3Com 3C5x9, 3c59x (EtherLink III) family
-device ep at isa, pci, pcmciabus: ether, ifnet, elink
+device ep at isa, pci: ether, ifnet, elink
file dev/isa/if_ep.c ep needs-flag
# Fujitsu MB8696[05]-based boards
-/* $OpenBSD: gus.c,v 1.7 1996/03/20 01:00:44 mickey Exp $ */
-/* $NetBSD: gus.c,v 1.7 1996/02/16 08:18:37 mycroft Exp $ */
+/* $OpenBSD: gus.c,v 1.8 1996/04/18 23:47:34 niklas Exp $ */
+/* $NetBSD: gus.c,v 1.10 1996/03/01 04:08:31 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
#include <dev/isa/ad1848var.h>
#include "gusreg.h"
+#ifdef AUDIO_DEBUG
+#define STATIC /* empty; for debugging symbols */
+#else
+#define STATIC static
+#endif
+
/*
* Software state of a single "voice" on the GUS
*/
int gusmax_get_in_port __P((void *));
int gus_getdev __P((void *, struct audio_device *));
-static void gus_deinterleave __P((struct gus_softc *, void *, int));
-static void gus_expand __P((void *, int, u_char *, int));
-static void gusmax_expand __P((void *, int, u_char *, int));
-
-static int gus_mic_ctl __P((void *, int));
-static int gus_linein_ctl __P((void *, int));
-static int gus_test_iobase __P((int));
-static void guspoke __P((int, long, u_char));
-static void gusdmaout __P((struct gus_softc *, int, u_long, caddr_t, int));
-static void gus_init_cs4231 __P((struct gus_softc *));
-static void gus_init_ics2101 __P((struct gus_softc *));
-
-static void gus_set_chan_addrs __P((struct gus_softc *));
-static void gusreset __P((struct gus_softc *, int));
-static void gus_set_voices __P((struct gus_softc *, int));
-static void gus_set_volume __P((struct gus_softc *, int, int));
-static void gus_set_samprate __P((struct gus_softc *, int, int));
-static void gus_set_recrate __P((struct gus_softc *, u_long));
-static void gus_start_voice __P((struct gus_softc *, int, int)),
+STATIC void gus_deinterleave __P((struct gus_softc *, void *, int));
+STATIC void gus_expand __P((void *, int, u_char *, int));
+STATIC void gusmax_expand __P((void *, int, u_char *, int));
+
+STATIC int gus_mic_ctl __P((void *, int));
+STATIC int gus_linein_ctl __P((void *, int));
+STATIC int gus_test_iobase __P((int));
+STATIC void guspoke __P((int, long, u_char));
+STATIC void gusdmaout __P((struct gus_softc *, int, u_long, caddr_t, int));
+STATIC void gus_init_cs4231 __P((struct gus_softc *));
+STATIC void gus_init_ics2101 __P((struct gus_softc *));
+
+STATIC void gus_set_chan_addrs __P((struct gus_softc *));
+STATIC void gusreset __P((struct gus_softc *, int));
+STATIC void gus_set_voices __P((struct gus_softc *, int));
+STATIC void gus_set_volume __P((struct gus_softc *, int, int));
+STATIC void gus_set_samprate __P((struct gus_softc *, int, int));
+STATIC void gus_set_recrate __P((struct gus_softc *, u_long));
+STATIC void gus_start_voice __P((struct gus_softc *, int, int)),
gus_stop_voice __P((struct gus_softc *, int, int)),
gus_set_endaddr __P((struct gus_softc *, int, u_long)),
gus_set_curaddr __P((struct gus_softc *, int, u_long));
-static u_long gus_get_curaddr __P((struct gus_softc *, int));
-static int gus_dmaout_intr __P((struct gus_softc *));
-static void gus_dmaout_dointr __P((struct gus_softc *));
-static void gus_dmaout_timeout __P((void *));
-static int gus_dmain_intr __P((struct gus_softc *));
-static int gus_voice_intr __P((struct gus_softc *));
-static void gus_start_playing __P((struct gus_softc *, int));
-static void gus_continue_playing __P((struct gus_softc *, int));
-static u_char guspeek __P((int, u_long));
-static unsigned long convert_to_16bit();
-static int gus_setfd __P((void *, int));
-static int gus_mixer_set_port __P((void *, mixer_ctrl_t *));
-static int gus_mixer_get_port __P((void *, mixer_ctrl_t *));
-static int gusmax_mixer_set_port __P((void *, mixer_ctrl_t *));
-static int gusmax_mixer_get_port __P((void *, mixer_ctrl_t *));
-static int gus_mixer_query_devinfo __P((void *, mixer_devinfo_t *));
-static int gusmax_mixer_query_devinfo __P((void *, mixer_devinfo_t *));
-static int gus_query_encoding __P((void *, struct audio_encoding *));
-
-static void gusics_master_mute __P((struct ics2101_softc *, int));
-static void gusics_dac_mute __P((struct ics2101_softc *, int));
-static void gusics_mic_mute __P((struct ics2101_softc *, int));
-static void gusics_linein_mute __P((struct ics2101_softc *, int));
-static void gusics_cd_mute __P((struct ics2101_softc *, int));
+STATIC u_long gus_get_curaddr __P((struct gus_softc *, int));
+STATIC int gus_dmaout_intr __P((struct gus_softc *));
+STATIC void gus_dmaout_dointr __P((struct gus_softc *));
+STATIC void gus_dmaout_timeout __P((void *));
+STATIC int gus_dmain_intr __P((struct gus_softc *));
+STATIC int gus_voice_intr __P((struct gus_softc *));
+STATIC void gus_start_playing __P((struct gus_softc *, int));
+STATIC int gus_continue_playing __P((struct gus_softc *, int));
+STATIC u_char guspeek __P((int, u_long));
+STATIC unsigned long convert_to_16bit();
+STATIC int gus_setfd __P((void *, int));
+STATIC int gus_mixer_set_port __P((void *, mixer_ctrl_t *));
+STATIC int gus_mixer_get_port __P((void *, mixer_ctrl_t *));
+STATIC int gusmax_mixer_set_port __P((void *, mixer_ctrl_t *));
+STATIC int gusmax_mixer_get_port __P((void *, mixer_ctrl_t *));
+STATIC int gus_mixer_query_devinfo __P((void *, mixer_devinfo_t *));
+STATIC int gusmax_mixer_query_devinfo __P((void *, mixer_devinfo_t *));
+STATIC int gus_query_encoding __P((void *, struct audio_encoding *));
+
+STATIC void gusics_master_mute __P((struct ics2101_softc *, int));
+STATIC void gusics_dac_mute __P((struct ics2101_softc *, int));
+STATIC void gusics_mic_mute __P((struct ics2101_softc *, int));
+STATIC void gusics_linein_mute __P((struct ics2101_softc *, int));
+STATIC void gusics_cd_mute __P((struct ics2101_softc *, int));
/*
* ISA bus driver routines
int
gusprobe(parent, match, aux)
- struct device *parent, *self;
+ struct device *parent;
void *match, *aux;
{
register struct gus_softc *sc = match;
* if it is.
*/
-static int
+STATIC int
gus_test_iobase (int iobase)
{
int i = splgus();
return 0;
}
-static void
+STATIC void
gusmax_expand(hdl, encoding, buf, count)
void *hdl;
int encoding;
gus_expand(ac->parent, encoding, buf, count);
}
-static void
+STATIC void
gus_expand(hdl, encoding, buf, count)
void *hdl;
int encoding;
gus_deinterleave(sc, (void *)buf, count);
}
-static void
+STATIC void
gus_deinterleave(sc, buf, size)
register struct gus_softc *sc;
void *buf;
int playcntr;
-static void
+STATIC void
gus_dmaout_timeout(arg)
void *arg;
{
* a DMA transfer for playback/record requests from the audio layer.
*/
-static int
+STATIC int
gus_dmaout_intr(sc)
struct gus_softc *sc;
{
return 0;
}
-static void
+STATIC void
gus_dmaout_dointr(sc)
struct gus_softc *sc;
{
register int port = sc->sc_iobase;
/* sc->sc_dmaoutcnt - 1 because DMA controller counts from zero?. */
- isa_dmadone(B_WRITE,
+ isa_dmadone(DMAMODE_WRITE,
sc->sc_dmaoutaddr,
sc->sc_dmaoutcnt - 1,
sc->sc_drq);
* Service voice interrupts
*/
-static int
+STATIC int
gus_voice_intr(sc)
struct gus_softc *sc;
{
gus_start_playing(sc, sc->sc_playbuf);
} else if (sc->sc_bufcnt < 0) {
#ifdef DDB
- printf("negative bufcnt in stopped voice\n");
+ printf("%s: negative bufcnt in stopped voice\n",
+ sc->sc_dev.dv_xname);
Debugger();
#else
- panic("negative bufcnt in stopped voice");
+ panic("%s: negative bufcnt in stopped voice",
+ sc->sc_dev.dv_xname);
#endif
} else {
sc->sc_playbuf = -1; /* none are active */
* is not stopped.
*/
gus_continues++;
- gus_continue_playing(sc, voice);
+ if (gus_continue_playing(sc, voice)) {
+ /*
+ * we shouldn't have continued--active DMA
+ * is in the way in the ring, for
+ * some as-yet undebugged reason.
+ */
+ gus_stop_voice(sc, GUS_VOICE_LEFT, 1);
+ /* also kill right voice */
+ gus_stop_voice(sc, GUS_VOICE_RIGHT, 0);
+ sc->sc_playbuf = -1;
+ gus_stops++;
+ }
}
/*
* call the upper level to send on down another
}
}
-static void
+STATIC void
gus_start_playing(sc, bufno)
struct gus_softc *sc;
int bufno;
sc->sc_playbuf = bufno;
}
-static void
+STATIC int
gus_continue_playing(sc, voice)
register struct gus_softc *sc;
int voice;
if (--sc->sc_bufcnt == 0) {
DPRINTF(("gus: bufcnt 0 on continuing voice?\n"));
}
- if (sc->sc_playbuf == sc->sc_dmabuf && (sc->sc_flags & GUS_LOCKED))
- printf("continue into active dmabuf?\n");
+ if (sc->sc_playbuf == sc->sc_dmabuf && (sc->sc_flags & GUS_LOCKED)) {
+ printf("%s: continue into active dmabuf?\n", sc->sc_dev.dv_xname);
+ return 1;
+ }
/*
* Select the end of the buffer based on the currently active
outb(port+GUS_DATA_HIGH, sc->sc_voc[voice].voccntl);
SELECT_GUS_REG(port, GUSREG_VOLUME_CONTROL);
outb(port+GUS_DATA_HIGH, sc->sc_voc[voice].volcntl);
+ return 0;
}
/*
* Send/receive data into GUS's DRAM using DMA. Called at splgus()
*/
-static void
+STATIC void
gusdmaout(sc, flags, gusaddr, buffaddr, length)
struct gus_softc *sc;
int flags, length;
sc->sc_dmaoutaddr = (u_char *) buffaddr;
sc->sc_dmaoutcnt = length;
- isa_dmastart(B_WRITE, buffaddr, length, sc->sc_drq);
+ isa_dmastart(DMAMODE_WRITE, buffaddr, length, sc->sc_drq);
/*
* Set up DMA address - use the upper 16 bits ONLY
* splgus().
*/
-static void
+STATIC void
gus_start_voice(sc, voice, intrs)
struct gus_softc *sc;
int voice;
* Stop a given voice. called at splgus()
*/
-static void
+STATIC void
gus_stop_voice(sc, voice, intrs_too)
struct gus_softc *sc;
int voice;
/*
* Set the volume of a given voice. Called at splgus().
*/
-static void
+STATIC void
gus_set_volume(sc, voice, volume)
struct gus_softc *sc;
int voice, volume;
return 0;
}
-static inline void gus_set_voices(sc, voices)
+STATIC inline void gus_set_voices(sc, voices)
struct gus_softc *sc;
int voices;
{
return 0;
}
-static void
+STATIC void
gus_set_chan_addrs(sc)
struct gus_softc *sc;
{
* Set the sample rate of the given voice. Called at splgus().
*/
-static void
+STATIC void
gus_set_samprate(sc, voice, freq)
struct gus_softc *sc;
int voice, freq;
* SDK. Called at splgus().
*/
-static void
+STATIC void
gus_set_recrate(sc, rate)
struct gus_softc *sc;
u_long rate;
return 0;
}
-static int
+STATIC int
gus_linein_ctl(addr, newstate)
void * addr;
int newstate;
return 0;
}
-static int
+STATIC int
gus_mic_ctl(addr, newstate)
void * addr;
int newstate;
* Set the end address of a give voice. Called at splgus()
*/
-static void
+STATIC void
gus_set_endaddr(sc, voice, addr)
struct gus_softc *sc;
int voice;
/*
* Set current address. called at splgus()
*/
-static void
+STATIC void
gus_set_curaddr(sc, voice, addr)
struct gus_softc *sc;
int voice;
/*
* Get current GUS playback address. Called at splgus().
*/
-static unsigned long
+STATIC unsigned long
gus_get_curaddr(sc, voice)
struct gus_softc *sc;
int voice;
* have NO idea
*/
-static unsigned long
+STATIC unsigned long
convert_to_16bit(address)
unsigned long address;
{
* Write a value into the GUS's DRAM
*/
-static void
+STATIC void
guspoke(port, address, value)
int port;
long address;
* Read a value from the GUS's DRAM
*/
-static unsigned char
+STATIC unsigned char
guspeek(port, address)
int port;
u_long address;
* Reset the Gravis UltraSound card, completely
*/
-static void
+STATIC void
gusreset(sc, voices)
struct gus_softc *sc;
int voices;
}
-static void
+STATIC void
gus_init_cs4231(sc)
struct gus_softc *sc;
{
dmac |= GUSMASK_SAMPLE_INVBIT;
if (sc->sc_channels == 2)
dmac |= GUSMASK_SAMPLE_STEREO;
- isa_dmastart(B_READ, (caddr_t) buf, size, sc->sc_recdrq);
+ isa_dmastart(DMAMODE_READ, (caddr_t) buf, size, sc->sc_recdrq);
DMAPRINTF(("gus_dma_input isa_dmastarted\n"));
sc->sc_flags |= GUS_DMAIN_ACTIVE;
return 0;
}
-static int
+STATIC int
gus_dmain_intr(sc)
struct gus_softc *sc;
{
DMAPRINTF(("gus_dmain_intr called\n"));
if (sc->sc_dmainintr) {
- isa_dmadone(B_READ, sc->sc_dmainaddr, sc->sc_dmaincnt - 1,
+ isa_dmadone(DMAMODE_READ, sc->sc_dmainaddr, sc->sc_dmaincnt - 1,
sc->sc_recdrq);
callback = sc->sc_dmainintr;
arg = sc->sc_inarg;
}
-static int
+STATIC int
gus_setfd(addr, flag)
void *addr;
int flag;
return(0); /* nothing fancy to do. */
}
-static inline int
+STATIC inline int
gus_to_vol(cp, vol)
mixer_ctrl_t *cp;
struct ad1848_volume *vol;
return(0);
}
-static inline int
+STATIC inline int
gus_from_vol(cp, vol)
mixer_ctrl_t *cp;
struct ad1848_volume *vol;
return(0);
}
-static int
+STATIC int
gusmax_mixer_get_port(addr, cp)
void *addr;
mixer_ctrl_t *cp;
return(error);
}
-static int
+STATIC int
gus_mixer_get_port(addr, cp)
void *addr;
mixer_ctrl_t *cp;
return error;
}
-static void
+STATIC void
gusics_master_mute(ic, mute)
struct ics2101_softc *ic;
int mute;
ics2101_mix_mute(ic, GUSMIX_CHAN_MASTER, ICSMIX_RIGHT, mute);
}
-static void
+STATIC void
gusics_mic_mute(ic, mute)
struct ics2101_softc *ic;
int mute;
ics2101_mix_mute(ic, GUSMIX_CHAN_MIC, ICSMIX_RIGHT, mute);
}
-static void
+STATIC void
gusics_linein_mute(ic, mute)
struct ics2101_softc *ic;
int mute;
ics2101_mix_mute(ic, GUSMIX_CHAN_LINE, ICSMIX_RIGHT, mute);
}
-static void
+STATIC void
gusics_cd_mute(ic, mute)
struct ics2101_softc *ic;
int mute;
ics2101_mix_mute(ic, GUSMIX_CHAN_CD, ICSMIX_RIGHT, mute);
}
-static void
+STATIC void
gusics_dac_mute(ic, mute)
struct ics2101_softc *ic;
int mute;
ics2101_mix_mute(ic, GUSMIX_CHAN_DAC, ICSMIX_RIGHT, mute);
}
-static int
+STATIC int
gusmax_mixer_set_port(addr, cp)
void *addr;
mixer_ctrl_t *cp;
return error;
}
-static int
+STATIC int
gus_mixer_set_port(addr, cp)
void *addr;
mixer_ctrl_t *cp;
return error;
}
-static int
+STATIC int
gusmax_mixer_query_devinfo(addr, dip)
void *addr;
register mixer_devinfo_t *dip;
return 0;
}
-static int
+STATIC int
gus_mixer_query_devinfo(addr, dip)
void *addr;
register mixer_devinfo_t *dip;
return 0;
}
-static int
+STATIC int
gus_query_encoding(addr, fp)
void *addr;
struct audio_encoding *fp;
* level. Levels as suggested by GUS SDK code.
*/
-static void
+STATIC void
gus_init_ics2101(sc)
struct gus_softc *sc;
{
-/* $OpenBSD: if_ed.c,v 1.8 1996/03/20 01:00:46 mickey Exp $ */
-/* $NetBSD: if_ed.c,v 1.87 1996/01/10 16:49:25 chuck Exp $ */
+/* $OpenBSD: if_ed.c,v 1.9 1996/04/18 23:47:37 niklas Exp $ */
+/* $NetBSD: if_ed.c,v 1.90 1996/03/16 07:24:15 cgd Exp $ */
/*
* Device driver for National Semiconductor DS8390/WD83C690 based ethernet
#define ED_NOTPRESENT 0x0002 /* card not present; do not allow
reconfiguration */
- int asic_addr; /* ASIC I/O bus address */
- int nic_addr; /* NIC (DS8390) I/O bus address */
+ int asic_base; /* Base ASIC I/O port */
+ int nic_base; /* Base NIC (DS8390) I/O port */
/*
* The following 'proto' variable is part of a work-around for 8013EBT asics
int edprobe __P((struct device *, void *, void *));
void edattach __P((struct device *, struct device *, void *));
+int ed_find __P((struct ed_softc *, struct cfdata *,
+ struct isa_attach_args *ia));
+int ed_probe_generic8390 __P((int));
+int ed_find_WD80x3 __P((struct ed_softc *, struct cfdata *,
+ struct isa_attach_args *ia));
+int ed_find_3Com __P((struct ed_softc *, struct cfdata *,
+ struct isa_attach_args *ia));
+int ed_find_Novell __P((struct ed_softc *, struct cfdata *,
+ struct isa_attach_args *ia));
int edintr __P((void *));
int edioctl __P((struct ifnet *, u_long, caddr_t));
void edstart __P((struct ifnet *));
#define ETHER_MAX_LEN 1518
#define ETHER_ADDR_LEN 6
-#define NIC_PUT(sc, off, val) outb(sc->nic_addr + off, val)
-#define NIC_GET(sc, off) inb(sc->nic_addr + off)
+#define NIC_PUT(base, off, val) outb((base) + (off), (val))
+#define NIC_GET(base, off) inb((base) + (off))
#if NPCMCIABUS > 0
struct cfdata *cf = sc->sc_dev.dv_cfdata;
struct isa_attach_args *ia = aux;
- if (ed_probe_WD80x3(sc, cf, ia))
+ return (ed_find(match, sc->sc_dev.dv_cfdata, aux));
+}
+
+/*
+ * Fill in softc (if given), based on device type, cfdata and attach args.
+ * Return 1 if successful, 0 otherwise.
+ */
+int
+ed_find(sc, cf, ia)
+ struct ed_softc *sc;
+ struct cfdata *cf;
+ struct isa_attach_args *ia;
+{
+
+ if (ed_find_WD80x3(sc, cf, ia))
return (1);
- if (ed_probe_3Com(sc, cf, ia))
+ if (ed_find_3Com(sc, cf, ia))
return (1);
- if (ed_probe_Novell(sc, cf, ia))
+ if (ed_find_Novell(sc, cf, ia))
return (1);
return (0);
}
* Return 1 if 8390 was found, 0 if not.
*/
int
-ed_probe_generic8390(sc)
- struct ed_softc *sc;
+ed_probe_generic8390(nicbase)
+ int nicbase;
{
- if ((NIC_GET(sc, ED_P0_CR) &
+ if ((NIC_GET(nicbase, ED_P0_CR) &
(ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
(ED_CR_RD2 | ED_CR_STP))
return (0);
- if ((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
+ if ((NIC_GET(nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
return (0);
return (1);
* Probe and vendor-specific initialization routine for SMC/WD80x3 boards.
*/
int
-ed_probe_WD80x3(sc, cf, ia)
+ed_find_WD80x3(sc, cf, ia)
struct ed_softc *sc;
struct cfdata *cf;
struct isa_attach_args *ia;
int i;
u_int memsize;
u_char iptr, isa16bit, sum;
+ int asicbase, nicbase;
- sc->asic_addr = ia->ia_iobase;
- sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
+ sc->asic_base = asicbase = ia->ia_iobase;
+ sc->nic_base = nicbase = asicbase + ED_WD_NIC_OFFSET;
sc->is790 = 0;
#ifdef TOSH_ETHER
- outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
+ outb(asicbase + ED_WD_MSR, ED_WD_MSR_POW);
delay(10000);
#endif
* Danpex boards for one.
*/
for (sum = 0, i = 0; i < 8; ++i)
- sum += inb(sc->asic_addr + ED_WD_PROM + i);
+ sum += inb(asicbase + ED_WD_PROM + i);
if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
/*
* clones. In this case, the checksum byte (the eighth byte)
* seems to always be zero.
*/
- if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
- inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
+ if (inb(asicbase + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
+ inb(asicbase + ED_WD_PROM + 7) != 0)
return (0);
}
/* Reset card to force it into a known state. */
#ifdef TOSH_ETHER
- outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
+ outb(asicbase + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
#else
- outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
+ outb(asicbase + ED_WD_MSR, ED_WD_MSR_RST);
#endif
delay(100);
- outb(sc->asic_addr + ED_WD_MSR,
- inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
+ outb(asicbase + ED_WD_MSR,
+ inb(asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST);
/* Wait in the case this card is reading it's EEROM. */
delay(5000);
sc->vendor = ED_VENDOR_WD_SMC;
- sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
+ sc->type = inb(asicbase + ED_WD_CARD_ID);
/* Set initial values for width/size. */
memsize = 8192;
isa16bit = 1;
break;
case ED_TYPE_WD8013EP: /* also WD8003EP */
- if (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) {
+ if (inb(asicbase + ED_WD_ICR) & ED_WD_ICR_16BIT) {
isa16bit = 1;
memsize = 16384;
sc->type_str = "WD8013EP";
case ED_TYPE_SMC8216T:
sc->type_str = (sc->type == ED_TYPE_SMC8216C) ?
"SMC8216/SMC8216C" : "SMC8216T";
- outb(sc->asic_addr + ED_WD790_HWR,
- inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
- switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
+ outb(asicbase + ED_WD790_HWR,
+ inb(asicbase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
+ switch (inb(asicbase + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
case ED_WD790_RAR_SZ64:
memsize = 65536;
break;
memsize = 8192;
break;
}
- outb(sc->asic_addr + ED_WD790_HWR,
- inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+ outb(asicbase + ED_WD790_HWR,
+ inb(asicbase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
isa16bit = 1;
sc->is790 = 1;
#ifdef TOSH_ETHER
(sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) &&
#endif
- ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
+ ((inb(asicbase + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
isa16bit = 0;
memsize = 8192;
}
sc->type, sc->type_str ?: "unknown", isa16bit, memsize,
ia->ia_msize);
for (i = 0; i < 8; i++)
- printf("%x -> %x\n", i, inb(sc->asic_addr + i));
+ printf("%x -> %x\n", i, inb(asicbase + i));
#endif
/* Allow the user to override the autoconfiguration. */
if (ia->ia_msize)
/* Get station address from on-board ROM. */
for (i = 0; i < ETHER_ADDR_LEN; ++i)
sc->sc_arpcom.ac_enaddr[i] =
- inb(sc->asic_addr + ED_WD_PROM + i);
+ inb(asicbase + ED_WD_PROM + i);
/*
* Set upper address bits and 8/16 bit access to shared memory.
if (isa16bit) {
if (sc->is790) {
sc->wd_laar_proto =
- inb(sc->asic_addr + ED_WD_LAAR) &
+ inb(asicbase + ED_WD_LAAR) &
~ED_WD_LAAR_M16EN;
} else {
sc->wd_laar_proto =
((kvtop(sc->mem_start) >> 19) &
ED_WD_LAAR_ADDRHI);
}
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
} else {
if ((sc->type & ED_WD_SOFTCONFIG) ||
sc->wd_laar_proto =
((kvtop(sc->mem_start) >> 19) &
ED_WD_LAAR_ADDRHI);
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
}
}
*/
if (!sc->is790) {
#ifdef TOSH_ETHER
- outb(sc->asic_addr + ED_WD_MSR + 1,
+ outb(asicbase + ED_WD_MSR + 1,
((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
- outb(sc->asic_addr + ED_WD_MSR + 2,
+ outb(asicbase + ED_WD_MSR + 2,
((kvtop(sc->mem_start) >> 16) & 0x0f));
sc->wd_msr_proto = ED_WD_MSR_POW;
#else
#endif
sc->cr_proto = ED_CR_RD2;
} else {
- outb(sc->asic_addr + 0x04,
- inb(sc->asic_addr + 0x04) | 0x80);
- outb(sc->asic_addr + 0x0b,
+ outb(asicbase + 0x04,
+ inb(asicbase + 0x04) | 0x80);
+ outb(asicbase + 0x0b,
((kvtop(sc->mem_start) >> 13) & 0x0f) |
((kvtop(sc->mem_start) >> 11) & 0x40) |
- (inb(sc->asic_addr + 0x0b) & 0xb0));
- outb(sc->asic_addr + 0x04,
- inb(sc->asic_addr + 0x04) & ~0x80);
+ (inb(asicbase + 0x0b) & 0xb0));
+ outb(asicbase + 0x04,
+ inb(asicbase + 0x04) & ~0x80);
sc->wd_msr_proto = 0x00;
sc->cr_proto = 0;
}
- outb(sc->asic_addr + ED_WD_MSR,
+ outb(asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
(void) inb(0x84);
kvtop(sc->mem_start + i));
/* Disable 16 bit access to shared memory. */
- outb(sc->asic_addr + ED_WD_MSR,
+ outb(asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (isa16bit)
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
(void) inb(0x84);
(void) inb(0x84);
* and 2) so that other 8 bit devices with shared memory can be
* used in this 128k region, too.
*/
- outb(sc->asic_addr + ED_WD_MSR, sc->wd_msr_proto);
+ outb(asicbase + ED_WD_MSR, sc->wd_msr_proto);
if (isa16bit)
- outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
+ outb(asicbase + ED_WD_LAAR, sc->wd_laar_proto);
(void) inb(0x84);
(void) inb(0x84);
* Probe and vendor-specific initialization routine for 3Com 3c503 boards.
*/
int
-ed_probe_3Com(sc, cf, ia)
+ed_find_3Com(sc, cf, ia)
struct ed_softc *sc;
struct cfdata *cf;
struct isa_attach_args *ia;
int i;
u_int memsize;
u_char isa16bit, sum, x;
- int ptr;
+ int ptr, asicbase, nicbase;
- sc->asic_addr = ia->ia_iobase + ED_3COM_ASIC_OFFSET;
- sc->nic_addr = ia->ia_iobase + ED_3COM_NIC_OFFSET;
+ sc->asic_base = asicbase = ia->ia_iobase + ED_3COM_ASIC_OFFSET;
+ sc->nic_base = nicbase = ia->ia_iobase + ED_3COM_NIC_OFFSET;
/*
* Verify that the kernel configured I/O address matches the board
* board is there; after all, we are already talking it at that
* address.
*/
- x = inb(sc->asic_addr + ED_3COM_BCFR);
+ x = inb(asicbase + ED_3COM_BCFR);
if (x == 0 || (x & (x - 1)) != 0)
return (0);
ptr = ffs(x) - 1;
} else
ia->ia_iobase = ed_3com_iobase[ptr];
- x = inb(sc->asic_addr + ED_3COM_PCFR);
+ x = inb(asicbase + ED_3COM_PCFR);
if (x == 0 || (x & (x - 1)) != 0)
return (0);
ptr = ffs(x) - 1;
ia->ia_maddr = ed_3com_maddr[ptr];
#if 0
- x = inb(sc->asic_addr + ED_3COM_IDCFR) & ED_3COM_IDCFR_IRQ;
+ x = inb(asicbase + ED_3COM_IDCFR) & ED_3COM_IDCFR_IRQ;
if (x == 0 || (x & (x - 1)) != 0)
return (0);
ptr = ffs(x) - 1;
* sequence because it'll lock up if the cable isn't connected if we
* don't.
*/
- outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
+ outb(asicbase + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
/* Wait for a while, then un-reset it. */
delay(50);
* reset - it's important to set it again after the following outb
* (this is done when we map the PROM below).
*/
- outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
+ outb(asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
/* Wait a bit for the NIC to recover from the reset. */
delay(5000);
* First, map ethernet address PROM over the top of where the NIC
* registers normally appear.
*/
- outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
+ outb(asicbase + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
for (i = 0; i < ETHER_ADDR_LEN; ++i)
- sc->sc_arpcom.ac_enaddr[i] = NIC_GET(sc, i);
+ sc->sc_arpcom.ac_enaddr[i] = NIC_GET(nicbase, i);
/*
* Unmap PROM - select NIC registers. The proper setting of the
* tranceiver is set in edinit so that the attach code is given a
* chance to set the default based on a compile-time config option.
*/
- outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
+ outb(asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
/* Determine if this is an 8bit or 16bit board. */
/* Select page 0 registers. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
/*
* Attempt to clear WTS bit. If it doesn't clear, then this is a
* 16-bit board.
*/
- NIC_PUT(sc, ED_P0_DCR, 0);
+ NIC_PUT(nicbase, ED_P0_DCR, 0);
/* Select page 2 registers. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_2 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_2 | ED_CR_STP);
/* The 3c503 forces the WTS bit to a one if this is a 16bit board. */
- if (NIC_GET(sc, ED_P2_DCR) & ED_DCR_WTS)
+ if (NIC_GET(nicbase, ED_P2_DCR) & ED_DCR_WTS)
isa16bit = 1;
else
isa16bit = 0;
/* Select page 0 registers. */
- NIC_PUT(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P2_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
sc->mem_start = ISA_HOLE_VADDR(ia->ia_maddr);
sc->mem_size = memsize;
* Initialize GA page start/stop registers. Probably only needed if
* doing DMA, but what the Hell.
*/
- outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
- outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
+ outb(asicbase + ED_3COM_PSTR, sc->rec_page_start);
+ outb(asicbase + ED_3COM_PSPR, sc->rec_page_stop);
/* Set IRQ. 3c503 only allows a choice of irq 3-5 or 9. */
switch (ia->ia_irq) {
case 9:
- outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
+ outb(asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
break;
case 3:
- outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
+ outb(asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
break;
case 4:
- outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
+ outb(asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
break;
case 5:
- outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
+ outb(asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
break;
default:
printf("%s: invalid irq configuration (%d) must be 3-5 or 9 for 3c503\n",
* Initialize GA configuration register. Set bank and enable shared
* mem.
*/
- outb(sc->asic_addr + ED_3COM_GACFR,
+ outb(asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
/*
* shared memory is disabled. We set them to 0xffff0...allegedly the
* reset vector.
*/
- outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
- outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
- outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
+ outb(asicbase + ED_3COM_VPTR2, 0xff);
+ outb(asicbase + ED_3COM_VPTR1, 0xff);
+ outb(asicbase + ED_3COM_VPTR0, 0x00);
/* Zero memory and verify that it is clear. */
bzero(sc->mem_start, memsize);
* Probe and vendor-specific initialization routine for NE1000/2000 boards.
*/
int
-ed_probe_Novell(sc, cf, ia)
+ed_find_Novell(sc, cf, ia)
struct ed_softc *sc;
struct cfdata *cf;
struct isa_attach_args *ia;
u_char romdata[16], isa16bit = 0, tmp;
static u_char test_pattern[32] = "THIS is A memory TEST pattern";
u_char test_buffer[32];
+ int asicbase, nicbase;
- sc->asic_addr = ia->ia_iobase + ED_NOVELL_ASIC_OFFSET;
- sc->nic_addr = ia->ia_iobase + ED_NOVELL_NIC_OFFSET;
+ sc->asic_base = asicbase = ia->ia_iobase + ED_NOVELL_ASIC_OFFSET;
+ sc->nic_base = nicbase = ia->ia_iobase + ED_NOVELL_NIC_OFFSET;
/* XXX - do Novell-specific probe here */
/* Reset the board. */
#ifdef GWETHER
- outb(sc->asic_addr + ED_NOVELL_RESET, 0);
+ outb(asicbase + ED_NOVELL_RESET, 0);
delay(200);
#endif /* GWETHER */
- tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
+ tmp = inb(asicbase + ED_NOVELL_RESET);
/*
* I don't know if this is necessary; probably cruft leftover from
* complete documentation on what the 'right' thing to do is...so we do
* the invasive thing for now. Yuck.]
*/
- outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
+ outb(asicbase + ED_NOVELL_RESET, tmp);
delay(5000);
/*
* XXX - this makes the probe invasive! ...Done against my better
* judgement. -DLG
*/
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
delay(5000);
/* Make sure that we really have an 8390 based board. */
- if (!ed_probe_generic8390(sc))
+ if (!ed_probe_generic8390(nicbase))
return (0);
sc->vendor = ED_VENDOR_NOVELL;
* This prevents packets from being stored in the NIC memory when the
* readmem routine turns on the start bit in the CR.
*/
- NIC_PUT(sc, ED_P0_RCR, ED_RCR_MON);
+ NIC_PUT(nicbase, ED_P0_RCR, ED_RCR_MON);
/* Temporarily initialize DCR for byte operations. */
- NIC_PUT(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+ NIC_PUT(nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
- NIC_PUT(sc, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
- NIC_PUT(sc, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
+ NIC_PUT(nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
+ NIC_PUT(nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
sc->isa16bit = 0;
if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
/* not an NE1000 - try NE2000 */
- NIC_PUT(sc, ED_P0_DCR,
+ NIC_PUT(nicbase, ED_P0_DCR,
ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
- NIC_PUT(sc, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
- NIC_PUT(sc, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
+ NIC_PUT(nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
+ NIC_PUT(nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
sc->isa16bit = 1;
#endif /* GWETHER */
/* Clear any pending interrupts that might have occurred above. */
- NIC_PUT(sc, ED_P0_ISR, 0xff);
+ NIC_PUT(nicbase, ED_P0_ISR, 0xff);
ia->ia_iosize = ED_NOVELL_IO_PORTS;
return (1);
struct isa_attach_args *ia = aux;
struct cfdata *cf = sc->sc_dev.dv_cfdata;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+ int asicbase;
+
+
+ asicbase = sc->asic_base;
/* Set interface to stopped condition (reset). */
edstop(sc);
case ED_VENDOR_WD_SMC:
if ((sc->type & ED_WD_SOFTCONFIG) == 0)
break;
- if ((inb(sc->asic_addr + ED_WD_IRR) & ED_WD_IRR_OUT2) == 0)
+ if ((inb(asicbase + ED_WD_IRR) & ED_WD_IRR_OUT2) == 0)
ifp->if_flags |= IFF_LINK0;
break;
}
edstop(sc)
struct ed_softc *sc;
{
+ int nicbase = sc->nic_base;
int n = 5000;
/* Stop everything on the interface, and select page 0 registers. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
/*
* Wait for interface to enter stopped state, but limit # of checks to
* 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
* just in case it's an old one.
*/
- while (((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
+ while (((NIC_GET(nicbase, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
}
/*
struct ed_softc *sc;
{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+ int nicbase = sc->nic_base, asicbase = sc->asic_base;
int i;
u_char command;
u_long mcaf[2];
sc->txb_next_tx = 0;
/* Set interface for page 0, remote DMA complete, stopped. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
if (sc->isa16bit) {
/*
* Set FIFO threshold to 8, No auto-init Remote DMA, byte
* order=80x86, word-wide DMA xfers,
*/
- NIC_PUT(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
+ NIC_PUT(nicbase, ED_P0_DCR,
+ ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
} else {
/* Same as above, but byte-wide DMA xfers. */
- NIC_PUT(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+ NIC_PUT(nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
}
/* Clear remote byte count registers. */
- NIC_PUT(sc, ED_P0_RBCR0, 0);
- NIC_PUT(sc, ED_P0_RBCR1, 0);
+ NIC_PUT(nicbase, ED_P0_RBCR0, 0);
+ NIC_PUT(nicbase, ED_P0_RBCR1, 0);
/* Tell RCR to do nothing for now. */
- NIC_PUT(sc, ED_P0_RCR, ED_RCR_MON);
+ NIC_PUT(nicbase, ED_P0_RCR, ED_RCR_MON);
/* Place NIC in internal loopback mode. */
- NIC_PUT(sc, ED_P0_TCR, ED_TCR_LB0);
+ NIC_PUT(nicbase, ED_P0_TCR, ED_TCR_LB0);
/* Set lower bits of byte addressable framing to 0. */
if (sc->is790)
- NIC_PUT(sc, 0x09, 0);
+ NIC_PUT(nicbase, 0x09, 0);
/* Initialize receive buffer ring. */
- NIC_PUT(sc, ED_P0_BNRY, sc->rec_page_start);
- NIC_PUT(sc, ED_P0_PSTART, sc->rec_page_start);
- NIC_PUT(sc, ED_P0_PSTOP, sc->rec_page_stop);
+ NIC_PUT(nicbase, ED_P0_BNRY, sc->rec_page_start);
+ NIC_PUT(nicbase, ED_P0_PSTART, sc->rec_page_start);
+ NIC_PUT(nicbase, ED_P0_PSTOP, sc->rec_page_stop);
/*
* Clear all interrupts. A '1' in each bit position clears the
* corresponding flag.
*/
- NIC_PUT(sc, ED_P0_ISR, 0xff);
+ NIC_PUT(nicbase, ED_P0_ISR, 0xff);
/*
* Enable the following interrupts: receive/transmit complete,
*
* Counter overflow and Remote DMA complete are *not* enabled.
*/
- NIC_PUT(sc, ED_P0_IMR,
+ NIC_PUT(nicbase, ED_P0_IMR,
ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE |
ED_IMR_OVWE);
/* Program command register for page 1. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
/* Copy out our station address. */
for (i = 0; i < ETHER_ADDR_LEN; ++i)
- NIC_PUT(sc, ED_P1_PAR0 + i, sc->sc_arpcom.ac_enaddr[i]);
+ NIC_PUT(nicbase, ED_P1_PAR0 + i, sc->sc_arpcom.ac_enaddr[i]);
/* Set multicast filter on chip. */
ed_getmcaf(&sc->sc_arpcom, mcaf);
for (i = 0; i < 8; i++)
- NIC_PUT(sc, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
+ NIC_PUT(nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
/*
* Set current page pointer to one page after the boundary pointer, as
* recommended in the National manual.
*/
sc->next_packet = sc->rec_page_start + 1;
- NIC_PUT(sc, ED_P1_CURR, sc->next_packet);
+ NIC_PUT(nicbase, ED_P1_CURR, sc->next_packet);
/* Program command register for page 0. */
- NIC_PUT(sc, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
+ NIC_PUT(nicbase, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
i = ED_RCR_AB | ED_RCR_AM;
if (ifp->if_flags & IFF_PROMISC) {
*/
i |= ED_RCR_PRO | ED_RCR_AR | ED_RCR_SEP;
}
- NIC_PUT(sc, ED_P0_RCR, i);
+ NIC_PUT(nicbase, ED_P0_RCR, i);
/* Take interface out of loopback. */
- NIC_PUT(sc, ED_P0_TCR, 0);
+ NIC_PUT(nicbase, ED_P0_TCR, 0);
/*
* If this is a 3Com board, the tranceiver must be software enabled
u_char x;
case ED_VENDOR_3COM:
if (ifp->if_flags & IFF_LINK0)
- outb(sc->asic_addr + ED_3COM_CR, 0);
+ outb(asicbase + ED_3COM_CR, 0);
else
- outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
+ outb(asicbase + ED_3COM_CR, ED_3COM_CR_XSEL);
break;
case ED_VENDOR_WD_SMC:
if ((sc->type & ED_WD_SOFTCONFIG) == 0)
break;
- x = inb(sc->asic_addr + ED_WD_IRR);
+ x = inb(asicbase + ED_WD_IRR);
if (ifp->if_flags & IFF_LINK0)
x &= ~ED_WD_IRR_OUT2;
else
x |= ED_WD_IRR_OUT2;
- outb(sc->asic_addr + ED_WD_IRR, x);
+ outb(asicbase + ED_WD_IRR, x);
break;
}
/* Fire up the interface. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/* Set 'running' flag, and clear output active flag. */
ifp->if_flags |= IFF_RUNNING;
struct ed_softc *sc;
{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+ int nicbase = sc->nic_base;
u_short len;
len = sc->txb_len[sc->txb_next_tx];
/* Set NIC for page 0 register access. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/* Set TX buffer start page. */
- NIC_PUT(sc, ED_P0_TPSR, sc->tx_page_start +
+ NIC_PUT(nicbase, ED_P0_TPSR, sc->tx_page_start +
sc->txb_next_tx * ED_TXBUF_SIZE);
/* Set TX length. */
- NIC_PUT(sc, ED_P0_TBCR0, len);
- NIC_PUT(sc, ED_P0_TBCR1, len >> 8);
+ NIC_PUT(nicbase, ED_P0_TBCR0, len);
+ NIC_PUT(nicbase, ED_P0_TBCR1, len >> 8);
/* Set page 0, remote DMA complete, transmit packet, and *start*. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR,
+ sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA);
/* Point to next transmit buffer slot and wrap if necessary. */
sc->txb_next_tx++;
struct ed_softc *sc = edcd.cd_devs[ifp->if_unit];
struct mbuf *m0, *m;
caddr_t buffer;
+ int asicbase = sc->asic_base;
int len;
if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
*/
case ED_VENDOR_3COM:
if (sc->isa16bit)
- outb(sc->asic_addr + ED_3COM_GACFR,
+ outb(asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL);
break;
/*
*/
case ED_VENDOR_WD_SMC:
if (sc->isa16bit)
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
- outb(sc->asic_addr + ED_WD_MSR,
+ outb(asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
(void) inb(0x84);
(void) inb(0x84);
switch (sc->vendor) {
case ED_VENDOR_3COM:
if (sc->isa16bit)
- outb(sc->asic_addr + ED_3COM_GACFR,
+ outb(asicbase + ED_3COM_GACFR,
ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
break;
case ED_VENDOR_WD_SMC:
- outb(sc->asic_addr + ED_WD_MSR,
+ outb(asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (sc->isa16bit)
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
(void) inb(0x84);
(void) inb(0x84);
ed_rint(sc)
struct ed_softc *sc;
{
+ int nicbase = sc->nic_base;
u_char boundary, current;
u_short len;
u_char nlen;
loop:
/* Set NIC to page 1 registers to get 'current' pointer. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
/*
* 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
* until the logical beginning equals the logical end (or in other
* words, until the ring-buffer is empty).
*/
- current = NIC_GET(sc, ED_P1_CURR);
+ current = NIC_GET(nicbase, ED_P1_CURR);
if (sc->next_packet == current)
return;
/* Set NIC to page 0 registers to update boundary register. */
- NIC_PUT(sc, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
do {
/* Get pointer to this buffer's header structure. */
boundary = sc->next_packet - 1;
if (boundary < sc->rec_page_start)
boundary = sc->rec_page_stop - 1;
- NIC_PUT(sc, ED_P0_BNRY, boundary);
+ NIC_PUT(nicbase, ED_P0_BNRY, boundary);
} while (sc->next_packet != current);
goto loop;
{
struct ed_softc *sc = arg;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+ int nicbase = sc->nic_base, asicbase = sc->asic_base;
u_char isr;
/* Set NIC to page 0 registers. */
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
- isr = NIC_GET(sc, ED_P0_ISR);
+ isr = NIC_GET(nicbase, ED_P0_ISR);
if (!isr)
return (0);
* '1' to each bit position that was set.
* (Writing a '1' *clears* the bit.)
*/
- NIC_PUT(sc, ED_P0_ISR, isr);
+ NIC_PUT(nicbase, ED_P0_ISR, isr);
/*
* Handle transmitter interrupts. Handle these first because
* the receiver will reset the board under some conditions.
*/
if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
- u_char collisions = NIC_GET(sc, ED_P0_NCR) & 0x0f;
+ u_char collisions = NIC_GET(nicbase, ED_P0_NCR) & 0x0f;
/*
* Check for transmit error. If a TX completed with an
* course, with UDP we're screwed, but this is expected
* when a network is heavily loaded.
*/
- (void) NIC_GET(sc, ED_P0_TSR);
+ (void) NIC_GET(nicbase, ED_P0_TSR);
if (isr & ED_ISR_TXE) {
/*
* Excessive collisions (16).
*/
- if ((NIC_GET(sc, ED_P0_TSR) & ED_TSR_ABT)
+ if ((NIC_GET(nicbase, ED_P0_TSR) & ED_TSR_ABT)
&& (collisions == 0)) {
/*
* When collisions total 16, the P0_NCR
#ifdef ED_DEBUG
printf("%s: receive error %x\n",
sc->sc_dev.dv_xname,
- NIC_GET(sc, ED_P0_RSR));
+ NIC_GET(nicbase, ED_P0_RSR));
#endif
}
*/
if (sc->vendor == ED_VENDOR_WD_SMC) {
if (sc->isa16bit)
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
- outb(sc->asic_addr + ED_WD_MSR,
+ outb(asicbase + ED_WD_MSR,
sc->wd_msr_proto | ED_WD_MSR_MENB);
(void) inb(0x84);
(void) inb(0x84);
/* Disable 16-bit access. */
if (sc->vendor == ED_VENDOR_WD_SMC) {
- outb(sc->asic_addr + ED_WD_MSR,
+ outb(asicbase + ED_WD_MSR,
sc->wd_msr_proto);
if (sc->isa16bit)
- outb(sc->asic_addr + ED_WD_LAAR,
+ outb(asicbase + ED_WD_LAAR,
sc->wd_laar_proto);
(void) inb(0x84);
(void) inb(0x84);
* set in the transmit routine, is *okay* - it is 'edge'
* triggered from low to high).
*/
- NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR,
+ sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
/*
* If the Network Talley Counters overflow, read them to reset
* otherwise - resulting in an infinite loop.
*/
if (isr & ED_ISR_CNT) {
- (void) NIC_GET(sc, ED_P0_CNTR0);
- (void) NIC_GET(sc, ED_P0_CNTR1);
- (void) NIC_GET(sc, ED_P0_CNTR2);
+ (void) NIC_GET(nicbase, ED_P0_CNTR0);
+ (void) NIC_GET(nicbase, ED_P0_CNTR1);
+ (void) NIC_GET(nicbase, ED_P0_CNTR2);
}
- isr = NIC_GET(sc, ED_P0_ISR);
+ isr = NIC_GET(nicbase, ED_P0_ISR);
if (!isr)
return (1);
}
int len;
{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
- struct mbuf *m;
+ struct mbuf *m;
struct ether_header *eh;
/* Pull packet off interface. */
caddr_t dst;
u_short amount;
{
+ int nicbase = sc->nic_base;
+
/* Select page 0 registers. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Round up to a word. */
if (amount & 1)
++amount;
/* Set up DMA byte count. */
- NIC_PUT(sc, ED_P0_RBCR0, amount);
- NIC_PUT(sc, ED_P0_RBCR1, amount >> 8);
+ NIC_PUT(nicbase, ED_P0_RBCR0, amount);
+ NIC_PUT(nicbase, ED_P0_RBCR1, amount >> 8);
/* Set up source address in NIC mem. */
- NIC_PUT(sc, ED_P0_RSAR0, src);
- NIC_PUT(sc, ED_P0_RSAR1, src >> 8);
+ NIC_PUT(nicbase, ED_P0_RSAR0, src);
+ NIC_PUT(nicbase, ED_P0_RSAR1, src >> 8);
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
if (sc->isa16bit)
- insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
+ insw(sc->asic_base + ED_NOVELL_DATA, dst, amount / 2);
else
- insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
+ insb(sc->asic_base + ED_NOVELL_DATA, dst, amount);
}
/*
u_short dst;
u_short len;
{
+ int nicbase = sc->nic_base;
int maxwait = 100; /* about 120us */
/* Select page 0 registers. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Reset remote DMA complete flag. */
- NIC_PUT(sc, ED_P0_ISR, ED_ISR_RDC);
+ NIC_PUT(nicbase, ED_P0_ISR, ED_ISR_RDC);
/* Set up DMA byte count. */
- NIC_PUT(sc, ED_P0_RBCR0, len);
- NIC_PUT(sc, ED_P0_RBCR1, len >> 8);
+ NIC_PUT(nicbase, ED_P0_RBCR0, len);
+ NIC_PUT(nicbase, ED_P0_RBCR1, len >> 8);
/* Set up destination address in NIC mem. */
- NIC_PUT(sc, ED_P0_RSAR0, dst);
- NIC_PUT(sc, ED_P0_RSAR1, dst >> 8);
+ NIC_PUT(nicbase, ED_P0_RSAR0, dst);
+ NIC_PUT(nicbase, ED_P0_RSAR1, dst >> 8);
/* Set remote DMA write. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
if (sc->isa16bit)
- outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
+ outsw(sc->asic_base + ED_NOVELL_DATA, src, len / 2);
else
- outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
+ outsb(sc->asic_base + ED_NOVELL_DATA, src, len);
/*
* Wait for remote DMA complete. This is necessary because on the
* waiting causes really bad things to happen - like the NIC
* irrecoverably jamming the ISA bus.
*/
- while (((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
+ while (((NIC_GET(nicbase, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
+ --maxwait);
}
/*
struct mbuf *m;
u_short dst;
{
+ int nicbase = sc->nic_base, asicbase = sc->asic_base;
u_short len;
struct mbuf *mp;
int maxwait = 100; /* about 120us */
len = m->m_pkthdr.len;
/* Select page 0 registers. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
/* Reset remote DMA complete flag. */
- NIC_PUT(sc, ED_P0_ISR, ED_ISR_RDC);
+ NIC_PUT(nicbase, ED_P0_ISR, ED_ISR_RDC);
/* Set up DMA byte count. */
- NIC_PUT(sc, ED_P0_RBCR0, len);
- NIC_PUT(sc, ED_P0_RBCR1, len >> 8);
+ NIC_PUT(nicbase, ED_P0_RBCR0, len);
+ NIC_PUT(nicbase, ED_P0_RBCR1, len >> 8);
/* Set up destination address in NIC mem. */
- NIC_PUT(sc, ED_P0_RSAR0, dst);
- NIC_PUT(sc, ED_P0_RSAR1, dst >> 8);
+ NIC_PUT(nicbase, ED_P0_RSAR0, dst);
+ NIC_PUT(nicbase, ED_P0_RSAR1, dst >> 8);
/* Set remote DMA write. */
- NIC_PUT(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
+ NIC_PUT(nicbase, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
/*
* Transfer the mbuf chain to the NIC memory.
/* NE1000s are easy. */
for (; m != 0; m = m->m_next) {
if (m->m_len) {
- outsb(sc->asic_addr + ED_NOVELL_DATA,
+ outsb(asicbase + ED_NOVELL_DATA,
mtod(m, u_char *), m->m_len);
}
}
/* Finish the last word. */
if (wantbyte) {
savebyte[1] = *data;
- outw(sc->asic_addr + ED_NOVELL_DATA,
+ outw(asicbase + ED_NOVELL_DATA,
*(u_short *)savebyte);
data++;
len--;
}
/* Output contiguous words. */
if (len > 1)
- outsw(sc->asic_addr + ED_NOVELL_DATA,
+ outsw(asicbase + ED_NOVELL_DATA,
data, len >> 1);
/* Save last byte, if necessary. */
if (len & 1) {
if (wantbyte) {
savebyte[1] = 0;
- outw(sc->asic_addr + ED_NOVELL_DATA,
- *(u_short *)savebyte);
+ outw(asicbase + ED_NOVELL_DATA, *(u_short *)savebyte);
}
}
* waiting causes really bad things to happen - like the NIC
* irrecoverably jamming the ISA bus.
*/
- while (((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
+ while (((NIC_GET(nicbase, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
+ --maxwait);
if (!maxwait) {
log(LOG_WARNING,
-/* $OpenBSD: if_ep.c,v 1.9 1996/03/20 01:00:49 mickey Exp $ */
-/* $NetBSD: if_ep.c,v 1.86 1995/12/24 02:31:27 mycroft Exp $ */
+/* $OpenBSD: if_ep.c,v 1.10 1996/04/18 23:47:40 niklas Exp $ */
+/* $NetBSD: if_ep.c,v 1.87 1996/02/19 20:18:40 christos Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@novatel.ca>
if (parent->dv_cfdata->cf_driver == &pcicd) {
struct pci_attach_args *pa = (struct pci_attach_args *) aux;
- if (PCI_VENDORID(pa->pa_id) != PCI_VENDOR_3COM ||
- (PCI_CHIPID(pa->pa_id) != PCI_PRODUCT_3COM_3C590
- && PCI_CHIPID(pa->pa_id) != PCI_PRODUCT_3COM_3C595))
+ if (PCI_VENDORID(pa->pa_id) != PCI_VENDOR_3COM)
return 0;
+ switch (PCI_CHIPID(pa->pa_id)) {
+ case PCI_PRODUCT_3COM_3C590:
+ case PCI_PRODUCT_3COM_3C595:
+ break;
+ default:
+ return 0;
+ }
+
if (nepcards >= MAXEPCARDS)
return 0;
-/* $OpenBSD: isa.c,v 1.4 1996/03/08 16:43:06 niklas Exp $ */
-/* $NetBSD: isa.c,v 1.76 1996/01/16 07:52:38 mycroft Exp $ */
+/* $OpenBSD: isa.c,v 1.5 1996/04/18 23:47:41 niklas Exp $ */
+/* $NetBSD: isa.c,v 1.78 1996/03/08 20:36:21 cgd Exp $ */
/*-
* Copyright (c) 1993, 1994 Charles Hannum. All rights reserved.
#include <dev/isa/isareg.h>
#include <dev/isa/isavar.h>
+int isamatch __P((struct device *, void *, void *));
+void isaattach __P((struct device *, struct device *, void *));
+
+struct cfdriver isacd = {
+ NULL, "isa", isamatch, isaattach, DV_DULL, sizeof(struct isa_softc), 1
+};
+
+int
+isamatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct isabus_attach_args *iba = aux;
+
+ if (strcmp(iba->iba_busname, cf->cf_driver->cd_name))
+ return (0);
+
+ /* XXX check other indicators */
+
+ return (1);
+}
+
+void
+isaattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct isa_softc *sc = (struct isa_softc *)self;
+ struct isabus_attach_args *iba = aux;
+
+ printf("\n");
+
+ sc->sc_bc = iba->iba_bc;
+
+ TAILQ_INIT(&sc->sc_subdevs);
+ config_scan(isascan, self);
+}
+
int
isaprint(aux, isa)
void *aux;
struct device *parent;
void *match;
{
+ struct isa_softc *sc = (struct isa_softc *)parent;
struct device *dev = match;
struct cfdata *cf = dev->dv_cfdata;
struct isa_attach_args ia;
if (cf->cf_fstate == FSTATE_STAR)
panic("clone devices not supported on ISA bus");
+ ia.ia_bc = sc->sc_bc;
ia.ia_iobase = cf->cf_loc[0];
ia.ia_iosize = 0x666;
ia.ia_maddr = cf->cf_loc[2];
-/* $NetBSD: isadma.c,v 1.12 1995/04/17 12:09:11 cgd Exp $ */
+/* $OpenBSD: isadma.c,v 1.3 1996/04/18 23:47:41 niklas Exp $ */
+/* $NetBSD: isadma.c,v 1.17 1996/03/01 04:35:27 mycroft Exp $ */
#include <sys/param.h>
#include <sys/systm.h>
};
static struct dma_info dma_info[8];
+static u_int8_t dma_finished;
/* high byte of address is stored in this port for i-th dma channel */
-static int dmapageport[8] =
- { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
+static int dmapageport[8] = {
+ 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a
+};
+
+static u_int8_t dmamode[4] = {
+ DMA37MD_READ | DMA37MD_SINGLE,
+ DMA37MD_WRITE | DMA37MD_SINGLE,
+ DMA37MD_READ | DMA37MD_LOOP,
+ DMA37MD_WRITE | DMA37MD_LOOP
+};
/*
* isadma_cascade(): program 8237 DMA controller channel to accept
int chan;
{
-#ifdef DIAGNOSTIC
+#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7)
panic("isadma_cascade: impossible request");
#endif
/* set dma channel mode, and set dma channel mode */
if ((chan & 4) == 0) {
- outb(DMA1_MODE, DMA37MD_CASCADE | chan);
+ outb(DMA1_MODE, chan | DMA37MD_CASCADE);
outb(DMA1_SMSK, chan);
} else {
- outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
- outb(DMA2_SMSK, chan & 3);
+ chan &= 3;
+
+ outb(DMA2_MODE, chan | DMA37MD_CASCADE);
+ outb(DMA2_SMSK, chan);
}
}
int mflags;
vm_size_t size;
-#ifdef DIAGNOSTIC
+#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7 ||
- ((flags & ISADMA_START_READ) == 0) == ((flags & ISADMA_START_WRITE) == 0) ||
+ (((flags & DMAMODE_READ) != 0) + ((flags & DMAMODE_WRITE) != 0) +
+ ((flags & DMAMODE_LOOP) != 0) != 1) ||
((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) :
(nbytes >= (1<<16))))
panic("isadma_start: impossible request");
if (isadma_map(addr, nbytes, di->phys, mflags) != 1)
panic("isadma_start: cannot map");
- if ((flags & ISADMA_START_READ) == 0)
+ /* XXX Will this do what we want with DMAMODE_LOOP? */
+ if ((flags & DMAMODE_READ) == 0)
isadma_copytobuf(addr, nbytes, 1, di->phys);
+ dma_finished &= ~(1 << chan);
+
if ((chan & 4) == 0) {
/*
* Program one of DMA channels 0..3. These are
* byte mode channels.
*/
/* set dma channel mode, and reset address ff */
- if (flags & ISADMA_START_READ)
- outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE);
- else
- outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ);
+ outb(DMA1_MODE, chan | dmamode[flags]);
outb(DMA1_FFC, 0);
/* send start address */
- waport = DMA1_CHN(chan);
+ waport = DMA1_CHN(chan);
+ outb(dmapageport[chan], di->phys[0].addr>>16);
outb(waport, di->phys[0].addr);
outb(waport, di->phys[0].addr>>8);
- outb(dmapageport[chan], di->phys[0].addr>>16);
/* send count */
outb(waport + 1, --nbytes);
* word mode channels.
*/
/* set dma channel mode, and reset address ff */
- if (flags & ISADMA_START_READ)
- outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE);
- else
- outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ);
+ outb(DMA2_MODE, (chan & 3) | dmamode[flags]);
outb(DMA2_FFC, 0);
/* send start address */
waport = DMA2_CHN(chan & 3);
+ outb(dmapageport[chan], di->phys[0].addr>>16);
outb(waport, di->phys[0].addr>>1);
outb(waport, di->phys[0].addr>>9);
- outb(dmapageport[chan], di->phys[0].addr>>16);
/* send count */
nbytes >>= 1;
{
struct dma_info *di;
-#ifdef DIAGNOSTIC
+#ifdef ISADMA_DEBUG
if (chan < 0 || chan > 7)
panic("isadma_abort: impossible request");
#endif
di->flags = 0;
}
+int
+isadma_finished(chan)
+ int chan;
+{
+
+#ifdef ISADMA_DEBUG
+ if (chan < 0 || chan > 7)
+ panic("isadma_finished: impossible request");
+#endif
+
+ /* check that the terminal count was reached */
+ if ((chan & 4) == 0)
+ dma_finished |= inb(DMA1_SR) & 0x0f;
+ else
+ dma_finished |= (inb(DMA2_SR) & 0x0f) << 4;
+
+ return ((dma_finished & (1 << chan)) != 0);
+}
+
void
isadma_done(chan)
int chan;
else
outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
- if (di->flags & ISADMA_START_READ)
+ /* XXX Will this do what we want with DMAMODE_LOOP? */
+ if (di->flags & DMAMODE_READ)
isadma_copyfrombuf(di->addr, di->nbytes, 1, di->phys);
isadma_unmap(di->addr, di->nbytes, 1, di->phys);
-/* $NetBSD: isadmavar.h,v 1.2 1994/10/27 04:17:09 cgd Exp $ */
+/* $OpenBSD: isadmavar.h,v 1.3 1996/04/18 23:47:42 niklas Exp $ */
+/* $NetBSD: isadmavar.h,v 1.4 1996/03/01 04:08:46 mycroft Exp $ */
+
+#define DMAMODE_WRITE 0
+#define DMAMODE_READ 1
+#define DMAMODE_LOOP 2
#define ISADMA_START_READ 0x0001 /* read from device */
#define ISADMA_START_WRITE 0x0002 /* write to device */
void isadma_cascade __P((int));
void isadma_start __P((caddr_t, vm_size_t, int, int));
void isadma_abort __P((int));
+int isadma_finished __P((int));
void isadma_done __P((int));
/*
* XXX these are needed until all drivers have been cleaned up
*/
#define isa_dmacascade(c) isadma_cascade((c))
-#define isa_dmastart(f, a, s, c) \
- isadma_start((a), (s), (c), (f)&B_READ?ISADMA_START_READ:ISADMA_START_WRITE)
+#define isa_dmastart(f, a, s, c) isadma_start((a), (s), (c), (f))
#define isa_dmaabort(c) isadma_abort((c))
+#define isa_dmafinished(c) isadma_finished((c))
#define isa_dmadone(a, s, c, f) isadma_abort((c))
-/* $OpenBSD: isavar.h,v 1.6 1996/03/20 01:00:55 mickey Exp $ */
-/* $NetBSD: isavar.h,v 1.17 1995/12/24 02:31:38 mycroft Exp $ */
+/* $OpenBSD: isavar.h,v 1.7 1996/04/18 23:47:43 niklas Exp $ */
+/* $NetBSD: isavar.h,v 1.20 1996/03/16 02:00:43 cgd Exp $ */
/*
* Copyright (c) 1995 Chris G. Demetriou
* BSDI Id: isavar.h,v 1.5 1992/12/01 18:06:00 karels Exp
*/
+#ifndef _DEV_ISA_ISAVAR_H_
+#define _DEV_ISA_ISAVAR_H_
+
/*
* Definitions for ISA autoconfiguration.
*/
#include <sys/queue.h>
+#include <machine/bus.h>
+
+/*
+ * ISA bus attach arguments
+ */
+struct isabus_attach_args {
+ char *iba_busname; /* XXX should be common */
+ bus_chipset_tag_t iba_bc; /* XXX should be common */
+};
/*
* ISA driver attach arguments
*/
struct isa_attach_args {
+ bus_chipset_tag_t ia_bc; /* bus chipset tag */
+
int ia_iobase; /* base i/o address */
int ia_iosize; /* span of ports used */
int ia_irq; /* interrupt request */
struct device sc_dev; /* base device */
TAILQ_HEAD(, isadev)
sc_subdevs; /* list of all children */
+
+ bus_chipset_tag_t sc_bc; /* bus chipset tag */
};
#define cf_iobase cf_loc[0]
void isa_establish __P((struct isadev *, struct device *));
#endif
-/*
- * software conventions
- */
-typedef enum { BUS_ISA, BUS_EISA } isa_type;
-
-extern isa_type isa_bustype; /* type of bus; XXX should be in softc */
+#endif /* _DEV_ISA_ISAVAR_H_ */
-/* $OpenBSD: lpt.c,v 1.7 1996/03/20 01:00:55 mickey Exp $ */
-/* $NetBSD: lpt.c,v 1.31 1995/12/24 02:31:40 mycroft Exp $ */
+/* $OpenBSD: lpt.c,v 1.8 1996/04/18 23:47:43 niklas Exp $ */
+/* $NetBSD: lpt.c,v 1.32 1996/03/08 22:17:58 cgd Exp $ */
/*
* Copyright (c) 1993, 1994 Charles Hannum.
#include <sys/syslog.h>
#include <machine/cpu.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/isa/lptreg.h>
u_char *sc_cp;
int sc_spinmax;
int sc_iobase;
+ bus_chipset_tag_t sc_bc;
+ bus_io_handle_t sc_ioh;
int sc_irq;
u_char sc_state;
#define LPT_OPEN 0x01 /* device is open */
#define LPS_INVERT (LPS_SELECT|LPS_NERR|LPS_NBSY|LPS_NACK)
#define LPS_MASK (LPS_SELECT|LPS_NERR|LPS_NBSY|LPS_NACK|LPS_NOPAPER)
-#define NOT_READY() ((inb(iobase + lpt_status) ^ LPS_INVERT) & LPS_MASK)
-#define NOT_READY_ERR() not_ready(inb(iobase + lpt_status), sc)
+#define NOT_READY() ((bus_io_read_1(bc, ioh, lpt_status) ^ LPS_INVERT) & LPS_MASK)
+#define NOT_READY_ERR() not_ready(bus_io_read_1(bc, ioh, lpt_status), sc)
static int not_ready __P((u_char, struct lpt_softc *));
static void lptwakeup __P((void *arg));
* Internal routine to lptprobe to do port tests of one byte value.
*/
int
-lpt_port_test(port, data, mask)
- int port;
+lpt_port_test(ioh, off, data, mask, base)
+ bus_io_handle_t ioh;
+ size_t off;
u_char data, mask;
+ u_long base;
{
int timeout;
u_char temp;
data &= mask;
- outb(port, data);
+ bus_io_write_1(bc, ioh, off, data);
timeout = 1000;
do {
delay(10);
- temp = inb(port) & mask;
+ temp = bus_io_read_1(bc, ioh, off) & mask;
} while (temp != data && --timeout);
- lprintf("lpt: port=0x%x out=0x%x in=0x%x timeout=%d\n", port, data,
- temp, timeout);
+ lprintf("lpt: port=0x%x out=0x%x in=0x%x timeout=%d\n", base + off,
+ data, temp, timeout);
return (temp == data);
}
void *match, *aux;
{
struct isa_attach_args *ia = aux;
- int iobase = ia->ia_iobase;
- int port;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
+ u_long base;
u_char mask, data;
- int i;
+ int i, rv;
#ifdef DEBUG
#define ABORT do {printf("lptprobe: mask %x data %x failed\n", mask, data); \
- return 0;} while (0)
+ goto out;} while (0)
#else
-#define ABORT return 0
+#define ABORT goto out
#endif
- port = iobase + lpt_data;
+ bc = ia->ia_bc;
+ base = ia->ia_iobase;
+ if (bus_io_map(bc, base, LPT_NPORTS, &ioh))
+ return 0;
+
+ rv = 0;
mask = 0xff;
data = 0x55; /* Alternating zeros */
- if (!lpt_port_test(port, data, mask))
+ if (!lpt_port_test(ioh, lpt_data, data, mask, base))
ABORT;
data = 0xaa; /* Alternating ones */
- if (!lpt_port_test(port, data, mask))
+ if (!lpt_port_test(ioh, lpt_data, data, mask, base))
ABORT;
for (i = 0; i < CHAR_BIT; i++) { /* Walking zero */
data = ~(1 << i);
- if (!lpt_port_test(port, data, mask))
+ if (!lpt_port_test(ioh, lpt_data, data, mask, base))
ABORT;
}
for (i = 0; i < CHAR_BIT; i++) { /* Walking one */
data = (1 << i);
- if (!lpt_port_test(port, data, mask))
+ if (!lpt_port_test(ioh, lpt_data, data, mask, base))
ABORT;
}
- outb(iobase + lpt_data, 0);
- outb(iobase + lpt_control, 0);
+ bus_io_write_1(bc, ioh, lpt_data, 0);
+ bus_io_write_1(bc, ioh, lpt_control, 0);
ia->ia_iosize = LPT_NPORTS;
ia->ia_msize = 0;
- return 1;
+
+ rv = 1;
+
+out:
+ bus_io_unmap(bc, ioh, LPT_NPORTS);
+ return rv;
}
void
{
struct lpt_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- int iobase = ia->ia_iobase;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
if (ia->ia_irq != IRQUNK)
printf("\n");
else
printf(": polled\n");
- sc->sc_iobase = iobase;
+ sc->sc_iobase = ia->ia_iobase;
sc->sc_irq = ia->ia_irq;
sc->sc_state = 0;
- outb(iobase + lpt_control, LPC_NINIT);
+
+ bc = sc->sc_bc = ia->ia_bc;
+ if (bus_io_map(bc, sc->sc_iobase, LPT_NPORTS, &ioh))
+ panic("lptattach: couldn't map I/O ports");
+ sc->sc_ioh = ioh;
+
+ bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
if (ia->ia_irq != IRQUNK)
sc->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_NONE,
int unit = LPTUNIT(dev);
u_char flags = LPTFLAGS(dev);
struct lpt_softc *sc;
- int iobase;
+ bus_chipset_tag_t bc;
+ bus_io_handle_t ioh;
u_char control;
int error;
int spin;
sc->sc_state = LPT_INIT;
sc->sc_flags = flags;
lprintf("%s: open: flags=0x%x\n", sc->sc_dev.dv_xname, flags);
- iobase = sc->sc_iobase;
+ bc = sc->sc_bc;
+ ioh = sc->sc_ioh;
if ((flags & LPT_NOPRIME) == 0) {
/* assert INIT for 100 usec to start up printer */
- outb(iobase + lpt_control, LPC_SELECT);
+ bus_io_write_1(bc, ioh, lpt_control, LPC_SELECT);
delay(100);
}
control = LPC_SELECT | LPC_NINIT;
- outb(iobase + lpt_control, control);
+ bus_io_write_1(bc, ioh, lpt_control, control);
/* wait till ready (printer running diagnostics) */
for (spin = 0; NOT_READY_ERR(); spin += STEP) {
if (flags & LPT_AUTOLF)
control |= LPC_AUTOLF;
sc->sc_control = control;
- outb(iobase + lpt_control, control);
+ bus_io_write_1(bc, ioh, lpt_control, control);
sc->sc_inbuf = geteblk(LPT_BSIZE);
sc->sc_count = 0;
{
int unit = LPTUNIT(dev);
struct lpt_softc *sc = lptcd.cd_devs[unit];
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
if (sc->sc_count)
(void) pushbytes(sc);
if ((sc->sc_flags & LPT_NOINTR) == 0)
untimeout(lptwakeup, sc);
- outb(iobase + lpt_control, LPC_NINIT);
+ bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
sc->sc_state = 0;
- outb(iobase + lpt_control, LPC_NINIT);
+ bus_io_write_1(bc, ioh, lpt_control, LPC_NINIT);
brelse(sc->sc_inbuf);
lprintf("%s: closed\n", sc->sc_dev.dv_xname);
pushbytes(sc)
struct lpt_softc *sc;
{
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
int error;
if (sc->sc_flags & LPT_NOINTR) {
break;
}
- outb(iobase + lpt_data, *sc->sc_cp++);
- outb(iobase + lpt_control, control | LPC_STROBE);
+ bus_io_write_1(bc, ioh, lpt_data, *sc->sc_cp++);
+ bus_io_write_1(bc, ioh, lpt_control, control | LPC_STROBE);
sc->sc_count--;
- outb(iobase + lpt_control, control);
+ bus_io_write_1(bc, ioh, lpt_control, control);
/* adapt busy-wait algorithm */
if (spin*2 + 16 < sc->sc_spinmax)
void *arg;
{
struct lpt_softc *sc = arg;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
+ bus_io_handle_t ioh = sc->sc_ioh;
if (((sc->sc_state & LPT_OPEN) == 0 && sc->sc_count == 0) || (sc->sc_flags & LPT_NOINTR))
return 0;
if (sc->sc_count) {
u_char control = sc->sc_control;
/* send char */
- outb(iobase + lpt_data, *sc->sc_cp++);
- outb(iobase + lpt_control, control | LPC_STROBE);
+ bus_io_write_1(bc, ioh, lpt_data, *sc->sc_cp++);
+ bus_io_write_1(bc, ioh, lpt_control, control | LPC_STROBE);
sc->sc_count--;
- outb(iobase + lpt_control, control);
+ bus_io_write_1(bc, ioh, lpt_control, control);
sc->sc_state |= LPT_OBUSY;
} else
sc->sc_state &= ~LPT_OBUSY;
-/* $OpenBSD: pas.c,v 1.7 1996/03/20 01:00:57 mickey Exp $ */
-/* $NetBSD: pas.c,v 1.12 1996/02/16 08:18:34 mycroft Exp $ */
+/* $OpenBSD: pas.c,v 1.8 1996/04/18 23:47:44 niklas Exp $ */
+/* $NetBSD: pas.c,v 1.13 1996/03/01 04:08:43 mycroft Exp $ */
/*
* Copyright (c) 1991-1993 Regents of the University of California.
* it is needed (and you pay the latency). Also, you might
* never need the buffer anyway.)
*/
- at_dma(1, &dmabuf, 1, ia->ia_drq);
+ at_dma(DMAMODE_READ, &dmabuf, 1, ia->ia_drq);
if (pas_wdsp(iobase, SB_DSP_RDMA) == 0) {
(void)pas_wdsp(iobase, 0);
(void)pas_wdsp(iobase, 0);
-/* $OpenBSD: rtfps.c,v 1.6 1996/03/20 01:01:01 mickey Exp $ */
-/* $NetBSD: rtfps.c,v 1.14 1995/12/24 02:31:48 mycroft Exp $ */
+/* $OpenBSD: rtfps.c,v 1.7 1996/04/18 23:47:45 niklas Exp $ */
+/* $NetBSD: rtfps.c,v 1.17 1996/03/10 09:01:28 cgd Exp $ */
/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1995 Charles Hannum. All rights reserved.
*
* This code is derived from public-domain software written by
#include <sys/param.h>
#include <sys/device.h>
-#include <machine/pio.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
+#include <dev/isa/comreg.h>
+#include <dev/isa/comvar.h>
+
+#define NSLAVES 4
struct rtfps_softc {
struct device sc_dev;
void *sc_ih;
+ bus_chipset_tag_t sc_bc;
int sc_iobase;
int sc_irqport;
- int sc_alive; /* mask of slave units attached */
- void *sc_slaves[4]; /* com device unit numbers */
+ bus_io_handle_t sc_irqioh;
+
+ int sc_alive; /* mask of slave units attached */
+ void *sc_slaves[NSLAVES]; /* com device unit numbers */
+ bus_io_handle_t sc_slaveioh[NSLAVES];
};
int rtfpsprobe();
void *aux;
{
struct isa_attach_args *ia = aux;
+ int iobase = ia->ia_iobase;
+ bus_chipset_tag_t bc = ia->ia_bc;
+ bus_io_handle_t ioh;
+ int i, rv = 1;
/*
* Do the normal com probe for the first UART and assume
- * its presence means there is a multiport board there.
+ * its presence, and the ability to map the other UARTS,
+ * means there is a multiport board there.
* XXX Needs more robustness.
*/
- ia->ia_iosize = 4 * 8;
- return comprobe1(ia->ia_iobase);
-}
-struct rtfps_attach_args {
- int ra_slave;
-};
+ /* if the first port is in use as console, then it. */
+ if (iobase == comconsaddr && !comconsattached)
+ goto checkmappings;
-int
-rtfpssubmatch(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- struct rtfps_softc *sc = (void *)parent;
- struct cfdata *cf = match;
- struct isa_attach_args *ia = aux;
- struct rtfps_attach_args *ra = ia->ia_aux;
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ rv = comprobe1(bc, ioh, iobase);
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ if (rv == 0)
+ goto out;
- if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ra->ra_slave)
- return (0);
- return ((*cf->cf_driver->cd_match)(parent, match, ia));
+checkmappings:
+ for (i = 1; i < NSLAVES; i++) {
+ iobase += COM_NPORTS;
+
+ if (iobase == comconsaddr && !comconsattached)
+ continue;
+
+ if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) {
+ rv = 0;
+ goto out;
+ }
+ bus_io_unmap(bc, ioh, COM_NPORTS);
+ }
+
+out:
+ if (rv)
+ ia->ia_iosize = NSLAVES * COM_NPORTS;
+ return (rv);
}
int
-rtfpsprint(aux, rtfps)
+rtfpsprint(aux, pnp)
void *aux;
- char *rtfps;
+ char *pnp;
{
- struct isa_attach_args *ia = aux;
- struct rtfps_attach_args *ra = ia->ia_aux;
+ struct commulti_attach_args *ca = aux;
- printf(" slave %d", ra->ra_slave);
+ if (pnp)
+ printf("com at %s", pnp);
+ printf(" slave %d", ca->ca_slave);
+ return (UNCONF);
}
void
{
struct rtfps_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- struct rtfps_attach_args ra;
+ struct commulti_attach_args ca;
struct isa_attach_args isa;
static int irqport[] = {
IOBASEUNK, IOBASEUNK, IOBASEUNK, IOBASEUNK,
IOBASEUNK, 0x2f2, 0x6f2, 0x6f3,
IOBASEUNK, IOBASEUNK, IOBASEUNK, IOBASEUNK
};
- int subunit;
+ int i, subunit;
+ sc->sc_bc = ia->ia_bc;
sc->sc_iobase = ia->ia_iobase;
if (ia->ia_irq >= 16 || irqport[ia->ia_irq] == IOBASEUNK)
panic("rtfpsattach: invalid irq");
sc->sc_irqport = irqport[ia->ia_irq];
- outb(sc->sc_irqport, 0);
+ for (i = 0; i < NSLAVES; i++)
+ if (bus_io_map(bc, sc->sc_iobase + i * COM_NPORTS, COM_NPORTS,
+ &sc->sc_slaveioh[i]))
+ panic("rtfpsattach: couldn't map slave %d", i);
+ if (bus_io_map(bc, sc->sc_irqport, 1, &sc->sc_irqioh))
+ panic("rtfpsattach: couldn't map irq port at 0x%x\n",
+ sc->sc_irqport);
+
+ bus_io_write_1(bc, sc->sc_irqioh, 0, 0);
printf("\n");
- isa.ia_aux = &ra;
- for (ra.ra_slave = 0; ra.ra_slave < 4; ra.ra_slave++) {
- struct cfdata *cf;
- isa.ia_iobase = sc->sc_iobase + 8 * ra.ra_slave;
- isa.ia_iosize = 0x666;
- isa.ia_irq = IRQUNK;
- isa.ia_drq = DRQUNK;
- isa.ia_msize = 0;
- if ((cf = config_search(rtfpssubmatch, self, &isa)) != 0) {
- subunit = cf->cf_unit; /* can change if unit == * */
- config_attach(self, cf, &isa, rtfpsprint);
- sc->sc_slaves[ra.ra_slave] =
- cf->cf_driver->cd_devs[subunit];
- sc->sc_alive |= 1 << ra.ra_slave;
+ for (i = 0; i < NSLAVES; i++) {
+ struct cfdata *match;
+
+ ca.ca_slave = i;
+ ca.ca_bc = sc->sc_bc;
+ ca.ca_ioh = sc->sc_slaveioh[i];
+ ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
+ ca.ca_noien = 0;
+
+ /* mimic config_found(), but with special functionality */
+ if ((match = config_search(NULL, self, &ca)) != NULL) {
+ subunit = match->cf_unit; /* can change if unit == * */
+ config_attach(self, match, &ca, rtfpsprint);
+ sc->sc_slaves[i] = match->cf_driver->cd_devs[subunit];
+ sc->sc_alive |= 1 << i;
+ } else {
+ rtfpsprint(&ca, self->dv_xname);
+ printf(" not configured\n");
}
}
- sc->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_TTY, rtfpsintr,
- sc, sc->sc_dev.dv_xname);
+ sc->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_TTY,
+ rtfpsintr, sc, sc->sc_dev.dv_xname);
}
int
void *arg;
{
struct rtfps_softc *sc = arg;
- int iobase = sc->sc_iobase;
+ bus_chipset_tag_t bc = sc->sc_bc;
int alive = sc->sc_alive;
- outb(sc->sc_irqport, 0);
+ bus_io_write_1(bc, sc->sc_irqioh, 0, 0);
#define TRY(n) \
if (alive & (1 << (n))) \
-/* $OpenBSD: sb.c,v 1.7 1996/03/20 01:01:01 mickey Exp $ */
-/* $NetBSD: sb.c,v 1.30 1996/02/16 08:18:32 mycroft Exp $ */
+/* $OpenBSD: sb.c,v 1.8 1996/04/18 23:47:46 niklas Exp $ */
+/* $NetBSD: sb.c,v 1.32 1996/03/16 04:00:09 jtk Exp $ */
/*
* Copyright (c) 1991-1993 Regents of the University of California.
NULL, "sb", sbprobe, sbattach, DV_DULL, sizeof(struct sbdsp_softc)
};
-struct audio_device sb_device = {
- "SoundBlaster",
- "x",
- "sb"
-};
-
int sbopen __P((dev_t, int));
int sb_getdev __P((void *, struct audio_device *));
return 0;
}
sc->sc_iobase = iobase;
+ sc->sc_irq = ia->ia_irq;
+ sc->sc_drq = ia->ia_drq;
+
if (sbdsp_probe(sc) == 0) {
DPRINTF(("sb: sbdsp probe failed\n"));
return 0;
}
}
- sc->sc_irq = ia->ia_irq;
- sc->sc_drq = ia->ia_drq;
-
if (ISSBPROCLASS(sc))
ia->ia_iosize = SBP_NPORT;
else
* it is needed (and you pay the latency). Also, you might
* never need the buffer anyway.)
*/
- at_dma(B_READ, &dmabuf, 1, ia->ia_drq);
+ at_dma(DMAMODE_READ, &dmabuf, 1, ia->ia_drq);
if (sbdsp_wdsp(iobase, SB_DSP_RDMA) == 0) {
(void)sbdsp_wdsp(iobase, 0);
(void)sbdsp_wdsp(iobase, 0);
sbdsp_attach(sc);
- sprintf(sb_device.version, "%d.%d",
- SBVER_MAJOR(sc->sc_model),
- SBVER_MINOR(sc->sc_model));
-
if ((err = audio_hardware_attach(&sb_hw_if, sc)) != 0)
printf("sb: could not attach to audio pseudo-device driver (%d)\n", err);
}
void *addr;
struct audio_device *retp;
{
- *retp = sb_device;
+ struct sbdsp_softc *sc = addr;
+
+ if (sc->sc_model & MODEL_JAZZ16)
+ strncpy(retp->name, "MV Jazz16", sizeof(retp->name));
+ else
+ strncpy(retp->name, "SoundBlaster", sizeof(retp->name));
+ sprintf(retp->version, "%d.%d",
+ SBVER_MAJOR(sc->sc_model),
+ SBVER_MINOR(sc->sc_model));
+ strncpy(retp->config, "sb", sizeof(retp->config));
+
return 0;
}
-/* $OpenBSD: sbdsp.c,v 1.3 1996/03/08 16:43:14 niklas Exp $ */
-/* $NetBSD: sbdsp.c,v 1.16 1996/02/16 10:10:21 mycroft Exp $ */
+/* $OpenBSD: sbdsp.c,v 1.4 1996/04/18 23:47:47 niklas Exp $ */
+/* $NetBSD: sbdsp.c,v 1.24 1996/03/16 04:00:11 jtk Exp $ */
/*
* Copyright (c) 1991-1993 Regents of the University of California.
int wmidi;
} sberr;
+int sbdsp_srtotc __P((struct sbdsp_softc *sc, int sr, int isdac,
+ int *tcp, int *modep));
+u_int sbdsp_jazz16_probe __P((struct sbdsp_softc *));
+
/*
* Time constant routines follow. See SBK, section 12.
* Although they don't come out and say it (in the docs),
printf("open %d dmachan %d iobase %x\n",
sc->sc_open, sc->sc_drq, sc->sc_iobase);
- printf("itc %d imode %d otc %d omode %d encoding %x\n",
- sc->sc_itc, sc->sc_imode, sc->sc_otc, sc->sc_omode, sc->encoding);
+ printf("irate %d itc %d imode %d orate %d otc %d omode %d encoding %x\n",
+ sc->sc_irate, sc->sc_itc, sc->sc_imode,
+ sc->sc_orate, sc->sc_otc, sc->sc_omode, sc->encoding);
printf("outport %d inport %d spkron %d nintr %d\n",
sc->out_port, sc->in_port, sc->spkr_state, sc->sc_interrupts);
- printf("chans %x intr %x arg %x\n",
- sc->sc_chans, sc->sc_intr, sc->sc_arg);
+ printf("precision %d channels %d intr %x arg %x\n",
+ sc->sc_precision, sc->sc_channels, sc->sc_intr, sc->sc_arg);
printf("gain: ");
for (i = 0; i < SB_NDEVS; i++)
printf("%d ", sc->gain[i]);
DPRINTF(("sbdsp: couldn't reset card\n"));
return 0;
}
- sc->sc_model = sbversion(sc);
+ /* if flags set, go and probe the jazz16 stuff */
+ if (sc->sc_dev.dv_cfdata->cf_flags != 0)
+ sc->sc_model = sbdsp_jazz16_probe(sc);
+ else
+ sc->sc_model = sbversion(sc);
return 1;
}
+/*
+ * Try add-on stuff for Jazz16.
+ */
+u_int
+sbdsp_jazz16_probe(sc)
+ struct sbdsp_softc *sc;
+{
+ static u_char jazz16_irq_conf[16] = {
+ -1, -1, 0x02, 0x03,
+ -1, 0x01, -1, 0x04,
+ -1, 0x02, 0x05, -1,
+ -1, -1, -1, 0x06};
+ static u_char jazz16_drq_conf[8] = {
+ -1, 0x01, -1, 0x02,
+ -1, 0x03, -1, 0x04};
+
+ u_int rval = sbversion(sc);
+ register int iobase = sc->sc_iobase;
+
+ if (jazz16_drq_conf[sc->sc_drq] == (u_char)-1 ||
+ jazz16_irq_conf[sc->sc_irq] == (u_char)-1)
+ return rval; /* give up, we can't do it. */
+ outb(JAZZ16_CONFIG_PORT, JAZZ16_WAKEUP);
+ delay(10000); /* delay 10 ms */
+ outb(JAZZ16_CONFIG_PORT, JAZZ16_SETBASE);
+ outb(JAZZ16_CONFIG_PORT, iobase & 0x70);
+
+ if (sbdsp_reset(sc) < 0)
+ return rval; /* XXX? what else could we do? */
+
+ if (sbdsp_wdsp(iobase, JAZZ16_READ_VER))
+ return rval;
+ if (sbdsp_rdsp(iobase) != JAZZ16_VER_JAZZ)
+ return rval;
+
+ if (sbdsp_wdsp(iobase, JAZZ16_SET_DMAINTR) ||
+ /* set both 8 & 16-bit drq to same channel, it works fine. */
+ sbdsp_wdsp(iobase,
+ (jazz16_drq_conf[sc->sc_drq] << 4) |
+ jazz16_drq_conf[sc->sc_drq]) ||
+ sbdsp_wdsp(iobase, jazz16_irq_conf[sc->sc_irq])) {
+ DPRINTF(("sbdsp: can't write jazz16 probe stuff"));
+ return rval;
+ }
+ return (rval | MODEL_JAZZ16);
+}
+
/*
* Attach hardware to driver, attach hardware driver to audio
* pseudo-device driver .
register int iobase = sc->sc_iobase;
/* Set defaults */
- if (ISSBPROCLASS(sc))
- sc->sc_itc = sc->sc_otc = SBPRO_ADC_HS_MAX;
+ if (ISSB16CLASS(sc))
+ sc->sc_irate = sc->sc_orate = 8000;
+ else if (ISSBPROCLASS(sc))
+ sc->sc_itc = sc->sc_otc = SB_8K;
else
- sc->sc_itc = sc->sc_otc = SBCLA_ADC_HS_MAX;
- sc->sc_chans = 1;
- sc->encoding = AUDIO_ENCODING_LINEAR;
+ sc->sc_itc = sc->sc_otc = SB_8K;
+ sc->sc_precision = 8;
+ sc->sc_channels = 1;
+ sc->encoding = AUDIO_ENCODING_ULAW;
(void) sbdsp_set_in_port(sc, SB_MIC_PORT);
(void) sbdsp_set_out_port(sc, SB_SPEAKER);
sbdsp_mix_write(sc, SBP_DAC_VOL,
sbdsp_stereo_vol(SBP_MAXVOL, SBP_MAXVOL));
sbdsp_mix_write(sc, SBP_MASTER_VOL,
- sbdsp_stereo_vol(SBP_MAXVOL, SBP_MAXVOL));
+ sbdsp_stereo_vol(SBP_MAXVOL/2, SBP_MAXVOL/2));
sbdsp_mix_write(sc, SBP_LINE_VOL,
sbdsp_stereo_vol(SBP_MAXVOL, SBP_MAXVOL));
for (i = 0; i < SB_NDEVS; i++)
sc->gain[i] = sbdsp_stereo_vol(SBP_MAXVOL, SBP_MAXVOL);
+ sc->in_filter = 0; /* no filters turned on, please */
}
- printf(": dsp v%d.%02d\n",
- SBVER_MAJOR(sc->sc_model), SBVER_MINOR(sc->sc_model));
+ printf(": dsp v%d.%02d%s\n",
+ SBVER_MAJOR(sc->sc_model), SBVER_MINOR(sc->sc_model),
+ ISJAZZ16(sc) ? ": <Jazz16>" : "");
+
+#ifdef notyet
+ sbdsp_mix_write(sc, SBP_SET_IRQ, 0x04);
+ sbdsp_mix_write(sc, SBP_SET_DRQ, 0x22);
+
+ printf("sbdsp_attach: irq=%02x, drq=%02x\n",
+ sbdsp_mix_read(sc, SBP_SET_IRQ),
+ sbdsp_mix_read(sc, SBP_SET_DRQ));
+#else
+ if (ISSB16CLASS(sc))
+ sc->sc_model = 0x0300;
+#endif
}
/*
{
register struct sbdsp_softc *sc = addr;
- return (sbdsp_srtotc(sc, sr, SB_INPUT_RATE, &sc->sc_itc, &sc->sc_imode));
+ if (ISSB16CLASS(sc))
+ return (sbdsp_setrate(sc, sr, SB_INPUT_RATE, &sc->sc_irate));
+ else
+ return (sbdsp_srtotc(sc, sr, SB_INPUT_RATE, &sc->sc_itc, &sc->sc_imode));
}
u_long
{
register struct sbdsp_softc *sc = addr;
- return (sbdsp_tctosr(sc, sc->sc_itc));
+ if (ISSB16CLASS(sc))
+ return (sc->sc_irate);
+ else
+ return (sbdsp_tctosr(sc, sc->sc_itc));
}
int
{
register struct sbdsp_softc *sc = addr;
- return (sbdsp_srtotc(sc, sr, SB_OUTPUT_RATE, &sc->sc_otc, &sc->sc_omode));
+ if (ISSB16CLASS(sc))
+ return (sbdsp_setrate(sc, sr, SB_OUTPUT_RATE, &sc->sc_orate));
+ else
+ return (sbdsp_srtotc(sc, sr, SB_OUTPUT_RATE, &sc->sc_otc, &sc->sc_omode));
}
u_long
{
register struct sbdsp_softc *sc = addr;
- return (sbdsp_tctosr(sc, sc->sc_otc));
+ if (ISSB16CLASS(sc))
+ return (sc->sc_orate);
+ else
+ return (sbdsp_tctosr(sc, sc->sc_otc));
}
int
}
int
-sbdsp_set_encoding(addr, enc)
+sbdsp_set_encoding(addr, encoding)
void *addr;
- u_int enc;
+ u_int encoding;
{
register struct sbdsp_softc *sc = addr;
- switch(enc){
+ switch (encoding) {
case AUDIO_ENCODING_ULAW:
sc->encoding = AUDIO_ENCODING_ULAW;
break;
default:
return (EINVAL);
}
+
return (0);
}
}
int
-sbdsp_set_precision(addr, prec)
+sbdsp_set_precision(addr, precision)
void *addr;
- u_int prec;
+ u_int precision;
{
+ register struct sbdsp_softc *sc = addr;
+
+ if (ISSB16CLASS(sc) || ISJAZZ16(sc)) {
+ if (precision != 16 && precision != 8)
+ return (EINVAL);
+ sc->sc_precision = precision;
+ } else {
+ if (precision != 8)
+ return (EINVAL);
+ sc->sc_precision = precision;
+ }
- if (prec != 8)
- return (EINVAL);
return (0);
}
sbdsp_get_precision(addr)
void *addr;
{
- return (8);
+ register struct sbdsp_softc *sc = addr;
+
+ return (sc->sc_precision);
}
int
-sbdsp_set_channels(addr, chans)
+sbdsp_set_channels(addr, channels)
void *addr;
- int chans;
+ int channels;
{
register struct sbdsp_softc *sc = addr;
if (ISSBPROCLASS(sc)) {
- if (chans != 1 && chans != 2)
+ if (channels != 1 && channels != 2)
return (EINVAL);
- sc->sc_chans = chans;
-
-#if 0
- if (rval = sbdsp_set_in_sr_real(addr, sc->sc_irate))
- return rval;
-#endif
-
- sbdsp_mix_write(sc, SBP_STEREO,
- (sbdsp_mix_read(sc, SBP_STEREO) & ~SBP_PLAYMODE_MASK) |
- (chans == 2 ? SBP_PLAYMODE_STEREO : SBP_PLAYMODE_MONO));
- /* recording channels needs to be done right when we start
- DMA recording. Just record number of channels for now
- and set stereo when ready. */
+ sc->sc_channels = channels;
+ sc->sc_dmadir = SB_DMA_NONE;
+ /*
+ * XXXX
+ * With 2 channels, SBPro can't do more than 22kHz.
+ * No framework to check this.
+ */
} else {
- if (chans != 1)
+ if (channels != 1)
return (EINVAL);
- sc->sc_chans = chans;
+ sc->sc_channels = channels;
}
return (0);
{
register struct sbdsp_softc *sc = addr;
-#if 0
- /* recording stereo may frob the mixer output */
+ return (sc->sc_channels);
+}
+
+int
+sbdsp_set_ifilter(addr, which)
+ void *addr;
+ int which;
+{
+ register struct sbdsp_softc *sc = addr;
+ int rval, mixval;
+
if (ISSBPROCLASS(sc)) {
- if ((sbdsp_mix_read(sc, SBP_STEREO) & SBP_PLAYMODE_MASK) == SBP_PLAYMODE_STEREO)
- sc->sc_chans = 2;
- else
- sc->sc_chans = 1;
+ mixval = sbdsp_mix_read(sc, SBP_INFILTER) & ~SBP_IFILTER_MASK;
+ switch (which) {
+ case 0:
+ mixval |= SBP_FILTER_OFF;
+ break;
+ case SBP_TREBLE_EQ:
+ mixval |= SBP_FILTER_ON | SBP_IFILTER_HIGH;
+ break;
+ case SBP_BASS_EQ:
+ mixval |= SBP_FILTER_ON | SBP_IFILTER_LOW;
+ break;
+ default:
+ return (EINVAL);
+ }
+ sc->in_filter = mixval & SBP_IFILTER_MASK;
+ sbdsp_mix_write(sc, SBP_INFILTER, mixval);
+ return (0);
} else
- sc->sc_chans = 1;
-#endif
+ return (EINVAL);
+}
- return (sc->sc_chans);
+int
+sbdsp_get_ifilter(addr)
+ void *addr;
+{
+ register struct sbdsp_softc *sc = addr;
+
+ if (ISSBPROCLASS(sc)) {
+ sc->in_filter =
+ sbdsp_mix_read(sc, SBP_INFILTER) & SBP_IFILTER_MASK;
+ switch (sc->in_filter) {
+ case SBP_FILTER_ON|SBP_IFILTER_HIGH:
+ return (SBP_TREBLE_EQ);
+ case SBP_FILTER_ON|SBP_IFILTER_LOW:
+ return (SBP_BASS_EQ);
+ case SBP_FILTER_OFF:
+ default:
+ return (0);
+ }
+ } else
+ return (0);
}
int
if (ISSBPROCLASS(sc)) {
/* record from that port */
sbdsp_mix_write(sc, SBP_RECORD_SOURCE,
- SBP_RECORD_FROM(sbport, SBP_FILTER_OFF,
- SBP_FILTER_HIGH));
+ SBP_RECORD_FROM(sbport, SBP_FILTER_OFF, SBP_IFILTER_HIGH));
/* fetch gain from that port */
sc->gain[port] = sbdsp_mix_read(sc, mixport);
}
sc->sc_last_hs_size = 0;
/* Higher speeds need bigger blocks to avoid popping and silence gaps. */
- if ((sc->sc_otc > SB_8K || sc->sc_itc > SB_8K) &&
- (blk > NBPG/2 || blk < NBPG/4))
- blk = NBPG/2;
+ if (blk < NBPG/4 || blk > NBPG/2) {
+ if (ISSB16CLASS(sc)) {
+ if (sc->sc_orate > 8000 || sc->sc_irate > 8000)
+ blk = NBPG/2;
+ } else {
+ if (sc->sc_otc > SB_8K || sc->sc_itc < SB_8K)
+ blk = NBPG/2;
+ }
+ }
/* don't try to DMA too much at once, though. */
if (blk > NBPG)
blk = NBPG;
- if (sc->sc_chans == 2)
+ if (sc->sc_channels == 2)
return (blk & ~1); /* must be even to preserve stereo separation */
else
return (blk); /* Anything goes :-) */
(adjust the proper channels), number of input channels (hit the
record rate and set mode) */
+ if (ISSBPRO(sc)) {
+ /*
+ * With 2 channels, SBPro can't do more than 22kHz.
+ * Whack the rates down to speed if necessary.
+ * Reset the time constant anyway
+ * because it may have been adjusted with a different number
+ * of channels, which means it might have computed the wrong
+ * mode (low/high speed).
+ */
+ if (sc->sc_channels == 2 &&
+ sbdsp_tctosr(sc, sc->sc_itc) > 22727) {
+ sbdsp_srtotc(sc, 22727, SB_INPUT_RATE,
+ &sc->sc_itc, &sc->sc_imode);
+ } else
+ sbdsp_srtotc(sc, sbdsp_tctosr(sc, sc->sc_itc),
+ SB_INPUT_RATE, &sc->sc_itc,
+ &sc->sc_imode);
+
+ if (sc->sc_channels == 2 &&
+ sbdsp_tctosr(sc, sc->sc_otc) > 22727) {
+ sbdsp_srtotc(sc, 22727, SB_OUTPUT_RATE,
+ &sc->sc_otc, &sc->sc_omode);
+ } else
+ sbdsp_srtotc(sc, sbdsp_tctosr(sc, sc->sc_otc),
+ SB_OUTPUT_RATE, &sc->sc_otc,
+ &sc->sc_omode);
+ }
+ if (ISSB16CLASS(sc) || ISJAZZ16(sc)) {
+ if (sc->encoding == AUDIO_ENCODING_ULAW &&
+ sc->sc_precision == 16) {
+ sc->sc_precision = 8;
+ return EINVAL; /* XXX what should we really do? */
+ }
+ }
/*
* XXX
* Should wait for chip to be idle.
return 0;
}
+int
+sbdsp16_wait(iobase)
+ int iobase;
+{
+ register int i;
+
+ for (i = SBDSP_NPOLL; --i >= 0; ) {
+ register u_char x;
+ x = inb(iobase + SBP_DSP_WSTAT);
+ delay(10);
+ if ((x & SB_DSP_BUSY) == 0)
+ continue;
+ return 0;
+ }
+ ++sberr.wdsp;
+ return -1;
+}
+
/*
* Write a byte to the dsp.
* XXX We are at the mercy of the card as we use a
return(0);
}
+int
+sbdsp_setrate(sc, sr, isdac, ratep)
+ register struct sbdsp_softc *sc;
+ int sr;
+ int isdac;
+ int *ratep;
+{
+
+ /*
+ * XXXX
+ * More checks here?
+ */
+ if (sr < 5000 || sr > 44100)
+ return (EINVAL);
+ *ratep = sr;
+ return (0);
+}
+
/*
* Convert a linear sampling rate into the DAC time constant.
* Set *mode to indicate the high/low-speed DMA operation.
int isdac;
int *tcp, *modep;
{
- int tc, mode;
+ int tc, realtc, mode;
+ /*
+ * Don't forget to compute which mode we'll be in based on whether
+ * we need to double the rate for stereo on SBPRO.
+ */
+
if (sr == 0) {
tc = SB_LS_MIN;
mode = SB_ADAC_LS;
}
tc = 256 - (1000000 / sr);
+
+ if (sc->sc_channels == 2 && ISSBPRO(sc))
+ /* compute based on 2x sample rate when needed */
+ realtc = 256 - ( 500000 / sr);
+ else
+ realtc = tc;
if (tc < SB_LS_MIN) {
tc = SB_LS_MIN;
- mode = SB_ADAC_LS;
+ mode = SB_ADAC_LS; /* NB: 2x minimum speed is still low
+ * speed mode. */
goto out;
} else if (isdac) {
- if (tc <= SB_DAC_LS_MAX)
+ if (realtc <= SB_DAC_LS_MAX)
mode = SB_ADAC_LS;
else {
mode = SB_ADAC_HS;
adc_hs_max = SBCLA_ADC_HS_MAX;
}
- if (tc <= adc_ls_max)
+ if (realtc <= adc_ls_max)
mode = SB_ADAC_LS;
else {
mode = SB_ADAC_HS;
}
int
-sbdsp_set_tc(sc, tc)
+sbdsp_set_timeconst(sc, tc)
register struct sbdsp_softc *sc;
int tc;
{
* A SBPro in stereo mode uses time constants at double the
* actual rate.
*/
- if (ISSBPRO(sc) && sc->sc_chans == 2)
+ if (ISSBPRO(sc) && sc->sc_channels == 2)
tc = 256 - ((256 - tc) / 2);
- DPRINTF(("sbdsp_set_tc: sc=%p tc=%d\n", sc, tc));
+ DPRINTF(("sbdsp_set_timeconst: sc=%p tc=%d\n", sc, tc));
iobase = sc->sc_iobase;
if (sbdsp_wdsp(iobase, SB_DSP_TIMECONST) < 0 ||
if (sbdspdebug > 1)
Dprintf("sbdsp_dma_input: cc=%d 0x%x (0x%x)\n", cc, intr, arg);
#endif
- if (sc->sc_chans == 2 && (cc & 1)) {
+ if (sc->sc_channels == 2 && (cc & 1)) {
DPRINTF(("sbdsp_dma_input: stereo input, odd bytecnt\n"));
return EIO;
}
iobase = sc->sc_iobase;
if (sc->sc_dmadir != SB_DMA_IN) {
- if (ISSBPROCLASS(sc)) {
- if (sc->sc_chans == 2) {
- if (sbdsp_wdsp(iobase, SB_DSP_RECORD_STEREO) < 0)
+ if (ISSBPRO(sc)) {
+ if (sc->sc_channels == 2) {
+ if (ISJAZZ16(sc) && sc->sc_precision == 16) {
+ if (sbdsp_wdsp(iobase,
+ JAZZ16_RECORD_STEREO) < 0) {
+ goto badmode;
+ }
+ } else if (sbdsp_wdsp(iobase,
+ SB_DSP_RECORD_STEREO) < 0)
goto badmode;
sbdsp_mix_write(sc, SBP_INFILTER,
- sbdsp_mix_read(sc, SBP_INFILTER) | SBP_FILTER_OFF);
+ (sbdsp_mix_read(sc, SBP_INFILTER) &
+ ~SBP_IFILTER_MASK) | SBP_FILTER_OFF);
} else {
- if (sbdsp_wdsp(iobase, SB_DSP_RECORD_MONO) < 0)
+ if (ISJAZZ16(sc) && sc->sc_precision == 16) {
+ if (sbdsp_wdsp(iobase,
+ JAZZ16_RECORD_MONO) < 0)
+ {
+ goto badmode;
+ }
+ } else if (sbdsp_wdsp(iobase, SB_DSP_RECORD_MONO) < 0)
goto badmode;
- sbdsp_mix_write(sc, SBP_INFILTER, sc->sc_itc > SB_8K ?
- sbdsp_mix_read(sc, SBP_INFILTER) | SBP_FILTER_OFF :
- sbdsp_mix_read(sc, SBP_INFILTER) & ~SBP_FILTER_MASK);
+ sbdsp_mix_write(sc, SBP_INFILTER,
+ (sbdsp_mix_read(sc, SBP_INFILTER) &
+ ~SBP_IFILTER_MASK) | sc->in_filter);
}
}
- sbdsp_set_tc(sc, sc->sc_itc);
+ if (ISSB16CLASS(sc)) {
+ if (sbdsp_wdsp(iobase, SB_DSP16_INPUTRATE) < 0 ||
+ sbdsp_wdsp(iobase, sc->sc_irate >> 8) < 0 ||
+ sbdsp_wdsp(iobase, sc->sc_irate) < 0)
+ goto giveup;
+ } else
+ sbdsp_set_timeconst(sc, sc->sc_itc);
sc->sc_dmadir = SB_DMA_IN;
}
- isa_dmastart(B_READ, p, cc, sc->sc_drq);
+ isa_dmastart(DMAMODE_READ, p, cc, sc->sc_drq);
sc->sc_intr = intr;
sc->sc_arg = arg;
- sc->dmaflags = B_READ;
+ sc->dmaflags = DMAMODE_READ;
sc->dmaaddr = p;
- sc->dmacnt = --cc; /* DMA controller is strange...? */
-
- if (sc->sc_imode == SB_ADAC_LS) {
+ sc->dmacnt = cc; /* DMA controller is strange...? */
+
+ if ((ISSB16CLASS(sc) && sc->sc_precision == 16) ||
+ (ISJAZZ16(sc) && sc->sc_drq > 3))
+ cc >>= 1;
+ --cc;
+ if (ISSB16CLASS(sc)) {
+ if (sbdsp_wdsp(iobase, sc->sc_precision == 16 ? SB_DSP16_RDMA_16 :
+ SB_DSP16_RDMA_8) < 0 ||
+ sbdsp_wdsp(iobase, (sc->sc_precision == 16 ? 0x10 : 0x00) |
+ (sc->sc_channels == 2 ? 0x20 : 0x00)) < 0 ||
+ sbdsp16_wait(iobase) ||
+ sbdsp_wdsp(iobase, cc) < 0 ||
+ sbdsp_wdsp(iobase, cc >> 8) < 0) {
+ DPRINTF(("sbdsp_dma_input: SB16 DMA start failed\n"));
+ goto giveup;
+ }
+ } else if (sc->sc_imode == SB_ADAC_LS) {
if (sbdsp_wdsp(iobase, SB_DSP_RDMA) < 0 ||
sbdsp_wdsp(iobase, cc) < 0 ||
sbdsp_wdsp(iobase, cc >> 8) < 0) {
DPRINTF(("sbdsp_dma_input: LS DMA start failed\n"));
goto giveup;
}
- }
- else {
+ } else {
if (cc != sc->sc_last_hs_size) {
if (sbdsp_wdsp(iobase, SB_DSP_BLOCKSIZE) < 0 ||
sbdsp_wdsp(iobase, cc) < 0 ||
badmode:
DPRINTF(("sbdsp_dma_input: can't set %s mode\n",
- sc->sc_chans == 2 ? "stereo" : "mono"));
+ sc->sc_channels == 2 ? "stereo" : "mono"));
return EIO;
}
if (sbdspdebug > 1)
Dprintf("sbdsp_dma_output: cc=%d 0x%x (0x%x)\n", cc, intr, arg);
#endif
- if (sc->sc_chans == 2 && (cc & 1)) {
+ if (sc->sc_channels == 2 && (cc & 1)) {
DPRINTF(("stereo playback odd bytes (%d)\n", cc));
return EIO;
}
iobase = sc->sc_iobase;
if (sc->sc_dmadir != SB_DMA_OUT) {
- if (ISSBPROCLASS(sc)) {
+ if (ISSBPRO(sc)) {
/* make sure we re-set stereo mixer bit when we start
output. */
sbdsp_mix_write(sc, SBP_STEREO,
(sbdsp_mix_read(sc, SBP_STEREO) & ~SBP_PLAYMODE_MASK) |
- (sc->sc_chans == 2 ? SBP_PLAYMODE_STEREO : SBP_PLAYMODE_MONO));
+ (sc->sc_channels == 2 ? SBP_PLAYMODE_STEREO : SBP_PLAYMODE_MONO));
+ if (ISJAZZ16(sc)) {
+ /* Yes, we write the record mode to set
+ 16-bit playback mode. weird, huh? */
+ if (sc->sc_precision == 16) {
+ sbdsp_wdsp(iobase,
+ sc->sc_channels == 2 ?
+ JAZZ16_RECORD_STEREO :
+ JAZZ16_RECORD_MONO);
+ } else {
+ sbdsp_wdsp(iobase,
+ sc->sc_channels == 2 ?
+ SB_DSP_RECORD_STEREO :
+ SB_DSP_RECORD_MONO);
+ }
+ }
}
- sbdsp_set_tc(sc, sc->sc_otc);
+ if (ISSB16CLASS(sc)) {
+ if (sbdsp_wdsp(iobase, SB_DSP16_OUTPUTRATE) < 0 ||
+ sbdsp_wdsp(iobase, sc->sc_orate >> 8) < 0 ||
+ sbdsp_wdsp(iobase, sc->sc_orate) < 0)
+ goto giveup;
+ } else
+ sbdsp_set_timeconst(sc, sc->sc_otc);
sc->sc_dmadir = SB_DMA_OUT;
}
- isa_dmastart(B_WRITE, p, cc, sc->sc_drq);
+ isa_dmastart(DMAMODE_WRITE, p, cc, sc->sc_drq);
sc->sc_intr = intr;
sc->sc_arg = arg;
- sc->dmaflags = B_WRITE;
+ sc->dmaflags = DMAMODE_WRITE;
sc->dmaaddr = p;
- sc->dmacnt = --cc; /* a vagary of how DMA works, apparently. */
-
- if (sc->sc_omode == SB_ADAC_LS) {
+ sc->dmacnt = cc; /* a vagary of how DMA works, apparently. */
+
+ if ((ISSB16CLASS(sc) && sc->sc_precision == 16) ||
+ (ISJAZZ16(sc) && sc->sc_drq > 3))
+ cc >>= 1;
+ --cc;
+ if (ISSB16CLASS(sc)) {
+ if (sbdsp_wdsp(iobase, sc->sc_precision == 16 ? SB_DSP16_WDMA_16 :
+ SB_DSP16_WDMA_8) < 0 ||
+ sbdsp_wdsp(iobase, (sc->sc_precision == 16 ? 0x10 : 0x00) |
+ (sc->sc_channels == 2 ? 0x20 : 0x00)) < 0 ||
+ sbdsp16_wait(iobase) ||
+ sbdsp_wdsp(iobase, cc) < 0 ||
+ sbdsp_wdsp(iobase, cc >> 8) < 0) {
+ DPRINTF(("sbdsp_dma_output: SB16 DMA start failed\n"));
+ goto giveup;
+ }
+ } else if (sc->sc_omode == SB_ADAC_LS) {
if (sbdsp_wdsp(iobase, SB_DSP_WDMA) < 0 ||
sbdsp_wdsp(iobase, cc) < 0 ||
sbdsp_wdsp(iobase, cc >> 8) < 0) {
DPRINTF(("sbdsp_dma_output: LS DMA start failed\n"));
goto giveup;
}
- }
- else {
+ } else {
if (cc != sc->sc_last_hs_size) {
if (sbdsp_wdsp(iobase, SB_DSP_BLOCKSIZE) < 0 ||
sbdsp_wdsp(iobase, cc) < 0 ||
if (sbdspdebug > 1)
Dprintf("sbdsp_intr: intr=0x%x\n", sc->sc_intr);
#endif
+ if (!isa_dmafinished(sc->sc_drq)) {
+ printf("sbdsp_intr: not finished\n");
+ return 0;
+ }
sc->sc_interrupts++;
/* clear interrupt */
+#ifdef notyet
+ x = sbdsp_mix_read(sc, 0x82);
+ x = inb(sc->sc_iobase + 15);
+#endif
x = inb(sc->sc_iobase + SBP_DSP_RSTAT);
delay(10);
-#if 0
- if ((x & SB_DSP_READY) == 0) {
- printf("sbdsp_intr: still busy\n");
- return 0;
- }
-#endif
#if 0
if (sc->sc_mintr != 0) {
x = sbdsp_rdsp(sc->sc_iobase);
} else
#endif
if (sc->sc_intr != 0) {
- /*
- * The SBPro used to develop and test this driver often
- * generated dma underruns--it interrupted to signal
- * completion of the DMA input recording block, but the
- * ISA DMA controller didn't think the channel was
- * finished. Maybe this is just a bus speed issue, I dunno,
- * but it seems strange and leads to channel-flipping with
- * stereo recording. Sigh.
- */
- isa_dmadone(sc->dmaflags, sc->dmaaddr, sc->dmacnt,
- sc->sc_drq);
+ isa_dmadone(sc->dmaflags, sc->dmaaddr, sc->dmacnt, sc->sc_drq);
(*sc->sc_intr)(sc->sc_arg);
}
else
#endif
u_int
-sbdsp_get_silence(enc)
- int enc;
+sbdsp_get_silence(encoding)
+ int encoding;
{
#define ULAW_SILENCE 0x7f
#define LINEAR_SILENCE 0
- u_int auzero;
+ u_int auzero;
- switch (enc) {
- case AUDIO_ENCODING_ULAW:
- auzero = ULAW_SILENCE;
- break;
- case AUDIO_ENCODING_PCM16:
- default:
- auzero = LINEAR_SILENCE;
- break;
- }
-
- return(auzero);
+ switch (encoding) {
+ case AUDIO_ENCODING_ULAW:
+ auzero = ULAW_SILENCE;
+ break;
+ case AUDIO_ENCODING_PCM16:
+ default:
+ auzero = LINEAR_SILENCE;
+ break;
+ }
+
+ return (auzero);
}
int
int
sbdsp_mixer_set_port(addr, cp)
- void *addr;
- mixer_ctrl_t *cp;
+ void *addr;
+ mixer_ctrl_t *cp;
{
- register struct sbdsp_softc *sc = addr;
- int error = 0;
- int src, gain;
- int left, right;
+ register struct sbdsp_softc *sc = addr;
+ int src, gain;
- DPRINTF(("sbdsp_mixer_set_port: port=%d num_channels=%d\n", cp->dev, cp->un.value.num_channels));
-
- /*
- * Everything is a value except for SBPro special OUTPUT_MODE and
- * RECORD_SOURCE
- */
- if (cp->type != AUDIO_MIXER_VALUE) {
- if (!ISSBPROCLASS(sc) || (cp->dev != SB_OUTPUT_MODE &&
- cp->dev != SB_RECORD_SOURCE))
- return EINVAL;
- }
- else {
+ DPRINTF(("sbdsp_mixer_set_port: port=%d num_channels=%d\n", cp->dev,
+ cp->un.value.num_channels));
+
+ if (!ISSBPROCLASS(sc))
+ return EINVAL;
+
/*
- * All the mixer ports are stereo except for the microphone.
- * If we get a single-channel gain value passed in, then we
- * duplicate it to both left and right channels.
- */
- if (cp->un.value.num_channels == 2) {
- left = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
- right = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
- }
- else
- left = right = cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
- }
-
- if (ISSBPROCLASS(sc)) {
- /* The _PORT things are all signal inputs to the mixer.
- * Here we are tweaking their mixing level.
- *
- * We can also tweak the output stage volume (MASTER_VOL)
+ * Everything is a value except for SBPro BASS/TREBLE and
+ * RECORD_SOURCE
*/
- gain = sbdsp_stereo_vol(SBP_AGAIN_TO_SBGAIN(left),
- SBP_AGAIN_TO_SBGAIN(right));
- switch(cp->dev) {
- case SB_MIC_PORT:
- src = SBP_MIC_VOL;
- if (cp->un.value.num_channels != 1)
- error = EINVAL;
- else
- /* handle funny microphone gain */
- gain = SBP_AGAIN_TO_MICGAIN(left);
- break;
- case SB_LINE_IN_PORT:
- src = SBP_LINE_VOL;
- break;
- case SB_DAC_PORT:
- src = SBP_DAC_VOL;
- break;
- case SB_FM_PORT:
- src = SBP_FM_VOL;
- break;
- case SB_CD_PORT:
- src = SBP_CD_VOL;
- break;
+ switch (cp->dev) {
case SB_SPEAKER:
- cp->dev = SB_MASTER_VOL;
- case SB_MASTER_VOL:
- src = SBP_MASTER_VOL;
- break;
-#if 0
- case SB_OUTPUT_MODE:
- if (cp->type == AUDIO_MIXER_ENUM)
- return sbdsp_set_channels(addr, cp->un.ord);
- /* fall through...carefully! */
-#endif
+ cp->dev = SB_MASTER_VOL;
+ case SB_MIC_PORT:
+ case SB_LINE_IN_PORT:
+ case SB_DAC_PORT:
+ case SB_FM_PORT:
+ case SB_CD_PORT:
+ case SB_MASTER_VOL:
+ if (cp->type != AUDIO_MIXER_VALUE)
+ return EINVAL;
+
+ /*
+ * All the mixer ports are stereo except for the microphone.
+ * If we get a single-channel gain value passed in, then we
+ * duplicate it to both left and right channels.
+ */
+
+ switch (cp->dev) {
+ case SB_MIC_PORT:
+ if (cp->un.value.num_channels != 1)
+ return EINVAL;
+
+ /* handle funny microphone gain */
+ gain = SBP_AGAIN_TO_MICGAIN(cp->un.value.level[AUDIO_MIXER_LEVEL_MONO]);
+ break;
+ case SB_LINE_IN_PORT:
+ case SB_DAC_PORT:
+ case SB_FM_PORT:
+ case SB_CD_PORT:
+ case SB_MASTER_VOL:
+ switch (cp->un.value.num_channels) {
+ case 1:
+ gain = sbdsp_mono_vol(SBP_AGAIN_TO_SBGAIN(cp->un.value.level[AUDIO_MIXER_LEVEL_MONO]));
+ break;
+ case 2:
+ gain = sbdsp_stereo_vol(SBP_AGAIN_TO_SBGAIN(cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT]),
+ SBP_AGAIN_TO_SBGAIN(cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]));
+ break;
+ default:
+ return EINVAL;
+ }
+ break;
+ }
+
+ switch (cp->dev) {
+ case SB_MIC_PORT:
+ src = SBP_MIC_VOL;
+ break;
+ case SB_MASTER_VOL:
+ src = SBP_MASTER_VOL;
+ break;
+ case SB_LINE_IN_PORT:
+ src = SBP_LINE_VOL;
+ break;
+ case SB_DAC_PORT:
+ src = SBP_DAC_VOL;
+ break;
+ case SB_FM_PORT:
+ src = SBP_FM_VOL;
+ break;
+ case SB_CD_PORT:
+ src = SBP_CD_VOL;
+ break;
+ }
+
+ sbdsp_mix_write(sc, src, gain);
+ sc->gain[cp->dev] = gain;
+ break;
+
+ case SB_TREBLE:
+ case SB_BASS:
case SB_RECORD_SOURCE:
- if (cp->type == AUDIO_MIXER_ENUM)
- return sbdsp_set_in_port(addr, cp->un.ord);
- /* else fall through: bad input */
- case SB_TREBLE:
- case SB_BASS:
- default:
- error = EINVAL;
- break;
- }
- if (!error)
- sbdsp_mix_write(sc, src, gain);
- }
- else if (cp->dev != SB_MIC_PORT &&
- cp->dev != SB_SPEAKER)
- error = EINVAL;
+ if (cp->type != AUDIO_MIXER_ENUM)
+ return EINVAL;
+
+ switch (cp->dev) {
+ case SB_TREBLE:
+ return sbdsp_set_ifilter(addr, cp->un.ord ? SBP_TREBLE_EQ : 0);
+ case SB_BASS:
+ return sbdsp_set_ifilter(addr, cp->un.ord ? SBP_BASS_EQ : 0);
+ case SB_RECORD_SOURCE:
+ return sbdsp_set_in_port(addr, cp->un.ord);
+ }
+
+ break;
- if (!error)
- sc->gain[cp->dev] = gain;
+ default:
+ return EINVAL;
+ }
- return(error);
+ return (0);
}
int
sbdsp_mixer_get_port(addr, cp)
- void *addr;
- mixer_ctrl_t *cp;
+ void *addr;
+ mixer_ctrl_t *cp;
{
- register struct sbdsp_softc *sc = addr;
- int error = 0;
- int done = 0;
+ register struct sbdsp_softc *sc = addr;
+ int gain;
- DPRINTF(("sbdsp_mixer_get_port: port=%d", cp->dev));
-
- if (ISSBPROCLASS(sc))
- switch(cp->dev) {
- case SB_MIC_PORT:
- if (cp->un.value.num_channels == 1) {
- cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
- SBP_MICGAIN_TO_AGAIN(sc->gain[cp->dev]);
- return 0;
- }
- else
+ DPRINTF(("sbdsp_mixer_get_port: port=%d", cp->dev));
+
+ if (!ISSBPROCLASS(sc))
return EINVAL;
- break;
- case SB_LINE_IN_PORT:
- case SB_DAC_PORT:
- case SB_FM_PORT:
- case SB_CD_PORT:
- case SB_MASTER_VOL:
- break;
+
+ switch (cp->dev) {
case SB_SPEAKER:
- cp->dev = SB_MASTER_VOL;
- break;
- default:
- error = EINVAL;
- break;
- }
- else {
- if (cp->un.value.num_channels != 1) /* no stereo on SB classic */
- error = EINVAL;
- else
- switch(cp->dev) {
- case SB_MIC_PORT:
- break;
- case SB_SPEAKER:
+ cp->dev = SB_MASTER_VOL;
+ case SB_MIC_PORT:
+ case SB_LINE_IN_PORT:
+ case SB_DAC_PORT:
+ case SB_FM_PORT:
+ case SB_CD_PORT:
+ case SB_MASTER_VOL:
+ gain = sc->gain[cp->dev];
+
+ switch (cp->dev) {
+ case SB_MIC_PORT:
+ if (cp->un.value.num_channels != 1)
+ return EINVAL;
+
+ cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = SBP_MICGAIN_TO_AGAIN(gain);
+ break;
+ case SB_LINE_IN_PORT:
+ case SB_DAC_PORT:
+ case SB_FM_PORT:
+ case SB_CD_PORT:
+ case SB_MASTER_VOL:
+ switch (cp->un.value.num_channels) {
+ case 1:
+ cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = SBP_SBGAIN_TO_AGAIN(gain);
+ break;
+ case 2:
+ cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = SBP_LEFTGAIN(gain);
+ cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = SBP_RIGHTGAIN(gain);
+ break;
+ default:
+ return EINVAL;
+ }
+ break;
+ }
+
break;
- default:
- error = EINVAL;
+
+ case SB_TREBLE:
+ case SB_BASS:
+ case SB_RECORD_SOURCE:
+ switch (cp->dev) {
+ case SB_TREBLE:
+ cp->un.ord = sbdsp_get_ifilter(addr) == SBP_TREBLE_EQ;
+ return 0;
+ case SB_BASS:
+ cp->un.ord = sbdsp_get_ifilter(addr) == SBP_BASS_EQ;
+ return 0;
+ case SB_RECORD_SOURCE:
+ cp->un.ord = sbdsp_get_in_port(addr);
+ return 0;
+ }
+
break;
- }
- }
- if (error == 0) {
- if (cp->un.value.num_channels == 1) {
- cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
- SBP_SBGAIN_TO_AGAIN(sc->gain[cp->dev]);
+
+ default:
+ return EINVAL;
}
- else if (cp->un.value.num_channels == 2) {
- cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
- SBP_LEFTGAIN(sc->gain[cp->dev]);
- cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
- SBP_RIGHTGAIN(sc->gain[cp->dev]);
- } else
- return EINVAL;
- }
- return(error);
+
+ return (0);
}
int
sbdsp_mixer_query_devinfo(addr, dip)
- void *addr;
- register mixer_devinfo_t *dip;
+ void *addr;
+ register mixer_devinfo_t *dip;
{
- register struct sbdsp_softc *sc = addr;
- int done = 0;
-
- DPRINTF(("sbdsp_mixer_query_devinfo: index=%d\n", dip->index));
-
- switch (dip->index) {
- case SB_MIC_PORT:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_INPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNmicrophone);
- dip->un.v.num_channels = 1;
- strcpy(dip->un.v.units.name, AudioNvolume);
- done = 1;
- break;
- case SB_SPEAKER:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_OUTPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNspeaker);
- dip->un.v.num_channels = 1;
- strcpy(dip->un.v.units.name, AudioNvolume);
- done = 1;
- break;
- case SB_INPUT_CLASS:
- dip->type = AUDIO_MIXER_CLASS;
- dip->mixer_class = SB_INPUT_CLASS;
- dip->next = dip->prev = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioCInputs);
- done = 1;
- break;
- case SB_OUTPUT_CLASS:
- dip->type = AUDIO_MIXER_CLASS;
- dip->mixer_class = SB_OUTPUT_CLASS;
- dip->next = dip->prev = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioCOutputs);
- done = 1;
- break;
- }
-
- if (!done) {
- if (ISSBPROCLASS(sc))
- switch(dip->index) {
- case SB_LINE_IN_PORT:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_INPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNline);
- dip->un.v.num_channels = 2;
- strcpy(dip->un.v.units.name, AudioNvolume);
- break;
- case SB_DAC_PORT:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_OUTPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNdac);
- dip->un.v.num_channels = 2;
- strcpy(dip->un.v.units.name, AudioNvolume);
- break;
- case SB_CD_PORT:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_INPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNcd);
- dip->un.v.num_channels = 2;
- strcpy(dip->un.v.units.name, AudioNvolume);
- break;
- case SB_FM_PORT:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_OUTPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNfmsynth);
- dip->un.v.num_channels = 2;
- strcpy(dip->un.v.units.name, AudioNvolume);
- break;
- case SB_MASTER_VOL:
- dip->type = AUDIO_MIXER_VALUE;
- dip->mixer_class = SB_OUTPUT_CLASS;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = /*TREBLE, BASS not handled, nor is SB_OUTPUT_MODE*/SB_RECORD_SOURCE;
- strcpy(dip->label.name, AudioNvolume);
- dip->un.v.num_channels = 2;
- strcpy(dip->un.v.units.name, AudioNvolume);
- break;
-#if 0
- case SB_OUTPUT_MODE:
- dip->mixer_class = SB_OUTPUT_CLASS;
- dip->type = AUDIO_MIXER_ENUM;
- dip->prev = SB_MASTER_VOL;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNmode);
- dip->un.e.num_mem = 2;
- strcpy(dip->un.e.member[0].label.name, AudioNmono);
- dip->un.e.member[0].ord = 1; /* nchans */
- strcpy(dip->un.e.member[1].label.name, AudioNstereo);
- dip->un.e.member[1].ord = 2; /* nchans */
- break;
-#endif
- case SB_RECORD_SOURCE:
- dip->mixer_class = SB_RECORD_CLASS;
- dip->type = AUDIO_MIXER_ENUM;
- dip->prev = AUDIO_MIXER_LAST;
- dip->next = AUDIO_MIXER_LAST;
- strcpy(dip->label.name, AudioNsource);
- dip->un.e.num_mem = 3;
- strcpy(dip->un.e.member[0].label.name, AudioNmicrophone);
- dip->un.e.member[0].ord = SB_MIC_PORT;
- strcpy(dip->un.e.member[1].label.name, AudioNcd);
- dip->un.e.member[1].ord = SB_CD_PORT;
- strcpy(dip->un.e.member[2].label.name, AudioNline);
- dip->un.e.member[2].ord = SB_LINE_IN_PORT;
- break;
- case SB_BASS:
- case SB_TREBLE:
- default:
- return ENXIO;
- /*NOTREACHED*/
- }
- else
- return ENXIO;
- }
+ register struct sbdsp_softc *sc = addr;
- DPRINTF(("AUDIO_MIXER_DEVINFO: name=%s\n", dip->label.name));
+ DPRINTF(("sbdsp_mixer_query_devinfo: index=%d\n", dip->index));
+
+ switch (dip->index) {
+ case SB_MIC_PORT:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNmicrophone);
+ dip->un.v.num_channels = 1;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case SB_SPEAKER:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_OUTPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNspeaker);
+ dip->un.v.num_channels = 1;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
- return 0;
+ case SB_INPUT_CLASS:
+ dip->type = AUDIO_MIXER_CLASS;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->next = dip->prev = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioCInputs);
+ return 0;
+
+ case SB_OUTPUT_CLASS:
+ dip->type = AUDIO_MIXER_CLASS;
+ dip->mixer_class = SB_OUTPUT_CLASS;
+ dip->next = dip->prev = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioCOutputs);
+ return 0;
+ }
+
+ if (ISSBPROCLASS(sc)) {
+ switch (dip->index) {
+ case SB_LINE_IN_PORT:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNline);
+ dip->un.v.num_channels = 2;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case SB_DAC_PORT:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNdac);
+ dip->un.v.num_channels = 2;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case SB_CD_PORT:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNcd);
+ dip->un.v.num_channels = 2;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case SB_FM_PORT:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNfmsynth);
+ dip->un.v.num_channels = 2;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case SB_MASTER_VOL:
+ dip->type = AUDIO_MIXER_VALUE;
+ dip->mixer_class = SB_OUTPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNvolume);
+ dip->un.v.num_channels = 2;
+ strcpy(dip->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case SB_RECORD_SOURCE:
+ dip->mixer_class = SB_RECORD_CLASS;
+ dip->type = AUDIO_MIXER_ENUM;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNsource);
+ dip->un.e.num_mem = 3;
+ strcpy(dip->un.e.member[0].label.name, AudioNmicrophone);
+ dip->un.e.member[0].ord = SB_MIC_PORT;
+ strcpy(dip->un.e.member[1].label.name, AudioNcd);
+ dip->un.e.member[1].ord = SB_CD_PORT;
+ strcpy(dip->un.e.member[2].label.name, AudioNline);
+ dip->un.e.member[2].ord = SB_LINE_IN_PORT;
+ return 0;
+
+ case SB_BASS:
+ dip->type = AUDIO_MIXER_ENUM;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNbass);
+ dip->un.e.num_mem = 2;
+ strcpy(dip->un.e.member[0].label.name, AudioNoff);
+ dip->un.e.member[0].ord = 0;
+ strcpy(dip->un.e.member[1].label.name, AudioNon);
+ dip->un.e.member[1].ord = 1;
+ return 0;
+
+ case SB_TREBLE:
+ dip->type = AUDIO_MIXER_ENUM;
+ dip->mixer_class = SB_INPUT_CLASS;
+ dip->prev = AUDIO_MIXER_LAST;
+ dip->next = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioNtreble);
+ dip->un.e.num_mem = 2;
+ strcpy(dip->un.e.member[0].label.name, AudioNoff);
+ dip->un.e.member[0].ord = 0;
+ strcpy(dip->un.e.member[1].label.name, AudioNon);
+ dip->un.e.member[1].ord = 1;
+ return 0;
+
+ case SB_RECORD_CLASS: /* record source class */
+ dip->type = AUDIO_MIXER_CLASS;
+ dip->mixer_class = SB_RECORD_CLASS;
+ dip->next = dip->prev = AUDIO_MIXER_LAST;
+ strcpy(dip->label.name, AudioCRecord);
+ return 0;
+ }
+ }
+
+ return ENXIO;
}
-/* $OpenBSD: sbdspvar.h,v 1.3 1996/03/08 16:43:15 niklas Exp $ */
-/* $NetBSD: sbdspvar.h,v 1.9 1996/02/16 10:10:23 mycroft Exp $ */
+/* $OpenBSD: sbdspvar.h,v 1.4 1996/04/18 23:47:48 niklas Exp $ */
+/* $NetBSD: sbdspvar.h,v 1.12 1996/03/16 04:00:13 jtk Exp $ */
/*
* Copyright (c) 1991-1993 Regents of the University of California.
#define SB_MIC_PORT 0
#define SB_SPEAKER 1
-#define SB_LINE_IN_PORT 2
-#define SB_DAC_PORT 3
-#define SB_FM_PORT 4
-#define SB_CD_PORT 5
-#define SB_MASTER_VOL 6
-#define SB_TREBLE 7
-#define SB_BASS 8
-#define SB_NDEVS 9
-
-#define SB_OUTPUT_MODE 9
+#define SB_INPUT_CLASS 2
+#define SB_OUTPUT_CLASS 3
+#define SB_LINE_IN_PORT 4
+#define SB_DAC_PORT 5
+#define SB_FM_PORT 6
+#define SB_CD_PORT 7
+#define SB_MASTER_VOL 8
+#define SB_TREBLE 9
+#define SB_BASS 10
+#define SB_NDEVS 11 /* XXX include classes above for
+ contiguous number space on
+ original SB */
+
+/*#define SB_OUTPUT_MODE 9
#define SB_SPKR_MONO 0
-#define SB_SPKR_STEREO 1
+#define SB_SPKR_STEREO 1*/
-#define SB_RECORD_SOURCE 10
+#define SB_RECORD_SOURCE 11
-#define SB_INPUT_CLASS 11
-#define SB_OUTPUT_CLASS 12
-#define SB_RECORD_CLASS 13
+#define SB_RECORD_CLASS 12
/*
int sc_iobase; /* I/O port base address */
int sc_irq; /* interrupt */
- int sc_drq; /* DMA */
+ int sc_drq; /* DMA (8-bit) */
+ int sc_drq16; /* DMA (16-bit) */
u_short sc_open; /* reference count of open calls */
u_int out_port; /* output port */
u_int in_port; /* input port */
+ u_int in_filter; /* one of SB_TREBLE_EQ, SB_BASS_EQ, 0 */
u_int spkr_state; /* non-null is on */
- int sc_itc; /* Sample rate for input */
- int sc_otc; /* ...and output */
+ int sc_irate, sc_itc; /* Sample rate for input */
+ int sc_orate, sc_otc; /* ...and output */
int sc_imode;
int sc_omode;
caddr_t dmaaddr;
vm_size_t dmacnt;
int sc_last_hs_size; /* last HS dma size */
- int sc_chans; /* # of channels */
+ int sc_precision; /* size of samples */
+ int sc_channels; /* # of channels */
int sc_dmadir; /* DMA direction */
#define SB_DMA_NONE 0
#define SB_DMA_IN 1
#define SB_DMA_OUT 2
u_int sc_model; /* DSP model */
-#define SBVER_MAJOR(v) ((v)>>8)
+#define SBVER_MAJOR(v) (((v)>>8) & 0xff)
#define SBVER_MINOR(v) ((v)&0xff)
-};
-#define ISSBPRO(sc) \
- (SBVER_MAJOR((sc)->sc_model) == 3)
+#define MODEL_JAZZ16 0x80000000
+};
#define ISSBPROCLASS(sc) \
(SBVER_MAJOR((sc)->sc_model) > 2)
+#define ISSBPRO(sc) \
+ (SBVER_MAJOR((sc)->sc_model) == 3)
+
#define ISSB16CLASS(sc) \
- (SBVER_MAJOR((sc)->sc_model) > 3)
+ (SBVER_MAJOR((sc)->sc_model) > 3)
+
+#define ISJAZZ16(sc) \
+ ((sc)->sc_model & MODEL_JAZZ16)
#ifdef _KERNEL
int sbdsp_get_precision __P((void *));
int sbdsp_set_channels __P((void *, int));
int sbdsp_get_channels __P((void *));
+int sbdsp_set_ifilter __P((void *, int));
+int sbdsp_get_ifilter __P((void *));
int sbdsp_round_blocksize __P((void *, int));
int sbdsp_set_out_port __P((void *, int));
int sbdsp_get_out_port __P((void *));
-/* $NetBSD: sbreg.h,v 1.12 1995/05/08 22:02:29 brezak Exp $ */
+/* $OpenBSD: sbreg.h,v 1.2 1996/04/18 23:47:49 niklas Exp $ */
+/* $NetBSD: sbreg.h,v 1.16 1996/03/16 04:00:14 jtk Exp $ */
/*
* Copyright (c) 1991-1993 Regents of the University of California.
#define SBP_RECORD_FROM(src, filteron, high) ((src) | (filteron) | (high))
#define SBP_FILTER_ON 0x0
#define SBP_FILTER_OFF 0x20
-#define SBP_FILTER_MASK 0x20
-#define SBP_FILTER_LOW 0
-#define SBP_FILTER_HIGH 0x08
+#define SBP_IFILTER_MASK 0x28
+#define SBP_OFILTER_MASK 0x20
+#define SBP_IFILTER_LOW 0
+#define SBP_IFILTER_HIGH 0x08
#define SBP_FROM_MIC 0x00
#define SBP_FROM_CD 0x02
#define SBP_FROM_LINE 0x06
+#define sbdsp_mono_vol(left) (((left) << 4) | (left))
#define sbdsp_stereo_vol(left, right) (((left) << 4) | (right))
#define SBP_MAXVOL 0xf /* per channel */
#define SBP_MINVOL 0x0 /* per channel */
#define SB_MIDI_UART_INTR 0x35 /* enter UART mode w/ read intrs */
#define SB_MIDI_WRITE 0x38 /* write a MIDI byte (non-UART mode) */
#define SB_DSP_TIMECONST 0x40 /* set ADAC time constant */
+#define SB_DSP16_OUTPUTRATE 0x41 /* set ADAC output rate */
+#define SB_DSP16_INPUTRATE 0x42 /* set ADAC input rate */
#define SB_DSP_BLOCKSIZE 0x48 /* set blk size for high speed xfer */
#define SB_DSP_WDMA_4 0x74 /* begin 4-bit ADPCM DMA output */
#define SB_DSP_WDMA_2_6 0x76 /* begin 2.6-bit ADPCM DMA output */
#define SB_DSP_HS_INPUT 0x99 /* set high speed mode for rdma */
#define SB_DSP_RECORD_MONO 0xA0 /* set mono recording */
#define SB_DSP_RECORD_STEREO 0xA8 /* set stereo recording */
+#define SB_DSP16_WDMA_16 0xB6 /* begin 16-bit linear output */
+#define SB_DSP16_RDMA_16 0xBE /* begin 16-bit linear input */
+#define SB_DSP16_WDMA_8 0xC6 /* begin 8-bit linear output */
+#define SB_DSP16_RDMA_8 0xCE /* begin 8-bit linear input */
#define SB_DSP_HALT 0xd0 /* temporarilty suspend DMA */
#define SB_DSP_SPKR_ON 0xd1 /* turn speaker on */
#define SB_DSP_SPKR_OFF 0xd3 /* turn speaker off */
#define SB_SPKR_ON 0xff
#define SB_DSP_VERSION 0xe1 /* get version number */
+/* Some of these come from linux driver (It serves as convenient unencumbered
+ documentation) */
+#define JAZZ16_READ_VER 0xFA /* 0x12 means ProSonic/Jazz16? */
+#define JAZZ16_VER_JAZZ 0x12
+#define JAZZ16_SET_DMAINTR 0xFB
+
+#define JAZZ16_CONFIG_PORT 0x201
+#define JAZZ16_WAKEUP 0xAF
+#define JAZZ16_SETBASE 0x50
+
+#define JAZZ16_RECORD_STEREO 0xAC /* 16-bit record */
+#define JAZZ16_RECORD_MONO 0xA4 /* 16-bit record */
+
+/*
+ * These come from Jazz16 chipset documentation, which doesn't include
+ * full register details, alas. Their source code CD-ROM probably includes
+ * details, but it has an NDA attached.
+ */
+#define JAZZ16_DIR_PB 0x10
+#define JAZZ16_SINGLE_PB 0x14
+#define JAZZ16_SINGLE_ALAW_PB 0x17
+#define JAZZ16_CONT_PB 0x1C
+#define JAZZ16_CONT_ALAW_PB 0x1F
+#define JAZZ16_DIR_PCM_REC 0x20
+#define JAZZ16_SINGLE_REC 0x24
+#define JAZZ16_SINGLE_ALAW_REC 0x27
+#define JAZZ16_CONT_REC 0x2C
+#define JAZZ16_CONT_ALAW_REC 0x2F
+#define JAZZ16_SINGLE_ADPCM_PB 0x74
+#define JAZZ16_SINGLE_MULAW_PB 0x77
+#define JAZZ16_CONT_ADPCM_PB 0x7C
+#define JAZZ16_SINGLE_ADPCM_REC 0x84
+#define JAZZ16_SINGLE_MULAW_REC 0x87
+#define JAZZ16_CONT_ADPCM_REC 0x8C
+#define JAZZ16_CONT_MULAW_REC 0x8F
+#define JAZZ16_CONT_PB_XX 0x90
+#define JAZZ16_SINGLE_PB_XX 0x91
+#define JAZZ16_SINGLE_REC_XX 0x98
+#define JAZZ16_CONT_REC_XX 0x99
+
+
/*
* The ADPCM encodings are differential, meaning each sample represents
* a difference to add to a running sum. The inital value is called the
-/* $OpenBSD: ultra14f.c,v 1.11 1996/03/20 01:01:04 mickey Exp $ */
-/* $NetBSD: ultra14f.c,v 1.61 1996/02/09 17:38:09 mycroft Exp $ */
+/* $OpenBSD: ultra14f.c,v 1.12 1996/04/18 23:47:50 niklas Exp $ */
+/* $NetBSD: ultra14f.c,v 1.62 1996/02/24 05:27:49 mycroft Exp $ */
/*
* Copyright (c) 1994 Charles Hannum. All rights reserved.
isa_establish(&uha->sc_id, &uha->sc_dev);
#endif
uha->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_BIO,
- uha->intr, uha, sc->sc_dev.dv_xname);
+ uha->intr, uha, uha->sc_dev.dv_xname);
/*
* ask the adapter what subunits are present
if (ia->ia_iobase == IOBASEUNK)
return ENXIO;
- model = inb(iobase + U14_ID) | (inb(iobase + U14_ID + 1) << 8);
+ model = (inb(iobase + U14_ID) << 8) | inb(iobase + U14_ID + 1);
if ((model & 0xfff0) != 0x5640)
return ENXIO;
- config = inb(iobase + U14_CONFIG) | (inb(iobase + U14_CONFIG + 1) << 8);
+ config = (inb(iobase + U14_CONFIG) << 8) | inb(iobase + U14_CONFIG + 1);
switch (model & 0x000f) {
case 0x0001:
-/* $NetBSD: wd.c,v 1.145 1996/01/08 21:21:56 mycroft Exp $ */
+/* $OpenBSD: wd.c,v 1.9 1996/04/18 23:47:51 niklas Exp $ */
+/* $NetBSD: wd.c,v 1.146 1996/03/01 04:08:51 mycroft Exp $ */
/*
* Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved.
WDCC_READDMA : WDCC_WRITEDMA;
/* Start the DMA channel and bounce the buffer if
necessary. */
- isa_dmastart(bp->b_flags & B_READ,
+ isa_dmastart(
+ bp->b_flags & B_READ ? DMAMODE_READ : DMAMODE_WRITE,
bp->b_data + wd->sc_skip,
wd->sc_nbytes, wdc->sc_drq);
break;
/* Turn off the DMA channel and unbounce the buffer. */
if (wd->sc_mode == WDM_DMA)
- isa_dmadone(bp->b_flags & B_READ, bp->b_data + wd->sc_skip,
- wd->sc_nbytes, wdc->sc_drq);
+ isa_dmadone(bp->b_flags & B_READ ? DMAMODE_READ : DMAMODE_WRITE,
+ bp->b_data + wd->sc_skip, wd->sc_nbytes, wdc->sc_drq);
/* Have we an error? */
if (wdc->sc_status & WDCS_ERR) {
-/* $NetBSD: wt.c,v 1.28 1996/01/12 00:54:23 thorpej Exp $ */
+/* $OpenBSD: wt.c,v 1.7 1996/04/18 23:47:52 niklas Exp $ */
+/* $NetBSD: wt.c,v 1.29 1996/03/01 04:08:40 mycroft Exp $ */
/*
* Streamer tape driver.
void *dmavaddr; /* virtual address of dma i/o buffer */
size_t dmatotal; /* size of i/o buffer */
- int dmaflags; /* i/o direction, B_READ or B_WRITE */
+ int dmaflags; /* i/o direction */
size_t dmacount; /* resulting length of dma i/o */
u_short error; /* code for error encountered */
/*
* Clean up dma.
*/
- if ((sc->dmaflags & B_READ) &&
+ if ((sc->dmaflags & DMAMODE_READ) &&
(sc->dmatotal - sc->dmacount) < sc->bsize) {
/* If reading short block, copy the internal buffer
* to the user memory. */
*/
if ((x & sc->NOEXCEP) == 0) {
WTDBPRINT(("i/o exception\n"));
- wtsense(sc, 1, (sc->dmaflags & B_READ) ? TP_WRP : 0);
+ wtsense(sc, 1, (sc->dmaflags & DMAMODE_READ) ? TP_WRP : 0);
if (sc->error & (TP_EOM | TP_FIL))
sc->flags |= TPVOL; /* end of file */
else
outb(sc->SDMAPORT, 0);
}
- if ((sc->dmaflags & B_READ) &&
+ if ((sc->dmaflags & DMAMODE_READ) &&
(sc->dmatotal - sc->dmacount) < sc->bsize) {
/* Reading short block; do it through the internal buffer. */
isa_dmastart(sc->dmaflags, sc->buf, sc->bsize, sc->chan);
sc->dmavaddr = vaddr;
sc->dmatotal = len;
sc->dmacount = 0;
- sc->dmaflags = flag;
+ sc->dmaflags = flag & B_READ ? DMAMODE_READ : DMAMODE_WRITE;
wtdma(sc);
return 1;
}
-/*
- * Copyright (c) 1995 John T. Kohl
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+/* $OpenBSD: mulaw.h,v 1.2 1996/04/18 23:47:03 niklas Exp $ */
+/* $NetBSD: mulaw.h,v 1.2 1996/02/27 22:29:42 jtc Exp $ */
+
+/*-
+ * Copyright (c) 1996 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by John T. Kohl.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
- *
*/
/*
+/* $OpenBSD: aic7870.c,v 1.5 1996/04/18 23:47:54 niklas Exp $ */
+/* $NetBSD: aic7870.c,v 1.8 1996/03/17 00:55:23 thorpej Exp $ */
+
/*
* Product specific probe and attach routines for:
* 294X and aic7870 motherboard SCSI controllers
* Justin T. Gibbs.
* 4. Modifications may be freely made to this file if the above conditions
* are met.
- *
- * $Id: aic7870.c,v 1.4 1996/02/20 04:36:13 tholo Exp $
*/
#include <sys/param.h>
#include <dev/ic/aic7xxxvar.h>
-#define PCI_BASEADR0 PCI_MAP_REG_START
+#define PCI_BASEADR0 PCI_MAPREG_START
#define PCI_VENDORID(x) ((x) & 0xFFFF)
#define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
static int aic7870_probe __P((struct device *, void *, void *));
static void aic7870_attach __P((struct device *, struct device *, void *));
-struct cfdriver ahccd = {
- NULL, "ahc", aic7870_probe, aic7870_attach, DV_DULL,
- sizeof(struct ahc_softc)
+struct cfattach ahc_ca = {
+ sizeof(struct ahc_softc), aic7870_probe, aic7870_attach
+};
+
+struct cfdriver ahc_cd = {
+ NULL, "ahc", DV_DULL
};
int ahcintr __P((void *));
switch (PCI_CHIPID(pa->pa_id)) {
case PCI_PRODUCT_ADP_AIC7870:
- case PCI_PRODUCT_ADP_AIC2940:
- case PCI_PRODUCT_ADP_AIC2940U:
+ case PCI_PRODUCT_ADP_2940:
+ case PCI_PRODUCT_ADP_2940U:
return 1;
default:
return 0;
ahc->type = AHC_AIC7870;
break;
- case PCI_PRODUCT_ADP_AIC2940:
- case PCI_PRODUCT_ADP_AIC2940U:
+ case PCI_PRODUCT_ADP_2940:
+ case PCI_PRODUCT_ADP_2940U:
ahc->type = AHC_294;
break;
}
ahcattach(ahc);
- ahc->sc_ih = pci_map_int(pa->pa_tag, IPL_BIO, ahcintr, ahc,
- ahc->sc_dev.dv_xname);
+ ahc->sc_ih = pci_map_int(pa->pa_tag, IPL_BIO, ahcintr, ahc
+ ahc->sc_dev.dv_xname);
}
-# $NetBSD: files.pci,v 1.9 1996/01/13 02:05:18 thorpej Exp $
+# $OpenBSD: files.pci,v 1.3 1996/04/18 23:47:55 niklas Exp $
+# $NetBSD: files.pci,v 1.12 1996/03/04 03:29:19 cgd Exp $
#
-# Config.new file and device description for machine-independent PCI code.
+# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
# defined first.
-# ports should define their own "device pci" line (like the one below,
-# but with the correct bus attachment).
+device pci at pcibus {[dev = -1], [function = -1]}
+file dev/pci/pci.c pci needs-flag
+file dev/pci/pci_subr.c pci
-#device pci at mainbus {[bus = -1], [dev = -1]}
-file dev/pci/pci_subr.c pci needs-flag
+# Adaptec 7870 chips
+device ahc at pci: scsi, aic7xxx
+file dev/pci/aic7870.c ahc
# Ethernet driver for DC21040-based boards
device de at pci: ether, ifnet
device ncr at pci: scsi
file dev/pci/ncr.c ncr
-# Adaptec 7870 chips
-device ahc at pci: scsi, aic7xxx
-file dev/pci/aic7870.c ahc
+# PCI-PCI bridge chips
+device ppb at pci: pcibus
+file dev/pci/ppb.c ppb
-/* $NetBSD: if_de.c,v 1.11 1995/12/24 02:32:13 mycroft Exp $ */
+/* $OpenBSD: if_de.c,v 1.5 1996/04/18 23:47:56 niklas Exp $ */
+/* $NetBSD: if_de.c,v 1.13 1996/03/14 03:04:17 cgd Exp $ */
/*-
* Copyright (c) 1994, 1995 Matt Thomas (matt@lkg.dec.com)
#endif /* __bsdi__ */
#if defined(__NetBSD__)
+#include <machine/bus.h>
+#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/ic/dc21040reg.h>
-#if defined(__i386__)
-#include <machine/pio.h>
+#ifdef __i386__ /* XXX -- fix later -- cgd */
#include <i386/isa/isa_machdep.h>
#endif
#endif /* __NetBSD__ */
#ifdef TULIP_IOMAPPED
#ifndef __NetBSD__
-typedef tulip_uint16_t tulip_csrptr_t;
#else
-typedef int tulip_csrptr_t;
#endif
#define TULIP_EISA_CSRSIZE 16
-#define TULIP_EISA_CSROFFSET 0
#define TULIP_PCI_CSRSIZE 8
-#define TULIP_PCI_CSROFFSET 0
+
+#ifndef __NetBSD__
+typedef tulip_uint16_t tulip_csrptr_t;
#define TULIP_READ_CSR(sc, csr) (inl((sc)->tulip_csrs.csr))
#define TULIP_WRITE_CSR(sc, csr, val) outl((sc)->tulip_csrs.csr, val)
#define TULIP_READ_CSRBYTE(sc, csr) (inb((sc)->tulip_csrs.csr))
#define TULIP_WRITE_CSRBYTE(sc, csr, val) outb((sc)->tulip_csrs.csr, val)
+#else
+typedef bus_io_size_t tulip_csrptr_t;
+
+#define TULIP_READ_CSR(sc, csr) \
+ bus_io_read_4((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr)
+#define TULIP_WRITE_CSR(sc, csr, val) \
+ bus_io_write_4((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr, (val))
+
+#define TULIP_READ_CSRBYTE(sc, csr) \
+ bus_io_read_1((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr)
+#define TULIP_WRITE_CSRBYTE(sc, csr, val) \
+ bus_io_write_1((sc)->tulip_bc, (sc)->tulip_ioh, (sc)->tulip_csrs.csr, (val))
+#endif
#else /* TULIP_IOMAPPED */
-typedef volatile tulip_uint32_t *tulip_csrptr_t;
+#define TULIP_PCI_CSRSIZE 8
-#if defined(__alpha__)
-#define TULIP_PCI_CSRSIZE (256 / sizeof(tulip_uint32_t))
-#define TULIP_PCI_CSROFFSET (24 / sizeof(tulip_uint32_t))
-#elif defined(__i386__)
-#define TULIP_PCI_CSRSIZE (8 / sizeof(tulip_uint32_t))
-#define TULIP_PCI_CSROFFSET 0
-#endif
+#ifndef __NetBSD__
+typedef volatile tulip_uint32_t *tulip_csrptr_t;
/*
* macros to read and write CSRs. Note that the "0 +" in
* and WRITE_CSR shouldn't be assigned from.
*/
#define TULIP_READ_CSR(sc, csr) (0 + *(sc)->tulip_csrs.csr)
-#ifndef __alpha__
#define TULIP_WRITE_CSR(sc, csr, val) \
((void)(*(sc)->tulip_csrs.csr = (val)))
#else
+typedef bus_mem_size_t tulip_csrptr_t;
+
+#define TULIP_READ_CSR(sc, csr) \
+ bus_mem_read_4((sc)->tulip_bc, (sc)->tulip_memh, (sc)->tulip_csrs.csr)
#define TULIP_WRITE_CSR(sc, csr, val) \
- ((void)(*(sc)->tulip_csrs.csr = (val), MB()))
+ bus_mem_write_4((sc)->tulip_bc, (sc)->tulip_memh, (sc)->tulip_csrs.csr, \
+ (val))
#endif
-
#endif /* TULIP_IOMAPPED */
typedef struct {
struct device tulip_dev; /* base device */
void *tulip_ih; /* intrrupt vectoring */
void *tulip_ats; /* shutdown hook */
+ bus_chipset_tag_t tulip_bc; /* bus chipset tag */
+#ifdef TULIP_IOMAPPED
+ bus_io_handle_t tulip_ioh; /* I/O region handle */
+#else
+ bus_io_handle_t tulip_memh; /* memory region handle */
+#endif
#endif
struct arpcom tulip_ac;
tulip_regfile_t tulip_csrs;
#if !defined(TULIP_IOMAPPED) && !defined(__bsdi__)
vm_offset_t pa_csrs;
#endif
- unsigned csroffset = TULIP_PCI_CSROFFSET;
unsigned csrsize = TULIP_PCI_CSRSIZE;
tulip_csrptr_t csr_base;
tulip_desc_t *rxdescs, *txdescs;
#if defined(TULIP_EISA)
} else {
revinfo = inl(ia->ia_iobase + DE425_CFRV) & 0xFF;
- csroffset = TULIP_EISA_CSROFFSET;
csrsize = TULIP_EISA_CSRSIZE;
chipid = TULIP_DE425;
#endif
#endif /* __bsdi__ */
#if defined(__NetBSD__)
+ sc->tulip_bc = pa->pa_bc;
#if defined(TULIP_IOMAPPED)
- retval = pci_map_io(pa->pa_tag, PCI_CBIO, &csr_base);
+ retval = pci_map_io(pa->pa_tag, PCI_CBIO, &sc->tulip_ioh);
#else
- retval = pci_map_mem(pa->pa_tag, PCI_CBMA, (vm_offset_t *) &csr_base, &pa_csrs);
+ retval = pci_map_mem(pa->pa_tag, PCI_CBMA, &sc->tulip_memh, &pa_csrs);
#endif
+ csr_base = 0;
if (retval) {
free((caddr_t) txdescs, M_DEVBUF);
free((caddr_t) rxdescs, M_DEVBUF);
}
#endif /* __NetBSD__ */
- tulip_initcsrs(sc, csr_base + csroffset, csrsize);
+ tulip_initcsrs(sc, csr_base, csrsize);
tulip_initring(sc, &sc->tulip_rxinfo, rxdescs, TULIP_RXDESCS);
tulip_initring(sc, &sc->tulip_txinfo, txdescs, TULIP_TXDESCS);
if ((retval = tulip_read_macaddr(sc)) < 0) {
-/* $NetBSD: if_fpa.c,v 1.2 1995/08/19 04:35:25 cgd Exp $ */
+/* $OpenBSD: if_fpa.c,v 1.4 1996/04/18 23:47:58 niklas Exp $ */
+/* $NetBSD: if_fpa.c,v 1.7 1996/03/17 00:55:30 thorpej Exp $ */
/*-
* Copyright (c) 1995 Matt Thomas (thomas@lkg.dec.com)
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Id: if_fpa.c,v 1.2 1995/08/20 18:56:11 thomas Exp
+ *
+ * Log: if_fpa.c,v
+ * Revision 1.2 1995/08/20 18:56:11 thomas
+ * Misc. changes for NetBSD
+ *
+ * Revision 1.1 1995/08/16 22:57:28 thomas
+ * Initial revision
+ *
+ * Revision 1.13 1995/08/04 21:54:56 thomas
+ * Clean IRQ processing under BSD/OS.
+ * A receive tweaks. (print source of MAC CRC errors, etc.)
+ *
+ * Revision 1.12 1995/06/02 16:04:22 thomas
+ * Use correct PCI defs for BSDI now that they have fixed them.
+ * Increment the slot number 0x1000, not one! (*duh*)
+ *
+ * Revision 1.11 1995/04/21 13:23:55 thomas
+ * Fix a few pub in the DEFPA BSDI support
+ *
+ * Revision 1.10 1995/04/20 21:46:42 thomas
+ * Why???
+ * ,
+ *
+ * Revision 1.9 1995/04/20 20:17:33 thomas
+ * Add PCI support for BSD/OS.
+ * Fix BSD/OS EISA support.
+ * Set latency timer for DEFPA to recommended value if 0.
+ *
+ * Revision 1.8 1995/04/04 22:54:29 thomas
+ * Fix DEFEA support
+ *
+ * Revision 1.7 1995/03/14 01:52:52 thomas
+ * Update for new FreeBSD PCI Interrupt interface
+ *
+ * Revision 1.6 1995/03/10 17:06:59 thomas
+ * Update for latest version of FreeBSD.
+ * Compensate for the fast that the ifp will not be first thing
+ * in softc on BSDI.
+ *
+ * Revision 1.5 1995/03/07 19:59:42 thomas
+ * First pass at BSDI EISA support
+ *
+ * Revision 1.4 1995/03/06 17:06:03 thomas
+ * Add transmit timeout support.
+ * Add support DEFEA (untested).
+ *
+ * Revision 1.3 1995/03/03 13:48:35 thomas
+ * more fixes
+ *
+ *
*/
/*
#include <sys/malloc.h>
#if defined(__FreeBSD__)
#include <sys/devconf.h>
-#elif defined(__bsdi__) || defined(__NetBSD__)
+#elif defined(__bsdi__) || defined(__NetBSD__) || defined(__OpenBSD__)
#include <sys/device.h>
#endif
#include <i386/pci/pci.h>
#include <i386/pci/pdqreg.h>
#include <i386/pci/pdq_os.h>
-#elif defined(__NetBSD__)
+#elif defined(__NetBSD__) || defined (__OpenBSD__)
+#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/ic/pdqreg.h>
#include <dev/ic/pdqvar.h>
-#endif /* __NetBSD__ */
+#endif /* __NetBSD__ || __OpenBSD */
#define DEC_VENDORID 0x1011
#define PDQ_PCI_UNIT_TO_SOFTC(unit) (pdqs_pci[unit])
#endif /* __FreeBSD__ */
-#if defined(__bsdi__) || defined(__NetBSD__)
+#if defined(__bsdi__)
extern struct cfdriver fpacd;
#define PDQ_PCI_UNIT_TO_SOFTC(unit) ((pdq_softc_t *)fpacd.cd_devs[unit])
#endif
+#if defined(__NetBSD__) || defined (__OpenBSD__)
+extern struct cfattach fpa_ca;
+extern struct cfdriver fpa_cd;
+#define PDQ_PCI_UNIT_TO_SOFTC(unit) ((pdq_softc_t *)fpa_cd.cd_devs[unit])
+#endif
+
static ifnet_ret_t
pdq_pci_ifinit(
int unit)
pdq_softc_t * const sc = (pdq_softc_t *) arg;
#ifdef __FreeBSD__
return pdq_interrupt(sc->sc_pdq);
-#elif defined(__bsdi__) || defined(__NetBSD__)
+#elif defined(__bsdi__) || defined(__NetBSD__) || defined(__OpenBSD__)
(void) pdq_interrupt(sc->sc_pdq);
return 1;
#endif
0, "fpa", pdq_pci_probe, pdq_pci_attach, DV_IFNET, sizeof(pdq_softc_t)
};
-#elif defined(__NetBSD__)
+#elif defined(__NetBSD__) || defined (__OpenBSD__)
static int
pdq_pci_probe(
sc->sc_if.if_unit, (void *) sc, PDQ_DEFPA);
if (sc->sc_pdq == NULL)
return;
- bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr, 6);
+ bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr,
+ 6);
pdq_ifattach(sc, pdq_pci_ifinit, pdq_pci_ifwatchdog);
- sc->sc_ih = pci_map_int(pa->pa_tag, IPL_NET, pdq_pci_ifintr, sc,
- sc->sc_dev.dv_xname);
+ sc->sc_ih = pci_map_int(pa->pa_tag, IPL_NET, pdq_pci_ifintr, sc
+ sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf("fpa%d: error: couldn't map interrupt\n", sc->sc_if.if_unit);
return;
#endif
}
-struct cfdriver fpacd = {
- 0, "fpa", pdq_pci_probe, pdq_pci_attach, DV_IFNET, sizeof(pdq_softc_t)
+struct cfattach fpa_ca = {
+ sizeof(pdq_softc_t), pdq_pci_probe, pdq_pci_attach
+};
+
+struct cfdriver fpa_cd = {
+ 0, "fpa", DV_IFNET
};
-#endif /* __NetBSD__ */
+#endif /* __NetBSD__ || __OpenBSD__ */
+/* $OpenBSD: ncr.c,v 1.6 1996/04/18 23:47:59 niklas Exp $ */
+/* $NetBSD: ncr.c,v 1.29 1996/03/14 05:21:20 cgd Exp $ */
+
/**************************************************************************
**
-** $Id: ncr.c,v 1.5 1996/02/20 04:36:17 tholo Exp $
-**
** Device driver for the NCR 53C810 PCI-SCSI-Controller.
**
** FreeBSD / NetBSD
extern PRINT_ADDR();
#else
#include <sys/device.h>
+#include <machine/bus.h>
#include <dev/pci/ncr_reg.h>
-#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
#define DELAY(x) delay(x)
-#endif /* __NetBSD */
+#endif /* __NetBSD__ */
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
#ifndef __NetBSD__
#include <machine/clock.h>
-#endif /* __NetBSD */
+#endif /* __NetBSD__ */
/*==========================================================
**==========================================================
*/
+#ifdef __NetBSD__
+
#ifdef NCR_IOMAPPED
+#define INB(r) \
+ INB_OFF(offsetof(struct ncr_reg, r))
+#define INB_OFF(o) \
+ bus_io_read_1 (np->sc_bc, np->sc_ioh, (o))
+#define INW(r) \
+ bus_io_read_2 (np->sc_bc, np->sc_ioh, offsetof(struct ncr_reg, r))
+#define INL(r) \
+ INL_OFF(offsetof(struct ncr_reg, r))
+#define INL_OFF(o) \
+ bus_io_read_4 (np->sc_bc, np->sc_ioh, (o))
+
+#define OUTB(r, val) \
+ bus_io_write_1 (np->sc_bc, np->sc_ioh, offsetof(struct ncr_reg, r), (val))
+#define OUTW(r, val) \
+ bus_io_write_2 (np->sc_bc, np->sc_ioh, offsetof(struct ncr_reg, r), (val))
+#define OUTL(r, val) \
+ OUTL_OFF(offsetof(struct ncr_reg, r), (val))
+#define OUTL_OFF(o, val) \
+ bus_io_write_4 (np->sc_bc, np->sc_ioh, (o), (val))
+
+#else
+
+#define INB(r) \
+ INB_OFF(offsetof(struct ncr_reg, r))
+#define INB_OFF(o) \
+ bus_mem_read_1 (np->sc_bc, np->sc_memh, (o))
+#define INW(r) \
+ bus_mem_read_2 (np->sc_bc, np->sc_memh, offsetof(struct ncr_reg, r))
+#define INL(r) \
+ INL_OFF(offsetof(struct ncr_reg, r))
+#define INL_OFF(o) \
+ bus_mem_read_4 (np->sc_bc, np->sc_memh, (o))
+
+#define OUTB(r, val) \
+ bus_mem_write_1 (np->sc_bc, np->sc_memh, offsetof(struct ncr_reg, r), (val))
+#define OUTW(r, val) \
+ bus_mem_write_2 (np->sc_bc, np->sc_memh, offsetof(struct ncr_reg, r), (val))
+#define OUTL(r, val) \
+ OUTL_OFF(offsetof(struct ncr_reg, r), (val))
+#define OUTL_OFF(o, val) \
+ bus_mem_write_4 (np->sc_bc, np->sc_memh, (o), (val))
+
+#endif
+
+#else /* !__NetBSD__ */
+
+#ifdef NCR_IOMAPPED
+
#define INB(r) inb (np->port + offsetof(struct ncr_reg, r))
+#define INB_OFF(o) inb (np->port + (o))
#define INW(r) inw (np->port + offsetof(struct ncr_reg, r))
#define INL(r) inl (np->port + offsetof(struct ncr_reg, r))
+#define INL_OFF(o) inl (np->port + (o))
#define OUTB(r, val) outb (np->port+offsetof(struct ncr_reg,r),(val))
#define OUTW(r, val) outw (np->port+offsetof(struct ncr_reg,r),(val))
#define OUTL(r, val) outl (np->port+offsetof(struct ncr_reg,r),(val))
+#define OUTL_OFF(o, val) outl (np->port+(o),(val))
#else
-#define INB(r) (np->reg->r)
-#define INW(r) (np->reg->r)
-#define INL(r) (np->reg->r)
+#define INB(r) (np->reg->r)
+#define INB_OFF(o) (*((volatile INT8 *)((char *)np->reg + (o))))
+#define INW(r) (np->reg->r)
+#define INL(r) (np->reg->r)
+#define INL_OFF(o) (*((volatile INT32 *)((char *)np->reg + (o))))
-#define OUTB(r, val) np->reg->r = val
-#define OUTW(r, val) np->reg->r = val
-#define OUTL(r, val) np->reg->r = val
+#define OUTB(r, val) np->reg->r = val
+#define OUTW(r, val) np->reg->r = val
+#define OUTL(r, val) np->reg->r = val
+#define OUTL_OFF(o, val) *((volatile INT32 *)((char *)np->reg + (o))) = val
#endif
+#endif /* __NetBSD__ */
+
/*==========================================================
**
** Command control block states.
**
** OS dependencies.
**
+** Note that various types are defined in ncr_reg.h.
+**
**==========================================================
*/
-#ifdef __NetBSD__
- #define INT32 int
- #define U_INT32 u_int
- #define TIMEOUT (void*)
-#else /*__NetBSD__*/
- #define INT32 int32
- #define U_INT32 u_int32
- #define TIMEOUT (timeout_func_t)
-#endif /*__NetBSD__*/
#define PRINT_ADDR(xp) sc_print_addr(xp->sc_link)
/*==========================================================
typedef struct ccb * ccb_p;
struct link {
- u_long l_cmd;
- u_long l_paddr;
+ ncrcmd l_cmd;
+ ncrcmd l_paddr;
};
struct usrcmd {
** the rest of the data.
*/
- u_long patch[8];
+ ncrcmd patch[8];
/*
** The general SCSI driver provides a
#ifdef __NetBSD__
struct device sc_dev;
void *sc_ih;
+ bus_chipset_tag_t sc_bc;
+#ifdef NCR_IOMAPPED
+ bus_io_handle_t sc_ioh;
+#else /* !NCR_IOMAPPED */
+ bus_mem_handle_t sc_memh;
+#endif /* NCR_IOMAPPED */
#else /* !__NetBSD__ */
int unit;
#endif /* __NetBSD__ */
** virtual and physical addresses
** of the 53c810 chip.
*/
+#ifndef __NetBSD__
vm_offset_t vaddr;
vm_offset_t paddr;
+#else
+ bus_mem_addr_t paddr;
+#endif
+#ifndef __NetBSD__
/*
** pointer to the chip's registers.
*/
volatile
struct ncr_reg* reg;
+#endif
/*
** A copy of the script, relocated for this ncb.
*/
u_char disc;
-#ifdef NCR_IOMAPPED
+#if defined(NCR_IOMAPPED) && !defined(__NetBSD__)
/*
** address of the ncr control registers in io space
*/
static char ident[] =
- "\n$Id: ncr.c,v 1.5 1996/02/20 04:36:17 tholo Exp $\n";
+ "\n$NetBSD: ncr.c,v 1.29 1996/03/14 05:21:20 cgd Exp $\n";
u_long ncr_version = NCR_VERSION * 11
+ (u_long) sizeof (struct ncb) * 7
#define RELOC_SOFTC 0x40000000
#define RELOC_LABEL 0x50000000
#define RELOC_REGISTER 0x60000000
+#define RELOC_KVAR 0x70000000
#define RELOC_MASK 0xf0000000
#define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label))
#define PADDR(label) (RELOC_LABEL | offsetof(struct script, label))
#define RADDR(label) (RELOC_REGISTER | REG(label))
#define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
+#define KVAR(which) (RELOC_KVAR | (which))
+
+#define SCRIPT_KVAR_MONO_TIME_TV_SEC (0)
+#define SCRIPT_KVAR_MONO_TIME (SCRIPT_KVAR_MONO_TIME_TV_SEC + 1)
+#define SCRIPT_KVAR_NCR_CACHE (SCRIPT_KVAR_MONO_TIME + 1)
+
+#define SCRIPT_KVAR_FIRST SCRIPT_KVAR_MONO_TIME_TV_SEC
+#define SCRIPT_KVAR_LAST SCRIPT_KVAR_NCR_CACHE
+
+/*
+ * Kernel variables referenced in the scripts.
+ * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY.
+ */
+static void *script_kvars[] =
+ { (void *)&mono_time.tv_sec, (void *)&mono_time, (void *)&ncr_cache };
static struct script script0 = {
/*--------------------------< START >-----------------------*/ {
** Claim to be still alive ...
*/
SCR_COPY (sizeof (((struct ncb *)0)->heartbeat)),
- (ncrcmd) &time.tv_sec,
+ KVAR(SCRIPT_KVAR_MONO_TIME_TV_SEC),
NADDR (heartbeat),
/*
** Make data structure address invalid.
** Set a time stamp for this selection
*/
SCR_COPY (sizeof (struct timeval)),
- (ncrcmd) &time,
+ KVAR(SCRIPT_KVAR_MONO_TIME),
NADDR (header.stamp.select),
/*
** load the savep (saved pointer) into
** ... set a timestamp ...
*/
SCR_COPY (sizeof (struct timeval)),
- (ncrcmd) &time,
+ KVAR(SCRIPT_KVAR_MONO_TIME),
NADDR (header.stamp.command),
/*
** ... and send the command
** set the timestamp.
*/
SCR_COPY (sizeof (struct timeval)),
- (ncrcmd) &time,
+ KVAR(SCRIPT_KVAR_MONO_TIME),
NADDR (header.stamp.status),
/*
** If this is a GETCC transfer,
** and count the disconnects.
*/
SCR_COPY (sizeof (struct timeval)),
- (ncrcmd) &time,
+ KVAR(SCRIPT_KVAR_MONO_TIME),
NADDR (header.stamp.disconnect),
SCR_COPY (4),
NADDR (disc_phys),
** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
** PADDR (no_data),
** SCR_COPY (sizeof (struct timeval)),
-** (ncrcmd) &time,
+** KVAR(SCRIPT_KVAR_MONO_TIME),
** NADDR (header.stamp.data),
** SCR_MOVE_TBL ^ SCR_DATA_IN,
** offsetof (struct dsb, data[ 0]),
** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
** PADDR (no_data),
** SCR_COPY (sizeof (struct timeval)),
-** (ncrcmd) &time,
+** KVAR(SCRIPT_KVAR_MONO_TIME),
** NADDR (header.stamp.data),
** SCR_MOVE_TBL ^ SCR_DATA_OUT,
** offsetof (struct dsb, data[ 0]),
**
**---------------------------------------------------------
*/
-(u_long)&ident
-
+0
}/*-------------------------< ABORTTAG >-------------------*/,{
/*
** Abort a bad reselection.
** Read the variable.
*/
SCR_COPY (4),
- (ncrcmd) &ncr_cache,
+ KVAR(SCRIPT_KVAR_NCR_CACHE),
RADDR (scratcha),
/*
** Write the variable.
*/
SCR_COPY (4),
RADDR (temp),
- (ncrcmd) &ncr_cache,
+ KVAR(SCRIPT_KVAR_NCR_CACHE),
/*
** Read back the variable.
*/
SCR_COPY (4),
- (ncrcmd) &ncr_cache,
+ KVAR(SCRIPT_KVAR_NCR_CACHE),
RADDR (temp),
}/*-------------------------< SNOOPEND >-------------------*/,{
/*
*p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN));
*p++ =PADDR (no_data);
*p++ =SCR_COPY (sizeof (struct timeval));
- *p++ =(ncrcmd) &time;
+ *p++ =KVAR(SCRIPT_KVAR_MONO_TIME);
*p++ =NADDR (header.stamp.data);
*p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
*p++ =offsetof (struct dsb, data[ 0]);
*p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT));
*p++ =PADDR (no_data);
*p++ =SCR_COPY (sizeof (struct timeval));
- *p++ =(ncrcmd) &time;
+ *p++ =KVAR(SCRIPT_KVAR_MONO_TIME);
*p++ =NADDR (header.stamp.data);
*p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
*p++ =offsetof (struct dsb, data[ 0]);
static void ncr_script_copy_and_bind (struct script *script, ncb_p np)
{
- ncrcmd opcode, new, old;
+ ncrcmd opcode, new, old, tmp1, tmp2;
ncrcmd *src, *dst, *start, *end;
int relocs;
#ifndef __NetBSD__
- np->script = (struct script*) vm_page_alloc_contig
+ np->script = (struct script*) vm_page_alloc_contig
(round_page(sizeof (struct script)), 0x100000, 0xffffffff, PAGE_SIZE);
#else /* !__NetBSD___ */
np->script = (struct script *)
};
if (DEBUG_FLAGS & DEBUG_SCRIPT)
- printf ("%x: <%x>\n",
- (unsigned)(src-1), (unsigned)opcode);
+ printf ("%p: <%x>\n", (src-1), (unsigned)opcode);
/*
** We don't have to decode ALL commands
** COPY has TWO arguments.
*/
relocs = 2;
- if ((src[0] ^ src[1]) & 3) {
+ tmp1 = src[0];
+ if ((tmp1 & RELOC_MASK) == RELOC_KVAR)
+ tmp1 = 0;
+ tmp2 = src[1];
+ if ((tmp2 & RELOC_MASK) == RELOC_KVAR)
+ tmp2 = 0;
+ if ((tmp1 ^ tmp2) & 3) {
printf ("%s: ERROR1 IN SCRIPT at %d.\n",
ncr_name(np), src-start-1);
DELAY (1000000);
case RELOC_SOFTC:
new = (old & ~RELOC_MASK) + vtophys(np);
break;
+ case RELOC_KVAR:
+ if (((old & ~RELOC_MASK) <
+ SCRIPT_KVAR_FIRST) ||
+ ((old & ~RELOC_MASK) >
+ SCRIPT_KVAR_LAST))
+ panic("ncr KVAR out of range");
+ new = vtophys(script_kvars[old &
+ ~RELOC_MASK]);
+ break;
case 0:
/* Don't relocate a 0 address. */
if (old == 0) {
}
/* fall through */
default:
- new = vtophys(old);
+ panic("ncr_script_copy_and_bind: weird relocation %x\n", old);
break;
}
int retval;
ncb_p np = (void *)self;
- /*
- ** XXX NetBSD
- ** Perhaps try to figure what which model chip it is and print that
- ** out.
- */
- printf("\n");
+ printf(": NCR ");
+ switch (pa->pa_id) {
+ case NCR_810_ID:
+ printf("53c810");
+ break;
+ case NCR_810AP_ID:
+ printf("53c810ap");
+ break;
+ case NCR_815_ID:
+ printf("53c815");
+ break;
+ case NCR_825_ID:
+ printf("53c825 Wide");
+ break;
+ case NCR_860_ID:
+ printf("53c860");
+ break;
+ case NCR_875_ID:
+ printf("53c875 Wide");
+ break;
+ }
+ printf(" SCSI\n");
/*
** Try to map the controller chip to
** virtual and physical memory.
*/
- retval = pci_map_mem(pa->pa_tag, 0x14, &np->vaddr, &np->paddr);
+ retval = pci_map_mem(pa->pa_tag, 0x14, (vm_offset_t *)&np->sc_memh,
+ &np->paddr);
if (retval)
return;
np->sc_ih = pci_map_int(pa->pa_tag, IPL_BIO, ncr_intr, np,
- np->sc_dev.dv_xname);
+ np->sc_dev.dv_xname);
if (np->sc_ih == NULL)
return;
np->jump_tcb.l_cmd = SCR_JUMP;
np->jump_tcb.l_paddr = NCB_SCRIPT_PHYS (np, abort);
+#ifndef __NetBSD__
/*
** Make the controller's registers available.
** Now the INB INW INL OUTB OUTW OUTL macros
*/
np->reg = (struct ncr_reg*) np->vaddr;
+#endif
/*
** Get SCSI addr of host adapter (set by bios?).
*/
bzero (&cp->phys.header.stamp, sizeof (struct tstamp));
- cp->phys.header.stamp.start = time;
+ cp->phys.header.stamp.start = mono_time;
/*----------------------------------------------------
**
*/
cp->jump_ccb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (cp->tag)));
- cp->tlimit = time.tv_sec + xp->timeout / 1000 + 2;
+ cp->tlimit = mono_time.tv_sec + xp->timeout / 1000 + 2;
cp->magic = CCB_MAGIC;
/*
ncb_profile (np, cp);
if (DEBUG_FLAGS & DEBUG_TINY)
- printf ("CCB=%x STAT=%x/%x\n", (unsigned)cp & 0xfff,
+ printf ("CCB=%x STAT=%x/%x\n", (unsigned long)cp & 0xfff,
cp->host_status,cp->scsi_status);
xp = cp->xfer;
** Other protocol messes
*/
PRINT_ADDR(xp);
- printf ("COMMAND FAILED (%x %x) @%x.\n",
- cp->host_status, cp->scsi_status, (unsigned)cp);
+ printf ("COMMAND FAILED (%x %x) @%p.\n",
+ cp->host_status, cp->scsi_status, cp);
xp->error = XS_TIMEOUT;
}
static void ncr_timeout (ncb_p np)
{
- u_long thistime = time.tv_sec;
+ u_long thistime = mono_time.tv_sec;
u_long step = np->ticks;
u_long count = 0;
long signed t;
cp->jump_ccb.l_cmd = (SCR_JUMP);
if (cp->phys.header.launch.l_paddr ==
NCB_SCRIPT_PHYS (np, select)) {
- printf ("%s: timeout ccb=%x (skip)\n",
- ncr_name (np), (unsigned)cp);
+ printf ("%s: timeout ccb=%p (skip)\n",
+ ncr_name (np), cp);
cp->phys.header.launch.l_paddr
= NCB_SCRIPT_PHYS (np, skip);
};
void ncr_exception (ncb_p np)
{
- u_char istat, dstat;
- u_short sist;
- u_long dsp, dsa;
+ U_INT8 istat, dstat;
+ U_INT16 sist;
+ U_INT32 dsp, dsa;
int i, script_ofs;
/*
**========================================
*/
- if (time.tv_sec - np->regtime.tv_sec>10) {
+ if (mono_time.tv_sec - np->regtime.tv_sec>10) {
int i;
- np->regtime = time;
+ np->regtime = mono_time;
for (i=0; i<sizeof(np->regdump); i++)
- ((char*)&np->regdump)[i] = ((char*)np->reg)[i];
+ ((char*)&np->regdump)[i] = INB_OFF(i);
np->regdump.nc_dstat = dstat;
np->regdump.nc_sist = sist;
};
printf ("\treg:\t");
for (i=0; i<16;i++)
- printf (" %02x", ((u_char*)np->reg)[i]);
+ printf (" %02x", INB_OFF(i));
printf (".\n");
/*----------------------------------------
printf (" ");
break;
};
- val = ((unsigned char*) np->vaddr) [i];
+ val = INB_OFF(i);
printf (" %x%x", val/16, val%16);
if (i%16==15) printf (".\n");
};
static void ncr_int_ma (ncb_p np)
{
- u_long dbc;
- u_long rest;
- u_long dsa;
- u_long dsp;
- u_long nxtdsp;
- u_long *vdsp;
- u_long oadr, olen;
- u_long *tblp, *newcmd;
- u_char cmd, sbcl, delta, ss0, ss2;
+ U_INT32 dbc;
+ U_INT32 rest;
+ U_INT32 dsa;
+ U_INT32 dsp;
+ U_INT32 nxtdsp;
+ U_INT32 *vdsp;
+ U_INT32 oadr, olen;
+ U_INT32 *tblp;
+ ncrcmd *newcmd;
+ U_INT32 cmd, sbcl, delta, ss0, ss2;
ccb_p cp;
dsp = INL (nc_dsp);
vdsp = &cp->patch[4];
nxtdsp = vdsp[3];
} else {
- vdsp = (u_long*) ((char*)np->script - np->p_script + dsp -8);
+ vdsp = (U_INT32 *) ((char*)np->script - np->p_script + dsp -8);
nxtdsp = dsp;
};
(unsigned) rest, (unsigned) delta, ss0);
};
if (DEBUG_FLAGS & DEBUG_PHASE) {
- printf ("\nCP=%x CP2=%x DSP=%x NXT=%x VDSP=%x CMD=%x ",
- (unsigned)cp, (unsigned)np->header.cp,
- (unsigned)dsp,
- (unsigned)nxtdsp, (unsigned)vdsp, cmd);
+ printf ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
+ cp, np->header.cp, (unsigned)dsp,
+ (unsigned)nxtdsp, vdsp, cmd);
};
/*
oadr = vdsp[1];
if (cmd & 0x10) { /* Table indirect */
- tblp = (u_long*) ((char*) &cp->phys + oadr);
+ tblp = (U_INT32 *) ((char*) &cp->phys + oadr);
olen = tblp[0];
oadr = tblp[1];
} else {
- tblp = (u_long*) 0;
+ tblp = (U_INT32 *) 0;
olen = vdsp[0] & 0xffffff;
};
if (DEBUG_FLAGS & DEBUG_PHASE) {
- printf ("OCMD=%x\nTBLP=%x OLEN=%x OADR=%x\n",
+ printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
(unsigned) (vdsp[0] >> 24),
- (unsigned) tblp,
+ tblp,
(unsigned) olen,
(unsigned) oadr);
};
if (DEBUG_FLAGS & DEBUG_ALLOC) {
PRINT_ADDR(xp);
- printf ("new ccb @%x.\n", (unsigned) cp);
+ printf ("new ccb @%p.\n", cp);
}
/*
#ifndef NCR_IOMAPPED
static int ncr_regtest (struct ncb* np)
{
- register volatile u_long data, *addr;
+ register volatile u_long data;
/*
** ncr registers may NOT be cached.
** write 0xffffffff to a read only register area,
** and try to read it back.
*/
- addr = (u_long*) &np->reg->nc_dstat;
data = 0xffffffff;
- *addr= data;
- data = *addr;
+ OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data);
+ data = INL_OFF(offsetof(struct ncr_reg, nc_dstat));
#if 1
if (data == 0xffffffff) {
#else
int co, da, st, en, di, se, post,work,disc;
u_long diff;
- PROFILE.end = time;
+ PROFILE.end = mono_time;
st = ncr_delta (&PROFILE.start,&PROFILE.status);
if (st<0) return; /* status not reached */
/*=========================================================================*/
#endif /* KERNEL */
-
-
-/* $NetBSD: ncr_reg.h,v 1.5.2.1 1995/11/23 20:50:10 perry Exp $ */
+/* $OpenBSD: ncr_reg.h,v 1.3 1996/04/18 23:48:01 niklas Exp $ */
+/* $NetBSD: ncr_reg.h,v 1.8 1996/03/11 23:06:04 cgd Exp $ */
/**************************************************************************
**
-** $Id: ncr_reg.h,v 1.2 1995/12/01 01:51:24 deraadt Exp $
-**
** Device driver for the NCR 53C810 PCI-SCSI-Controller.
**
-** 386bsd / FreeBSD / NetBSD
+** 386bsd / FreeBSD / NetBSD / OpenBSD
**
**-------------------------------------------------------------------------
**
#ifndef __NCR_REG_H__
#define __NCR_REG_H__
+/*==========================================================
+**
+** OS dependencies.
+**
+**==========================================================
+*/
+
+#if defined(__NetBSD__) || defined (__OpenBSD__)
+ #define INT8 int8_t
+ #define U_INT8 u_int8_t
+ #define INT16 int16_t
+ #define U_INT16 u_int16_t
+ #define INT32 int32_t
+ #define U_INT32 u_int32_t
+ #define TIMEOUT (void*)
+#else /* __NetBSD__ || __OpenBSD__ */
+ #define INT8 char
+ #define U_INT8 u_char
+ #define INT16 short
+ #define U_INT16 u_short
+ #define INT32 int32
+ #define U_INT32 u_int32
+ #define TIMEOUT (timeout_func_t)
+#endif /* __NetBSD__ || __OpenBSD__ */
+
/*-----------------------------------------------------------------
**
** The ncr 53c810 register structure.
*/
struct ncr_reg {
-/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
+/*00*/ U_INT8 nc_scntl0; /* full arb., ena parity, par->ATN */
-/*01*/ u_char nc_scntl1; /* no reset */
+/*01*/ U_INT8 nc_scntl1; /* no reset */
#define ISCON 0x10 /* connected to scsi */
#define CRST 0x08 /* force reset */
-/*02*/ u_char nc_scntl2; /* no disconnect expected */
+/*02*/ U_INT8 nc_scntl2; /* no disconnect expected */
#define SDU 0x80 /* cmd: disconnect will raise error */
#define CHM 0x40 /* sta: chained mode */
#define WSS 0x08 /* sta: wide scsi send [W]*/
#define WSR 0x01 /* sta: wide scsi received [W]*/
-/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
+/*03*/ U_INT8 nc_scntl3; /* cnf system clock dependent */
#define EWS 0x08 /* cmd: enable wide scsi [W]*/
-/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
+/*04*/ U_INT8 nc_scid; /* cnf host adapter scsi address */
#define RRE 0x40 /* r/w:e enable response to resel. */
#define SRE 0x20 /* r/w:e enable response to select */
-/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
+/*05*/ U_INT8 nc_sxfer; /* ### Sync speed and count */
-/*06*/ u_char nc_sdid; /* ### Destination-ID */
+/*06*/ U_INT8 nc_sdid; /* ### Destination-ID */
-/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
+/*07*/ U_INT8 nc_gpreg; /* ??? IO-Pins */
-/*08*/ u_char nc_sfbr; /* ### First byte in phase */
+/*08*/ U_INT8 nc_sfbr; /* ### First byte in phase */
-/*09*/ u_char nc_socl;
+/*09*/ U_INT8 nc_socl;
#define CREQ 0x80 /* r/w: SCSI-REQ */
#define CACK 0x40 /* r/w: SCSI-ACK */
#define CBSY 0x20 /* r/w: SCSI-BSY */
#define CC_D 0x02 /* r/w: SCSI-C_D */
#define CI_O 0x01 /* r/w: SCSI-I_O */
-/*0a*/ u_char nc_ssid;
+/*0a*/ U_INT8 nc_ssid;
-/*0b*/ u_char nc_sbcl;
+/*0b*/ U_INT8 nc_sbcl;
-/*0c*/ u_char nc_dstat;
+/*0c*/ U_INT8 nc_dstat;
#define DFE 0x80 /* sta: dma fifo empty */
#define MDPE 0x40 /* int: master data parity error */
#define BF 0x20 /* int: script: bus fault */
#define SIR 0x04 /* int: script: interrupt instruct. */
#define IID 0x01 /* int: script: illegal instruct. */
-/*0d*/ u_char nc_sstat0;
+/*0d*/ U_INT8 nc_sstat0;
#define ILF 0x80 /* sta: data in SIDL register lsb */
#define ORF 0x40 /* sta: data in SODR register lsb */
#define OLF 0x20 /* sta: data in SODL register lsb */
#define IRST 0x02 /* sta: scsi reset signal */
#define SDP 0x01 /* sta: scsi parity signal */
-/*0e*/ u_char nc_sstat1;
+/*0e*/ U_INT8 nc_sstat1;
#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
-/*0f*/ u_char nc_sstat2;
+/*0f*/ U_INT8 nc_sstat2;
#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
#define LDSC 0x02 /* sta: disconnect & reconnect */
-/*10*/ u_long nc_dsa; /* --> Base page */
+/*10*/ U_INT32 nc_dsa; /* --> Base page */
-/*14*/ u_char nc_istat; /* --> Main Command and status */
+/*14*/ U_INT8 nc_istat; /* --> Main Command and status */
#define CABRT 0x80 /* cmd: abort current operation */
#define SRST 0x40 /* mod: reset chip */
#define SIGP 0x20 /* r/w: message from host to ncr */
#define SIP 0x02 /* sta: scsi-interrupt */
#define DIP 0x01 /* sta: host/script interrupt */
-/*15*/ u_char nc_15_;
-/*16*/ u_char nc_16_;
-/*17*/ u_char nc_17_;
+/*15*/ U_INT8 nc_15_;
+/*16*/ U_INT8 nc_16_;
+/*17*/ U_INT8 nc_17_;
-/*18*/ u_char nc_ctest0;
-/*19*/ u_char nc_ctest1;
+/*18*/ U_INT8 nc_ctest0;
+/*19*/ U_INT8 nc_ctest1;
-/*1a*/ u_char nc_ctest2;
+/*1a*/ U_INT8 nc_ctest2;
#define CSIGP 0x40
-/*1b*/ u_char nc_ctest3;
+/*1b*/ U_INT8 nc_ctest3;
#define CLF 0x04 /* clear scsi fifo */
-/*1c*/ u_long nc_temp; /* ### Temporary stack */
+/*1c*/ U_INT32 nc_temp; /* ### Temporary stack */
-/*20*/ u_char nc_dfifo;
-/*21*/ u_char nc_ctest4;
-/*22*/ u_char nc_ctest5;
-/*23*/ u_char nc_ctest6;
+/*20*/ U_INT8 nc_dfifo;
+/*21*/ U_INT8 nc_ctest4;
+/*22*/ U_INT8 nc_ctest5;
+/*23*/ U_INT8 nc_ctest6;
-/*24*/ u_long nc_dbc; /* ### Byte count and command */
-/*28*/ u_long nc_dnad; /* ### Next command register */
-/*2c*/ u_long nc_dsp; /* --> Script Pointer */
-/*30*/ u_long nc_dsps; /* --> Script pointer save/opcode#2 */
-/*34*/ u_long nc_scratcha; /* ??? Temporary register a */
+/*24*/ U_INT32 nc_dbc; /* ### Byte count and command */
+/*28*/ U_INT32 nc_dnad; /* ### Next command register */
+/*2c*/ U_INT32 nc_dsp; /* --> Script Pointer */
+/*30*/ U_INT32 nc_dsps; /* --> Script pointer save/opcode#2 */
+/*34*/ U_INT32 nc_scratcha; /* ??? Temporary register a */
-/*38*/ u_char nc_dmode;
-/*39*/ u_char nc_dien;
-/*3a*/ u_char nc_dwt;
+/*38*/ U_INT8 nc_dmode;
+/*39*/ U_INT8 nc_dien;
+/*3a*/ U_INT8 nc_dwt;
-/*3b*/ u_char nc_dcntl; /* --> Script execution control */
+/*3b*/ U_INT8 nc_dcntl; /* --> Script execution control */
#define SSM 0x10 /* mod: single step mode */
#define STD 0x04 /* cmd: start dma mode */
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
-/*3c*/ u_long nc_adder;
+/*3c*/ U_INT32 nc_adder;
-/*40*/ u_short nc_sien; /* -->: interrupt enable */
-/*42*/ u_short nc_sist; /* <--: interrupt status */
+/*40*/ U_INT16 nc_sien; /* -->: interrupt enable */
+/*42*/ U_INT16 nc_sist; /* <--: interrupt status */
#define STO 0x0400/* sta: timeout (select) */
#define GEN 0x0200/* sta: timeout (general) */
#define HTH 0x0100/* sta: timeout (handshake) */
#define RST 0x02 /* sta: scsi bus reset detected */
#define PAR 0x01 /* sta: scsi parity error */
-/*44*/ u_char nc_slpar;
-/*45*/ u_char nc_swide;
-/*46*/ u_char nc_macntl;
-/*47*/ u_char nc_gpcntl;
-/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
-/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
-/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
+/*44*/ U_INT8 nc_slpar;
+/*45*/ U_INT8 nc_swide;
+/*46*/ U_INT8 nc_macntl;
+/*47*/ U_INT8 nc_gpcntl;
+/*48*/ U_INT8 nc_stime0; /* cmd: timeout for select&handshake*/
+/*49*/ U_INT8 nc_stime1; /* cmd: timeout user defined */
+/*4a*/ U_INT16 nc_respid; /* sta: Reselect-IDs */
-/*4c*/ u_char nc_stest0;
+/*4c*/ U_INT8 nc_stest0;
-/*4d*/ u_char nc_stest1;
+/*4d*/ U_INT8 nc_stest1;
-/*4e*/ u_char nc_stest2;
+/*4e*/ U_INT8 nc_stest2;
#define ROF 0x40 /* reset scsi offset (after gross error!) */
#define EXT 0x02 /* extended filtering */
-/*4f*/ u_char nc_stest3;
+/*4f*/ U_INT8 nc_stest3;
#define TE 0x80 /* c: tolerAnt enable */
#define CSF 0x02 /* c: clear scsi fifo */
-/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
-/*52*/ u_short nc_52_;
-/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
-/*56*/ u_short nc_56_;
-/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
-/*5a*/ u_short nc_5a_;
-/*5c*/ u_char nc_scr0; /* Working register B */
-/*5d*/ u_char nc_scr1; /* */
-/*5e*/ u_char nc_scr2; /* */
-/*5f*/ u_char nc_scr3; /* */
+/*50*/ U_INT16 nc_sidl; /* Lowlevel: latched from scsi data */
+/*52*/ U_INT16 nc_52_;
+/*54*/ U_INT16 nc_sodl; /* Lowlevel: data out to scsi data */
+/*56*/ U_INT16 nc_56_;
+/*58*/ U_INT16 nc_sbdl; /* Lowlevel: data from scsi data */
+/*5a*/ U_INT16 nc_5a_;
+/*5c*/ U_INT8 nc_scr0; /* Working register B */
+/*5d*/ U_INT8 nc_scr1; /* */
+/*5e*/ U_INT8 nc_scr2; /* */
+/*5f*/ U_INT8 nc_scr3; /* */
/*60*/
};
#define TARGET_MODE 0
#endif
-typedef unsigned long ncrcmd;
+typedef U_INT32 ncrcmd;
/*-----------------------------------------------------------
**
#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
struct scr_tblmove {
- u_long size;
- u_long addr;
+ U_INT32 size;
+ U_INT32 addr;
};
/*-----------------------------------------------------------
#define SCR_SEL_TBL_ATN 0x43000000
struct scr_tblsel {
- u_char sel_0;
- u_char sel_sxfer;
- u_char sel_id;
- u_char sel_scntl3;
+ U_INT8 sel_0;
+ U_INT8 sel_sxfer;
+ U_INT8 sel_id;
+ U_INT8 sel_scntl3;
};
#define SCR_JMP_REL 0x04000000
-#define SCR_ID(id) (((u_long)(id)) << 16)
+#define SCR_ID(id) (((U_INT32)(id)) << 16)
/*-----------------------------------------------------------
**
/*
** Messages
*/
-#ifdef __NetBSD__
+#if defined(__NetBSD__) || defined(__OpenBSD__)
#include <scsi/scsi_message.h>
#define M_COMPLETE MSG_CMDCOMPLETE
--- /dev/null
+/* $OpenBSD: pci.c,v 1.1 1996/04/18 23:48:02 niklas Exp $ */
+/* $NetBSD: pci.c,v 1.15 1996/03/14 04:03:01 cgd Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
+ * Copyright (c) 1994 Charles Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI bus autoconfiguration.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+int pcimatch __P((struct device *, void *, void *));
+void pciattach __P((struct device *, struct device *, void *));
+
+struct cfdriver pcicd = {
+ NULL, "pci", pcimatch, pciattach, DV_DULL, sizeof(struct device)
+};
+
+int pciprint __P((void *, char *));
+int pcisubmatch __P((struct device *, void *, void *));
+
+int
+pcimatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct pcibus_attach_args *pba = aux;
+
+ if (strcmp(pba->pba_busname, cf->cf_driver->cd_name))
+ return (0);
+
+ /* Check the locators */
+ if (cf->pcibuscf_bus != PCIBUS_UNK_BUS &&
+ cf->pcibuscf_bus != pba->pba_bus)
+ return (0);
+
+ /* sanity */
+ if (pba->pba_bus < 0 || pba->pba_bus > 255)
+ return (0);
+
+ /*
+ * XXX check other (hardware?) indicators
+ */
+
+ return 1;
+}
+
+void
+pciattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct pcibus_attach_args *pba = aux;
+ bus_chipset_tag_t bc;
+ int device, function, nfunctions;
+
+ pci_md_attach_hook(parent, self, pba);
+ printf("\n");
+
+ for (device = 0; device < PCI_MAX_DEVICE_NUMBER; device++) {
+ pcitag_t tag;
+ pcireg_t id, class;
+ struct pci_attach_args pa;
+ struct cfdata *cf;
+ int supported;
+
+ tag = pci_make_tag(pba->pba_bus, device, 0);
+ id = pci_conf_read(tag, PCI_ID_REG);
+ if (id == 0 || id == 0xffffffff)
+ continue;
+
+ nfunctions = 1; /* XXX */
+
+ for (function = 0; function < nfunctions; function++) {
+ tag = pci_make_tag(pba->pba_bus, device, function);
+ id = pci_conf_read(tag, PCI_ID_REG);
+ if (id == 0 || id == 0xffffffff)
+ continue;
+ class = pci_conf_read(tag, PCI_CLASS_REG);
+
+ pa.pa_bc = pba->pba_bc;
+ pa.pa_device = device;
+ pa.pa_function = function;
+ pa.pa_tag = tag;
+ pa.pa_id = id;
+ pa.pa_class = class;
+
+ config_found_sm(self, &pa, pciprint, pcisubmatch);
+ }
+ }
+}
+
+int
+pciprint(aux, pnp)
+ void *aux;
+ char *pnp;
+{
+ register struct pci_attach_args *pa = aux;
+ char devinfo[256];
+
+ if (pnp) {
+ pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo);
+ printf("%s at %s", devinfo, pnp);
+ }
+ printf(" dev %d function %d", pa->pa_device, pa->pa_function);
+ return (UNCONF);
+}
+
+int
+pcisubmatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct pci_attach_args *pa = aux;
+
+ if (cf->pcicf_dev != PCI_UNK_DEV &&
+ cf->pcicf_dev != pa->pa_device)
+ return 0;
+ if (cf->pcicf_function != PCI_UNK_FUNCTION &&
+ cf->pcicf_function != pa->pa_function)
+ return 0;
+ return ((*cf->cf_driver->cd_match)(parent, match, aux));
+}
-/* $NetBSD: pci_subr.c,v 1.12 1995/08/16 04:54:50 cgd Exp $ */
+/* $OpenBSD: pci_subr.c,v 1.2 1996/04/18 23:48:03 niklas Exp $ */
+/* $NetBSD: pci_subr.c,v 1.17 1996/03/02 02:28:48 cgd Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou. All rights reserved.
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1994 Charles Hannum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <dev/pci/pcidevs.h>
#endif
-int
-pciprint(aux, pci)
- void *aux;
- char *pci;
-{
- register struct pci_attach_args *pa = aux;
-
- printf(" bus %d device %d", pa->pa_bus, pa->pa_device);
- return (UNCONF);
-}
-
-int
-pcisubmatch(parent, match, aux)
- struct device *parent;
- void *match, *aux;
-{
- struct cfdata *cf = match;
- struct pci_attach_args *pa = aux;
-
- if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != pa->pa_bus)
- return 0;
- if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != pa->pa_device)
- return 0;
- return ((*cf->cf_driver->cd_match)(parent, match, aux));
-}
-
-/*
- * Try to find and attach the PCI device at the give bus and device number.
- * Return 1 if successful, 0 if unsuccessful.
- */
-int
-pci_attach_subdev(pcidev, bus, device)
- struct device *pcidev;
- int bus, device;
-{
- pcitag_t tag;
- pcireg_t id, class;
- struct pci_attach_args pa;
- struct cfdata *cf;
- int supported;
- char devinfo[256];
-
- tag = pci_make_tag(bus, device, 0);
- id = pci_conf_read(tag, PCI_ID_REG);
- if (id == 0 || id == 0xffffffff)
- return (0);
- class = pci_conf_read(tag, PCI_CLASS_REG);
-
- pa.pa_bus = bus;
- pa.pa_device = device;
- pa.pa_tag = tag;
- pa.pa_id = id;
- pa.pa_class = class;
-
-#if defined(PCIVERBOSE) && 0 /* _too_ verbose */
- pci_devinfo(id, class, devinfo, NULL);
- printf("%s bus %d device %d: %s\n", pcidev->dv_xname, bus,
- device, devinfo);
-#endif /* _too_ verbose */
-
- if ((cf = config_search(pcisubmatch, pcidev, &pa)) != NULL)
- config_attach(pcidev, cf, &pa, pciprint);
- else {
- pci_devinfo(id, class, devinfo, &supported);
- printf("%s bus %d device %d: %s not %s\n", pcidev->dv_xname,
- bus, device, devinfo,
- supported ? "configured" : "supported");
- return (0);
- }
-
- return (1);
-}
-
/*
* Descriptions of known PCI classes and subclasses.
*
int flags;
char *vendorname, *productname;
};
-#define PCI_KNOWNDEV_UNSUPP 0x01 /* unsupported device */
-#define PCI_KNOWNDEV_NOPROD 0x02 /* match on vendor only */
+#define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */
#include <dev/pci/pcidevs_data.h>
#endif /* PCIVERBOSE */
void
-pci_devinfo(id_reg, class_reg, cp, supp)
+pci_devinfo(id_reg, class_reg, showclass, cp)
pcireg_t id_reg, class_reg;
+ int showclass;
char *cp;
- int *supp;
{
pci_vendor_id_t vendor;
pci_product_id_t product;
struct pci_class *classp, *subclassp;
#ifdef PCIVERBOSE
struct pci_knowndev *kdp;
+ const char *unmatched = "unknown ";
+#else
+ const char *unmatched = "";
#endif
vendor = PCI_VENDOR(id_reg);
break;
kdp++;
}
- if (kdp->vendorname == NULL) {
+ if (kdp->vendorname == NULL)
vendor_namep = product_namep = NULL;
- if (supp != NULL)
- *supp = 0;
- } else {
+ else {
vendor_namep = kdp->vendorname;
product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ?
kdp->productname : NULL;
- if (supp != NULL)
- *supp = (kdp->flags & PCI_KNOWNDEV_UNSUPP) == 0;
}
#else /* PCIVERBOSE */
vendor_namep = product_namep = NULL;
- if (supp != NULL)
- *supp = 1; /* always say 'not configured' */
#endif /* PCIVERBOSE */
classp = pci_class;
}
if (vendor_namep == NULL)
- cp += sprintf(cp, "unknown vendor/product: 0x%04x/0x%04x",
- vendor, product);
+ cp += sprintf(cp, "%svendor 0x%04x product 0x%04x",
+ unmatched, vendor, product);
else if (product_namep != NULL)
cp += sprintf(cp, "%s %s", vendor_namep, product_namep);
else
- cp += sprintf(cp, "vendor: %s, unknown product: 0x%x",
+ cp += sprintf(cp, "vendor %s, unknown product 0x%x",
vendor_namep, product);
- cp += sprintf(cp, " (");
- if (classp->name == NULL)
- cp += sprintf(cp, "unknown class/subclass: 0x%02x/0x%02x",
- class, subclass);
- else {
- cp += sprintf(cp, "class: %s, ", classp->name);
- if (subclassp == NULL || subclassp->name == NULL)
- cp += sprintf(cp, "unknown subclass: 0x%02x",
- subclass);
- else
- cp += sprintf(cp, "subclass: %s", subclassp->name);
- }
+ if (showclass) {
+ cp += sprintf(cp, " (");
+ if (classp->name == NULL)
+ cp += sprintf(cp,
+ "unknown class 0x%2x, subclass 0x%02x",
+ class, subclass);
+ else {
+ cp += sprintf(cp, "class %s, ", classp->name);
+ if (subclassp == NULL || subclassp->name == NULL)
+ cp += sprintf(cp, "unknown subclass 0x%02x",
+ subclass);
+ else
+ cp += sprintf(cp, "subclass %s",
+ subclassp->name);
+ }
#if 0 /* not very useful */
- cp += sprintf(cp, ", interface: 0x%02x", interface);
+ cp += sprintf(cp, ", interface 0x%02x", interface);
#endif
- cp += sprintf(cp, ", revision: 0x%02x)", revision);
+ cp += sprintf(cp, ", revision 0x%02x)", revision);
+ }
}
-$NetBSD: pcidevs,v 1.3 1995/11/10 19:36:09 christos Exp $
+$OpenBSD: pcidevs,v 1.6 1996/04/18 23:48:04 niklas Exp $
+/* $NetBSD: pcidevs,v 1.6 1996/02/19 20:08:25 christos Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* List of known PCI vendors
*/
-vendor OLDCOMPAQ 0x0E11 Compaq # Old ID. see "COMPAQ" below.
-vendor OLDNCR 0x1000 NCR # Old ID. see "NCR" below.
-vendor ATI 0x1002 ATI
-vendor VLSI 0x1004 VLSI
-vendor ADL 0x1005 Advance Logic
-vendor NS 0x100B NS
-vendor TSENG 0x100C Tseng'Lab
-vendor WEITEK 0x100E Weitek
-vendor DEC 0x1011 DEC
-vendor CIRRUS 0x1013 Cirrus Logic
-vendor IBM 0x1014 IBM
-vendor NCR 0x101A NCR
-vendor WD 0x101C Western Digital
-vendor AMD 0x1022 AMD
-vendor TRIDENT 0x1023 Trident
-vendor ACER 0x1025 Acer Incorporated
-vendor MATROX 0x102B Matrox
-vendor CT 0x102C Chips & Technologies
-vendor COMPAQ 0x1032 Compaq
-vendor NEC 0x1033 NEC
-vendor FD 0x1036 Future Domain
-vendor SIS 0x1039 Silicon Integrated Systems
-vendor HP 0x103C Hewlett-Packard
-vendor KPC 0x1040 Kubota Pacific Corp.
-vendor PCTECH 0x1042 PCTECH
-vendor DPT 0x1044 DPT
-vendor OPTI 0x1045 OPTI
-vendor SGS 0x104A SGS Thomson
-vendor BUSLOGIC 0x104B BusLogic
-vendor TI 0x104C Texas Instruments
-vendor SONY 0x104D Sony
-vendor MOT 0x1057 Motorola
-vendor PROMISE 0x105A Promise
-vendor N9 0x105D Number Nine
-vendor UMC 0x1060 UMC
-vendor X 0x1061 X TECHNOLOGY
-vendor MYLEX 0x1069 Mylex
-vendor APPLE 0x106B Apple
-vendor NEXGEN 0x1074 NexGen
-vendor QLOGIC 0x1077 Q Logic
-vendor LEADTEK 0x107D Leadtek Research
-vendor CONTAQ 0x1080 Contaq
-vendor FOREX 0x1083 Forex
-vendor BIT3 0x108A Bit3 Computer Corp.
-vendor QLICOM 0x108D Qlicom
-vendor CMD 0x1095 CMD Technologies
-vendor VISION 0x1098 Vision
-vendor SIERRA 0x10A8 Sierra
-vendor ACC 0x10AA ACC MICROELECTRONICS
-vendor WINBOND 0x10AD Winbond
-vendor CABLETRON 0x10B1 Cabletron
-vendor 3COM 0x10B7 3Com
-vendor AL 0x10B9 Acer Labs
-vendor ASP 0x10CD Advanced System Products
-vendor CERN 0x10DC CERN # ??? XXX
-vendor ECP 0x10DC ECP # ??? XXX
-vendor ECU 0x10DC ECU # ??? XXX
-vendor IMS 0x10E0 IMS
-vendor TEKRAM2 0x10E1 Tekram
-vendor AMCC 0x10E8 AMCC
-vendor INTERG 0x10EA Intergraphics
-vendor REALTEK 0x10EC Realtek
-vendor INIT 0x1101 Initio Corp
-vendor VIA 0x1106 VIA Technologies
-vendor PROTEON 0x1108 Proteon
-vendor VORTEX 0x1119 VORTEX
-vendor EF 0x111A Efficient Networks
-vendor FORE 0x1127 Fore Systems
-vendor IMAGINGTECH 0x112F Imaging Technology
-vendor PLX 0x113C PLX
-vendor ALLIANCE 0x1142 Alliance
-vendor MUTECH 0x1159 Mutech
-vendor ZEITNET 0x1193 ZeitNet
-vendor SPECIALIX 0x11CB Specialix
-vendor CYCLADES 0x120E Cyclades
-vendor SYMPHONY 0x1C1C Symphony
-vendor TEKRAM 0x1DE1 Tekram
-vendor AVANCE 0x4005 Avance
-vendor S3 0x5333 S3 Inc.
-vendor INTEL 0x8086 Intel
-vendor ADP 0x9004 Adaptec
-vendor ATRONICS 0x907F Atronics
-vendor HERCULES 0xEDD8 Hercules
+vendor OLDCOMPAQ 0x0e11 Compaq # Old ID. see "COMPAQ" below.
+vendor OLDNCR 0x1000 NCR # Old ID. see "NCR" below.
+vendor ATI 0x1002 ATI Technologies
+vendor ULSI 0x1003 ULSI Systems
+vendor VLSI 0x1004 VLSI Technology
+vendor AVANCE 0x1005 Avance Logic
+vendor REPLY 0x1006 Reply Group
+vendor NETFRAME 0x1007 NetFrame Systems
+vendor EPSON 0x1008 Epson
+vendor PHOENIX 0x100a Phoenix Technologies
+vendor NS 0x100b National Semiconductor
+vendor TSENG 0x100c Tseng Labs
+vendor AST 0x100d AST Research
+vendor WEITEK 0x100e Weitek
+vendor VIDEOLOGIC 0x1010 Video Logic, Ltd.
+vendor DEC 0x1011 Digital Equipment
+vendor MICRONICS 0x1012 Micronics Computers
+vendor CIRRUS 0x1013 Cirrus Logic
+vendor IBM 0x1014 IBM
+vendor ICLPERSONAL 0x1016 ICL Personal Systems
+vendor SPEA 0x1017 SPEA Software
+vendor UNISYS 0x1018 Unisys Systems
+vendor ELITEGROUP 0x1019 Elitegroup Computer Systems
+vendor NCR 0x101a NCR
+vendor VITESSE 0x101b Vitesse Semiconductor
+vendor WD 0x101c Western Digital
+vendor AMI 0x101e American Megatrends
+vendor PICTURETEL 0x101f PictureTel
+vendor HITACHICOMP 0x1020 Hitachi Computer Products
+vendor OKI 0x1021 OKI Electric Industry
+vendor AMD 0x1022 AMD
+vendor TRIDENT 0x1023 Trident Microsystems
+vendor ZENITH 0x1024 Zenith Data Systems
+vendor ACER 0x1025 Acer
+vendor DELL 0x1028 Dell Computer
+vendor SIEMENS 0x1029 Siemens Nixdorf IS
+vendor MATROX 0x102b Matrox
+vendor CHIPS 0x102c Chips and Technologies
+vendor WYSE 0x102d WYSE Technology
+vendor OLIVETTI 0x102e Olivetti Advanced Technology
+vendor TOSHIBA 0x102f Toshiba America
+vendor TMCRESEARCH 0x1030 TMC Research
+vendor MIRO 0x1031 Miro Computer Products
+vendor COMPAQ 0x1032 Compaq
+vendor NEC 0x1033 NEC
+vendor BURNDY 0x1034 Burndy
+vendor COMPCOMM 0x1035 Comp. & Comm. Research Lab
+vendor FUTUREDOMAIN 0x1036 Future Domain
+vendor HITACHIMICRO 0x1037 Hitach Microsystems
+vendor AMP 0x1038 AMP
+vendor SIS 0x1039 Silicon Integrated System
+vendor SEIKOEPSON 0x103a Seiko Epson
+vendor TATUNGAMERICA 0x103b Tatung Co. of America
+vendor HP 0x103C Hewlett-Packard
+vendor SOLLIDAY 0x103e Solliday Engineering
+vendor LOGICMODELLING 0x103f Logic Modeling
+vendor KPC 0x1040 Kubota Pacific
+vendor COMPUTREND 0x1041 Computrend
+vendor PCTECH 0x1042 PC Technology
+vendor ASUSTEK 0x1043 Asustek Computer
+vendor DPT 0x1044 Distributed Processing Technology
+vendor OPTI 0x1045 Opti
+vendor IPCCORP 0x1046 IPC Corporation
+vendor GENOA 0x1047 Genoa Systems
+vendor ELSA 0x1048 Elsa
+vendor FOUNTAINTECH 0x1049 Fountain Technology
+vendor SGSTHOMSON 0x104a SGS Thomson Microelectric
+vendor BUSLOGIC 0x104b BusLogic
+vendor TI 0x104C Texas Instruments
+vendor SONY 0x104D Sony
+vendor OAKTECH 0x104e Oak Technology
+vendor COTIME 0x104f Co-time Computer
+vendor WINBOND 0x1050 Winbond Electronics
+vendor ANIGMA 0x1051 Anigma
+vendor YOUNGMICRO 0x1052 Young Micro Systems
+vendor HITACHI 0x1054 Hitachi
+vendor EFARMICRO 0x1055 Efar Microsystems
+vendor ICL 0x1056 ICL
+vendor MOT 0x1057 Motorola
+vendor ETR 0x1058 Electronics & Telec. RSH
+vendor TEKNOR 0x1059 Teknor Microsystems
+vendor PROMISE 0x105a Promise Technology
+vendor FOXCONN 0x105b Foxconn International
+vendor WIPRO 0x105c Wipro Infotech
+vendor NUMBER9 0x105d Number 9 Computer Company
+vendor VTECH 0x105e Vtech Computers
+vendor INFOTRONIC 0x105f Infotronic America
+vendor UMC 0x1060 United Microelectronics
+vendor ITT 0x1061 I. T. T. (or X technology?)
+vendor MASPAR 0x1062 Maspar Computer
+vendor OCEANOA 0x1063 Ocean Office Automation
+vendor ALCATEL 0x1064 Alcatel CIT
+vendor TEXASMICRO 0x1065 Texas Microsystems
+vendor PICOPOWER 0x1066 Picopower Technology
+vendor MITSUBISHI 0x1067 Mitsubishi
+vendor DIVERSIFIED 0x1068 Diversified Technology
+vendor MYLEX 0x1069 Mylex
+vendor ATEN 0x106a Aten Research
+vendor APPLE 0x106B Apple
+vendor HYUNDAI 0x106c Hyundai Electronics America
+vendor SEQUENT 0x106d Sequent
+vendor DFI 0x106e DFI
+vendor CITYGATE 0x106f City Gate Development
+vendor DAEWOO 0x1070 Daewoo Telecom
+vendor MITAC 0x1071 Mitac
+vendor GIT 0x1072 GIT Co.
+vendor YAMAHA 0x1073 Yamaha
+vendor NEXGEN 0x1074 NexGen Microsystems
+vendor AIR 0x1075 Advanced Integration Research
+vendor CHAINTECH 0x1076 Chaintech Computer
+vendor QLOGIC 0x1077 Q Logic
+vendor CYRIX 0x1078 Cyrix Corporation
+vendor IBUS 0x1079 I-Bus
+vendor NETWORTH 0x107a NetWorth
+vendor GATEWAY 0x107b Gateway 2000
+vendor GOLDSTART 0x107c Goldstar
+vendor LEADTEK 0x107d LeadTek Research
+vendor INTERPHASE 0x107e Interphase
+vendor DATATECH 0x107f Data Technology Corporation
+vendor CONTAQ 0x1080 Contaq Microsystems
+vendor SUPERMAC 0x1081 Supermac Technology
+vendor EFA 0x1082 EFA Corporation of America
+vendor FOREX 0x1083 Forex Computer
+vendor PARADOR 0x1084 Parador
+vendor TULIP 0x1085 Tulip Computers
+vendor JBOND 0x1086 J. Bond Computer Systems
+vendor CACHECOMP 0x1087 Cache Computer
+vendor MICROCOMP 0x1088 Microcomputer Systems
+vendor DG 0x1089 Data General Corporation
+vendor BIT3 0x108A Bit3 Computer Corp.
+vendor OAKLEIGH 0x108c Oakleigh Systems
+vendor OLICOM 0x108d Olicom
+vendor SYSTEMSOFT 0x108f Systemsoft
+vendor ENCORE 0x1090 Encore Computer
+vendor INTERGRAPH 0x1091 Intergraph
+vendor DIAMOND 0x1092 Diamond Computer Systems
+vendor NATIONALINST 0x1093 National Instruments
+vendor FICOMP 0x1094 First Int'l Computers
+vendor CMDTECH 0x1095 CMD Technology
+vendor ALACRON 0x1096 Alacron
+vendor APPIAN 0x1097 Appian Technology
+vendor QUANTUMDESIGNS 0x1098 Quantum Designs (or Vision?)
+vendor SAMSUNGELEC 0x1099 Samsung Electronics
+vendor PACKARDBELL 0x109a Packard Bell
+vendor GEMLIGHT 0x109b Gemlight Computer
+vendor MEGACHIPS 0x109c Megachips
+vendor ZIDA 0x109d Zida Technologies
+vendor BROOKTREE 0x109e Brooktree
+vendor TRIGEM 0x109f Trigem Computer
+vendor MEIDENSHA 0x10a0 Meidensha
+vendor JUKO 0x10a1 Juko Electronics
+vendor QUANTUM 0x10a2 Quantum
+vendor EVEREX 0x10a3 Everex Systems
+vendor GLOBE 0x10a4 Globe Manufacturing Sales
+vendor RACAL 0x10a5 Racal Interlan
+vendor INFORMTECH 0x10a6 Informtech Industrial
+vendor BENCHMARQ 0x10a7 Benchmarq Microelectronics
+vendor SIERRA 0x10a8 Sierra Semiconductor
+vendor SGI 0x10a9 Silicon Graphics
+vendor ACC 0x10aa ACC Microelectronics
+vendor DIGICOM 0x10ab Digicom
+vendor HONEYWELL 0x10ac Honeywell IASD
+vendor SYMPHONY 0x10ad Symphony Labs (or Winbond?)
+vendor CORNERSTONE 0x10ae Cornerstone Technology
+vendor MICROCOMPSON 0x10af Micro Computer Sysytems (M) SON
+vendor CARDEXPER 0x10b0 CardExpert Technology
+vendor CABLETRON 0x10B1 Cabletron Systems
+vendor RAYETHON 0x10b2 Raytheon
+vendor DATABOOK 0x10b3 Databook
+vendor STB 0x10b4 STB Systems
+vendor PLX 0x10b5 PLX Technology
+vendor MADGE 0x10b6 Madge Networks
+vendor 3COM 0x10B7 3Com
+vendor SMC 0x10b8 Standard Microsystems
+vendor ALI 0x10b9 Acer Labs
+vendor MITSUBISHIELEC 0x10ba Mitsubishi Electronics
+vendor DAPHA 0x10bb Dapha Electronics
+vendor ALR 0x10bc Advanced Logic Research
+vendor SURECOM 0x10bd Surecom Technology
+vendor TSENGLABS 0x10be Tseng Labs International
+vendor MOST 0x10bf Most
+vendor BOCA 0x10c0 Boca Research
+vendor ICM 0x10c1 ICM
+vendor AUSPEX 0x10c2 Auspex Systems
+vendor SAMSUNGSEMI 0x10c3 Samsung Semiconductors
+vendor AWARD 0x10c4 Award Software Int'l
+vendor XEROX 0x10c5 Xerox
+vendor RAMBUS 0x10c6 Rambus
+vendor MEDIAVIS 0x10c7 Media Vision
+vendor NEOMAGIC 0x10c8 Neomagic
+vendor DATAEXPERT 0x10c9 Dataexpert
+vendor FUJITSU 0x10ca Fujitsu
+vendor OMRON 0x10cb Omron
+vendor MENTOR 0x10cc Mentor ARC
+vendor ADVSYSPROD 0x10cd Advanced System Products
+vendor RADIUS 0x10ce Radius
+vendor CITICORP 0x10cf Citicorp TTI
+vendor FUJUTSU 0x10d0 Fujitsu Limited
+vendor FUTUREPLUS 0x10d1 Future+ Systems
+vendor MOLEX 0x10d2 Molex
+vendor JABIL 0x10d3 Jabil Circuit
+vendor HAULON 0x10d4 Hualon Microelectronics
+vendor AUTOLOGIC 0x10d5 Autologic
+vendor CETIA 0x10d6 Cetia
+vendor BCM 0x10d7 BCM Advanced
+vendor APL 0x10d8 Advanced Peripherals Labs
+vendor MACRONIX 0x10d9 Macronix
+vendor THOMASCONRAD 0x10da Thomas-Conrad
+vendor ROHM 0x10db Rohm Research
+vendor CERN 0x10DC CERN/ECP/EDU
+vendor ES 0x10dd Evans & Sutherland
+vendor NVIDIA 0x10de Nvidia Corporation
+vendor EMULEX 0x10df Emulex
+vendor IMS 0x10e0 Integrated Micro Solutions
+vendor TEKRAM 0x10e1 Tekram Technology
+vendor APTIX 0x10e2 Aptix Corporation
+vendor NEWBRIDGE 0x10e3 Newbridge Microsystems
+vendor TANDEM 0x10e4 Tandem Computers
+vendor MICROINDUSTRIES 0x10e5 Micro Industries
+vendor GAINBERY 0x10e6 Gainbery Computer Products
+vendor VADEM 0x10e7 Vadem
+vendor AMCIRCUITS 0x10e8 Applied Micro Circuits
+vendor ALPSELECTIC 0x10e9 Alps Electric
+vendor INTERGRAPHICS 0x10ea Integraphics Systems
+vendor ARTISTSGRAPHICS 0x10eb Artists Graphics
+vendor REALTEK 0x10ec Realtek Semiconductor
+vendor ASCIICORP 0x10ed ASCII Corporation
+vendor XILINX 0x10ee Xilinx
+vendor RACORE 0x10ef Racore Computer Products
+vendor PERITEK 0x10f0 Peritek
+vendor TYAN 0x10f1 Tyan Computer
+vendor ACHME 0x10f2 Achme Computer
+vendor ALARIS 0x10f3 Alaris
+vendor SMOS 0x10f4 S-MOS Systems
+vendor MKK 0x10f5 NKK Corporation
+vendor CREATIVE 0x10f6 Creative Electronic Systems
+vendor MATSUSHITA 0x10f7 Matsushita
+vendor ALTOS 0x10f8 Altos India
+vendor PCDIRECT 0x10f9 PC Direct
+vendor TRUEVISIO 0x10fa Truevision
+vendor THESYS 0x10fb Thesys Ges. F. Mikroelektronik
+vendor IODATA 0x10fc I-O Data Device
+vendor SOYO 0x10fd Soyo Technology
+vendor FAST 0x10fe Fast Electronic
+vendor NCUBE 0x10ff NCube
+vendor JAZZ 0x1100 Jazz Multimedia
+vendor INITIO 0x1101 Initio
+vendor CREATIVELABS 0x1102 Creative Labs
+vendor TRIONES 0x1103 Triones Technologies
+vendor RASTEROPS 0x1104 RasterOps
+vendor SIGMA 0x1105 Sigma Designs
+vendor VIATECH 0x1106 Via Technologies
+vendor STRATIS 0x1107 Stratus Computer
+vendor PROTEON 0x1108 Proteon
+vendor COGENT 0x1109 Cogent Data Technologies
+vendor XENON 0x110b Xenon Microsystems
+vendor MINIMAX 0x110c Mini-Max Technology
+vendor ZNYX 0x110d Znyx Advanced Systems
+vendor CPUTECH 0x110e CPU Technology
+vendor ROSS 0x110f Ross Technology
+vendor POWERHOUSE 0x1110 Powerhouse Systems
+vendor SCO 0x1111 Santa Cruz Operation
+vendor ROCKWELL 0x1112 Rockwell Network Systems
+vendor ACCTON 0x1113 Accton Technology
+vendor ATMEL 0x1114 Atmel
+vendor 3DLABS 0x1115 3D Labs
+vendor DATATRANSLATION 0x1116 Data Translation
+vendor DATACUBE 0x1117 Datacube
+vendor BERG 0x1118 Berg Electronics
+vendor VORTEX 0x1119 Vortex Computer Systems
+vendor EFFICIENTNETS 0x111a Efficent Networks
+vendor TELEDYNE 0x111b Teledyne Electronic Systems
+vendor TRICORD 0x111c Tricord Systems
+vendor IDT 0x111d IDT
+vendor ELDEC 0x111e Eldec
+vendor PDI 0x111f Prescision Digital Images
+vendor EMC 0x1120 Emc
+vendor ZILOG 0x1121 Zilog
+vendor MULTITECH 0x1122 Multi-tech Systems
+vendor LEUTRON 0x1124 Leutron Vision
+vendor EUROCORE 0x1125 Eurocore
+vendor VIGRA 0x1125 Vigra
+vendor FORE 0x1127 FORE Systems
+vendor FIRMWORKS 0x1129 Firmworks
+vendor HERMES 0x112a Hermes Electronics
+vendor LINOTYPE 0x112b Linotype
+vendor RAVICAD 0x112d Ravicad
+vendor INFOMEDIA 0x112e Infomedia Microelectronics
+vendor IMAGINGTECH 0x112f Imaging Technlogy
+vendor COMPUTERVISION 0x1130 Computervision
+vendor PHILIPS 0x1131 Philips
+vendor MITEL 0x1132 Mitel
+vendor EICON 0x1133 Eicon Technology
+vendor MCS 0x1134 Mercury Computer Systems
+vendor FUJIXEROX 0x1135 Fuji Xerox
+vendor MOMENTUM 0x1136 Momentum Data Systems
+vendor CISCO 0x1137 Cisco Systems
+vendor ZIATECH 0x1138 Ziatech
+vendor DYNPIC 0x1139 Dynamic Pictures
+vendor FWB 0x113a FWB
+vendor CYCLONE 0x113c Cyclone Micro
+vendor LEADINGEDGE 0x113d Leading Edge
+vendor SANYO 0x113e Sanyo Electric
+vendor EQUINOX 0x113f Equinox Systems
+vendor INTERVOICE 0x1140 Intervoice
+vendor CREST 0x1141 Crest Microsystem
+vendor ALLIANCE 0x1142 Alliance Semiconductor
+vendor NETPOWER 0x1143 NetPower
+vendor CINMILACRON 0x1144 Cincinnati Milacron
+vendor WORKBIT 0x1145 Workbit
+vendor FORCE 0x1146 Force Computers
+vendor INTERFACE 0x1147 Interface
+vendor SCHNEIDERKOCH 0x1148 Schneider & Koch
+vendor WINSYSTEM 0x1149 Win System
+vendor VMIC 0x114a VMIC
+vendor CANOPUS 0x114b Canopus
+vendor ANNABOOKS 0x114c Annabooks
+vendor IC 0x114d IC Corporation
+vendor NIKON 0x114e Nikon Systems
+vendor DIGIINTERNAT 0x114f Digi International
+vendor TMC 0x1150 Thinking Machines
+vendor JAE 0x1151 JAE Electronics
+vendor MEGATEK 0x1152 Megatek
+vendor LANDWIN 0x1153 Land Win Electronic
+vendor MELCO 0x1154 Melco
+vendor PINETECH 0x1155 Pine Technology
+vendor PERISCOPE 0x1156 Periscope Engineering
+vendor AVSYS 0x1157 Avsys
+vendor VOARX 0x1158 Voarx R & D
+vendor MUTECH 0x1159 Mutech
+vendor HARLEQUIN 0x115a Harlequin
+vendor PARALLAX 0x115b Parallax Graphics
+vendor XIRCOM 0x115d Xircom
+vendor PEERPROTO 0x115e Peer Protocols
+vendor MAXTOR 0x115f Maxtor
+vendor MEGASOFT 0x1160 Megasoft
+vendor PFU 0x1161 PFU Limited
+vendor OALAB 0x1162 OA Laboratory
+vendor SYNEMA 0x1163 Synema Corporation
+vendor APT 0x1164 Advanced Peripherals Technologies
+vendor IMAGRAPH 0x1165 Imagraph
+vendor PEQUR 0x1166 Pequr Technology
+vendor MUTOH 0x1167 Mutoh Industries
+vendor THINE 0x1168 Thine Electronics
+vendor CDAC 0x1169 Centre for Dev. of Advanced Computing
+vendor POLARIS 0x116a Polaris Communications
+vendor CONNECTWARE 0x116b Connectware
+vendor MARTINMARIETTA 0x116d Martin-Marietta
+vendor WSTECH 0x116f Workstation Technology
+vendor INVENTEC 0x1170 Inventec
+vendor ZEITNET 0x1193 ZeitNet
+vendor SPECIALIX 0x11cb Specialix
+vendor CYCLADES 0x120e Cyclades
+vendor SYMPHONY2 0x1c1c Symphony (duplicate? see 0x10ad)
+vendor TEKRAM2 0x1de1 Tekram (mistyped? see 0x10e1)
+vendor AVANCE2 0x4005 Avance Logic (mistyped? see 0x1005)
+vendor S3 0x5333 S3
+vendor INTEL 0x8086 Intel
+vendor ADP 0x9004 Adaptec
+vendor ATRONICS 0x907f Atronics
+vendor NETPOWERNEW 0xdead NetPower
+vendor ARK 0xedd8 Ark Logic (or Arc? or Hercules?)
/*
* List of known products. Grouped by vendor.
*/
+/* 3COM Products */
+product 3COM 3C590 0x5900 3c590
+product 3COM 3C595 0x5950 3c595
+
+/* Acer products */
+product ACER M1435 0x1435 M1435
+
/* Adaptec products */
-product ADP AIC7850 0x7075 UNSUPP AIC-7850
-product ADP AIC7870 0x7078 UNSUPP AIC-7870
-product ADP AIC2940 0x7178 UNSUPP AIC-2940
-product ADP AIC2940U 0x8178 UNSUPP AIC-2940 (\"Ultra\")
+product ADP 3940U 0x8278 AHA-3940 Ultra
+product ADP 2944U 0x8478 AHA-2944 Ultra
+product ADP 2940U 0x8178 AHA-2940 Ultra
+product ADP 3940 0x7278 AHA-3940
+product ADP 2944 0x7478 AHA-2944
+product ADP 2940 0x7178 AHA-2940
+product ADP AIC7880 0x8078 AIC-7880 Ultra
+product ADP AIC7870 0x7078 AIC-7870
+product ADP AIC7850 0x5078 AIC-7850
/* ATI products */
-product ATI MACH32 0x4158 UNSUPP Mach32
-product ATI MACH64_CX 0x4358 UNSUPP Mach64-CX
-product ATI MACH64_GX 0x4758 UNSUPP Mach64-GX
+product ATI MACH32 0x4158 Mach32
+product ATI MACH64_CX 0x4358 Mach64-CX
+product ATI MACH64_GX 0x4758 Mach64-GX
+
+/* BusLogic products */
+product BUSLOGIC 946C 0x0140 946C
+
+/* Cirrus Logic products */
+/* product CIRRUS UNK 0x00a4 unknown */
+product CIRRUS 5434 0x00a8 5434
/* DEC products */
-product DEC 21050 0x0001 UNSUPP DECchip 21050 (\"PPB\")
-product DEC 21040 0x0002 DECchip 21040 (\"Tulip\")
-product DEC 21030 0x0004 UNSUPP DECchip 21030 (\"TGA\")
-product DEC NVRAM 0x0007 UNSUPP Zephyr NV-RAM
-product DEC KZPSA 0x0008 UNSUPP KZPSA
-product DEC 21140 0x0009 DECchip 21140 (\"FasterNet\")
-product DEC DEFPA 0x000f UNSUPP DEFPA
-/* product DEC ??? 0x0010 UNSUPP ??? VME Interface */
-product DEC 21041 0x0014 DECchip 21041 (\"Tulip Pass 3\")
+product DEC 21050 0x0001 DECchip 21050 PCI-PCI Bridge
+product DEC 21040 0x0002 DECchip 21040 (\"Tulip\")
+product DEC 21030 0x0004 DECchip 21030 (\"TGA\")
+product DEC NVRAM 0x0007 Zephyr NV-RAM
+product DEC KZPSA 0x0008 KZPSA
+product DEC 21140 0x0009 DECchip 21140 (\"FasterNet\")
+product DEC DEFPA 0x000f DEFPA
+/* product DEC ??? 0x0010 ??? VME Interface */
+product DEC 21041 0x0014 DECchip 21041 (\"Tulip Pass 3\")
-/* Intel products */
-/* XXX name? */
-product INTEL PCEB 0x0482 UNSUPP 82375EB PCI-EISA Bridge
-product INTEL PCIB 0x0486 UNSUPP 82426EX PCI-ISA Bridge
-product INTEL PCMC 0x04a3 UNSUPP 82434LX PCI, Cache, and Memory controller
+/* Diamond products */
+product DIAMOND vIPER 0x9001 Viper/PCI
+
+/* CMD Technologies Products */
+product CMDTECH PCI0640 0x0640 UNSUPP PCI to IDE Controller
-/* XXX the following two Intel products are UNVERIFIED. */
-product INTEL CDC 0x0483 UNSUPP 82424 Cache and DRAM controller
-/* XXX Supported on the Alpha. XXX unverified. XXX includes PCI-ISA bridge */
-product INTEL SIO 0x0484 UNSUPP 82378 System I/O
+/* FORE products */
+product FORE PCA200 0x0210 ATM PCA-200
+
+/* Intel products */
+product INTEL PCEB 0x0482 82375EB PCI-EISA Bridge
+product INTEL CDC 0x0483 82424ZX Cache and DRAM controller
+product INTEL SIO 0x0484 82378IB PCI-ISA Bridge (System I/O)
+product INTEL PCIB 0x0486 82426EX PCI-ISA Bridge
+product INTEL PCMC 0x04a3 82434LX PCI, Cache, and Memory Controller
/* Mylex products */
-product MYLEX 960P 0x0001 UNSUPP RAID controller
+product MYLEX 960P 0x0001 RAID controller
/* NCR/Symbios Logic products */
-product NCR 810 0x0001 53c810
-product OLDNCR 810 0x0001 53c810
-product NCR 825 0x0003 53c825
-product OLDNCR 825 0x0003 53c825
-product NCR 815 0x0004 53c815
-product OLDNCR 815 0x0004 53c815
+product OLDNCR 810 0x0001 53c810
+product OLDNCR 820 0x0002 53c820
+product OLDNCR 825 0x0003 53c825
+product OLDNCR 815 0x0004 53c815
+/* do the NCR chips use the new ID, as well? */
+
+/* Number Nine products */
+product NUMBER9 IMAG128 0x2309 Imagine-128
+
+/* Opti products */
+product OPTI 82C822 0xc822 82C822
+product OPTI 82C621 0xc821 82C621
/* QLogic products */
-product QLOGIC ISP1020 0x1020 UNSUPP ISP1020
+product QLOGIC ISP1020 0x1020 ISP1020
-/* S3 Products */
-product S3 VISION864 0x88c0 UNSUPP Vision 864
+/* S3 products */
+/* Names??? */
+product S3 TRIO64 0x8811 Trio64
+product S3 928 0x88b0 928
+product S3 864_0 0x88c0 Vision 864-0
+product S3 864_1 0x88c1 Vision 864-1
+product S3 964 0x88d0 964
-/* 3COM Products */
-product 3COM 3C590 0x5900 3c590
-product 3COM 3C595 0x5950 3c595
+/* SMC products */
+product SMC 37C665 0x1000 37C665
-/* CMD Technologies Products */
-product CMD PCI0640 0x0640 UNSUPP PCI to IDE Controller
+/* Tseng Labs products */
+product TSENG W32P_A 0x3202 ET4000w32p rev A
+product TSENG W32P_D 0x3207 ET4000w32p rev D
+
+/* UMC products */
+product UMC UM8673F 0x0101 UM8673F
+product UMC UM8881F 0x8881 UM8881F
+product UMC UM8886F 0x8886 UM8886F
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.3 1995/11/10 19:36:09 christos Exp
+ * OpenBSD
*/
+/* $NetBSD: pcidevs,v 1.6 1996/02/19 20:08:25 christos Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* List of known PCI vendors
*/
-#define PCI_VENDOR_OLDCOMPAQ 0x0E11 /* Compaq (Old ID. see "COMPAQ" below.) */
+#define PCI_VENDOR_OLDCOMPAQ 0x0e11 /* Compaq (Old ID. see "COMPAQ" below.) */
#define PCI_VENDOR_OLDNCR 0x1000 /* NCR (Old ID. see "NCR" below.) */
-#define PCI_VENDOR_ATI 0x1002 /* ATI */
-#define PCI_VENDOR_VLSI 0x1004 /* VLSI */
-#define PCI_VENDOR_ADL 0x1005 /* Advance Logic */
-#define PCI_VENDOR_NS 0x100B /* NS */
-#define PCI_VENDOR_TSENG 0x100C /* Tseng'Lab */
-#define PCI_VENDOR_WEITEK 0x100E /* Weitek */
-#define PCI_VENDOR_DEC 0x1011 /* DEC */
+#define PCI_VENDOR_ATI 0x1002 /* ATI Technologies */
+#define PCI_VENDOR_ULSI 0x1003 /* ULSI Systems */
+#define PCI_VENDOR_VLSI 0x1004 /* VLSI Technology */
+#define PCI_VENDOR_AVANCE 0x1005 /* Avance Logic */
+#define PCI_VENDOR_REPLY 0x1006 /* Reply Group */
+#define PCI_VENDOR_NETFRAME 0x1007 /* NetFrame Systems */
+#define PCI_VENDOR_EPSON 0x1008 /* Epson */
+#define PCI_VENDOR_PHOENIX 0x100a /* Phoenix Technologies */
+#define PCI_VENDOR_NS 0x100b /* National Semiconductor */
+#define PCI_VENDOR_TSENG 0x100c /* Tseng Labs */
+#define PCI_VENDOR_AST 0x100d /* AST Research */
+#define PCI_VENDOR_WEITEK 0x100e /* Weitek */
+#define PCI_VENDOR_VIDEOLOGIC 0x1010 /* Video Logic, Ltd. */
+#define PCI_VENDOR_DEC 0x1011 /* Digital Equipment */
+#define PCI_VENDOR_MICRONICS 0x1012 /* Micronics Computers */
#define PCI_VENDOR_CIRRUS 0x1013 /* Cirrus Logic */
#define PCI_VENDOR_IBM 0x1014 /* IBM */
-#define PCI_VENDOR_NCR 0x101A /* NCR */
-#define PCI_VENDOR_WD 0x101C /* Western Digital */
+#define PCI_VENDOR_ICLPERSONAL 0x1016 /* ICL Personal Systems */
+#define PCI_VENDOR_SPEA 0x1017 /* SPEA Software */
+#define PCI_VENDOR_UNISYS 0x1018 /* Unisys Systems */
+#define PCI_VENDOR_ELITEGROUP 0x1019 /* Elitegroup Computer Systems */
+#define PCI_VENDOR_NCR 0x101a /* NCR */
+#define PCI_VENDOR_VITESSE 0x101b /* Vitesse Semiconductor */
+#define PCI_VENDOR_WD 0x101c /* Western Digital */
+#define PCI_VENDOR_AMI 0x101e /* American Megatrends */
+#define PCI_VENDOR_PICTURETEL 0x101f /* PictureTel */
+#define PCI_VENDOR_HITACHICOMP 0x1020 /* Hitachi Computer Products */
+#define PCI_VENDOR_OKI 0x1021 /* OKI Electric Industry */
#define PCI_VENDOR_AMD 0x1022 /* AMD */
-#define PCI_VENDOR_TRIDENT 0x1023 /* Trident */
-#define PCI_VENDOR_ACER 0x1025 /* Acer Incorporated */
-#define PCI_VENDOR_MATROX 0x102B /* Matrox */
-#define PCI_VENDOR_CT 0x102C /* Chips & Technologies */
+#define PCI_VENDOR_TRIDENT 0x1023 /* Trident Microsystems */
+#define PCI_VENDOR_ZENITH 0x1024 /* Zenith Data Systems */
+#define PCI_VENDOR_ACER 0x1025 /* Acer */
+#define PCI_VENDOR_DELL 0x1028 /* Dell Computer */
+#define PCI_VENDOR_SIEMENS 0x1029 /* Siemens Nixdorf IS */
+#define PCI_VENDOR_MATROX 0x102b /* Matrox */
+#define PCI_VENDOR_CHIPS 0x102c /* Chips and Technologies */
+#define PCI_VENDOR_WYSE 0x102d /* WYSE Technology */
+#define PCI_VENDOR_OLIVETTI 0x102e /* Olivetti Advanced Technology */
+#define PCI_VENDOR_TOSHIBA 0x102f /* Toshiba America */
+#define PCI_VENDOR_TMCRESEARCH 0x1030 /* TMC Research */
+#define PCI_VENDOR_MIRO 0x1031 /* Miro Computer Products */
#define PCI_VENDOR_COMPAQ 0x1032 /* Compaq */
#define PCI_VENDOR_NEC 0x1033 /* NEC */
-#define PCI_VENDOR_FD 0x1036 /* Future Domain */
-#define PCI_VENDOR_SIS 0x1039 /* Silicon Integrated Systems */
+#define PCI_VENDOR_BURNDY 0x1034 /* Burndy */
+#define PCI_VENDOR_COMPCOMM 0x1035 /* Comp. & Comm. Research Lab */
+#define PCI_VENDOR_FUTUREDOMAIN 0x1036 /* Future Domain */
+#define PCI_VENDOR_HITACHIMICRO 0x1037 /* Hitach Microsystems */
+#define PCI_VENDOR_AMP 0x1038 /* AMP */
+#define PCI_VENDOR_SIS 0x1039 /* Silicon Integrated System */
+#define PCI_VENDOR_SEIKOEPSON 0x103a /* Seiko Epson */
+#define PCI_VENDOR_TATUNGAMERICA 0x103b /* Tatung Co. of America */
#define PCI_VENDOR_HP 0x103C /* Hewlett-Packard */
-#define PCI_VENDOR_KPC 0x1040 /* Kubota Pacific Corp. */
-#define PCI_VENDOR_PCTECH 0x1042 /* PCTECH */
-#define PCI_VENDOR_DPT 0x1044 /* DPT */
-#define PCI_VENDOR_OPTI 0x1045 /* OPTI */
-#define PCI_VENDOR_SGS 0x104A /* SGS Thomson */
-#define PCI_VENDOR_BUSLOGIC 0x104B /* BusLogic */
+#define PCI_VENDOR_SOLLIDAY 0x103e /* Solliday Engineering */
+#define PCI_VENDOR_LOGICMODELLING 0x103f /* Logic Modeling */
+#define PCI_VENDOR_KPC 0x1040 /* Kubota Pacific */
+#define PCI_VENDOR_COMPUTREND 0x1041 /* Computrend */
+#define PCI_VENDOR_PCTECH 0x1042 /* PC Technology */
+#define PCI_VENDOR_ASUSTEK 0x1043 /* Asustek Computer */
+#define PCI_VENDOR_DPT 0x1044 /* Distributed Processing Technology */
+#define PCI_VENDOR_OPTI 0x1045 /* Opti */
+#define PCI_VENDOR_IPCCORP 0x1046 /* IPC Corporation */
+#define PCI_VENDOR_GENOA 0x1047 /* Genoa Systems */
+#define PCI_VENDOR_ELSA 0x1048 /* Elsa */
+#define PCI_VENDOR_FOUNTAINTECH 0x1049 /* Fountain Technology */
+#define PCI_VENDOR_SGSTHOMSON 0x104a /* SGS Thomson Microelectric */
+#define PCI_VENDOR_BUSLOGIC 0x104b /* BusLogic */
#define PCI_VENDOR_TI 0x104C /* Texas Instruments */
#define PCI_VENDOR_SONY 0x104D /* Sony */
+#define PCI_VENDOR_OAKTECH 0x104e /* Oak Technology */
+#define PCI_VENDOR_COTIME 0x104f /* Co-time Computer */
+#define PCI_VENDOR_WINBOND 0x1050 /* Winbond Electronics */
+#define PCI_VENDOR_ANIGMA 0x1051 /* Anigma */
+#define PCI_VENDOR_YOUNGMICRO 0x1052 /* Young Micro Systems */
+#define PCI_VENDOR_HITACHI 0x1054 /* Hitachi */
+#define PCI_VENDOR_EFARMICRO 0x1055 /* Efar Microsystems */
+#define PCI_VENDOR_ICL 0x1056 /* ICL */
#define PCI_VENDOR_MOT 0x1057 /* Motorola */
-#define PCI_VENDOR_PROMISE 0x105A /* Promise */
-#define PCI_VENDOR_N9 0x105D /* Number Nine */
-#define PCI_VENDOR_UMC 0x1060 /* UMC */
-#define PCI_VENDOR_X 0x1061 /* X TECHNOLOGY */
+#define PCI_VENDOR_ETR 0x1058 /* Electronics & Telec. RSH */
+#define PCI_VENDOR_TEKNOR 0x1059 /* Teknor Microsystems */
+#define PCI_VENDOR_PROMISE 0x105a /* Promise Technology */
+#define PCI_VENDOR_FOXCONN 0x105b /* Foxconn International */
+#define PCI_VENDOR_WIPRO 0x105c /* Wipro Infotech */
+#define PCI_VENDOR_NUMBER9 0x105d /* Number 9 Computer Company */
+#define PCI_VENDOR_VTECH 0x105e /* Vtech Computers */
+#define PCI_VENDOR_INFOTRONIC 0x105f /* Infotronic America */
+#define PCI_VENDOR_UMC 0x1060 /* United Microelectronics */
+#define PCI_VENDOR_ITT 0x1061 /* I. T. T. (or X technology?) */
+#define PCI_VENDOR_MASPAR 0x1062 /* Maspar Computer */
+#define PCI_VENDOR_OCEANOA 0x1063 /* Ocean Office Automation */
+#define PCI_VENDOR_ALCATEL 0x1064 /* Alcatel CIT */
+#define PCI_VENDOR_TEXASMICRO 0x1065 /* Texas Microsystems */
+#define PCI_VENDOR_PICOPOWER 0x1066 /* Picopower Technology */
+#define PCI_VENDOR_MITSUBISHI 0x1067 /* Mitsubishi */
+#define PCI_VENDOR_DIVERSIFIED 0x1068 /* Diversified Technology */
#define PCI_VENDOR_MYLEX 0x1069 /* Mylex */
+#define PCI_VENDOR_ATEN 0x106a /* Aten Research */
#define PCI_VENDOR_APPLE 0x106B /* Apple */
-#define PCI_VENDOR_NEXGEN 0x1074 /* NexGen */
+#define PCI_VENDOR_HYUNDAI 0x106c /* Hyundai Electronics America */
+#define PCI_VENDOR_SEQUENT 0x106d /* Sequent */
+#define PCI_VENDOR_DFI 0x106e /* DFI */
+#define PCI_VENDOR_CITYGATE 0x106f /* City Gate Development */
+#define PCI_VENDOR_DAEWOO 0x1070 /* Daewoo Telecom */
+#define PCI_VENDOR_MITAC 0x1071 /* Mitac */
+#define PCI_VENDOR_GIT 0x1072 /* GIT Co. */
+#define PCI_VENDOR_YAMAHA 0x1073 /* Yamaha */
+#define PCI_VENDOR_NEXGEN 0x1074 /* NexGen Microsystems */
+#define PCI_VENDOR_AIR 0x1075 /* Advanced Integration Research */
+#define PCI_VENDOR_CHAINTECH 0x1076 /* Chaintech Computer */
#define PCI_VENDOR_QLOGIC 0x1077 /* Q Logic */
-#define PCI_VENDOR_LEADTEK 0x107D /* Leadtek Research */
-#define PCI_VENDOR_CONTAQ 0x1080 /* Contaq */
-#define PCI_VENDOR_FOREX 0x1083 /* Forex */
+#define PCI_VENDOR_CYRIX 0x1078 /* Cyrix Corporation */
+#define PCI_VENDOR_IBUS 0x1079 /* I-Bus */
+#define PCI_VENDOR_NETWORTH 0x107a /* NetWorth */
+#define PCI_VENDOR_GATEWAY 0x107b /* Gateway 2000 */
+#define PCI_VENDOR_GOLDSTART 0x107c /* Goldstar */
+#define PCI_VENDOR_LEADTEK 0x107d /* LeadTek Research */
+#define PCI_VENDOR_INTERPHASE 0x107e /* Interphase */
+#define PCI_VENDOR_DATATECH 0x107f /* Data Technology Corporation */
+#define PCI_VENDOR_CONTAQ 0x1080 /* Contaq Microsystems */
+#define PCI_VENDOR_SUPERMAC 0x1081 /* Supermac Technology */
+#define PCI_VENDOR_EFA 0x1082 /* EFA Corporation of America */
+#define PCI_VENDOR_FOREX 0x1083 /* Forex Computer */
+#define PCI_VENDOR_PARADOR 0x1084 /* Parador */
+#define PCI_VENDOR_TULIP 0x1085 /* Tulip Computers */
+#define PCI_VENDOR_JBOND 0x1086 /* J. Bond Computer Systems */
+#define PCI_VENDOR_CACHECOMP 0x1087 /* Cache Computer */
+#define PCI_VENDOR_MICROCOMP 0x1088 /* Microcomputer Systems */
+#define PCI_VENDOR_DG 0x1089 /* Data General Corporation */
#define PCI_VENDOR_BIT3 0x108A /* Bit3 Computer Corp. */
-#define PCI_VENDOR_QLICOM 0x108D /* Qlicom */
-#define PCI_VENDOR_CMD 0x1095 /* CMD Technologies */
-#define PCI_VENDOR_VISION 0x1098 /* Vision */
-#define PCI_VENDOR_SIERRA 0x10A8 /* Sierra */
-#define PCI_VENDOR_ACC 0x10AA /* ACC MICROELECTRONICS */
-#define PCI_VENDOR_WINBOND 0x10AD /* Winbond */
-#define PCI_VENDOR_CABLETRON 0x10B1 /* Cabletron */
+#define PCI_VENDOR_OAKLEIGH 0x108c /* Oakleigh Systems */
+#define PCI_VENDOR_OLICOM 0x108d /* Olicom */
+#define PCI_VENDOR_SYSTEMSOFT 0x108f /* Systemsoft */
+#define PCI_VENDOR_ENCORE 0x1090 /* Encore Computer */
+#define PCI_VENDOR_INTERGRAPH 0x1091 /* Intergraph */
+#define PCI_VENDOR_DIAMOND 0x1092 /* Diamond Computer Systems */
+#define PCI_VENDOR_NATIONALINST 0x1093 /* National Instruments */
+#define PCI_VENDOR_FICOMP 0x1094 /* First Int'l Computers */
+#define PCI_VENDOR_CMDTECH 0x1095 /* CMD Technology */
+#define PCI_VENDOR_ALACRON 0x1096 /* Alacron */
+#define PCI_VENDOR_APPIAN 0x1097 /* Appian Technology */
+#define PCI_VENDOR_QUANTUMDESIGNS 0x1098 /* Quantum Designs (or Vision?) */
+#define PCI_VENDOR_SAMSUNGELEC 0x1099 /* Samsung Electronics */
+#define PCI_VENDOR_PACKARDBELL 0x109a /* Packard Bell */
+#define PCI_VENDOR_GEMLIGHT 0x109b /* Gemlight Computer */
+#define PCI_VENDOR_MEGACHIPS 0x109c /* Megachips */
+#define PCI_VENDOR_ZIDA 0x109d /* Zida Technologies */
+#define PCI_VENDOR_BROOKTREE 0x109e /* Brooktree */
+#define PCI_VENDOR_TRIGEM 0x109f /* Trigem Computer */
+#define PCI_VENDOR_MEIDENSHA 0x10a0 /* Meidensha */
+#define PCI_VENDOR_JUKO 0x10a1 /* Juko Electronics */
+#define PCI_VENDOR_QUANTUM 0x10a2 /* Quantum */
+#define PCI_VENDOR_EVEREX 0x10a3 /* Everex Systems */
+#define PCI_VENDOR_GLOBE 0x10a4 /* Globe Manufacturing Sales */
+#define PCI_VENDOR_RACAL 0x10a5 /* Racal Interlan */
+#define PCI_VENDOR_INFORMTECH 0x10a6 /* Informtech Industrial */
+#define PCI_VENDOR_BENCHMARQ 0x10a7 /* Benchmarq Microelectronics */
+#define PCI_VENDOR_SIERRA 0x10a8 /* Sierra Semiconductor */
+#define PCI_VENDOR_SGI 0x10a9 /* Silicon Graphics */
+#define PCI_VENDOR_ACC 0x10aa /* ACC Microelectronics */
+#define PCI_VENDOR_DIGICOM 0x10ab /* Digicom */
+#define PCI_VENDOR_HONEYWELL 0x10ac /* Honeywell IASD */
+#define PCI_VENDOR_SYMPHONY 0x10ad /* Symphony Labs (or Winbond?) */
+#define PCI_VENDOR_CORNERSTONE 0x10ae /* Cornerstone Technology */
+#define PCI_VENDOR_MICROCOMPSON 0x10af /* Micro Computer Sysytems (M) SON */
+#define PCI_VENDOR_CARDEXPER 0x10b0 /* CardExpert Technology */
+#define PCI_VENDOR_CABLETRON 0x10B1 /* Cabletron Systems */
+#define PCI_VENDOR_RAYETHON 0x10b2 /* Raytheon */
+#define PCI_VENDOR_DATABOOK 0x10b3 /* Databook */
+#define PCI_VENDOR_STB 0x10b4 /* STB Systems */
+#define PCI_VENDOR_PLX 0x10b5 /* PLX Technology */
+#define PCI_VENDOR_MADGE 0x10b6 /* Madge Networks */
#define PCI_VENDOR_3COM 0x10B7 /* 3Com */
-#define PCI_VENDOR_AL 0x10B9 /* Acer Labs */
-#define PCI_VENDOR_ASP 0x10CD /* Advanced System Products */
-#define PCI_VENDOR_CERN 0x10DC /* CERN (??? XXX) */
-#define PCI_VENDOR_ECP 0x10DC /* ECP (??? XXX) */
-#define PCI_VENDOR_ECU 0x10DC /* ECU (??? XXX) */
-#define PCI_VENDOR_IMS 0x10E0 /* IMS */
-#define PCI_VENDOR_TEKRAM2 0x10E1 /* Tekram */
-#define PCI_VENDOR_AMCC 0x10E8 /* AMCC */
-#define PCI_VENDOR_INTERG 0x10EA /* Intergraphics */
-#define PCI_VENDOR_REALTEK 0x10EC /* Realtek */
-#define PCI_VENDOR_INIT 0x1101 /* Initio Corp */
-#define PCI_VENDOR_VIA 0x1106 /* VIA Technologies */
+#define PCI_VENDOR_SMC 0x10b8 /* Standard Microsystems */
+#define PCI_VENDOR_ALI 0x10b9 /* Acer Labs */
+#define PCI_VENDOR_MITSUBISHIELEC 0x10ba /* Mitsubishi Electronics */
+#define PCI_VENDOR_DAPHA 0x10bb /* Dapha Electronics */
+#define PCI_VENDOR_ALR 0x10bc /* Advanced Logic Research */
+#define PCI_VENDOR_SURECOM 0x10bd /* Surecom Technology */
+#define PCI_VENDOR_TSENGLABS 0x10be /* Tseng Labs International */
+#define PCI_VENDOR_MOST 0x10bf /* Most */
+#define PCI_VENDOR_BOCA 0x10c0 /* Boca Research */
+#define PCI_VENDOR_ICM 0x10c1 /* ICM */
+#define PCI_VENDOR_AUSPEX 0x10c2 /* Auspex Systems */
+#define PCI_VENDOR_SAMSUNGSEMI 0x10c3 /* Samsung Semiconductors */
+#define PCI_VENDOR_AWARD 0x10c4 /* Award Software Int'l */
+#define PCI_VENDOR_XEROX 0x10c5 /* Xerox */
+#define PCI_VENDOR_RAMBUS 0x10c6 /* Rambus */
+#define PCI_VENDOR_MEDIAVIS 0x10c7 /* Media Vision */
+#define PCI_VENDOR_NEOMAGIC 0x10c8 /* Neomagic */
+#define PCI_VENDOR_DATAEXPERT 0x10c9 /* Dataexpert */
+#define PCI_VENDOR_FUJITSU 0x10ca /* Fujitsu */
+#define PCI_VENDOR_OMRON 0x10cb /* Omron */
+#define PCI_VENDOR_MENTOR 0x10cc /* Mentor ARC */
+#define PCI_VENDOR_ADVSYSPROD 0x10cd /* Advanced System Products */
+#define PCI_VENDOR_RADIUS 0x10ce /* Radius */
+#define PCI_VENDOR_CITICORP 0x10cf /* Citicorp TTI */
+#define PCI_VENDOR_FUJUTSU 0x10d0 /* Fujitsu Limited */
+#define PCI_VENDOR_FUTUREPLUS 0x10d1 /* Future+ Systems */
+#define PCI_VENDOR_MOLEX 0x10d2 /* Molex */
+#define PCI_VENDOR_JABIL 0x10d3 /* Jabil Circuit */
+#define PCI_VENDOR_HAULON 0x10d4 /* Hualon Microelectronics */
+#define PCI_VENDOR_AUTOLOGIC 0x10d5 /* Autologic */
+#define PCI_VENDOR_CETIA 0x10d6 /* Cetia */
+#define PCI_VENDOR_BCM 0x10d7 /* BCM Advanced */
+#define PCI_VENDOR_APL 0x10d8 /* Advanced Peripherals Labs */
+#define PCI_VENDOR_MACRONIX 0x10d9 /* Macronix */
+#define PCI_VENDOR_THOMASCONRAD 0x10da /* Thomas-Conrad */
+#define PCI_VENDOR_ROHM 0x10db /* Rohm Research */
+#define PCI_VENDOR_CERN 0x10DC /* CERN/ECP/EDU */
+#define PCI_VENDOR_ES 0x10dd /* Evans & Sutherland */
+#define PCI_VENDOR_NVIDIA 0x10de /* Nvidia Corporation */
+#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
+#define PCI_VENDOR_IMS 0x10e0 /* Integrated Micro Solutions */
+#define PCI_VENDOR_TEKRAM 0x10e1 /* Tekram Technology */
+#define PCI_VENDOR_APTIX 0x10e2 /* Aptix Corporation */
+#define PCI_VENDOR_NEWBRIDGE 0x10e3 /* Newbridge Microsystems */
+#define PCI_VENDOR_TANDEM 0x10e4 /* Tandem Computers */
+#define PCI_VENDOR_MICROINDUSTRIES 0x10e5 /* Micro Industries */
+#define PCI_VENDOR_GAINBERY 0x10e6 /* Gainbery Computer Products */
+#define PCI_VENDOR_VADEM 0x10e7 /* Vadem */
+#define PCI_VENDOR_AMCIRCUITS 0x10e8 /* Applied Micro Circuits */
+#define PCI_VENDOR_ALPSELECTIC 0x10e9 /* Alps Electric */
+#define PCI_VENDOR_INTERGRAPHICS 0x10ea /* Integraphics Systems */
+#define PCI_VENDOR_ARTISTSGRAPHICS 0x10eb /* Artists Graphics */
+#define PCI_VENDOR_REALTEK 0x10ec /* Realtek Semiconductor */
+#define PCI_VENDOR_ASCIICORP 0x10ed /* ASCII Corporation */
+#define PCI_VENDOR_XILINX 0x10ee /* Xilinx */
+#define PCI_VENDOR_RACORE 0x10ef /* Racore Computer Products */
+#define PCI_VENDOR_PERITEK 0x10f0 /* Peritek */
+#define PCI_VENDOR_TYAN 0x10f1 /* Tyan Computer */
+#define PCI_VENDOR_ACHME 0x10f2 /* Achme Computer */
+#define PCI_VENDOR_ALARIS 0x10f3 /* Alaris */
+#define PCI_VENDOR_SMOS 0x10f4 /* S-MOS Systems */
+#define PCI_VENDOR_MKK 0x10f5 /* NKK Corporation */
+#define PCI_VENDOR_CREATIVE 0x10f6 /* Creative Electronic Systems */
+#define PCI_VENDOR_MATSUSHITA 0x10f7 /* Matsushita */
+#define PCI_VENDOR_ALTOS 0x10f8 /* Altos India */
+#define PCI_VENDOR_PCDIRECT 0x10f9 /* PC Direct */
+#define PCI_VENDOR_TRUEVISIO 0x10fa /* Truevision */
+#define PCI_VENDOR_THESYS 0x10fb /* Thesys Ges. F. Mikroelektronik */
+#define PCI_VENDOR_IODATA 0x10fc /* I-O Data Device */
+#define PCI_VENDOR_SOYO 0x10fd /* Soyo Technology */
+#define PCI_VENDOR_FAST 0x10fe /* Fast Electronic */
+#define PCI_VENDOR_NCUBE 0x10ff /* NCube */
+#define PCI_VENDOR_JAZZ 0x1100 /* Jazz Multimedia */
+#define PCI_VENDOR_INITIO 0x1101 /* Initio */
+#define PCI_VENDOR_CREATIVELABS 0x1102 /* Creative Labs */
+#define PCI_VENDOR_TRIONES 0x1103 /* Triones Technologies */
+#define PCI_VENDOR_RASTEROPS 0x1104 /* RasterOps */
+#define PCI_VENDOR_SIGMA 0x1105 /* Sigma Designs */
+#define PCI_VENDOR_VIATECH 0x1106 /* Via Technologies */
+#define PCI_VENDOR_STRATIS 0x1107 /* Stratus Computer */
#define PCI_VENDOR_PROTEON 0x1108 /* Proteon */
-#define PCI_VENDOR_VORTEX 0x1119 /* VORTEX */
-#define PCI_VENDOR_EF 0x111A /* Efficient Networks */
-#define PCI_VENDOR_FORE 0x1127 /* Fore Systems */
-#define PCI_VENDOR_IMAGINGTECH 0x112F /* Imaging Technology */
-#define PCI_VENDOR_PLX 0x113C /* PLX */
-#define PCI_VENDOR_ALLIANCE 0x1142 /* Alliance */
+#define PCI_VENDOR_COGENT 0x1109 /* Cogent Data Technologies */
+#define PCI_VENDOR_XENON 0x110b /* Xenon Microsystems */
+#define PCI_VENDOR_MINIMAX 0x110c /* Mini-Max Technology */
+#define PCI_VENDOR_ZNYX 0x110d /* Znyx Advanced Systems */
+#define PCI_VENDOR_CPUTECH 0x110e /* CPU Technology */
+#define PCI_VENDOR_ROSS 0x110f /* Ross Technology */
+#define PCI_VENDOR_POWERHOUSE 0x1110 /* Powerhouse Systems */
+#define PCI_VENDOR_SCO 0x1111 /* Santa Cruz Operation */
+#define PCI_VENDOR_ROCKWELL 0x1112 /* Rockwell Network Systems */
+#define PCI_VENDOR_ACCTON 0x1113 /* Accton Technology */
+#define PCI_VENDOR_ATMEL 0x1114 /* Atmel */
+#define PCI_VENDOR_3DLABS 0x1115 /* 3D Labs */
+#define PCI_VENDOR_DATATRANSLATION 0x1116 /* Data Translation */
+#define PCI_VENDOR_DATACUBE 0x1117 /* Datacube */
+#define PCI_VENDOR_BERG 0x1118 /* Berg Electronics */
+#define PCI_VENDOR_VORTEX 0x1119 /* Vortex Computer Systems */
+#define PCI_VENDOR_EFFICIENTNETS 0x111a /* Efficent Networks */
+#define PCI_VENDOR_TELEDYNE 0x111b /* Teledyne Electronic Systems */
+#define PCI_VENDOR_TRICORD 0x111c /* Tricord Systems */
+#define PCI_VENDOR_IDT 0x111d /* IDT */
+#define PCI_VENDOR_ELDEC 0x111e /* Eldec */
+#define PCI_VENDOR_PDI 0x111f /* Prescision Digital Images */
+#define PCI_VENDOR_EMC 0x1120 /* Emc */
+#define PCI_VENDOR_ZILOG 0x1121 /* Zilog */
+#define PCI_VENDOR_MULTITECH 0x1122 /* Multi-tech Systems */
+#define PCI_VENDOR_LEUTRON 0x1124 /* Leutron Vision */
+#define PCI_VENDOR_EUROCORE 0x1125 /* Eurocore */
+#define PCI_VENDOR_VIGRA 0x1125 /* Vigra */
+#define PCI_VENDOR_FORE 0x1127 /* FORE Systems */
+#define PCI_VENDOR_FIRMWORKS 0x1129 /* Firmworks */
+#define PCI_VENDOR_HERMES 0x112a /* Hermes Electronics */
+#define PCI_VENDOR_LINOTYPE 0x112b /* Linotype */
+#define PCI_VENDOR_RAVICAD 0x112d /* Ravicad */
+#define PCI_VENDOR_INFOMEDIA 0x112e /* Infomedia Microelectronics */
+#define PCI_VENDOR_IMAGINGTECH 0x112f /* Imaging Technlogy */
+#define PCI_VENDOR_COMPUTERVISION 0x1130 /* Computervision */
+#define PCI_VENDOR_PHILIPS 0x1131 /* Philips */
+#define PCI_VENDOR_MITEL 0x1132 /* Mitel */
+#define PCI_VENDOR_EICON 0x1133 /* Eicon Technology */
+#define PCI_VENDOR_MCS 0x1134 /* Mercury Computer Systems */
+#define PCI_VENDOR_FUJIXEROX 0x1135 /* Fuji Xerox */
+#define PCI_VENDOR_MOMENTUM 0x1136 /* Momentum Data Systems */
+#define PCI_VENDOR_CISCO 0x1137 /* Cisco Systems */
+#define PCI_VENDOR_ZIATECH 0x1138 /* Ziatech */
+#define PCI_VENDOR_DYNPIC 0x1139 /* Dynamic Pictures */
+#define PCI_VENDOR_FWB 0x113a /* FWB */
+#define PCI_VENDOR_CYCLONE 0x113c /* Cyclone Micro */
+#define PCI_VENDOR_LEADINGEDGE 0x113d /* Leading Edge */
+#define PCI_VENDOR_SANYO 0x113e /* Sanyo Electric */
+#define PCI_VENDOR_EQUINOX 0x113f /* Equinox Systems */
+#define PCI_VENDOR_INTERVOICE 0x1140 /* Intervoice */
+#define PCI_VENDOR_CREST 0x1141 /* Crest Microsystem */
+#define PCI_VENDOR_ALLIANCE 0x1142 /* Alliance Semiconductor */
+#define PCI_VENDOR_NETPOWER 0x1143 /* NetPower */
+#define PCI_VENDOR_CINMILACRON 0x1144 /* Cincinnati Milacron */
+#define PCI_VENDOR_WORKBIT 0x1145 /* Workbit */
+#define PCI_VENDOR_FORCE 0x1146 /* Force Computers */
+#define PCI_VENDOR_INTERFACE 0x1147 /* Interface */
+#define PCI_VENDOR_SCHNEIDERKOCH 0x1148 /* Schneider & Koch */
+#define PCI_VENDOR_WINSYSTEM 0x1149 /* Win System */
+#define PCI_VENDOR_VMIC 0x114a /* VMIC */
+#define PCI_VENDOR_CANOPUS 0x114b /* Canopus */
+#define PCI_VENDOR_ANNABOOKS 0x114c /* Annabooks */
+#define PCI_VENDOR_IC 0x114d /* IC Corporation */
+#define PCI_VENDOR_NIKON 0x114e /* Nikon Systems */
+#define PCI_VENDOR_DIGIINTERNAT 0x114f /* Digi International */
+#define PCI_VENDOR_TMC 0x1150 /* Thinking Machines */
+#define PCI_VENDOR_JAE 0x1151 /* JAE Electronics */
+#define PCI_VENDOR_MEGATEK 0x1152 /* Megatek */
+#define PCI_VENDOR_LANDWIN 0x1153 /* Land Win Electronic */
+#define PCI_VENDOR_MELCO 0x1154 /* Melco */
+#define PCI_VENDOR_PINETECH 0x1155 /* Pine Technology */
+#define PCI_VENDOR_PERISCOPE 0x1156 /* Periscope Engineering */
+#define PCI_VENDOR_AVSYS 0x1157 /* Avsys */
+#define PCI_VENDOR_VOARX 0x1158 /* Voarx R & D */
#define PCI_VENDOR_MUTECH 0x1159 /* Mutech */
+#define PCI_VENDOR_HARLEQUIN 0x115a /* Harlequin */
+#define PCI_VENDOR_PARALLAX 0x115b /* Parallax Graphics */
+#define PCI_VENDOR_XIRCOM 0x115d /* Xircom */
+#define PCI_VENDOR_PEERPROTO 0x115e /* Peer Protocols */
+#define PCI_VENDOR_MAXTOR 0x115f /* Maxtor */
+#define PCI_VENDOR_MEGASOFT 0x1160 /* Megasoft */
+#define PCI_VENDOR_PFU 0x1161 /* PFU Limited */
+#define PCI_VENDOR_OALAB 0x1162 /* OA Laboratory */
+#define PCI_VENDOR_SYNEMA 0x1163 /* Synema Corporation */
+#define PCI_VENDOR_APT 0x1164 /* Advanced Peripherals Technologies */
+#define PCI_VENDOR_IMAGRAPH 0x1165 /* Imagraph */
+#define PCI_VENDOR_PEQUR 0x1166 /* Pequr Technology */
+#define PCI_VENDOR_MUTOH 0x1167 /* Mutoh Industries */
+#define PCI_VENDOR_THINE 0x1168 /* Thine Electronics */
+#define PCI_VENDOR_CDAC 0x1169 /* Centre for Dev. of Advanced Computing */
+#define PCI_VENDOR_POLARIS 0x116a /* Polaris Communications */
+#define PCI_VENDOR_CONNECTWARE 0x116b /* Connectware */
+#define PCI_VENDOR_MARTINMARIETTA 0x116d /* Martin-Marietta */
+#define PCI_VENDOR_WSTECH 0x116f /* Workstation Technology */
+#define PCI_VENDOR_INVENTEC 0x1170 /* Inventec */
#define PCI_VENDOR_ZEITNET 0x1193 /* ZeitNet */
-#define PCI_VENDOR_SPECIALIX 0x11CB /* Specialix */
-#define PCI_VENDOR_CYCLADES 0x120E /* Cyclades */
-#define PCI_VENDOR_SYMPHONY 0x1C1C /* Symphony */
-#define PCI_VENDOR_TEKRAM 0x1DE1 /* Tekram */
-#define PCI_VENDOR_AVANCE 0x4005 /* Avance */
-#define PCI_VENDOR_S3 0x5333 /* S3 Inc. */
+#define PCI_VENDOR_SPECIALIX 0x11cb /* Specialix */
+#define PCI_VENDOR_CYCLADES 0x120e /* Cyclades */
+#define PCI_VENDOR_SYMPHONY2 0x1c1c /* Symphony (duplicate? see 0x10ad) */
+#define PCI_VENDOR_TEKRAM2 0x1de1 /* Tekram (mistyped? see 0x10e1) */
+#define PCI_VENDOR_AVANCE2 0x4005 /* Avance Logic (mistyped? see 0x1005) */
+#define PCI_VENDOR_S3 0x5333 /* S3 */
#define PCI_VENDOR_INTEL 0x8086 /* Intel */
#define PCI_VENDOR_ADP 0x9004 /* Adaptec */
-#define PCI_VENDOR_ATRONICS 0x907F /* Atronics */
-#define PCI_VENDOR_HERCULES 0xEDD8 /* Hercules */
+#define PCI_VENDOR_ATRONICS 0x907f /* Atronics */
+#define PCI_VENDOR_NETPOWERNEW 0xdead /* NetPower */
+#define PCI_VENDOR_ARK 0xedd8 /* Ark Logic (or Arc? or Hercules?) */
/*
* List of known products. Grouped by vendor.
*/
+/* 3COM Products */
+#define PCI_PRODUCT_3COM_3C590 0x5900 /* 3c590 */
+#define PCI_PRODUCT_3COM_3C595 0x5950 /* 3c595 */
+
+/* Acer products */
+#define PCI_PRODUCT_ACER_M1435 0x1435 /* M1435 */
+
/* Adaptec products */
-#define PCI_PRODUCT_ADP_AIC7850 0x7075 /* AIC-7850 */
+#define PCI_PRODUCT_ADP_3940U 0x8278 /* AHA-3940 Ultra */
+#define PCI_PRODUCT_ADP_2944U 0x8478 /* AHA-2944 Ultra */
+#define PCI_PRODUCT_ADP_2940U 0x8178 /* AHA-2940 Ultra */
+#define PCI_PRODUCT_ADP_3940 0x7278 /* AHA-3940 */
+#define PCI_PRODUCT_ADP_2944 0x7478 /* AHA-2944 */
+#define PCI_PRODUCT_ADP_2940 0x7178 /* AHA-2940 */
+#define PCI_PRODUCT_ADP_AIC7880 0x8078 /* AIC-7880 Ultra */
#define PCI_PRODUCT_ADP_AIC7870 0x7078 /* AIC-7870 */
-#define PCI_PRODUCT_ADP_AIC2940 0x7178 /* AIC-2940 */
-#define PCI_PRODUCT_ADP_AIC2940U 0x8178 /* AIC-2940 (\"Ultra\") */
+#define PCI_PRODUCT_ADP_AIC7850 0x5078 /* AIC-7850 */
/* ATI products */
#define PCI_PRODUCT_ATI_MACH32 0x4158 /* Mach32 */
#define PCI_PRODUCT_ATI_MACH64_CX 0x4358 /* Mach64-CX */
#define PCI_PRODUCT_ATI_MACH64_GX 0x4758 /* Mach64-GX */
+/* BusLogic products */
+#define PCI_PRODUCT_BUSLOGIC_946C 0x0140 /* 946C */
+
+/* Cirrus Logic products */
+/* product CIRRUS UNK 0x00a4 unknown */
+#define PCI_PRODUCT_CIRRUS_5434 0x00a8 /* 5434 */
+
/* DEC products */
-#define PCI_PRODUCT_DEC_21050 0x0001 /* DECchip 21050 (\"PPB\") */
+#define PCI_PRODUCT_DEC_21050 0x0001 /* DECchip 21050 PCI-PCI Bridge */
#define PCI_PRODUCT_DEC_21040 0x0002 /* DECchip 21040 (\"Tulip\") */
#define PCI_PRODUCT_DEC_21030 0x0004 /* DECchip 21030 (\"TGA\") */
#define PCI_PRODUCT_DEC_NVRAM 0x0007 /* Zephyr NV-RAM */
#define PCI_PRODUCT_DEC_KZPSA 0x0008 /* KZPSA */
#define PCI_PRODUCT_DEC_21140 0x0009 /* DECchip 21140 (\"FasterNet\") */
#define PCI_PRODUCT_DEC_DEFPA 0x000f /* DEFPA */
-/* product DEC ??? 0x0010 UNSUPP ??? VME Interface */
+/* product DEC ??? 0x0010 ??? VME Interface */
#define PCI_PRODUCT_DEC_21041 0x0014 /* DECchip 21041 (\"Tulip Pass 3\") */
+/* Diamond products */
+#define PCI_PRODUCT_DIAMOND_vIPER 0x9001 /* Viper/PCI */
+
+/* CMD Technologies Products */
+#define PCI_PRODUCT_CMDTECH_PCI0640 0x0640 /* PCI to IDE Controller */
+
+/* FORE products */
+#define PCI_PRODUCT_FORE_PCA200 0x0210 /* ATM PCA-200 */
+
/* Intel products */
-/* XXX name? */
#define PCI_PRODUCT_INTEL_PCEB 0x0482 /* 82375EB PCI-EISA Bridge */
+#define PCI_PRODUCT_INTEL_CDC 0x0483 /* 82424ZX Cache and DRAM controller */
+#define PCI_PRODUCT_INTEL_SIO 0x0484 /* 82378IB PCI-ISA Bridge (System I/O) */
#define PCI_PRODUCT_INTEL_PCIB 0x0486 /* 82426EX PCI-ISA Bridge */
-#define PCI_PRODUCT_INTEL_PCMC 0x04a3 /* 82434LX PCI, Cache, and Memory controller */
-
-/* XXX the following two Intel products are UNVERIFIED. */
-#define PCI_PRODUCT_INTEL_CDC 0x0483 /* 82424 Cache and DRAM controller */
-/* XXX Supported on the Alpha. XXX unverified. XXX includes PCI-ISA bridge */
-#define PCI_PRODUCT_INTEL_SIO 0x0484 /* 82378 System I/O */
+#define PCI_PRODUCT_INTEL_PCMC 0x04a3 /* 82434LX PCI, Cache, and Memory Controller */
/* Mylex products */
#define PCI_PRODUCT_MYLEX_960P 0x0001 /* RAID controller */
/* NCR/Symbios Logic products */
-#define PCI_PRODUCT_NCR_810 0x0001 /* 53c810 */
#define PCI_PRODUCT_OLDNCR_810 0x0001 /* 53c810 */
-#define PCI_PRODUCT_NCR_825 0x0003 /* 53c825 */
+#define PCI_PRODUCT_OLDNCR_820 0x0002 /* 53c820 */
#define PCI_PRODUCT_OLDNCR_825 0x0003 /* 53c825 */
-#define PCI_PRODUCT_NCR_815 0x0004 /* 53c815 */
#define PCI_PRODUCT_OLDNCR_815 0x0004 /* 53c815 */
+/* do the NCR chips use the new ID, as well? */
+
+/* Number Nine products */
+#define PCI_PRODUCT_NUMBER9_IMAG128 0x2309 /* Imagine-128 */
+
+/* Opti products */
+#define PCI_PRODUCT_OPTI_82C822 0xc822 /* 82C822 */
+#define PCI_PRODUCT_OPTI_82C621 0xc821 /* 82C621 */
/* QLogic products */
#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 /* ISP1020 */
-/* S3 Products */
-#define PCI_PRODUCT_S3_VISION864 0x88c0 /* Vision 864 */
+/* S3 products */
+/* Names??? */
+#define PCI_PRODUCT_S3_TRIO64 0x8811 /* Trio64 */
+#define PCI_PRODUCT_S3_928 0x88b0 /* 928 */
+#define PCI_PRODUCT_S3_864_0 0x88c0 /* Vision 864-0 */
+#define PCI_PRODUCT_S3_864_1 0x88c1 /* Vision 864-1 */
+#define PCI_PRODUCT_S3_964 0x88d0 /* 964 */
-/* 3COM Products */
-#define PCI_PRODUCT_3COM_3C590 0x5900 /* 3c590 */
-#define PCI_PRODUCT_3COM_3C595 0x5950 /* 3c595 */
+/* SMC products */
+#define PCI_PRODUCT_SMC_37C665 0x1000 /* 37C665 */
-/* CMD Technologies Products */
-#define PCI_PRODUCT_CMD_PCI0640 0x0640 /* PCI to IDE Controller */
+/* Tseng Labs products */
+#define PCI_PRODUCT_TSENG_W32P_A 0x3202 /* ET4000w32p rev A */
+#define PCI_PRODUCT_TSENG_W32P_D 0x3207 /* ET4000w32p rev D */
+
+/* UMC products */
+#define PCI_PRODUCT_UMC_UM8673F 0x0101 /* UM8673F */
+#define PCI_PRODUCT_UMC_UM8881F 0x8881 /* UM8881F */
+#define PCI_PRODUCT_UMC_UM8886F 0x8886 /* UM8886F */
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.3 1995/11/10 19:36:09 christos Exp
+ * OpenBSD
*/
+/* $NetBSD: pcidevs,v 1.6 1996/02/19 20:08:25 christos Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*/
struct pci_knowndev pci_knowndevs[] = {
+ {
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C590,
+ 0,
+ "3Com",
+ "3c590",
+ },
+ {
+ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595,
+ 0,
+ "3Com",
+ "3c595",
+ },
+ {
+ PCI_VENDOR_ACER, PCI_PRODUCT_ACER_M1435,
+ 0,
+ "Acer",
+ "M1435",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940U,
+ 0,
+ "Adaptec",
+ "AHA-3940 Ultra",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944U,
+ 0,
+ "Adaptec",
+ "AHA-2944 Ultra",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940U,
+ 0,
+ "Adaptec",
+ "AHA-2940 Ultra",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940,
+ 0,
+ "Adaptec",
+ "AHA-3940",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944,
+ 0,
+ "Adaptec",
+ "AHA-2944",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940,
+ 0,
+ "Adaptec",
+ "AHA-2940",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7880,
+ 0,
+ "Adaptec",
+ "AIC-7880 Ultra",
+ },
+ {
+ PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7870,
+ 0,
+ "Adaptec",
+ "AIC-7870",
+ },
{
PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7850,
- PCI_KNOWNDEV_UNSUPP,
+ 0,
"Adaptec",
"AIC-7850",
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7870,
- PCI_KNOWNDEV_UNSUPP,
- "Adaptec",
- "AIC-7870",
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH32,
+ 0,
+ "ATI Technologies",
+ "Mach32",
+ },
+ {
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_CX,
+ 0,
+ "ATI Technologies",
+ "Mach64-CX",
+ },
+ {
+ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_GX,
+ 0,
+ "ATI Technologies",
+ "Mach64-GX",
+ },
+ {
+ PCI_VENDOR_BUSLOGIC, PCI_PRODUCT_BUSLOGIC_946C,
+ 0,
+ "BusLogic",
+ "946C",
+ },
+ {
+ PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_5434,
+ 0,
+ "Cirrus Logic",
+ "5434",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21050,
+ 0,
+ "Digital Equipment",
+ "DECchip 21050 PCI-PCI Bridge",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21040,
+ 0,
+ "Digital Equipment",
+ "DECchip 21040 (\"Tulip\")",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21030,
+ 0,
+ "Digital Equipment",
+ "DECchip 21030 (\"TGA\")",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_NVRAM,
+ 0,
+ "Digital Equipment",
+ "Zephyr NV-RAM",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_KZPSA,
+ 0,
+ "Digital Equipment",
+ "KZPSA",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21140,
+ 0,
+ "Digital Equipment",
+ "DECchip 21140 (\"FasterNet\")",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_DEFPA,
+ 0,
+ "Digital Equipment",
+ "DEFPA",
+ },
+ {
+ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21041,
+ 0,
+ "Digital Equipment",
+ "DECchip 21041 (\"Tulip Pass 3\")",
+ },
+ {
+ PCI_VENDOR_DIAMOND, PCI_PRODUCT_DIAMOND_vIPER,
+ 0,
+ "Diamond Computer Systems",
+ "Viper/PCI",
+ },
+ {
+ PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_PCI0640,
+ PCI_KNOWNDEV_UNSUPP,
+ "CMD Technology",
+ "PCI to IDE Controller",
+ },
+ {
+ PCI_VENDOR_FORE, PCI_PRODUCT_FORE_PCA200,
+ 0,
+ "FORE Systems",
+ "ATM PCA-200",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCEB,
+ 0,
+ "Intel",
+ "82375EB PCI-EISA Bridge",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CDC,
+ 0,
+ "Intel",
+ "82424ZX Cache and DRAM controller",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_SIO,
+ 0,
+ "Intel",
+ "82378IB PCI-ISA Bridge (System I/O)",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCIB,
+ 0,
+ "Intel",
+ "82426EX PCI-ISA Bridge",
+ },
+ {
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC,
+ 0,
+ "Intel",
+ "82434LX PCI, Cache, and Memory Controller",
+ },
+ {
+ PCI_VENDOR_MYLEX, PCI_PRODUCT_MYLEX_960P,
+ 0,
+ "Mylex",
+ "RAID controller",
+ },
+ {
+ PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_810,
+ 0,
+ "NCR",
+ "53c810",
+ },
+ {
+ PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_820,
+ 0,
+ "NCR",
+ "53c820",
+ },
+ {
+ PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_825,
+ 0,
+ "NCR",
+ "53c825",
+ },
+ {
+ PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_815,
+ 0,
+ "NCR",
+ "53c815",
+ },
+ {
+ PCI_VENDOR_NUMBER9, PCI_PRODUCT_NUMBER9_IMAG128,
+ 0,
+ "Number 9 Computer Company",
+ "Imagine-128",
+ },
+ {
+ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C822,
+ 0,
+ "Opti",
+ "82C822",
+ },
+ {
+ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C621,
+ 0,
+ "Opti",
+ "82C621",
+ },
+ {
+ PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1020,
+ 0,
+ "Q Logic",
+ "ISP1020",
+ },
+ {
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_TRIO64,
+ 0,
+ "S3",
+ "Trio64",
+ },
+ {
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_928,
+ 0,
+ "S3",
+ "928",
+ },
+ {
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_864_0,
+ 0,
+ "S3",
+ "Vision 864-0",
+ },
+ {
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_864_1,
+ 0,
+ "S3",
+ "Vision 864-1",
+ },
+ {
+ PCI_VENDOR_S3, PCI_PRODUCT_S3_964,
+ 0,
+ "S3",
+ "964",
+ },
+ {
+ PCI_VENDOR_SMC, PCI_PRODUCT_SMC_37C665,
+ 0,
+ "Standard Microsystems",
+ "37C665",
+ },
+ {
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_W32P_A,
+ 0,
+ "Tseng Labs",
+ "ET4000w32p rev A",
+ },
+ {
+ PCI_VENDOR_TSENG, PCI_PRODUCT_TSENG_W32P_D,
+ 0,
+ "Tseng Labs",
+ "ET4000w32p rev D",
+ },
+ {
+ PCI_VENDOR_UMC, PCI_PRODUCT_UMC_UM8673F,
+ 0,
+ "United Microelectronics",
+ "UM8673F",
+ },
+ {
+ PCI_VENDOR_UMC, PCI_PRODUCT_UMC_UM8881F,
+ 0,
+ "United Microelectronics",
+ "UM8881F",
+ },
+ {
+ PCI_VENDOR_UMC, PCI_PRODUCT_UMC_UM8886F,
+ 0,
+ "United Microelectronics",
+ "UM8886F",
+ },
+ {
+ PCI_VENDOR_OLDCOMPAQ, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Compaq",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OLDNCR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NCR",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ATI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ATI Technologies",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ULSI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ULSI Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_VLSI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "VLSI Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AVANCE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Avance Logic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_REPLY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Reply Group",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NETFRAME, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NetFrame Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_EPSON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Epson",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PHOENIX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Phoenix Technologies",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "National Semiconductor",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TSENG, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tseng Labs",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AST, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "AST Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_WEITEK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Weitek",
+ NULL,
+ },
+ {
+ PCI_VENDOR_VIDEOLOGIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Video Logic, Ltd.",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DEC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Digital Equipment",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MICRONICS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Micronics Computers",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CIRRUS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cirrus Logic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_IBM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "IBM",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ICLPERSONAL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ICL Personal Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SPEA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "SPEA Software",
+ NULL,
+ },
+ {
+ PCI_VENDOR_UNISYS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Unisys Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ELITEGROUP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Elitegroup Computer Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NCR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NCR",
+ NULL,
+ },
+ {
+ PCI_VENDOR_VITESSE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Vitesse Semiconductor",
+ NULL,
+ },
+ {
+ PCI_VENDOR_WD, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Western Digital",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AMI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "American Megatrends",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PICTURETEL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "PictureTel",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HITACHICOMP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Hitachi Computer Products",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OKI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "OKI Electric Industry",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AMD, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "AMD",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TRIDENT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Trident Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ZENITH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Zenith Data Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ACER, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Acer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DELL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Dell Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SIEMENS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Siemens Nixdorf IS",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MATROX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Matrox",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CHIPS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Chips and Technologies",
+ NULL,
+ },
+ {
+ PCI_VENDOR_WYSE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "WYSE Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OLIVETTI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Olivetti Advanced Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TOSHIBA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Toshiba America",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TMCRESEARCH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "TMC Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MIRO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Miro Computer Products",
+ NULL,
+ },
+ {
+ PCI_VENDOR_COMPAQ, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Compaq",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NEC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NEC",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BURNDY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Burndy",
+ NULL,
+ },
+ {
+ PCI_VENDOR_COMPCOMM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Comp. & Comm. Research Lab",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FUTUREDOMAIN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Future Domain",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HITACHIMICRO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Hitach Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AMP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "AMP",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SIS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Silicon Integrated System",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SEIKOEPSON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Seiko Epson",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TATUNGAMERICA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tatung Co. of America",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Hewlett-Packard",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SOLLIDAY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Solliday Engineering",
+ NULL,
+ },
+ {
+ PCI_VENDOR_LOGICMODELLING, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Logic Modeling",
+ NULL,
+ },
+ {
+ PCI_VENDOR_KPC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Kubota Pacific",
+ NULL,
+ },
+ {
+ PCI_VENDOR_COMPUTREND, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Computrend",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PCTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "PC Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ASUSTEK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Asustek Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DPT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Distributed Processing Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OPTI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Opti",
+ NULL,
+ },
+ {
+ PCI_VENDOR_IPCCORP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "IPC Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GENOA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Genoa Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ELSA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Elsa",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FOUNTAINTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Fountain Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SGSTHOMSON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "SGS Thomson Microelectric",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BUSLOGIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "BusLogic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Texas Instruments",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SONY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Sony",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OAKTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Oak Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_COTIME, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Co-time Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_WINBOND, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Winbond Electronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ANIGMA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Anigma",
+ NULL,
+ },
+ {
+ PCI_VENDOR_YOUNGMICRO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Young Micro Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HITACHI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Hitachi",
+ NULL,
+ },
+ {
+ PCI_VENDOR_EFARMICRO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Efar Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ICL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ICL",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MOT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Motorola",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ETR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Electronics & Telec. RSH",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TEKNOR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Teknor Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PROMISE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Promise Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FOXCONN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Foxconn International",
+ NULL,
+ },
+ {
+ PCI_VENDOR_WIPRO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Wipro Infotech",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NUMBER9, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Number 9 Computer Company",
+ NULL,
+ },
+ {
+ PCI_VENDOR_VTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Vtech Computers",
+ NULL,
+ },
+ {
+ PCI_VENDOR_INFOTRONIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Infotronic America",
+ NULL,
+ },
+ {
+ PCI_VENDOR_UMC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "United Microelectronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ITT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "I. T. T. (or X technology?)",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MASPAR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Maspar Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OCEANOA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Ocean Office Automation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALCATEL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Alcatel CIT",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TEXASMICRO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Texas Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PICOPOWER, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Picopower Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MITSUBISHI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Mitsubishi",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DIVERSIFIED, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Diversified Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MYLEX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Mylex",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ATEN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Aten Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_APPLE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Apple",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HYUNDAI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Hyundai Electronics America",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SEQUENT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Sequent",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DFI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "DFI",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CITYGATE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "City Gate Development",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DAEWOO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Daewoo Telecom",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MITAC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Mitac",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GIT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "GIT Co.",
+ NULL,
+ },
+ {
+ PCI_VENDOR_YAMAHA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Yamaha",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NEXGEN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NexGen Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AIR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Advanced Integration Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CHAINTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Chaintech Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_QLOGIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Q Logic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CYRIX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cyrix Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_IBUS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "I-Bus",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NETWORTH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NetWorth",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GATEWAY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Gateway 2000",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GOLDSTART, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Goldstar",
+ NULL,
+ },
+ {
+ PCI_VENDOR_LEADTEK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "LeadTek Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_INTERPHASE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Interphase",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DATATECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Data Technology Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CONTAQ, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Contaq Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SUPERMAC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Supermac Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_EFA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "EFA Corporation of America",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FOREX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Forex Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PARADOR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Parador",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TULIP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tulip Computers",
+ NULL,
+ },
+ {
+ PCI_VENDOR_JBOND, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "J. Bond Computer Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CACHECOMP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cache Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MICROCOMP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Microcomputer Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DG, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Data General Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BIT3, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Bit3 Computer Corp.",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OAKLEIGH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Oakleigh Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OLICOM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Olicom",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SYSTEMSOFT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Systemsoft",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ENCORE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Encore Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_INTERGRAPH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Intergraph",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DIAMOND, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Diamond Computer Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NATIONALINST, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "National Instruments",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FICOMP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "First Int'l Computers",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CMDTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "CMD Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALACRON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Alacron",
+ NULL,
+ },
+ {
+ PCI_VENDOR_APPIAN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Appian Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_QUANTUMDESIGNS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Quantum Designs (or Vision?)",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SAMSUNGELEC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Samsung Electronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PACKARDBELL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Packard Bell",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GEMLIGHT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Gemlight Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MEGACHIPS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Megachips",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ZIDA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Zida Technologies",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BROOKTREE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Brooktree",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TRIGEM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Trigem Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MEIDENSHA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Meidensha",
+ NULL,
+ },
+ {
+ PCI_VENDOR_JUKO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Juko Electronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_QUANTUM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Quantum",
+ NULL,
+ },
+ {
+ PCI_VENDOR_EVEREX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Everex Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GLOBE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Globe Manufacturing Sales",
+ NULL,
+ },
+ {
+ PCI_VENDOR_RACAL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Racal Interlan",
+ NULL,
+ },
+ {
+ PCI_VENDOR_INFORMTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Informtech Industrial",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BENCHMARQ, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Benchmarq Microelectronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SIERRA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Sierra Semiconductor",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SGI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Silicon Graphics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ACC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ACC Microelectronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DIGICOM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Digicom",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HONEYWELL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Honeywell IASD",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SYMPHONY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Symphony Labs (or Winbond?)",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CORNERSTONE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cornerstone Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MICROCOMPSON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Micro Computer Sysytems (M) SON",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CARDEXPER, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "CardExpert Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CABLETRON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cabletron Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_RAYETHON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Raytheon",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DATABOOK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Databook",
+ NULL,
+ },
+ {
+ PCI_VENDOR_STB, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "STB Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PLX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "PLX Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MADGE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Madge Networks",
+ NULL,
+ },
+ {
+ PCI_VENDOR_3COM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "3Com",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SMC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Standard Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Acer Labs",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MITSUBISHIELEC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Mitsubishi Electronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DAPHA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Dapha Electronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Advanced Logic Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SURECOM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Surecom Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TSENGLABS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tseng Labs International",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MOST, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Most",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BOCA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Boca Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ICM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ICM",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AUSPEX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Auspex Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SAMSUNGSEMI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Samsung Semiconductors",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AWARD, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Award Software Int'l",
+ NULL,
+ },
+ {
+ PCI_VENDOR_XEROX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Xerox",
+ NULL,
+ },
+ {
+ PCI_VENDOR_RAMBUS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Rambus",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MEDIAVIS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Media Vision",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NEOMAGIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Neomagic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_DATAEXPERT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Dataexpert",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FUJITSU, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Fujitsu",
+ NULL,
+ },
+ {
+ PCI_VENDOR_OMRON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Omron",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MENTOR, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Mentor ARC",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ADVSYSPROD, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Advanced System Products",
+ NULL,
+ },
+ {
+ PCI_VENDOR_RADIUS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Radius",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CITICORP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Citicorp TTI",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FUJUTSU, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Fujitsu Limited",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FUTUREPLUS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Future+ Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MOLEX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Molex",
+ NULL,
+ },
+ {
+ PCI_VENDOR_JABIL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Jabil Circuit",
+ NULL,
+ },
+ {
+ PCI_VENDOR_HAULON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Hualon Microelectronics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AUTOLOGIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Autologic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CETIA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cetia",
+ NULL,
+ },
+ {
+ PCI_VENDOR_BCM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "BCM Advanced",
+ NULL,
+ },
+ {
+ PCI_VENDOR_APL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Advanced Peripherals Labs",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MACRONIX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Macronix",
+ NULL,
+ },
+ {
+ PCI_VENDOR_THOMASCONRAD, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Thomas-Conrad",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ROHM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Rohm Research",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CERN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "CERN/ECP/EDU",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ES, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Evans & Sutherland",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NVIDIA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Nvidia Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_EMULEX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Emulex",
+ NULL,
+ },
+ {
+ PCI_VENDOR_IMS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Integrated Micro Solutions",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TEKRAM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tekram Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_APTIX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Aptix Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NEWBRIDGE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Newbridge Microsystems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TANDEM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tandem Computers",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MICROINDUSTRIES, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Micro Industries",
+ NULL,
+ },
+ {
+ PCI_VENDOR_GAINBERY, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Gainbery Computer Products",
+ NULL,
+ },
+ {
+ PCI_VENDOR_VADEM, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Vadem",
+ NULL,
+ },
+ {
+ PCI_VENDOR_AMCIRCUITS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Applied Micro Circuits",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALPSELECTIC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Alps Electric",
+ NULL,
+ },
+ {
+ PCI_VENDOR_INTERGRAPHICS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Integraphics Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ARTISTSGRAPHICS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Artists Graphics",
+ NULL,
+ },
+ {
+ PCI_VENDOR_REALTEK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Realtek Semiconductor",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ASCIICORP, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "ASCII Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_XILINX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Xilinx",
+ NULL,
+ },
+ {
+ PCI_VENDOR_RACORE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Racore Computer Products",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PERITEK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Peritek",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TYAN, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tyan Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ACHME, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Achme Computer",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALARIS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Alaris",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SMOS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "S-MOS Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MKK, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NKK Corporation",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CREATIVE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Creative Electronic Systems",
+ NULL,
+ },
+ {
+ PCI_VENDOR_MATSUSHITA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Matsushita",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ALTOS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Altos India",
+ NULL,
+ },
+ {
+ PCI_VENDOR_PCDIRECT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "PC Direct",
+ NULL,
+ },
+ {
+ PCI_VENDOR_TRUEVISIO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Truevision",
+ NULL,
+ },
+ {
+ PCI_VENDOR_THESYS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Thesys Ges. F. Mikroelektronik",
+ NULL,
+ },
+ {
+ PCI_VENDOR_IODATA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "I-O Data Device",
+ NULL,
+ },
+ {
+ PCI_VENDOR_SOYO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Soyo Technology",
+ NULL,
+ },
+ {
+ PCI_VENDOR_FAST, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Fast Electronic",
+ NULL,
+ },
+ {
+ PCI_VENDOR_NCUBE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NCube",
+ NULL,
+ },
+ {
+ PCI_VENDOR_JAZZ, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Jazz Multimedia",
+ NULL,
+ },
+ {
+ PCI_VENDOR_INITIO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Initio",
+ NULL,
+ },
+ {
+ PCI_VENDOR_CREATIVELABS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Creative Labs",
+ NULL,
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC2940,
- PCI_KNOWNDEV_UNSUPP,
- "Adaptec",
- "AIC-2940",
+ PCI_VENDOR_TRIONES, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Triones Technologies",
+ NULL,
},
{
- PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC2940U,
- PCI_KNOWNDEV_UNSUPP,
- "Adaptec",
- "AIC-2940 (\"Ultra\")",
+ PCI_VENDOR_RASTEROPS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "RasterOps",
+ NULL,
},
{
- PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH32,
- PCI_KNOWNDEV_UNSUPP,
- "ATI",
- "Mach32",
+ PCI_VENDOR_SIGMA, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Sigma Designs",
+ NULL,
},
{
- PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_CX,
- PCI_KNOWNDEV_UNSUPP,
- "ATI",
- "Mach64-CX",
+ PCI_VENDOR_VIATECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Via Technologies",
+ NULL,
},
{
- PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MACH64_GX,
- PCI_KNOWNDEV_UNSUPP,
- "ATI",
- "Mach64-GX",
+ PCI_VENDOR_STRATIS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Stratus Computer",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21050,
- PCI_KNOWNDEV_UNSUPP,
- "DEC",
- "DECchip 21050 (\"PPB\")",
+ PCI_VENDOR_PROTEON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Proteon",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21040,
- 0,
- "DEC",
- "DECchip 21040 (\"Tulip\")",
+ PCI_VENDOR_COGENT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Cogent Data Technologies",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21030,
- PCI_KNOWNDEV_UNSUPP,
- "DEC",
- "DECchip 21030 (\"TGA\")",
+ PCI_VENDOR_XENON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Xenon Microsystems",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_NVRAM,
- PCI_KNOWNDEV_UNSUPP,
- "DEC",
- "Zephyr NV-RAM",
+ PCI_VENDOR_MINIMAX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Mini-Max Technology",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_KZPSA,
- PCI_KNOWNDEV_UNSUPP,
- "DEC",
- "KZPSA",
+ PCI_VENDOR_ZNYX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Znyx Advanced Systems",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21140,
- 0,
- "DEC",
- "DECchip 21140 (\"FasterNet\")",
+ PCI_VENDOR_CPUTECH, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "CPU Technology",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_DEFPA,
- PCI_KNOWNDEV_UNSUPP,
- "DEC",
- "DEFPA",
+ PCI_VENDOR_ROSS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Ross Technology",
+ NULL,
},
{
- PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21041,
- 0,
- "DEC",
- "DECchip 21041 (\"Tulip Pass 3\")",
+ PCI_VENDOR_POWERHOUSE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Powerhouse Systems",
+ NULL,
},
{
- PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCEB,
- PCI_KNOWNDEV_UNSUPP,
- "Intel",
- "82375EB PCI-EISA Bridge",
+ PCI_VENDOR_SCO, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Santa Cruz Operation",
+ NULL,
},
{
- PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCIB,
- PCI_KNOWNDEV_UNSUPP,
- "Intel",
- "82426EX PCI-ISA Bridge",
+ PCI_VENDOR_ROCKWELL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Rockwell Network Systems",
+ NULL,
},
{
- PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC,
- PCI_KNOWNDEV_UNSUPP,
- "Intel",
- "82434LX PCI, Cache, and Memory controller",
+ PCI_VENDOR_ACCTON, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Accton Technology",
+ NULL,
},
{
- PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CDC,
- PCI_KNOWNDEV_UNSUPP,
- "Intel",
- "82424 Cache and DRAM controller",
+ PCI_VENDOR_ATMEL, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Atmel",
+ NULL,
},
{
- PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_SIO,
- PCI_KNOWNDEV_UNSUPP,
- "Intel",
- "82378 System I/O",
+ PCI_VENDOR_3DLABS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "3D Labs",
+ NULL,
},
{
- PCI_VENDOR_MYLEX, PCI_PRODUCT_MYLEX_960P,
- PCI_KNOWNDEV_UNSUPP,
- "Mylex",
- "RAID controller",
+ PCI_VENDOR_DATATRANSLATION, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Data Translation",
+ NULL,
},
{
- PCI_VENDOR_NCR, PCI_PRODUCT_NCR_810,
- 0,
- "NCR",
- "53c810",
+ PCI_VENDOR_DATACUBE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Datacube",
+ NULL,
},
{
- PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_810,
- 0,
- "NCR",
- "53c810",
+ PCI_VENDOR_BERG, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Berg Electronics",
+ NULL,
},
{
- PCI_VENDOR_NCR, PCI_PRODUCT_NCR_825,
- 0,
- "NCR",
- "53c825",
+ PCI_VENDOR_VORTEX, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Vortex Computer Systems",
+ NULL,
},
{
- PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_825,
- 0,
- "NCR",
- "53c825",
+ PCI_VENDOR_EFFICIENTNETS, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Efficent Networks",
+ NULL,
},
{
- PCI_VENDOR_NCR, PCI_PRODUCT_NCR_815,
- 0,
- "NCR",
- "53c815",
+ PCI_VENDOR_TELEDYNE, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Teledyne Electronic Systems",
+ NULL,
},
{
- PCI_VENDOR_OLDNCR, PCI_PRODUCT_OLDNCR_815,
- 0,
- "NCR",
- "53c815",
+ PCI_VENDOR_TRICORD, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Tricord Systems",
+ NULL,
},
{
- PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1020,
- PCI_KNOWNDEV_UNSUPP,
- "Q Logic",
- "ISP1020",
+ PCI_VENDOR_IDT, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "IDT",
+ NULL,
},
{
- PCI_VENDOR_S3, PCI_PRODUCT_S3_VISION864,
- PCI_KNOWNDEV_UNSUPP,
- "S3 Inc.",
- "Vision 864",
+ PCI_VENDOR_ELDEC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Eldec",
+ NULL,
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C590,
- 0,
- "3Com",
- "3c590",
+ PCI_VENDOR_PDI, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Prescision Digital Images",
+ NULL,
},
{
- PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C595,
- 0,
- "3Com",
- "3c595",
+ PCI_VENDOR_EMC, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Emc",
+ NULL,
},
{
- PCI_VENDOR_CMD, PCI_PRODUCT_CMD_PCI0640,
- PCI_KNOWNDEV_UNSUPP,
- "CMD Technologies",
- "PCI to IDE Controller",
+ PCI_VENDOR_ZILOG, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "Zilog",
+ NULL,
},
{
- PCI_VENDOR_OLDCOMPAQ, 0,
+ PCI_VENDOR_MULTITECH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Compaq",
+ "Multi-tech Systems",
NULL,
},
{
- PCI_VENDOR_OLDNCR, 0,
+ PCI_VENDOR_LEUTRON, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "NCR",
+ "Leutron Vision",
NULL,
},
{
- PCI_VENDOR_ATI, 0,
+ PCI_VENDOR_EUROCORE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "ATI",
+ "Eurocore",
NULL,
},
{
- PCI_VENDOR_VLSI, 0,
+ PCI_VENDOR_VIGRA, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "VLSI",
+ "Vigra",
NULL,
},
{
- PCI_VENDOR_ADL, 0,
+ PCI_VENDOR_FORE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Advance Logic",
+ "FORE Systems",
NULL,
},
{
- PCI_VENDOR_NS, 0,
+ PCI_VENDOR_FIRMWORKS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "NS",
+ "Firmworks",
NULL,
},
{
- PCI_VENDOR_TSENG, 0,
+ PCI_VENDOR_HERMES, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Tseng'Lab",
+ "Hermes Electronics",
NULL,
},
{
- PCI_VENDOR_WEITEK, 0,
+ PCI_VENDOR_LINOTYPE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Weitek",
+ "Linotype",
NULL,
},
{
- PCI_VENDOR_DEC, 0,
+ PCI_VENDOR_RAVICAD, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "DEC",
+ "Ravicad",
NULL,
},
{
- PCI_VENDOR_CIRRUS, 0,
+ PCI_VENDOR_INFOMEDIA, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Cirrus Logic",
+ "Infomedia Microelectronics",
NULL,
},
{
- PCI_VENDOR_IBM, 0,
+ PCI_VENDOR_IMAGINGTECH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "IBM",
+ "Imaging Technlogy",
NULL,
},
{
- PCI_VENDOR_NCR, 0,
+ PCI_VENDOR_COMPUTERVISION, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "NCR",
+ "Computervision",
NULL,
},
{
- PCI_VENDOR_WD, 0,
+ PCI_VENDOR_PHILIPS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Western Digital",
+ "Philips",
NULL,
},
{
- PCI_VENDOR_AMD, 0,
+ PCI_VENDOR_MITEL, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "AMD",
+ "Mitel",
NULL,
},
{
- PCI_VENDOR_TRIDENT, 0,
+ PCI_VENDOR_EICON, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Trident",
+ "Eicon Technology",
NULL,
},
{
- PCI_VENDOR_ACER, 0,
+ PCI_VENDOR_MCS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Acer Incorporated",
+ "Mercury Computer Systems",
NULL,
},
{
- PCI_VENDOR_MATROX, 0,
+ PCI_VENDOR_FUJIXEROX, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Matrox",
+ "Fuji Xerox",
NULL,
},
{
- PCI_VENDOR_CT, 0,
+ PCI_VENDOR_MOMENTUM, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Chips & Technologies",
+ "Momentum Data Systems",
NULL,
},
{
- PCI_VENDOR_COMPAQ, 0,
+ PCI_VENDOR_CISCO, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Compaq",
+ "Cisco Systems",
NULL,
},
{
- PCI_VENDOR_NEC, 0,
+ PCI_VENDOR_ZIATECH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "NEC",
+ "Ziatech",
NULL,
},
{
- PCI_VENDOR_FD, 0,
+ PCI_VENDOR_DYNPIC, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Future Domain",
+ "Dynamic Pictures",
NULL,
},
{
- PCI_VENDOR_SIS, 0,
+ PCI_VENDOR_FWB, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Silicon Integrated Systems",
+ "FWB",
NULL,
},
{
- PCI_VENDOR_HP, 0,
+ PCI_VENDOR_CYCLONE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Hewlett-Packard",
+ "Cyclone Micro",
NULL,
},
{
- PCI_VENDOR_KPC, 0,
+ PCI_VENDOR_LEADINGEDGE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Kubota Pacific Corp.",
+ "Leading Edge",
NULL,
},
{
- PCI_VENDOR_PCTECH, 0,
+ PCI_VENDOR_SANYO, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "PCTECH",
+ "Sanyo Electric",
NULL,
},
{
- PCI_VENDOR_DPT, 0,
+ PCI_VENDOR_EQUINOX, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "DPT",
+ "Equinox Systems",
NULL,
},
{
- PCI_VENDOR_OPTI, 0,
+ PCI_VENDOR_INTERVOICE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "OPTI",
+ "Intervoice",
NULL,
},
{
- PCI_VENDOR_SGS, 0,
+ PCI_VENDOR_CREST, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "SGS Thomson",
+ "Crest Microsystem",
NULL,
},
{
- PCI_VENDOR_BUSLOGIC, 0,
+ PCI_VENDOR_ALLIANCE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "BusLogic",
+ "Alliance Semiconductor",
NULL,
},
{
- PCI_VENDOR_TI, 0,
+ PCI_VENDOR_NETPOWER, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Texas Instruments",
+ "NetPower",
NULL,
},
{
- PCI_VENDOR_SONY, 0,
+ PCI_VENDOR_CINMILACRON, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Sony",
+ "Cincinnati Milacron",
NULL,
},
{
- PCI_VENDOR_MOT, 0,
+ PCI_VENDOR_WORKBIT, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Motorola",
+ "Workbit",
NULL,
},
{
- PCI_VENDOR_PROMISE, 0,
+ PCI_VENDOR_FORCE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Promise",
+ "Force Computers",
NULL,
},
{
- PCI_VENDOR_N9, 0,
+ PCI_VENDOR_INTERFACE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Number Nine",
+ "Interface",
NULL,
},
{
- PCI_VENDOR_UMC, 0,
+ PCI_VENDOR_SCHNEIDERKOCH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "UMC",
+ "Schneider & Koch",
NULL,
},
{
- PCI_VENDOR_X, 0,
+ PCI_VENDOR_WINSYSTEM, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "X TECHNOLOGY",
+ "Win System",
NULL,
},
{
- PCI_VENDOR_MYLEX, 0,
+ PCI_VENDOR_VMIC, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Mylex",
+ "VMIC",
NULL,
},
{
- PCI_VENDOR_APPLE, 0,
+ PCI_VENDOR_CANOPUS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Apple",
+ "Canopus",
NULL,
},
{
- PCI_VENDOR_NEXGEN, 0,
+ PCI_VENDOR_ANNABOOKS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "NexGen",
+ "Annabooks",
NULL,
},
{
- PCI_VENDOR_QLOGIC, 0,
+ PCI_VENDOR_IC, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Q Logic",
+ "IC Corporation",
NULL,
},
{
- PCI_VENDOR_LEADTEK, 0,
+ PCI_VENDOR_NIKON, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Leadtek Research",
+ "Nikon Systems",
NULL,
},
{
- PCI_VENDOR_CONTAQ, 0,
+ PCI_VENDOR_DIGIINTERNAT, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Contaq",
+ "Digi International",
NULL,
},
{
- PCI_VENDOR_FOREX, 0,
+ PCI_VENDOR_TMC, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Forex",
+ "Thinking Machines",
NULL,
},
{
- PCI_VENDOR_BIT3, 0,
+ PCI_VENDOR_JAE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Bit3 Computer Corp.",
+ "JAE Electronics",
NULL,
},
{
- PCI_VENDOR_QLICOM, 0,
+ PCI_VENDOR_MEGATEK, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Qlicom",
+ "Megatek",
NULL,
},
{
- PCI_VENDOR_CMD, 0,
+ PCI_VENDOR_LANDWIN, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "CMD Technologies",
+ "Land Win Electronic",
NULL,
},
{
- PCI_VENDOR_VISION, 0,
+ PCI_VENDOR_MELCO, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Vision",
+ "Melco",
NULL,
},
{
- PCI_VENDOR_SIERRA, 0,
+ PCI_VENDOR_PINETECH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Sierra",
+ "Pine Technology",
NULL,
},
{
- PCI_VENDOR_ACC, 0,
+ PCI_VENDOR_PERISCOPE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "ACC MICROELECTRONICS",
+ "Periscope Engineering",
NULL,
},
{
- PCI_VENDOR_WINBOND, 0,
+ PCI_VENDOR_AVSYS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Winbond",
+ "Avsys",
NULL,
},
{
- PCI_VENDOR_CABLETRON, 0,
+ PCI_VENDOR_VOARX, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Cabletron",
+ "Voarx R & D",
NULL,
},
{
- PCI_VENDOR_3COM, 0,
+ PCI_VENDOR_MUTECH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "3Com",
+ "Mutech",
NULL,
},
{
- PCI_VENDOR_AL, 0,
+ PCI_VENDOR_HARLEQUIN, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Acer Labs",
+ "Harlequin",
NULL,
},
{
- PCI_VENDOR_ASP, 0,
+ PCI_VENDOR_PARALLAX, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Advanced System Products",
+ "Parallax Graphics",
NULL,
},
{
- PCI_VENDOR_CERN, 0,
+ PCI_VENDOR_XIRCOM, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "CERN",
+ "Xircom",
NULL,
},
{
- PCI_VENDOR_ECP, 0,
+ PCI_VENDOR_PEERPROTO, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "ECP",
+ "Peer Protocols",
NULL,
},
{
- PCI_VENDOR_ECU, 0,
+ PCI_VENDOR_MAXTOR, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "ECU",
+ "Maxtor",
NULL,
},
{
- PCI_VENDOR_IMS, 0,
+ PCI_VENDOR_MEGASOFT, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "IMS",
+ "Megasoft",
NULL,
},
{
- PCI_VENDOR_TEKRAM2, 0,
+ PCI_VENDOR_PFU, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Tekram",
+ "PFU Limited",
NULL,
},
{
- PCI_VENDOR_AMCC, 0,
+ PCI_VENDOR_OALAB, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "AMCC",
+ "OA Laboratory",
NULL,
},
{
- PCI_VENDOR_INTERG, 0,
+ PCI_VENDOR_SYNEMA, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Intergraphics",
+ "Synema Corporation",
NULL,
},
{
- PCI_VENDOR_REALTEK, 0,
+ PCI_VENDOR_APT, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Realtek",
+ "Advanced Peripherals Technologies",
NULL,
},
{
- PCI_VENDOR_INIT, 0,
+ PCI_VENDOR_IMAGRAPH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Initio Corp",
+ "Imagraph",
NULL,
},
{
- PCI_VENDOR_VIA, 0,
+ PCI_VENDOR_PEQUR, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "VIA Technologies",
+ "Pequr Technology",
NULL,
},
{
- PCI_VENDOR_PROTEON, 0,
+ PCI_VENDOR_MUTOH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Proteon",
+ "Mutoh Industries",
NULL,
},
{
- PCI_VENDOR_VORTEX, 0,
+ PCI_VENDOR_THINE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "VORTEX",
+ "Thine Electronics",
NULL,
},
{
- PCI_VENDOR_EF, 0,
+ PCI_VENDOR_CDAC, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Efficient Networks",
+ "Centre for Dev. of Advanced Computing",
NULL,
},
{
- PCI_VENDOR_FORE, 0,
+ PCI_VENDOR_POLARIS, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Fore Systems",
+ "Polaris Communications",
NULL,
},
{
- PCI_VENDOR_IMAGINGTECH, 0,
+ PCI_VENDOR_CONNECTWARE, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Imaging Technology",
+ "Connectware",
NULL,
},
{
- PCI_VENDOR_PLX, 0,
+ PCI_VENDOR_MARTINMARIETTA, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "PLX",
+ "Martin-Marietta",
NULL,
},
{
- PCI_VENDOR_ALLIANCE, 0,
+ PCI_VENDOR_WSTECH, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Alliance",
+ "Workstation Technology",
NULL,
},
{
- PCI_VENDOR_MUTECH, 0,
+ PCI_VENDOR_INVENTEC, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Mutech",
+ "Inventec",
NULL,
},
{
NULL,
},
{
- PCI_VENDOR_SYMPHONY, 0,
+ PCI_VENDOR_SYMPHONY2, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Symphony",
+ "Symphony (duplicate? see 0x10ad)",
NULL,
},
{
- PCI_VENDOR_TEKRAM, 0,
+ PCI_VENDOR_TEKRAM2, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Tekram",
+ "Tekram (mistyped? see 0x10e1)",
NULL,
},
{
- PCI_VENDOR_AVANCE, 0,
+ PCI_VENDOR_AVANCE2, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Avance",
+ "Avance Logic (mistyped? see 0x1005)",
NULL,
},
{
PCI_VENDOR_S3, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "S3 Inc.",
+ "S3",
NULL,
},
{
NULL,
},
{
- PCI_VENDOR_HERCULES, 0,
+ PCI_VENDOR_NETPOWERNEW, 0,
+ PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
+ "NetPower",
+ NULL,
+ },
+ {
+ PCI_VENDOR_ARK, 0,
PCI_KNOWNDEV_UNSUPP | PCI_KNOWNDEV_NOPROD,
- "Hercules",
+ "Ark Logic (or Arc? or Hercules?)",
NULL,
},
{ 0, 0, 0, NULL, NULL, }
-/* $NetBSD: pcireg.h,v 1.4 1995/07/27 00:29:02 mycroft Exp $ */
+/* $OpenBSD: pcireg.h,v 1.2 1996/04/18 23:48:07 niklas Exp $ */
+/* $NetBSD: pcireg.h,v 1.5 1996/03/04 19:30:51 cgd Exp $ */
/*
- * Copyright (c) 1995 Christopher G. Demetriou. All rights reserved.
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1994 Charles Hannum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
/*
* Mapping registers
- * XXX ADJUST
*/
-#define PCI_MAP_REG_START 0x10
-#define PCI_MAP_REG_END 0x28
+#define PCI_MAPREG_START 0x10
+#define PCI_MAPREG_END 0x28
-#define PCI_MAP_MEMORY 0x00000000
+#define PCI_MAPREG_TYPE(mr) \
+ ((mr) & PCI_MAPREG_TYPE_MASK)
+#define PCI_MAPREG_TYPE_MASK 0x00000001
-#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
-#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
-#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
-#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
-#define PCI_MAP_MEMORY_CACHABLE 0x00000008
-#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
+#define PCI_MAPREG_TYPE_MEM 0x00000000
+#define PCI_MAPREG_TYPE_IO 0x00000001
-#define PCI_MAP_IO 0x00000001
+#define PCI_MAPREG_MEM_TYPE(mr) \
+ ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
+#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
-#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffe
+#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
+#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
+#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
+
+#define PCI_MAPREG_MEM_CACHEABLE(mr) \
+ (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0)
+#define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008
+
+#define PCI_MAPREG_MEM_ADDR(mr) \
+ ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
+#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
+
+#define PCI_MAPREG_IO_ADDR(mr) \
+ ((mr) & PCI_MAPREG_IO_ADDR_MASK)
+#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe
/*
* Interrupt Configuration Register; contains interrupt pin and line.
+/* $OpenBSD: pcivar.h,v 1.6 1996/04/18 23:48:08 niklas Exp $ */
/* $NetBSD: pcivar.h,v 1.8 1995/06/18 01:26:50 cgd Exp $ */
/*
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef _DEV_PCI_PCIVAR_H_
+#define _DEV_PCI_PCIVAR_H_
+
/*
* Definitions for PCI autoconfiguration.
*
* separated into pci_machdep.h.
*/
+#include <machine/bus.h>
+
#if (alpha + i386 != 1)
ERROR: COMPILING FOR UNSUPPORTED MACHINE, OR MORE THAN ONE.
#endif
#include <i386/pci/pci_machdep.h>
#endif
+/*
+ * The maximum number of devices on a PCI bus is 32. However, some
+ * PCI chipsets (e.g. chipsets that implement 'Configuration Mechanism #2'
+ * on the i386) can't deal with that many, so let pci_machdep.h override it.
+ */
+#ifndef PCI_MAX_DEVICE_NUMBER
+#define PCI_MAX_DEVICE_NUMBER 32
+#endif
+
+/*
+ * PCI bus attach arguments.
+ */
+struct pcibus_attach_args {
+ char *pba_busname; /* XXX should be common */
+ bus_chipset_tag_t pba_bc; /* XXX should be common */
+
+ int pba_bus; /* PCI bus number */
+};
+
+/*
+ * PCI device attach arguments.
+ */
struct pci_attach_args {
- int pa_bus;
- int pa_device;
- pcitag_t pa_tag;
- pcireg_t pa_id, pa_class;
+ bus_chipset_tag_t pa_bc; /* bus chipset tag */
+
+ int pa_device;
+ int pa_function;
+ pcitag_t pa_tag;
+ pcireg_t pa_id, pa_class;
};
+/*
+ * Locators devices that attach to 'pcibus', as specified to config.
+ */
+#define pcibuscf_bus cf_loc[0]
+#define PCIBUS_UNK_BUS -1 /* wildcarded 'bus' */
+
+/*
+ * Locators for PCI devices, as specified to config.
+ */
+#define pcicf_dev cf_loc[0]
+#define PCI_UNK_DEV -1 /* wildcarded 'dev' */
+
+#define pcicf_function cf_loc[1]
+#define PCI_UNK_FUNCTION -1 /* wildcarded 'function' */
+
pcireg_t pci_conf_read __P((pcitag_t, int));
void pci_conf_write __P((pcitag_t, int, pcireg_t));
-void pci_devinfo __P((pcireg_t, pcireg_t, char *, int *));
+void pci_devinfo __P((pcireg_t, pcireg_t, int, char *));
pcitag_t pci_make_tag __P((int, int, int));
void *pci_map_int __P((pcitag_t, int, int (*)(void *), void *, char *));
int pci_map_mem __P((pcitag_t, int, vm_offset_t *, vm_offset_t *));
-int pci_attach_subdev __P((struct device *, int, int));
+#endif /* _DEV_PCI_PCIVAR_H_ */
--- /dev/null
+/* $OpenBSD: ppb.c,v 1.1 1996/04/18 23:48:09 niklas Exp $ */
+/* $NetBSD: ppb.c,v 1.4 1996/03/14 04:03:03 cgd Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * XXX NOTE:
+ * XXX PROPER OPERATION OF DEVICES BEHIND PPB'S WHICH USE INTERRUPTS
+ * XXX ON SYSTEMS OTHER THAN THE i386 IS NOT POSSIBLE AT THIS TIME.
+ * XXX There needs to be some support for 'swizzling' the interrupt
+ * XXX pin. In general, pci_map_int() has to have a different
+ * XXX interface.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/ppbreg.h>
+
+int ppbmatch __P((struct device *, void *, void *));
+void ppbattach __P((struct device *, struct device *, void *));
+
+struct cfdriver ppbcd = {
+ NULL, "ppb", ppbmatch, ppbattach, DV_DULL, sizeof(struct device)
+};
+
+static int ppbprint __P((void *, char *pnp));
+
+int
+ppbmatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct pci_attach_args *pa = aux;
+
+ /*
+ * Check the ID register to see that it's a PCI bridge.
+ * If it is, we assume that we can deal with it; it _should_
+ * work in a standardized way...
+ */
+ if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
+ PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI)
+ return (1);
+
+ return (0);
+}
+
+void
+ppbattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct pci_attach_args *pa = aux;
+ struct pcibus_attach_args pba;
+ pcireg_t data;
+ char devinfo[256];
+
+ pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
+ printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
+
+ data = pci_conf_read(pa->pa_tag, PPB_REG_BUSINFO);
+
+ if (PPB_BUSINFO_SECONDARY(data) == 0) {
+ printf("%s: not configured by system firmware\n",
+ self->dv_xname);
+ return;
+ }
+
+#if 0
+ /*
+ * XXX can't do this, because we're not given our bus number
+ * (we shouldn't need it) and we can't decompose our tag.
+ */
+
+ /* sanity check. */
+ if (pa->pa_bus != PPB_BUSINFO_PRIMARY(data))
+ panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
+ pa->pa_bus, PPB_BUSINFO_PRIMARY(data));
+#endif
+
+ /*
+ * Attach the PCI bus than hangs off of it.
+ */
+ pba.pba_busname = "pci";
+ pba.pba_bus = PPB_BUSINFO_SECONDARY(data);
+
+ config_found(self, &pba, ppbprint);
+}
+
+static int
+ppbprint(aux, pnp)
+ void *aux;
+ char *pnp;
+{
+ struct pcibus_attach_args *pba = aux;
+
+ /* only PCIs can attach to PPBs; easy. */
+ if (pnp)
+ printf("pci at %s", pnp);
+ printf(" bus %d", pba->pba_bus);
+ return (UNCONF);
+}
--- /dev/null
+/* $OpenBSD: ppbreg.h,v 1.1 1996/04/18 23:48:09 niklas Exp $ */
+/* $NetBSD: ppbreg.h,v 1.2 1996/03/14 02:35:35 cgd Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI-PCI Bridge chip register definitions and macros.
+ * Derived from information found in the ``PCI to PCI Bridge
+ * Architecture Specification, Revision 1.0, April 5, 1994.''
+ *
+ * XXX much is missing.
+ */
+
+/*
+ * Register offsets
+ */
+#define PPB_REG_BASE0 0x10 /* Base Addr Reg. 0 */
+#define PPB_REG_BASE1 0x14 /* Base Addr Reg. 1 */
+#define PPB_REG_BUSINFO 0x18 /* Bus information */
+#define PPB_REG_IOSTATUS 0x1c /* I/O base+lim & sec stat */
+#define PPB_REG_MEM 0x20 /* Memory base/limit */
+#define PPB_REG_PREFMEM 0x24 /* Pref Mem base/limit */
+#define PPB_REG_PREFBASE_HI32 0x28 /* Pref Mem base high bits */
+#define PPB_REG_PREFLIM_HI32 0x2c /* Pref Mem lim high bits */
+#define PPB_REG_IO_HI 0x30 /* I/O base+lim high bits */
+#define PPB_REG_BRIDGECONTROL PCI_INTERRUPT_REG /* bridge control register */
+
+/*
+ * Macros to extract the contents of the "Bus Info" register.
+ */
+#define PPB_BUSINFO_PRIMARY(bir) \
+ ((bir >> 0) & 0xff)
+#define PPB_BUSINFO_SECONDARY(bir) \
+ ((bir >> 8) & 0xff)
+#define PPB_BUSINFO_SUBORDINATE(bir) \
+ ((bir >> 16) & 0xff)
+#define PPB_BUSINFO_SECLAT(bir) \
+ ((bir >> 24) & 0xff)
+
+/*
+ * Routine to translate between secondary bus interrupt pin/device number and
+ * primary bus interrupt pin number.
+ */
+#define PPB_INTERRUPT_SWIZZLE(pin, device) \
+ ((((pin) + (device) - 1) % 4) + 1)
-# $NetBSD: files.pci,v 1.2 1995/04/17 17:54:35 cgd Exp $
+# $OpenBSD: files.pcmcia,v 1.2 1996/04/18 23:48:11 niklas Exp $
#
-# Config.new file and device description for machine-independent PCMCIA code.
+# Config file and device description for machine-independent PCMCIA code.
# Included by ports that need it.
+# XXX Does this comment hold?
# ports should define their own "device pcmcia" line (like the one below,
# but with the correct bus attachment).
-#define pcmciabus {[port = -1], [size = 0],
-# [iomem = -1], [iosiz = 0],
-# [irq = -1], [drq = -1]}
+device pcmcia at pcicbus: isa
-
-file dev/pcmcia/pcmcia.c pcmciabus needs-count
-file dev/pcmcia/pcmcia_conf.c pcmciabus
+file dev/pcmcia/pcmcia.c pcmcia needs-count
+file dev/pcmcia/pcmcia_conf.c pcmcia
-/* $NetBSD: ramdisk.c,v 1.4 1996/01/07 22:03:31 thorpej Exp $ */
+/* $OpenBSD: ramdisk.c,v 1.4 1996/04/18 23:47:04 niklas Exp $ */
+/* $NetBSD: ramdisk.c,v 1.5 1996/03/07 10:26:29 leo Exp $ */
/*
* Copyright (c) 1995 Gordon W. Ross, Leo Weppelman.
void *self;
void *aux;
{
+#ifdef RAMDISK_HOOKS
+ /*
+ * This external function allows for a machine dependent
+ * match function.
+ */
+ return (rd_match_hook(parent, self, aux));
+#else
return(1);
+#endif
}
static void
-/* $NetBSD: ramdisk.h,v 1.2 1995/10/26 15:46:24 gwr Exp $ */
+/* $OpenBSD: ramdisk.h,v 1.3 1996/04/18 23:47:04 niklas Exp $ */
+/* $NetBSD: ramdisk.h,v 1.3 1996/03/07 10:26:31 leo Exp $ */
/*
* Copyright (c) 1995 Gordon W. Ross
/*
* If the option RAMDISK_HOOKS is on, then these functions are
* called by the ramdisk driver to allow machine-dependent to
- * configure and/or load each ramdisk unit.
+ * match/configure and/or load each ramdisk unit.
*/
+extern int rd_match_hook __P((struct device *, void *, void *));
extern void rd_attach_hook __P((int unit, struct rd_conf *));
extern void rd_open_hook __P((int unit, struct rd_conf *));
#endif
-/* $NetBSD: raster_op.c,v 1.3 1995/11/29 22:12:58 pk Exp $ */
+/* $OpenBSD: raster_op.c,v 1.3 1996/04/18 23:48:12 niklas Exp $ */
+/* $NetBSD: raster_op.c,v 1.4 1996/03/14 19:02:30 christos Exp $ */
/*-
* Copyright (c) 1991, 1993
/* Forward routines. */
-static int raster_blit();
-
+static int raster_blit __P((struct raster *, u_int32_t *, int, int, int,
+ struct raster *, u_int32_t *, int, int, int,
+ int, int));
/* Raster operations. */
-/* $NetBSD: rcons.h,v 1.3 1995/10/05 13:17:51 pk Exp $ */
+/* $OpenBSD: rcons.h,v 1.2 1996/04/18 23:48:13 niklas Exp $ */
+/* $NetBSD: rcons.h,v 1.4 1996/03/14 19:02:32 christos Exp $ */
/*
* Copyright (c) 1992, 1993
#define FB_INESC 0x001 /* processing an escape sequence */
#define FB_STANDOUT 0x002 /* standout mode */
-/* #define FB_BOLD 0x? /* boldface mode */
+#ifdef notyet
+#define FB_BOLD 0x? /* boldface mode */
+#endif
#define FB_INVERT 0x008 /* white on black mode */
#define FB_VISBELL 0x010 /* visual bell */
#define FB_CURSOR 0x020 /* cursor is visible */
#define FB_P0 0x400 /* working on param 0 */
#define FB_P1 0x800 /* working on param 1 */
-extern void rcons_cnputc __P((int));
+
+/* rcons_kern.c */
+void rcons_cnputc __P((int));
+void rcons_bell __P((struct rconsole *));
+void rcons_init __P((struct rconsole *));
+
+/* rcons_subr.c */
+void rcons_puts __P((struct rconsole *, unsigned char *, int));
+void rcons_text __P((struct rconsole *, unsigned char *, int));
+void rcons_pctrl __P((struct rconsole *, int));
+void rcons_esc __P((struct rconsole *, int));
+void rcons_doesc __P((struct rconsole *, int));
+void rcons_cursor __P((struct rconsole *));
+void rcons_invert __P((struct rconsole *, int));
+void rcons_clear2eop __P((struct rconsole *));
+void rcons_clear2eol __P((struct rconsole *));
+void rcons_scroll __P((struct rconsole *, int));
+void rcons_delchar __P((struct rconsole *, int));
+void rcons_delline __P((struct rconsole *, int));
+void rcons_insertchar __P((struct rconsole *, int));
+void rcons_insertline __P((struct rconsole *, int));
-/* $NetBSD: rcons_kern.c,v 1.3 1995/11/29 22:09:23 pk Exp $ */
+/* $OpenBSD: rcons_kern.c,v 1.3 1996/04/18 23:48:14 niklas Exp $ */
+/* $NetBSD: rcons_kern.c,v 1.4 1996/03/14 19:02:33 christos Exp $ */
/*
* Copyright (c) 1991, 1993
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
+#include <sys/proc.h>
#include <dev/rcons/raster.h>
#include <dev/rcons/rcons.h>
#include "rcons_subr.h"
static struct rconsole *mydevicep;
+static void rcons_output __P((struct tty *));
void
rcons_cnputc(c)
rcons_output(tp)
register struct tty *tp;
{
- register int s, n, i;
+ register int s, n;
char buf[OBUFSIZ];
s = spltty();
-/* $NetBSD: kbd.c,v 1.1.1.1 1996/01/24 01:15:35 gwr Exp $ */
+/* $OpenBSD: kbd.c,v 1.2 1996/04/18 23:48:15 niklas Exp $ */
+/* $NetBSD: kbd.c,v 1.4 1996/02/29 19:32:14 gwr Exp $ */
/*
* Copyright (c) 1992, 1993
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/ioctl.h>
-/* #include <sys/tty.h> */
#include <sys/time.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
};
/* Prototypes */
-void kbd_ascii(struct tty *);
-void kbd_serial(struct tty *, void (*)(), void (*)());
-int kbd_iopen(int unit);
-void kbd_was_reset(struct kbd_softc *);
-void kbd_new_layout(struct kbd_softc *);
-void kbd_rint(int);
int kbd_docmd(struct kbd_softc *k, int cmd);
+int kbd_iopen(int unit);
+void kbd_new_layout(struct kbd_softc *k);
void kbd_output(struct kbd_softc *k, int c);
-void kbd_start_tx(struct kbd_softc *k);
void kbd_repeat(void *arg);
+void kbd_set_leds(struct kbd_softc *k, int leds);
+void kbd_start_tx(struct kbd_softc *k);
+void kbd_update_leds(struct kbd_softc *k);
+void kbd_was_reset(struct kbd_softc *k);
extern void kd_input(int ascii);
int reset, s, tconst;
cf = k->k_dev.dv_cfdata;
- kbd_unit = cf->cf_unit;
+ kbd_unit = k->k_dev.dv_unit;
channel = args->channel;
cs = &zsc->zsc_cs[channel];
cs->cs_private = k;
/* Not the console; may need reset. */
reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
- ZS_WRITE(cs, 9, reset);
+ zs_write_reg(cs, 9, reset);
}
/* These are OK as set by zscc: WR3, WR4, WR5 */
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
break;
case KIOCSLED:
- error = kbd_set_leds(k, data);
+ error = kbd_drain_tx(k);
+ kbd_set_leds(k, *(int *)data);
break;
case KIOCGLED:
*/
if (KEY_UP(c))
km = ks->kbd_k.k_release;
- else {
- if (ks->kbd_modbits & KBMOD_CTRL_MASK)
- km = ks->kbd_k.k_control;
- else {
- if (ks->kbd_modbits & KBMOD_SHIFT_MASK)
- km = ks->kbd_k.k_shifted;
- else
- km = ks->kbd_k.k_normal;
- }
- }
+ else if (ks->kbd_modbits & KBMOD_CTRL_MASK)
+ km = ks->kbd_k.k_control;
+ else if (ks->kbd_modbits & KBMOD_SHIFT_MASK)
+ km = ks->kbd_k.k_shifted;
+ else
+ km = ks->kbd_k.k_normal;
+
if (km == NULL) {
/*
* Do not know how to translate yet.
* We will find out when a RESET comes along.
*/
- keysym = KEYSYM_NOP;
- } else
- keysym = km->keymap[KEY_CODE(c)];
+ return (KEYSYM_NOP);
+ }
+ keysym = km->keymap[KEY_CODE(c)];
+
+ /*
+ * Post-processing for Caps-lock
+ */
+ if ((ks->kbd_modbits & (1 << KBMOD_CAPSLOCK)) &&
+ (KEYSYM_CLASS(keysym) == KEYSYM_ASCII) )
+ {
+ if (('a' <= keysym) && (keysym <= 'z'))
+ keysym -= ('a' - 'A');
+ }
+
+ /*
+ * Post-processing for Num-lock
+ */
+ if ((ks->kbd_modbits & (1 << KBMOD_NUMLOCK)) &&
+ (KEYSYM_CLASS(keysym) == KEYSYM_FUNC) )
+ {
+ keysym = kbd_numlock_map[keysym & 0x3F];
+ }
return (keysym);
}
register int keysym;
{
struct kbd_state *ks = &k->k_state;
- register int class, data;
+ register int data;
- class = KEYSYM_CLASS(keysym);
- switch (class) {
+ switch (KEYSYM_CLASS(keysym)) {
case KEYSYM_ASCII:
data = KEYSYM_DATA(keysym);
case KEYSYM_INVMOD:
data = 1 << (keysym & 0x1F);
ks->kbd_modbits ^= data;
+ kbd_update_leds(k);
break;
case KEYSYM_ALL_UP:
put = k->k_rbput;
/* Read the input data ASAP. */
- c = *(cs->cs_reg_data);
- ZS_DELAY();
+ c = zs_read_data(cs);
/* Save the status register too. */
- rr1 = ZS_READ(cs, 1);
+ rr1 = zs_read_reg(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
/*
k = cs->cs_private;
- *(cs->cs_reg_csr) = ZSWR0_RESET_TXINT;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_TXINT);
k->k_intr_flags |= INTR_TX_EMPTY;
/* Ask for softint() call. */
k = cs->cs_private;
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
-
- *(cs->cs_reg_csr) = ZSWR0_RESET_STATUS;
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
+ zs_write_csr(cs, ZSWR0_RESET_STATUS);
#if 0
if (rr0 & ZSRR0_BREAK) {
/* Need splzs to avoid interruption of the delay. */
(void) splzs();
- *(cs->cs_reg_data) = c;
- ZS_DELAY();
+ zs_write_data(cs, c);
out:
splx(s);
}
-int
-kbd_set_leds(k, data)
+void
+kbd_set_leds(k, new_leds)
struct kbd_softc *k;
- caddr_t data;
+ int new_leds;
{
struct kbd_state *ks = &k->k_state;
- int error, s;
- char new_leds;
+ int s;
- error = 0;
- new_leds = *(char*)data;
s = spltty();
/* Don't send unless state changes. */
if (ks->kbd_id < 4)
goto out;
- error = kbd_drain_tx(k);
kbd_output(k, KBD_CMD_SETLED);
kbd_output(k, new_leds);
kbd_start_tx(k);
out:
splx(s);
- return(error);
+}
+
+void
+kbd_update_leds(k)
+ struct kbd_softc *k;
+{
+ struct kbd_state *ks = &k->k_state;
+ register char leds;
+
+ leds = ks->kbd_leds;
+ leds &= ~(LED_CAPS_LOCK|LED_NUM_LOCK);
+
+ if (ks->kbd_modbits & (1 << KBMOD_CAPSLOCK))
+ leds |= LED_CAPS_LOCK;
+ if (ks->kbd_modbits & (1 << KBMOD_NUMLOCK))
+ leds |= LED_NUM_LOCK;
+
+ kbd_set_leds(k, leds);
}
kbd_start_tx(k);
return (0);
}
-
-/* $NetBSD: kbd_tables.c,v 1.1.1.1 1996/01/24 01:15:35 gwr Exp $ */
+/* $OpenBSD: kbd_tables.c,v 1.2 1996/04/18 23:48:16 niklas Exp $ */
+/* $NetBSD: kbd_tables.c,v 1.2 1996/02/29 19:32:18 gwr Exp $ */
/*
* Copyright (c) 1996 Gordon W. Ross
{ 0x1b, '[', 'C', 0 }, /* Right */
};
+/*
+ * The "NumLock" map, which is used to remap
+ * function keysyms when NumLock is on.
+ */
+unsigned short kbd_numlock_map[64] = {
+ /* KEYSYM_FUNC_L: Identity map */
+ 0x600, 0x601, 0x602, 0x603, 0x604, 0x605, 0x606, 0x607,
+ 0x608, 0x609, 0x60a, 0x60b, 0x60c, 0x60d, 0x60e, 0x60f,
+
+ /* KEYSYM_FUNC_R: remap to numbers... */
+ 0x610, 0x611, 0x612,
+ '=', '/', '*',
+ '7', '8', '9',
+ '4', '5', '6',
+ '1', '2', '3',
+ 0x61f,
+
+ /* KEYSYM_FUNC_F: Identity map */
+ 0x620, 0x621, 0x622, 0x623, 0x624, 0x625, 0x626, 0x627,
+ 0x628, 0x629, 0x62a, 0x62b, 0x62c, 0x62d, 0x62e, 0x62f,
+
+ /* KEYSYM_FUNC_N: remap just a few... */
+ 0x630, 0x631, 0x632, 0x633, 0x634, 0x635, 0x636, '0',
+ 0x638, '.', '\r', 0x63b, 0x63c, '+', '-', 0x63f,
+};
+
+
/*
* Keyboard descriptions for each type.
*/
-/* $NetBSD: kbd_tables.h,v 1.1.1.1 1996/01/24 01:15:35 gwr Exp $ */
+/* $OpenBSD: kbd_tables.h,v 1.2 1996/04/18 23:48:17 niklas Exp $ */
+/* $NetBSD: kbd_tables.h,v 1.3 1996/02/29 19:37:53 gwr Exp $ */
/*
* Copyright (c) 1996 Gordon W. Ross
struct keymap *k_control; /* Ctrl is down */
struct keymap *k_normal; /* No shifts */
struct keymap *k_shifted; /* Shift is down */
- /* capslock? numlock? */
};
extern char kbd_stringtab[16][10];
+extern unsigned short kbd_numlock_map[64];
+
extern struct keyboard * keyboards[];
extern int kbd_max_type;
#define KBD_MIN_TYPE 2
-/* $NetBSD: ms.c,v 1.1.1.1 1996/01/24 01:15:35 gwr Exp $ */
+/* $OpenBSD: ms.c,v 1.2 1996/04/18 23:48:18 niklas Exp $ */
+/* $NetBSD: ms.c,v 1.3 1996/02/19 04:36:15 gwr Exp $ */
/*
* Copyright (c) 1992, 1993
int reset, s, tconst;
cf = ms->ms_dev.dv_cfdata;
- ms_unit = cf->cf_unit;
+ ms_unit = ms->ms_dev.dv_unit;
channel = args->channel;
cs = &zsc->zsc_cs[channel];
cs->cs_private = ms;
/* May need reset... */
reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
- ZS_WRITE(cs, 9, reset);
+ zs_write_reg(cs, 9, reset);
/* These are OK as set by zscc: WR3, WR4, WR5 */
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_preg[12] = tconst;
put = ms->ms_rbput;
/* Read the input data ASAP. */
- c = *(cs->cs_reg_data);
- ZS_DELAY();
+ c = zs_read_data(cs);
/* Save the status register too. */
- rr1 = ZS_READ(cs, 1);
+ rr1 = zs_read_reg(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
ms->ms_rbuf[put] = (c << 8) | rr1;
ms = cs->cs_private;
- *(cs->cs_reg_csr) = ZSWR0_RESET_TXINT;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_TXINT);
ms->ms_intr_flags |= INTR_TX_EMPTY;
/* Ask for softint() call. */
ms = cs->cs_private;
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
-
- *(cs->cs_reg_csr) = ZSWR0_RESET_STATUS;
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
+ zs_write_csr(cs, ZSWR0_RESET_STATUS);
ms->ms_intr_flags |= INTR_ST_CHECK;
/* Ask for softint() call. */
--- /dev/null
+# $OpenBSD: Makefile,v 1.1 1996/04/18 23:48:19 niklas Exp $
+# $NetBSD: Makefile,v 1.1 1996/03/02 01:16:47 cgd Exp $
+
+AWK= awk
+
+tcdevs.h tcdevs_data.h: tcdevs devlist2h.awk
+ /bin/rm -f tcdevs.h tcdevs_data.h
+ ${AWK} -f devlist2h.awk tcdevs
--- /dev/null
+#! /usr/bin/awk -f
+# $OpenBSD: devlist2h.awk,v 1.1 1996/04/18 23:48:20 niklas Exp $
+# $NetBSD: devlist2h.awk,v 1.2 1996/03/05 23:15:05 cgd Exp $
+#
+# Copyright (c) 1995, 1996 Christopher G. Demetriou
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# 3. All advertising materials mentioning features or use of this software
+# must display the following acknowledgement:
+# This product includes software developed by Christopher G. Demetriou.
+# 4. The name of the author may not be used to endorse or promote products
+# derived from this software without specific prior written permission
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+BEGIN {
+ nproducts = 0
+ dfile="tcdevs_data.h"
+ hfile="tcdevs.h"
+}
+NR == 1 {
+ VERSION = $0
+ gsub("\\$", "", VERSION)
+
+ printf("/*\n") > dfile
+ printf(" * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n") \
+ > dfile
+ printf(" *\n") > dfile
+ printf(" * generated from:\n") > dfile
+ printf(" *\t%s\n", VERSION) > dfile
+ printf(" */\n") > dfile
+
+ printf("/*\n") > hfile
+ printf(" * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n") \
+ > hfile
+ printf(" *\n") > hfile
+ printf(" * generated from:\n") > hfile
+ printf(" *\t%s\n", VERSION) > hfile
+ printf(" */\n") > hfile
+
+ next
+}
+$1 == "device" {
+ ndevices++
+
+ devices[ndevices, 0] = $2; # devices id
+ devices[ndevices, 1] = $2; # C identifier for device
+ gsub("-", "_", devices[ndevices, 1]);
+
+ devices[ndevices, 2] = $3; /* driver name */
+
+ printf("\n") > hfile
+ printf("#define\tTC_DEVICE_%s\t\"%s\"\n", devices[ndevices, 1],
+ devices[ndevices, 2]) > hfile
+
+ printf("#define\tTC_DESCRIPTION_%s\t\"", devices[ndevices, 1]) > hfile
+
+ f = 4;
+ i = 3;
+
+ # comments
+ ocomment = oparen = 0
+ if (f <= NF) {
+ ocomment = 1;
+ }
+ while (f <= NF) {
+ if ($f == "#") {
+ printf("(") > hfile
+ oparen = 1
+ f++
+ continue
+ }
+ if (oparen) {
+ printf("%s", $f) > hfile
+ if (f < NF)
+ printf(" ") > hfile
+ f++
+ continue
+ }
+ devices[ndevices, i] = $f
+ printf("%s", devices[ndevices, i]) > hfile
+ if (f < NF)
+ printf(" ") > hfile
+ i++; f++;
+ }
+ if (oparen)
+ printf(")") > hfile
+ if (ocomment)
+ printf("\"") > hfile
+ printf("\n") > hfile
+
+ next
+}
+{
+ if ($0 == "")
+ blanklines++
+ if (blanklines < 2)
+ print $0 > hfile
+ if (blanklines < 2)
+ print $0 > dfile
+}
+END {
+ # print out the match tables
+
+ printf("\n") > dfile
+
+ printf("struct tc_knowndev tc_knowndevs[] = {\n") > dfile
+ for (i = 1; i <= ndevices; i++) {
+ printf("\t{\n") > dfile
+ printf("\t \"%-8s\",\n", devices[i, 0]) \
+ > dfile
+ printf("\t TC_DEVICE_%s,\n", devices[i, 1]) \
+ > dfile
+ printf("\t TC_DESCRIPTION_%s,\n", devices[i, 1]) \
+ > dfile
+
+ printf("\t},\n") > dfile
+ }
+ printf("\t{ NULL, NULL, NULL, }\n") > dfile
+ printf("};\n") > dfile
+}
-# $NetBSD: files.tc,v 1.1 1995/12/20 00:54:18 cgd Exp $
+# $OpenBSD: files.tc,v 1.2 1996/04/18 23:48:21 niklas Exp $
+# $NetBSD: files.tc,v 1.2 1996/02/27 22:00:04 cgd Exp $
#
# Config.new file and device description for machine-independent
# TurboChannel code. Included by ports that need it.
-# ports should define "chipsets" which have the tcbus attribute
-# and attach their TC bus subdevices
-
-define tcbus { }
-
device tc at tcbus {[slot = -1], [offset = -1]}
file dev/tc/tc.c tc needs-flag
-/* $NetBSD: if_le.c,v 1.1 1995/12/20 00:52:16 cgd Exp $ */
+/* $OpenBSD: if_le.c,v 1.2 1996/04/18 23:48:21 niklas Exp $ */
+/* $NetBSD: if_le.c,v 1.3 1996/02/26 23:38:38 cgd Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
#define CAN_HAVE_TC 1
#endif
#ifdef pmax
-/* XXX PMAX BASEBOARD OPTIONS? */
#define CAN_HAVE_IOASIC 1
#define CAN_HAVE_TC 1
+#define CAN_HAVE_MAINBUS 1
#endif
#include "bpfilter.h"
-/* XXX PMAX BASEBOARD OPTIONS? */
+#ifdef CAN_HAVE_MAINBUS
+/*XXX TEST FOR KN01 OR MIPSFAIR? */
+#endif
#ifdef CAN_HAVE_TC
#include "tc.h"
#endif
#include <machine/autoconf.h>
-/* XXX PMAX BASEBOARD OPTIONS? */
#if CAN_HAVE_TC && (NTC > 0)
#include <dev/tc/tcvar.h>
#endif
#if CAN_HAVE_IOASIC && (NIOASIC > 0)
#include <dev/tc/ioasicvar.h>
#endif
+#if CAN_HAVE_MAINBUS
+#include <pmax/pmax/kn01.h>
+extern struct cfdriver mainbuscd; /* XXX */
+#endif
#include <dev/tc/if_levar.h>
#include <dev/ic/am7990reg.h>
void *match, *aux;
{
- /* XXX VARIOUS PMAX BASEBOARD CASES? */
#if CAN_HAVE_IOASIC && (NIOASIC > 0)
if (parent->dv_cfdata->cf_driver == &ioasiccd) {
struct ioasicdev_attach_args *d = aux;
if (parent->dv_cfdata->cf_driver == &tccd) {
struct tcdev_attach_args *d = aux;
- if (!tc_submatch(match, aux))
- return (0);
if (strncmp("PMAD-AA ", d->tcda_modname, TC_ROM_LLEN) &&
strncmp("PMAD-BA ", d->tcda_modname, TC_ROM_LLEN))
return (0);
} else
#endif /* TC */
+#if CAN_HAVE_MAINBUS /* XXX TEST FOR KN01 OR MIPSFAIR? */
+ if (parent->dv_cfdata->cf_driver == &mainbuscd) {
+ /* XXX VARIOUS PMAX BASEBOARD CASES? */
+ } else
+#endif /* MAINBUS */
return (0);
return (1);
u_char *cp; /* pointer to MAC address */
int i;
- /* XXX VARIOUS PMAX BASEBOARD CASES? */
#if CAN_HAVE_IOASIC && (NIOASIC > 0)
if (parent->dv_cfdata->cf_driver == &ioasiccd) {
struct ioasicdev_attach_args *d = aux;
ioasic_lance_dma_setup(le_iomem); /* XXX more thought */
ie_fn = ioasic_intr_establish;
+ sc->sc_cookie = (void*)d->iada_cookie;
} else
#endif /* IOASIC */
-#if CAN_HAVE_TC && (NTC > 0) /* XXX KN02 BASEBOARD CASE? */
+#if CAN_HAVE_TC && (NTC > 0)
if (parent->dv_cfdata->cf_driver == &tccd) {
struct tcdev_attach_args *d = aux;
/*
- * It's on the turbochannel proper.
+ * It's on the turbochannel proper, or a kn02
+ * baseboard implementation of a TC option card.
*/
sc->sc_r1 = (struct lereg1 *)(d->tcda_addr + LE_OFFSET_LANCE);
sc->sc_mem = (void *)(d->tcda_addr + LE_OFFSET_RAM);
sc->sc_copyfrombuf = copyfrombuf_contig;
sc->sc_zerobuf = zerobuf_contig;
- /* XXX DMA setup fn? */
+ sc->sc_cookie = d->tcda_cookie;
+ /*
+ * TC lance boards have onboard SRAM buffers. DMA
+ * between the onbard RAM and main memory is not possible,
+ * so DMA setup is not required.
+ */
ie_fn = tc_intr_establish;
} else
#endif /* TC */
+#if CAN_HAVE_MAINBUS /* XXX TEST FOR KN01 OR MIPSFAIR? */
+ if (parent->dv_cfdata->cf_driver == &mainbuscd) {
+ struct confargs *ca = aux;
+
+ /*
+ * It's on the baseboeard, with a dedicated interrupt line.
+ */
+/*XXX*/ sc->sc_r1 = (struct lereg1 *)(ca->ca_addr);
+/*XXX*/ sc->sc_mem = (void *)TC_PHYS_TO_UNCACHED(0x19000000);
+/*XXX*/ cp = (u_char *)(TC_PHYS_TO_UNCACHED(KN01_SYS_CLOCK) + 1);
+
+ sc->sc_copytodesc = copytobuf_gap2;
+ sc->sc_copyfromdesc = copyfrombuf_gap2;
+ sc->sc_copytobuf = copytobuf_gap2;
+ sc->sc_copyfrombuf = copyfrombuf_gap2;
+ sc->sc_zerobuf = zerobuf_gap2;
+
+ sc->sc_cookie = (void *)ca->ca_slotpri; /*XXX more thought */
+ /* XXX BASEBOARD INTERRUPT ESTABLISH FUNCTION? */
+ } else
+#endif /* MAINBUS */
+
panic("leattach: can't be here");
sc->sc_conf3 = 0;
-/* $NetBSD: tc.c,v 1.1 1995/12/20 00:48:32 cgd Exp $ */
+/* $OpenBSD: tc.c,v 1.2 1996/04/18 23:48:22 niklas Exp $ */
+/* $NetBSD: tc.c,v 1.10 1996/03/05 23:15:07 cgd Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
#include <dev/tc/tcreg.h>
#include <dev/tc/tcvar.h>
+#include <dev/tc/tcdevs.h>
struct tc_softc {
struct device sc_dv;
+ int sc_speed;
int sc_nslots;
struct tc_slotdesc *sc_slots;
{ NULL, "tc", tcmatch, tcattach, DV_DULL, sizeof (struct tc_softc) };
int tcprint __P((void *, char *));
+int tcsubmatch __P((struct device *, void *, void *));
int tc_checkslot __P((tc_addr_t, char *));
+void tc_devinfo __P((const char *, char *));
int
tcmatch(parent, cfdata, aux)
void *cfdata;
void *aux;
{
+ struct cfdata *cf = cfdata;
+ struct tcbus_attach_args *tba = aux;
+
+ if (strcmp(tba->tba_busname, cf->cf_driver->cd_name))
+ return (0);
+
+ /* XXX check other indicators */
return (1);
}
void *aux;
{
struct tc_softc *sc = (struct tc_softc *)self;
- struct tc_attach_args *tc = aux;
- struct tcdev_attach_args tcdev;
+ struct tcbus_attach_args *tba = aux;
+ struct tc_attach_args ta;
const struct tc_builtin *builtin;
struct tc_slotdesc *slot;
tc_addr_t tcaddr;
+ void *match;
int i;
- printf("\n");
+ printf("%s MHz clock\n",
+ tba->tba_speed == TC_SPEED_25_MHZ ? "25" : "12.5");
/*
* Save important CPU/chipset information.
*/
- sc->sc_nslots = tc->tca_nslots;
- sc->sc_slots = tc->tca_slots;
- sc->sc_intr_establish = tc->tca_intr_establish;
- sc->sc_intr_disestablish = tc->tca_intr_disestablish;
+ sc->sc_speed = tba->tba_speed;
+ sc->sc_nslots = tba->tba_nslots;
+ sc->sc_slots = tba->tba_slots;
+ sc->sc_intr_establish = tba->tba_intr_establish;
+ sc->sc_intr_disestablish = tba->tba_intr_disestablish;
/*
* Try to configure each built-in device
*/
- for (i = 0; i < tc->tca_nbuiltins; i++) {
- builtin = &tc->tca_builtins[i];
+ for (i = 0; i < tba->tba_nbuiltins; i++) {
+ builtin = &tba->tba_builtins[i];
/* sanity check! */
if (builtin->tcb_slot > sc->sc_nslots)
/*
* Set up the device attachment information.
*/
- strncpy(tcdev.tcda_modname, builtin->tcb_modname, TC_ROM_LLEN);
- tcdev.tcda_modname[TC_ROM_LLEN] = '\0';
- tcdev.tcda_slot = builtin->tcb_slot;
- tcdev.tcda_offset = builtin->tcb_offset;
- tcdev.tcda_addr = tcaddr;
- tcdev.tcda_cookie = builtin->tcb_cookie;
+ strncpy(ta.ta_modname, builtin->tcb_modname, TC_ROM_LLEN);
+ ta.ta_modname[TC_ROM_LLEN] = '\0';
+ ta.ta_slot = builtin->tcb_slot;
+ ta.ta_offset = builtin->tcb_offset;
+ ta.ta_addr = tcaddr;
+ ta.ta_cookie = builtin->tcb_cookie;
+ ta.ta_busspeed = sc->sc_speed;
/*
* Mark the slot as used, so we don't check it later.
/*
* Attach the device.
*/
- config_found(self, &tcdev, tcprint);
+ config_found_sm(self, &ta, tcprint, tcsubmatch);
}
/*
tcaddr = slot->tcs_addr;
if (tc_badaddr(tcaddr))
continue;
- if (tc_checkslot(tcaddr, tcdev.tcda_modname) == 0)
+ if (tc_checkslot(tcaddr, ta.ta_modname) == 0)
continue;
/*
* Set up the rest of the attachment information.
*/
- tcdev.tcda_slot = i;
- tcdev.tcda_offset = 0;
- tcdev.tcda_addr = tcaddr;
- tcdev.tcda_cookie = slot->tcs_cookie;
+ ta.ta_slot = i;
+ ta.ta_offset = 0;
+ ta.ta_addr = tcaddr;
+ ta.ta_cookie = slot->tcs_cookie;
/*
* Mark the slot as used.
/*
* Attach the device.
*/
- config_found(self, &tcdev, tcprint);
+ config_found_sm(self, &ta, tcprint, tcsubmatch);
}
}
void *aux;
char *pnp;
{
- struct tcdev_attach_args *tcdev = aux;
+ struct tc_attach_args *ta = aux;
+ char devinfo[256];
- if (pnp)
- printf("%s at %s", tcdev->tcda_modname, pnp); /* XXX */
- printf(" slot %d offset 0x%lx", tcdev->tcda_slot,
- (long)tcdev->tcda_offset);
- return (UNCONF);
+ if (pnp) {
+ tc_devinfo(ta->ta_modname, devinfo);
+ printf("%s at %s", devinfo, pnp);
+ }
+ printf(" slot %d offset 0x%lx", ta->ta_slot,
+ (long)ta->ta_offset);
+ return (UNCONF);
}
-int
-tc_submatch(match, d)
- struct cfdata *match;
- struct tcdev_attach_args *d;
+int
+tcsubmatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
{
+ struct cfdata *cf = match;
+ struct tc_attach_args *d = aux;
- return (((match->tccf_slot == d->tcda_slot) ||
- (match->tccf_slot == TCCF_SLOT_UNKNOWN)) &&
- ((match->tccf_offset == d->tcda_offset) ||
- (match->tccf_offset == TCCF_OFFSET_UNKNOWN)));
+ if ((cf->tccf_slot != TCCF_SLOT_UNKNOWN) &&
+ (cf->tccf_slot != d->ta_slot))
+ return 0;
+ if ((cf->tccf_offset != TCCF_SLOT_UNKNOWN) &&
+ (cf->tccf_offset != d->ta_offset))
+ return 0;
+
+ return ((*cf->cf_driver->cd_match)(parent, match, aux));
}
(*sc->sc_intr_disestablish)(sc->sc_dv.dv_parent, cookie);
}
+
+#ifdef TCVERBOSE
+/*
+ * Descriptions of of known devices.
+ */
+struct tc_knowndev {
+ const char *id, *driver, *description;
+};
+
+#include <dev/tc/tcdevs_data.h>
+#endif /* TCVERBOSE */
+
+void
+tc_devinfo(id, cp)
+ const char *id;
+ char *cp;
+{
+ const char *driver, *description;
+#ifdef TCVERBOSE
+ struct tc_knowndev *tdp;
+ int match;
+ const char *unmatched = "unknown ";
+#else
+ const char *unmatched = "";
+#endif
+
+ driver = NULL;
+ description = id;
+
+#ifdef TCVERBOSE
+ /* find the device in the table, if possible. */
+ tdp = tc_knowndevs;
+ while (tdp->id != NULL) {
+ /* check this entry for a match */
+ match = !strcmp(tdp->id, id);
+ if (match) {
+ driver = tdp->driver;
+ description = tdp->description;
+ break;
+ }
+ tdp++;
+ }
+#endif
+
+ if (driver == NULL)
+ cp += sprintf(cp, "%sdevice %s", unmatched, id);
+ else
+ cp += sprintf(cp, "%s (%s)", driver, description);
+}
--- /dev/null
+$OpenBSD: tcdevs,v 1.1 1996/04/18 23:48:23 niklas Exp $
+/* $NetBSD: tcdevs,v 1.3 1996/03/05 23:15:59 cgd Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+device KZTSA-AA tza TZA FWD SCSI
+device PMAD-AA le LANCE Ethernet
+device PMAF-AA fza FZA FDDI
+device PMAG-AA mfb Monochrome Frame Buffer
+device PMAG-BA cfb Color Frame Buffer
+device PMAG-CA ga 2D Graphic Board
+device PMAG-DA gq 3D Graphic Board (LM)
+device PMAG-FA gq 3D Graphic Board (HE)
+# the following entry may be incorrect
+device PMAG-DV xcfb Maxine Color Frame Buffer
+device PMAGB-BA sfb Smart Frame Buffer
+device PMAZ-AA asc 53c94 SCSI
+device T3PKT tt DECWRL Turbochannel T3
+device T1D4PKT ds DECWRL Turbochannel T1
+device FORE_ATM fa Fore TCA-100 ATM
--- /dev/null
+/*
+ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * generated from:
+ * OpenBSD
+ */
+/* $NetBSD: tcdevs,v 1.3 1996/03/05 23:15:59 cgd Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define TC_DEVICE_KZTSA_AA "tza"
+#define TC_DESCRIPTION_KZTSA_AA "TZA FWD SCSI"
+
+#define TC_DEVICE_PMAD_AA "le"
+#define TC_DESCRIPTION_PMAD_AA "LANCE Ethernet"
+
+#define TC_DEVICE_PMAF_AA "fza"
+#define TC_DESCRIPTION_PMAF_AA "FZA FDDI"
+
+#define TC_DEVICE_PMAG_AA "mfb"
+#define TC_DESCRIPTION_PMAG_AA "Monochrome Frame Buffer"
+
+#define TC_DEVICE_PMAG_BA "cfb"
+#define TC_DESCRIPTION_PMAG_BA "Color Frame Buffer"
+
+#define TC_DEVICE_PMAG_CA "ga"
+#define TC_DESCRIPTION_PMAG_CA "2D Graphic Board"
+
+#define TC_DEVICE_PMAG_DA "gq"
+#define TC_DESCRIPTION_PMAG_DA "3D Graphic Board (LM)"
+
+#define TC_DEVICE_PMAG_FA "gq"
+#define TC_DESCRIPTION_PMAG_FA "3D Graphic Board (HE)"
+
+#define TC_DEVICE_PMAG_DV "xcfb"
+#define TC_DESCRIPTION_PMAG_DV "Maxine Color Frame Buffer"
+
+#define TC_DEVICE_PMAGB_BA "sfb"
+#define TC_DESCRIPTION_PMAGB_BA "Smart Frame Buffer"
+
+#define TC_DEVICE_PMAZ_AA "asc"
+#define TC_DESCRIPTION_PMAZ_AA "53c94 SCSI"
+
+#define TC_DEVICE_T3PKT "tt"
+#define TC_DESCRIPTION_T3PKT "DECWRL Turbochannel T3"
+
+#define TC_DEVICE_T1D4PKT "ds"
+#define TC_DESCRIPTION_T1D4PKT "DECWRL Turbochannel T1"
+
+#define TC_DEVICE_FORE_ATM "fa"
+#define TC_DESCRIPTION_FORE_ATM "Fore TCA-100 ATM"
--- /dev/null
+/*
+ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * generated from:
+ * OpenBSD
+ */
+/* $NetBSD: tcdevs,v 1.3 1996/03/05 23:15:59 cgd Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+struct tc_knowndev tc_knowndevs[] = {
+ {
+ "KZTSA-AA",
+ TC_DEVICE_KZTSA_AA,
+ TC_DESCRIPTION_KZTSA_AA,
+ },
+ {
+ "PMAD-AA ",
+ TC_DEVICE_PMAD_AA,
+ TC_DESCRIPTION_PMAD_AA,
+ },
+ {
+ "PMAF-AA ",
+ TC_DEVICE_PMAF_AA,
+ TC_DESCRIPTION_PMAF_AA,
+ },
+ {
+ "PMAG-AA ",
+ TC_DEVICE_PMAG_AA,
+ TC_DESCRIPTION_PMAG_AA,
+ },
+ {
+ "PMAG-BA ",
+ TC_DEVICE_PMAG_BA,
+ TC_DESCRIPTION_PMAG_BA,
+ },
+ {
+ "PMAG-CA ",
+ TC_DEVICE_PMAG_CA,
+ TC_DESCRIPTION_PMAG_CA,
+ },
+ {
+ "PMAG-DA ",
+ TC_DEVICE_PMAG_DA,
+ TC_DESCRIPTION_PMAG_DA,
+ },
+ {
+ "PMAG-FA ",
+ TC_DEVICE_PMAG_FA,
+ TC_DESCRIPTION_PMAG_FA,
+ },
+ {
+ "PMAG-DV ",
+ TC_DEVICE_PMAG_DV,
+ TC_DESCRIPTION_PMAG_DV,
+ },
+ {
+ "PMAGB-BA",
+ TC_DEVICE_PMAGB_BA,
+ TC_DESCRIPTION_PMAGB_BA,
+ },
+ {
+ "PMAZ-AA ",
+ TC_DEVICE_PMAZ_AA,
+ TC_DESCRIPTION_PMAZ_AA,
+ },
+ {
+ "T3PKT ",
+ TC_DEVICE_T3PKT,
+ TC_DESCRIPTION_T3PKT,
+ },
+ {
+ "T1D4PKT ",
+ TC_DEVICE_T1D4PKT,
+ TC_DESCRIPTION_T1D4PKT,
+ },
+ {
+ "FORE_ATM",
+ TC_DEVICE_FORE_ATM,
+ TC_DESCRIPTION_FORE_ATM,
+ },
+ { NULL, NULL, NULL, }
+};
-/* $NetBSD: tcvar.h,v 1.1 1995/12/20 00:48:36 cgd Exp $ */
+/* $OpenBSD: tcvar.h,v 1.2 1996/04/18 23:48:24 niklas Exp $ */
+/* $NetBSD: tcvar.h,v 1.3 1996/02/27 01:37:33 cgd Exp $ */
/*
* Copyright (c) 1995 Carnegie-Mellon University.
/*
* Arguments used to attach TurboChannel busses.
*/
-struct tc_attach_args {
- u_int tca_nslots;
- struct tc_slotdesc *tca_slots;
-
- u_int tca_nbuiltins;
- const struct tc_builtin *tca_builtins;
-
- void (*tca_intr_establish) __P((struct device *, void *,
+struct tcbus_attach_args {
+ char *tba_busname; /* XXX should be common */
+
+ /* Bus information */
+ u_int tba_speed; /* see TC_SPEED_* below */
+ u_int tba_nslots;
+ struct tc_slotdesc *tba_slots;
+ u_int tba_nbuiltins;
+ const struct tc_builtin *tba_builtins;
+
+
+ /* TC bus resource management; XXX will move elsewhere eventually. */
+ void (*tba_intr_establish) __P((struct device *, void *,
tc_intrlevel_t, int (*)(void *), void *));
- void (*tca_intr_disestablish) __P((struct device *, void *));
+ void (*tba_intr_disestablish) __P((struct device *, void *));
};
/*
* Arguments used to attach TurboChannel devices.
*/
-struct tcdev_attach_args {
- char tcda_modname[TC_ROM_LLEN+1];
- u_int tcda_slot;
- tc_offset_t tcda_offset;
- tc_addr_t tcda_addr;
- void *tcda_cookie;
+struct tc_attach_args {
+ char ta_modname[TC_ROM_LLEN+1];
+ u_int ta_slot;
+ tc_offset_t ta_offset;
+ tc_addr_t ta_addr;
+ void *ta_cookie;
+ u_int ta_busspeed; /* see TC_SPEED_* below */
};
/*
* code to the TurboChannel bus driver.
*/
struct tc_slotdesc {
- tc_addr_t tcs_addr;
- void *tcs_cookie;
- int tcs_used;
+ tc_addr_t tcs_addr;
+ void *tcs_cookie;
+ int tcs_used;
};
/*
* machine-dependent code to the TurboChannel bus driver.
*/
struct tc_builtin {
- char *tcb_modname;
- u_int tcb_slot;
- tc_offset_t tcb_offset;
- void *tcb_cookie;
+ char *tcb_modname;
+ u_int tcb_slot;
+ tc_offset_t tcb_offset;
+ void *tcb_cookie;
};
/*
#define TCCF_SLOT_UNKNOWN -1
#define TCCF_OFFSET_UNKNOWN -1
+/*
+ * Miscellaneous definitions.
+ */
+#define TC_SPEED_12_5_MHZ 0 /* 12.5MHz TC bus */
+#define TC_SPEED_25_MHZ 1 /* 25MHz TC bus */
+
/*
* The TurboChannel bus cfdriver, so that subdevices can more
* easily tell what bus they're on.
projects / openbsd / commitdiff