Implement software control for the internal delays of the RTL8211F PHY.

Since we need to retain the hardware/firmware configuration of the delays
in most existing hardware that uses rgephy(4) (such as PCIe NICs), add a
bew MIIF_SETDELAY flag that controls the software configuration of the
delays.

ok dlg@, jsg@

diff --git a/sys/dev/mii/miivar.h b/sys/dev/mii/miivar.h
index 3d55c3c..e3f5061 100644 (file)
--- a/sys/dev/mii/miivar.h
+++ b/sys/dev/mii/miivar.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: miivar.h,v 1.36 2020/11/03 21:49:42 patrick Exp $     */
+/*     $OpenBSD: miivar.h,v 1.37 2023/04/05 10:45:07 kettenis Exp $    */
 /*     $NetBSD: miivar.h,v 1.17 2000/03/06 20:56:57 thorpej Exp $      */
 
 /*-
@@ -152,9 +152,10 @@ typedef struct mii_softc mii_softc_t;
 #define        MIIF_DOPAUSE    0x0100          /* advertise PAUSE capability */
 #define        MIIF_IS_HPNA    0x0200          /* is a HomePNA device */
 #define        MIIF_FORCEANEG  0x0400          /* force autonegotiation */
-#define        MIIF_RXID       0x0800          /* add Rx delay */
-#define        MIIF_TXID       0x1000          /* add Tx delay */
-#define        MIIF_SGMII      0x2000          /* MAC to PHY interface is SGMII */
+#define        MIIF_SETDELAY   0x0800          /* set internal delay */
+#define        MIIF_RXID       0x1000          /* add Rx delay */
+#define        MIIF_TXID       0x2000          /* add Tx delay */
+#define        MIIF_SGMII      0x4000          /* MAC to PHY interface is SGMII */
 
 #define        MIIF_INHERIT_MASK       (MIIF_NOISOLATE|MIIF_NOLOOP|MIIF_AUTOTSLEEP)
 

diff --git a/sys/dev/mii/rgephy.c b/sys/dev/mii/rgephy.c
index de6a58f..54ee588 100644 (file)
--- a/sys/dev/mii/rgephy.c
+++ b/sys/dev/mii/rgephy.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rgephy.c,v 1.42 2023/04/02 11:28:23 kettenis Exp $    */
+/*     $OpenBSD: rgephy.c,v 1.43 2023/04/05 10:45:07 kettenis Exp $    */
 /*
  * Copyright (c) 2003
  *     Bill Paul <wpaul@windriver.com>.  All rights reserved.
@@ -76,6 +76,7 @@ void  rgephy_status(struct mii_softc *);
 int    rgephy_mii_phy_auto(struct mii_softc *);
 void   rgephy_reset(struct mii_softc *);
 void   rgephy_loop(struct mii_softc *);
+void   rgephy_init_rtl8211f(struct mii_softc *);
 void   rgephy_load_dspcode(struct mii_softc *);
 
 const struct mii_phy_funcs rgephy_funcs = {
@@ -137,6 +138,11 @@ rgephyattach(struct device *parent, struct device *self, void *aux)
            (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
                mii_phy_add_media(sc);
 
+       if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
+           (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
+            sc->mii_rev == RGEPHY_8211F))
+               rgephy_init_rtl8211f(sc);
+
        PHY_RESET(sc);
 }
 
@@ -440,6 +446,35 @@ rgephy_loop(struct mii_softc *sc)
        }
 }
 
+void
+rgephy_init_rtl8211f(struct mii_softc *sc)
+{
+       if (sc->mii_flags & MIIF_SETDELAY) {
+               int page, val;
+
+               /* save page */
+               page = PHY_READ(sc, RGEPHY_PS);
+               PHY_WRITE(sc, RGEPHY_PS, RGEPHY_PS_PAGE_MII);
+
+               val = PHY_READ(sc, RGEPHY_MIICR1);
+               if (sc->mii_flags & MIIF_TXID)
+                       val |= RGEPHY_MIICR1_TXDLY_EN;
+               else
+                       val &= ~RGEPHY_MIICR1_TXDLY_EN;
+               PHY_WRITE(sc, RGEPHY_MIICR1, val);
+
+               val = PHY_READ(sc, RGEPHY_MIICR2);
+               if (sc->mii_flags & MIIF_RXID)
+                       val |= RGEPHY_MIICR2_RXDLY_EN;
+               else
+                       val &= ~RGEPHY_MIICR2_RXDLY_EN;
+               PHY_WRITE(sc, RGEPHY_MIICR2, val);
+
+               /* restore page */
+               PHY_WRITE(sc, RGEPHY_PS, page);
+       }
+}
+
 #define PHY_SETBIT(x, y, z) \
        PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
 #define PHY_CLRBIT(x, y, z) \

diff --git a/sys/dev/mii/rgephyreg.h b/sys/dev/mii/rgephyreg.h
index 7f4b269..a9beaba 100644 (file)
--- a/sys/dev/mii/rgephyreg.h
+++ b/sys/dev/mii/rgephyreg.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rgephyreg.h,v 1.9 2018/02/27 19:47:10 kettenis Exp $  */
+/*     $OpenBSD: rgephyreg.h,v 1.10 2023/04/05 10:45:07 kettenis Exp $ */
 /*
  * Copyright (c) 2003
  *     Bill Paul <wpaul@windriver.com>.  All rights reserved.
@@ -105,4 +105,11 @@
 #define RGEPHY_PS_PAGE_3       0x0003
 #define RGEPHY_PS_PAGE_4       0x0004
 
+/* RTL8211F */
+#define RGEPHY_PS_PAGE_MII     0x0d08
+#define RGEPHY_MIICR1          0x11
+#define RGEPHY_MIICR1_TXDLY_EN 0x0100
+#define RGEPHY_MIICR2          0x15
+#define RGEPHY_MIICR2_RXDLY_EN 0x0008
+
 #endif /* _DEV_RGEPHY_MIIREG_H_ */