Add an entry to report the bus clock on bernd's atom laptop.

Intel don't publish the EST voltage tables, and they don't
even publish the MSRs for a shipping processor so we
can figure out how to do this in the backwards highest/lowest
way cleanly.

The mapping might look like the Core * one, but who really knows
for sure outside of a few guys at Intel.  Other machines with
Atom processors and a different bus clock will have to be added
one by one until this stupidity changes.

Tested by bernd, ok gwk

diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 25a34b8..95bd7c2 100644 (file)
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: machdep.c,v 1.433 2008/06/27 17:22:14 miod Exp $      */
+/*     $OpenBSD: machdep.c,v 1.434 2008/07/07 13:41:59 jsg Exp $       */
 /*     $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $    */
 
 /*-
@@ -2021,6 +2021,19 @@ p3_get_bus_clock(struct cpu_info *ci)
                        goto print_msr;
                }
                break;
+       case 0xc: /* Atom */
+               msr = rdmsr(MSR_FSB_FREQ);
+               bus = (msr >> 0) & 0x7;
+               switch (bus) {
+               case 1:
+                       bus_clock = BUS133;
+                       break;
+               default:
+                       printf("%s: unknown Atom FSB_FREQ value %d",
+                           ci->ci_dev.dv_xname, bus);
+                       goto print_msr;
+               }
+               break;
        case 0x1: /* Pentium Pro, model 1 */
        case 0x3: /* Pentium II, model 3 */
        case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */