*******************************************************************************/
-/* $OpenBSD: if_em_hw.c,v 1.114 2022/01/27 18:28:44 bluhm Exp $ */
+/* $OpenBSD: if_em_hw.c,v 1.115 2022/06/23 09:38:28 jsg Exp $ */
/*
* if_em_hw.c Shared functions for accessing and configuring the MAC
*/
case E1000_DEV_ID_PCH_CMP_I219_V10:
case E1000_DEV_ID_PCH_CMP_I219_LM11:
case E1000_DEV_ID_PCH_CMP_I219_V11:
+ hw->mac_type = em_pch_cnp;
+ break;
case E1000_DEV_ID_PCH_TGP_I219_LM13:
case E1000_DEV_ID_PCH_TGP_I219_V13:
case E1000_DEV_ID_PCH_TGP_I219_LM14:
case E1000_DEV_ID_PCH_TGP_I219_V14:
case E1000_DEV_ID_PCH_TGP_I219_LM15:
case E1000_DEV_ID_PCH_TGP_I219_V15:
+ hw->mac_type = em_pch_tgp;
+ break;
case E1000_DEV_ID_PCH_ADP_I219_LM16:
case E1000_DEV_ID_PCH_ADP_I219_V16:
case E1000_DEV_ID_PCH_ADP_I219_LM17:
case E1000_DEV_ID_PCH_MTP_I219_V18:
case E1000_DEV_ID_PCH_MTP_I219_LM19:
case E1000_DEV_ID_PCH_MTP_I219_V19:
- hw->mac_type = em_pch_cnp;
+ hw->mac_type = em_pch_adp;
break;
case E1000_DEV_ID_EP80579_LAN_1:
hw->mac_type = em_icp_xxxx;
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
hw->swfwhw_semaphore_present = TRUE;
hw->asf_firmware_present = TRUE;
break;
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
case em_82573:
case em_82574:
/*
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
if (!hw->phy_reset_disable &&
em_check_phy_reset_block(hw) == E1000_SUCCESS) {
/*
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
if (hw->mac_type == em_ich8lan)
/* Set TARC0 bits 29 and 28 */
reg_tarc0 |= 0x30000000;
hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp) {
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp) {
/*
* The MAC-PHY interconnect may still be in SMBus mode
* after Sx->S0. Toggle the LANPHYPC Value bit to force
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
/*
* Old code always initialized queue 1,
* even when unused, keep behaviour
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
case em_82573:
case em_82574:
hw->fc = E1000_FC_FULL;
hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp)
ret_val = em_set_lplu_state_pchlan(hw, FALSE);
else
ret_val = em_set_d0_lplu_state(hw, FALSE);
hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp)
ret_val = em_set_lplu_state_pchlan(hw, FALSE);
/* Enable CRS on TX. This must be set for half-duplex operation. */
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
/*
* Set the mac to wait the maximum time between each
* iteration and increase the max iterations when polling the
if (hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp) {
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp) {
ret_val = em_set_eee_pchlan(hw);
if (ret_val)
return ret_val;
hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp)
return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE));
if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) ||
*phy_data = (uint16_t) mdic;
if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
- hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp)
usec_delay(100);
} else {
/*
hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp)
return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE));
if (em_swfw_sync_acquire(hw, hw->swfw))
}
if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
- hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp)
usec_delay(100);
} else {
/*
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
if (hw->phy_id == I217_E_PHY_ID)
match = TRUE;
break;
}
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
{
int32_t i = 0;
uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */);
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
word = EEPROM_COMPAT;
valid_csum_mask = EEPROM_COMPAT_VALID_CSUM;
break;
DEBUGFUNC("em_init_rx_addrs");
if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp || hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp || hw->mac_type == em_pch2lan)
if (em_phy_no_cable_workaround(hw))
printf(" ...failed to apply em_phy_no_cable_"
"workaround.\n");
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
(hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt &&
- hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp))
+ hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp &&
+ hw->mac_type != em_pch_tgp && hw->mac_type != em_pch_adp))
return;
temp = E1000_READ_REG(hw, ICRXPTC);
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
hw->bus_type = em_bus_type_pci_express;
hw->bus_speed = em_bus_speed_2500;
hw->bus_width = em_bus_width_pciex_1;
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
while (timeout) {
if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
break;
switch (hw->mac_type) {
case em_pch_spt:
case em_pch_cnp:
+ case em_pch_tgp:
+ case em_pch_adp:
bank1_offset = hw->flash_bank_size * 2;
act_offset = E1000_ICH_NVM_SIG_WORD * 2;
hw->mac_type == em_pch2lan ||
hw->mac_type == em_pch_lpt ||
hw->mac_type == em_pch_spt ||
- hw->mac_type == em_pch_cnp)
+ hw->mac_type == em_pch_cnp ||
+ hw->mac_type == em_pch_tgp ||
+ hw->mac_type == em_pch_adp)
sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
else
sw_cfg_mask = FEXTNVM_SW_CONFIG;