Read RAM base address and size so we know where to put the firmware.

diff --git a/sys/dev/ic/bwfm.c b/sys/dev/ic/bwfm.c
index 7023976..1563493 100644 (file)
--- a/sys/dev/ic/bwfm.c
+++ b/sys/dev/ic/bwfm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: bwfm.c,v 1.16 2017/12/16 23:39:58 patrick Exp $ */
+/* $OpenBSD: bwfm.c,v 1.17 2017/12/16 23:45:16 patrick Exp $ */
 /*
  * Copyright (c) 2010-2016 Broadcom Corporation
  * Copyright (c) 2016,2017 Patrick Wildt <patrick@blueri.se>
@@ -80,6 +80,10 @@ int   bwfm_chip_ca7_set_active(struct bwfm_softc *, uint32_t);
 void    bwfm_chip_ca7_set_passive(struct bwfm_softc *);
 int     bwfm_chip_cm3_set_active(struct bwfm_softc *);
 void    bwfm_chip_cm3_set_passive(struct bwfm_softc *);
+void    bwfm_chip_socram_ramsize(struct bwfm_softc *, struct bwfm_core *);
+void    bwfm_chip_sysmem_ramsize(struct bwfm_softc *, struct bwfm_core *);
+void    bwfm_chip_tcm_ramsize(struct bwfm_softc *, struct bwfm_core *);
+void    bwfm_chip_tcm_rambase(struct bwfm_softc *);
 
 int     bwfm_proto_bcdc_query_dcmd(struct bwfm_softc *, int,
             int, char *, size_t *);
@@ -572,7 +576,15 @@ bwfm_chip_attach(struct bwfm_softc *sc)
                bwfm_chip_set_passive(sc);
        }
 
-       /* TODO: get raminfo */
+       if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4)) != NULL) {
+               bwfm_chip_tcm_ramsize(sc, core);
+               bwfm_chip_tcm_rambase(sc);
+       } else if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_SYS_MEM)) != NULL) {
+               bwfm_chip_sysmem_ramsize(sc, core);
+               bwfm_chip_tcm_rambase(sc);
+       } else if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM)) != NULL) {
+               bwfm_chip_socram_ramsize(sc, core);
+       }
 
        core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
        sc->sc_chip.ch_cc_caps = sc->sc_buscore_ops->bc_read(sc,
@@ -919,6 +931,79 @@ bwfm_chip_cm3_set_passive(struct bwfm_softc *sc)
        }
 }
 
+/* RAM size helpers */
+void
+bwfm_chip_socram_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
+{
+       panic("%s: socram ramsize not supported", DEVNAME(sc));
+}
+
+void
+bwfm_chip_sysmem_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
+{
+       panic("%s: sysmem ramsize not supported", DEVNAME(sc));
+}
+
+void
+bwfm_chip_tcm_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
+{
+       uint32_t cap, nab, nbb, totb, bxinfo, memsize = 0;
+       int i;
+
+       cap = sc->sc_buscore_ops->bc_read(sc, core->co_base + BWFM_ARMCR4_CAP);
+       nab = (cap & BWFM_ARMCR4_CAP_TCBANB_MASK) >> BWFM_ARMCR4_CAP_TCBANB_SHIFT;
+       nbb = (cap & BWFM_ARMCR4_CAP_TCBBNB_MASK) >> BWFM_ARMCR4_CAP_TCBBNB_SHIFT;
+       totb = nab + nbb;
+
+       for (i = 0; i < totb; i++) {
+               sc->sc_buscore_ops->bc_write(sc,
+                   core->co_base + BWFM_ARMCR4_BANKIDX, i);
+               bxinfo = sc->sc_buscore_ops->bc_read(sc,
+                   core->co_base + BWFM_ARMCR4_BANKINFO);
+               memsize += ((bxinfo & BWFM_ARMCR4_BANKINFO_BSZ_MASK) + 1) *
+                   BWFM_ARMCR4_BANKINFO_BSZ_MULT;
+       }
+
+       sc->sc_chip.ch_ramsize = memsize;
+}
+
+void
+bwfm_chip_tcm_rambase(struct bwfm_softc *sc)
+{
+       switch (sc->sc_chip.ch_chip) {
+       case BRCM_CC_4345_CHIP_ID:
+               sc->sc_chip.ch_rambase = 0x198000;
+               break;
+       case BRCM_CC_4335_CHIP_ID:
+       case BRCM_CC_4339_CHIP_ID:
+       case BRCM_CC_4350_CHIP_ID:
+       case BRCM_CC_4354_CHIP_ID:
+       case BRCM_CC_4356_CHIP_ID:
+       case BRCM_CC_43567_CHIP_ID:
+       case BRCM_CC_43569_CHIP_ID:
+       case BRCM_CC_43570_CHIP_ID:
+       case BRCM_CC_4358_CHIP_ID:
+       case BRCM_CC_4359_CHIP_ID:
+       case BRCM_CC_43602_CHIP_ID:
+       case BRCM_CC_4371_CHIP_ID:
+               sc->sc_chip.ch_rambase = 0x180000;
+               break;
+       case BRCM_CC_43465_CHIP_ID:
+       case BRCM_CC_43525_CHIP_ID:
+       case BRCM_CC_4365_CHIP_ID:
+       case BRCM_CC_4366_CHIP_ID:
+               sc->sc_chip.ch_rambase = 0x200000;
+               break;
+       case CY_CC_4373_CHIP_ID:
+               sc->sc_chip.ch_rambase = 0x160000;
+               break;
+       default:
+               printf("%s: unknown chip: %d\n", DEVNAME(sc),
+                   sc->sc_chip.ch_chip);
+               break;
+       }
+}
+
 /* BCDC protocol implementation */
 int
 bwfm_proto_bcdc_query_dcmd(struct bwfm_softc *sc, int ifidx,

diff --git a/sys/dev/ic/bwfmreg.h b/sys/dev/ic/bwfmreg.h
index 428214a..79b7409 100644 (file)
--- a/sys/dev/ic/bwfmreg.h
+++ b/sys/dev/ic/bwfmreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: bwfmreg.h,v 1.9 2017/10/21 20:43:20 patrick Exp $ */
+/* $OpenBSD: bwfmreg.h,v 1.10 2017/12/16 23:45:16 patrick Exp $ */
 /*
  * Copyright (c) 2010-2016 Broadcom Corporation
  * Copyright (c) 2016,2017 Patrick Wildt <patrick@blueri.se>
@@ -49,6 +49,7 @@
 #define  BWFM_CHIP_REG_CAPABILITIES_PMU                        0x10000000
 #define BWFM_CHIP_REG_CAPABILITIES_EXT         0x000000AC
 #define  BWFM_CHIP_REG_CAPABILITIES_EXT_AOB_PRESENT    0x00000040
+#define BWFM_CHIP_REG_WATCHDOG                 0x00000080
 #define BWFM_CHIP_REG_EROMPTR                  0x000000FC
 #define BWFM_CHIP_REG_PMUCONTROL               0x00000600
 #define  BWFM_CHIP_REG_PMUCONTROL_RES_MASK             0x00006000
@@ -64,6 +65,7 @@
 #define  BWFM_AGENT_IOCTL_CORE_BITS                    0x3FFC
 #define  BWFM_AGENT_IOCTL_PME_EN                       0x4000
 #define  BWFM_AGENT_IOCTL_BIST_EN                      0x8000
+#define  BWFM_AGENT_IOCTL_ARMCR4_CPUHALT               0x0020
 #define BWFM_AGENT_RESET_CTL                   0x0800
 #define  BWFM_AGENT_RESET_CTL_RESET                    0x0001
 
@@ -74,14 +76,28 @@
 #define BWFM_AGENT_CORE_PMU                    0x827
 #define BWFM_AGENT_CORE_SDIO_DEV               0x829
 #define BWFM_AGENT_CORE_ARM_CM3                        0x82A
+#define BWFM_AGENT_CORE_PCIE2                  0x83C
 #define BWFM_AGENT_CORE_ARM_CR4                        0x83E
 #define BWFM_AGENT_CORE_ARM_CA7                        0x847
+#define BWFM_AGENT_SYS_MEM                     0x849
 
 /* Specific Core Bits */
 #define BWFM_AGENT_ARMCR4_IOCTL_CPUHALT                0x0020
 #define BWFM_AGENT_D11_IOCTL_PHYCLOCKEN                0x0004
 #define BWFM_AGENT_D11_IOCTL_PHYRESET          0x0008
 
+/* CR4 registers */
+#define BWFM_ARMCR4_CAP                                0x0004
+#define  BWFM_ARMCR4_CAP_TCBANB_MASK                   0x0f
+#define  BWFM_ARMCR4_CAP_TCBANB_SHIFT                  0
+#define  BWFM_ARMCR4_CAP_TCBBNB_MASK                   0xf0
+#define  BWFM_ARMCR4_CAP_TCBBNB_SHIFT                  4
+#define BWFM_ARMCR4_BANKIDX                    0x0040
+#define BWFM_ARMCR4_BANKINFO                   0x0044
+#define  BWFM_ARMCR4_BANKINFO_BSZ_MASK                 0x3f
+#define  BWFM_ARMCR4_BANKINFO_BSZ_MULT                 8192
+#define BWFM_ARMCR4_BANKPDA                    0x004C
+
 /* SOCRAM registers */
 #define BWFM_SOCRAM_BANKIDX                    0x0010
 #define BWFM_SOCRAM_BANKPDA                    0x0044