Matching i386 commit to previous amd64 commit (initial support for vmctl
authormlarkin <mlarkin@openbsd.org>
Tue, 2 May 2017 07:18:19 +0000 (07:18 +0000)
committermlarkin <mlarkin@openbsd.org>
Tue, 2 May 2017 07:18:19 +0000 (07:18 +0000)
send/receive)

sys/arch/i386/i386/vmm.c
sys/arch/i386/include/vmmvar.h

index e9bf6e2..d19be70 100644 (file)
@@ -1,4 +1,4 @@
-/* $OpenBSD: vmm.c,v 1.28 2017/04/26 08:02:14 mlarkin Exp $ */
+/* $OpenBSD: vmm.c,v 1.29 2017/05/02 07:18:19 mlarkin Exp $ */
 /*
  * Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
  *
@@ -1338,7 +1338,9 @@ vcpu_readregs_vmx(struct vcpu *vcpu, uint64_t regmask,
        uint32_t sel, limit, ar;
        uint32_t *gprs = vrs->vrs_gprs;
        uint32_t *crs = vrs->vrs_crs;
+       uint32_t *msrs = vrs->vrs_msrs;
        struct vcpu_segment_info *sregs = vrs->vrs_sregs;
+       struct vmx_msr_store *msr_store;
 
        if (vcpu_reload_vmcs_vmx(&vcpu->vc_control_pa))
                return (EINVAL);
@@ -1398,6 +1400,14 @@ vcpu_readregs_vmx(struct vcpu *vcpu, uint64_t regmask,
                        goto errout;
        }
 
+       msr_store = (struct vmx_msr_store *)vcpu->vc_vmx_msr_exit_save_va;
+
+       if (regmask & VM_RWREGS_MSRS) {
+               for (i = 0; i < VCPU_REGS_NMSRS; i++) {
+                       msrs[i] = msr_store[i].vms_data;
+               }
+       }
+
        goto out;
 
 errout:
@@ -1444,7 +1454,9 @@ vcpu_writeregs_vmx(struct vcpu *vcpu, uint64_t regmask, int loadvmcs,
        uint32_t limit, ar;
        uint32_t *gprs = vrs->vrs_gprs;
        uint32_t *crs = vrs->vrs_crs;
+       uint32_t *msrs = vrs->vrs_msrs;
        struct vcpu_segment_info *sregs = vrs->vrs_sregs;
+       struct vmx_msr_store *msr_store;
 
        if (loadvmcs) {
                if (vcpu_reload_vmcs_vmx(&vcpu->vc_control_pa))
@@ -1506,6 +1518,14 @@ vcpu_writeregs_vmx(struct vcpu *vcpu, uint64_t regmask, int loadvmcs,
                        goto errout;
        }
 
+       msr_store = (struct vmx_msr_store *)vcpu->vc_vmx_msr_exit_save_va;
+
+       if (regmask & VM_RWREGS_MSRS) {
+               for (i = 0; i < VCPU_REGS_NMSRS; i++) {
+                       msr_store[i].vms_data = msrs[i];
+               }
+       }
+
        goto out;
 
 errout:
@@ -2240,7 +2260,6 @@ vcpu_reset_regs_vmx(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
        msr_store = (struct vmx_msr_store *)vcpu->vc_vmx_msr_exit_save_va;
 
        msr_store[0].vms_index = MSR_EFER;
-       msr_store[0].vms_data = 0ULL;           /* Initial value */
 
        /*
         * Currently we have the same count of entry/exit MSRs loads/stores
index a828b9f..7e62b31 100644 (file)
@@ -331,9 +331,13 @@ struct vcpu_segment_info {
 #define VCPU_REGS_TR           7
 #define VCPU_REGS_NSREGS       (VCPU_REGS_TR + 1)
 
+#define VCPU_REGS_EFER         0
+#define VCPU_REGS_NMSRS                (VCPU_REGS_EFER + 1)
+
 struct vcpu_reg_state {
        uint32_t                        vrs_gprs[VCPU_REGS_NGPRS];
        uint32_t                        vrs_crs[VCPU_REGS_NCRS];
+       uint32_t                        vrs_msrs[VCPU_REGS_NMSRS];
        struct vcpu_segment_info        vrs_sregs[VCPU_REGS_NSREGS];
        struct vcpu_segment_info        vrs_gdtr;
        struct vcpu_segment_info        vrs_idtr;
@@ -418,7 +422,9 @@ struct vm_intr_params {
 #define VM_RWREGS_GPRS 0x1     /* read/write GPRs */
 #define VM_RWREGS_SREGS        0x2     /* read/write segment registers */
 #define VM_RWREGS_CRS  0x4     /* read/write CRs */
-#define VM_RWREGS_ALL  (VM_RWREGS_GPRS | VM_RWREGS_SREGS | VM_RWREGS_CRS)
+#define VM_RWREGS_MSRS 0x8     /* read/write MSRs */
+#define VM_RWREGS_ALL  (VM_RWREGS_GPRS | VM_RWREGS_SREGS | VM_RWREGS_CRS | \
+    VM_RWREGS_MSRS)
 
 struct vm_rwregs_params {
        uint32_t                vrwp_vm_id;