Implement H3/H5 thermal sensor clocks.
authorkettenis <kettenis@openbsd.org>
Sun, 31 Dec 2017 13:52:18 +0000 (13:52 +0000)
committerkettenis <kettenis@openbsd.org>
Sun, 31 Dec 2017 13:52:18 +0000 (13:52 +0000)
sys/dev/fdt/sxiccmu_clocks.h

index 12ff9b9..d22b1d2 100644 (file)
@@ -292,6 +292,7 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
 #define H3_CLK_BUS_OHCI2       39
 #define H3_CLK_BUS_OHCI3       40
 #define H3_CLK_BUS_PIO         54
+#define H3_CLK_BUS_THS         55
 #define H3_CLK_BUS_I2C0                59
 #define H3_CLK_BUS_I2C1                60
 #define H3_CLK_BUS_I2C2                61
@@ -301,6 +302,7 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
 #define H3_CLK_BUS_UART3       65
 #define H3_CLK_BUS_EPHY                67
 
+#define H3_CLK_THS             69
 #define H3_CLK_MMC0            71
 #define H3_CLK_MMC1            74
 #define H3_CLK_MMC2            77
@@ -327,6 +329,7 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
        [H3_CLK_BUS_OHCI2] = { 0x0060, 30 },
        [H3_CLK_BUS_OHCI3] = { 0x0060, 31 },
        [H3_CLK_BUS_PIO]   = { 0x0068, 5 },
+       [H3_CLK_BUS_THS]   = { 0x0068, 8 },
        [H3_CLK_BUS_I2C0]  = { 0x006c, 0, H3_CLK_APB2 },
        [H3_CLK_BUS_I2C1]  = { 0x006c, 1, H3_CLK_APB2 },
        [H3_CLK_BUS_I2C2]  = { 0x006c, 2, H3_CLK_APB2 },
@@ -335,6 +338,7 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
        [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 },
        [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 },
        [H3_CLK_BUS_EPHY]  = { 0x0070, 0 },
+       [H3_CLK_THS]       = { 0x0074, 31 },
        [H3_CLK_MMC0]      = { 0x0088, 31 },
        [H3_CLK_MMC1]      = { 0x008c, 31 },
        [H3_CLK_MMC2]      = { 0x0090, 31 },
@@ -582,9 +586,8 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
 #define H3_RST_BUS_OHCI1       23
 #define H3_RST_BUS_OHCI2       24
 #define H3_RST_BUS_OHCI3       25
-
 #define H3_RST_BUS_EPHY                39
-
+#define H3_RST_BUS_THS         42
 #define H3_RST_BUS_I2C0                46
 #define H3_RST_BUS_I2C1                47
 #define H3_RST_BUS_I2C2                48
@@ -607,6 +610,7 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
        [H3_RST_BUS_OHCI2] = { 0x02c0, 30 },
        [H3_RST_BUS_OHCI3] = { 0x02c0, 31 },
        [H3_RST_BUS_EPHY]  = { 0x02c8, 2 },
+       [H3_RST_BUS_THS]   = { 0x02d0, 8 },
        [H3_RST_BUS_I2C0]  = { 0x02d8, 0 },
        [H3_RST_BUS_I2C1]  = { 0x02d8, 1 },
        [H3_RST_BUS_I2C2]  = { 0x02d8, 2 },