return MI_ARB_CHECK | 1 << 8 | state;
}
+static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
+{
+ if (IS_PONTEVECCHIO(engine->i915))
+ return false;
+
+ /*
+ * so far platforms supported by i915 having
+ * flat ccs do not require AUX invalidation
+ */
+ return !HAS_FLAT_CCS(engine->i915);
+}
+
u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg)
{
u32 gsi_offset = gt->uncore->gsi_offset;
else if (engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
- if (!HAS_FLAT_CCS(rq->engine->i915))
+ if (gen12_needs_ccs_aux_inv(rq->engine))
count = 8 + 4;
else
count = 8;
cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
- if (!HAS_FLAT_CCS(rq->engine->i915)) {
+ if (gen12_needs_ccs_aux_inv(rq->engine)) {
/* hsdes: 1809175790 */
cs = gen12_emit_aux_table_inv(rq->engine->gt, cs,
GEN12_CCS_AUX_INV);
if (mode & EMIT_INVALIDATE) {
cmd += 2;
- if (!HAS_FLAT_CCS(rq->engine->i915) &&
+ if (gen12_needs_ccs_aux_inv(rq->engine) &&
(rq->engine->class == VIDEO_DECODE_CLASS ||
rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
aux_inv = rq->engine->mask &