drm/amdgpu/sdma5.2: use legacy HDP flush for SDMA2/3

From Alex Deucher
b33d7aaa2d3d1bef20fd5d9ab0d1776376fc98b6 in linux-6.6.y/6.6.30
9792b7cc18aaa0c2acae6af5d0acf249bcb1ab0d in mainline linux

diff --git a/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c b/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
index 0e6be54..ac3ae21 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
+++ b/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
@@ -292,17 +292,21 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
        u32 ref_and_mask = 0;
        const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 
-       ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
-                         SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
-                         SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
-       amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
-       amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
-       amdgpu_ring_write(ring, ref_and_mask); /* reference */
-       amdgpu_ring_write(ring, ref_and_mask); /* mask */
-       amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-                         SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
+       if (ring->me > 1) {
+               amdgpu_asic_flush_hdp(adev, ring);
+       } else {
+               ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
+
+               amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+                                 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
+                                 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
+               amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
+               amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
+               amdgpu_ring_write(ring, ref_and_mask); /* reference */
+               amdgpu_ring_write(ring, ref_and_mask); /* mask */
+               amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+                                 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
+       }
 }
 
 /**