drm/amd/display: fix unbounded requesting for high pixel rate modes on dcn315

From Dmytro Laktyushkin
ad8c20954406491a8280d0a442ac4bb9ea9e674e in linux-6.1.y/6.1.43
655435df0936ce2fda0d5ced7e50101179a3acfd in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c
index 31cbc57..19f2025 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1707,7 +1707,9 @@ static int dcn315_populate_dml_pipes_from_context(
                        dc->config.enable_4to1MPC = true;
                        context->bw_ctx.dml.ip.det_buffer_size_kbytes =
                                        (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
-               } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
+               } else if (!is_dual_plane(pipe->plane_state->format)
+                               && pipe->plane_state->src_rect.width <= 5120
+                               && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
                        /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
                        context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
                        pipes[0].pipe.src.unbounded_req_mode = true;

diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index aa1c291..e48923f 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -807,3 +807,8 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
        else
                dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA);
 }
+
+int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc)
+{
+       return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0);
+}

diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
index fd58b25..ab8c48b 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
@@ -46,5 +46,6 @@ void dcn31_calculate_wm_and_dlg_fp(
 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc);
 
 #endif /* __DCN31_FPU_H__*/