isa16bit = 1;
break;
case ED_TYPE_SMC8216C:
- sc->type_str = "SMC8216/SMC8216C";
- memsize = 16384;
- isa16bit = 1;
- sc->is790 = 1;
- break;
case ED_TYPE_SMC8216T:
- sc->type_str = "SMC8216T";
- memsize = 16384;
+ sc->type_str = (sc->type == ED_TYPE_SMC8216C) ?
+ "SMC8216/SMC8216C" : "SMC8216T";
+ outb(sc->asic_addr + ED_WD790_HWR,
+ inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
+ switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
+ case ED_WD790_RAR_SZ64:
+ memsize = 65536;
+ break;
+ case ED_WD790_RAR_SZ32:
+ memsize = 32768;
+ break;
+ case ED_WD790_RAR_SZ16:
+ memsize = 16384;
+ break;
+ case ED_WD790_RAR_SZ8:
+ /* 8216 has 16K shared mem -- 8416 has 8K */
+ sc->type_str = (sc->type == ED_TYPE_SMC8216C) ?
+ "SMC8416C/SMC8416BT" : "SMC8416T";
+ memsize = 8192;
+ break;
+ }
+ outb(sc->asic_addr + ED_WD790_HWR,
+ inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+
isa16bit = 1;
sc->is790 = 1;
break;
#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
+/*
+ * REV/IOPA Revision / I/O Pipe register for the 83C79X
+ */
+#define ED_WD790_REV 7
+
+#define ED_WD790 0x20
+#define ED_WD795 0x40
+
+/*
+ * 79X RAM Address Register (RAR)
+ * Enabled with SWH bit=1 in HWR register
+ */
+
+#define ED_WD790_RAR 0x0b
+
+#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
+#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
+#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
+#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
+
/*
* General Control Register (GCR)
* Eanbled with SWH bit == 1 in HWR register