Add some resets for the PCIe controllers on the RK3588.

ok kettenis@

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index cbe3a9c..d11c104 100644 (file)
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rkclock.c,v 1.80 2023/07/07 16:53:39 patrick Exp $    */
+/*     $OpenBSD: rkclock.c,v 1.81 2023/07/08 08:37:39 patrick Exp $    */
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -4388,10 +4388,42 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
        uint32_t bit, mask, reg;
 
        switch (idx) {
+       case RK3588_SRST_PCIE0_POWER_UP:
+               reg = RK3588_CRU_SOFTRST_CON(32);
+               bit = 13;
+               break;
+       case RK3588_SRST_PCIE1_POWER_UP:
+               reg = RK3588_CRU_SOFTRST_CON(32);
+               bit = 14;
+               break;
+       case RK3588_SRST_PCIE2_POWER_UP:
+               reg = RK3588_CRU_SOFTRST_CON(32);
+               bit = 15;
+               break;
+       case RK3588_SRST_PCIE3_POWER_UP:
+               reg = RK3588_CRU_SOFTRST_CON(33);
+               bit = 0;
+               break;
        case RK3588_SRST_PCIE4_POWER_UP:
                reg = RK3588_CRU_SOFTRST_CON(33);
                bit = 1;
                break;
+       case RK3588_SRST_P_PCIE0:
+               reg = RK3588_CRU_SOFTRST_CON(33);
+               bit = 12;
+               break;
+       case RK3588_SRST_P_PCIE1:
+               reg = RK3588_CRU_SOFTRST_CON(33);
+               bit = 13;
+               break;
+       case RK3588_SRST_P_PCIE2:
+               reg = RK3588_CRU_SOFTRST_CON(33);
+               bit = 14;
+               break;
+       case RK3588_SRST_P_PCIE3:
+               reg = RK3588_CRU_SOFTRST_CON(33);
+               bit = 15;
+               break;
        case RK3588_SRST_P_PCIE4:
                reg = RK3588_CRU_SOFTRST_CON(34);
                bit = 0;
@@ -4412,6 +4444,10 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
                reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
                bit = 5;
                break;
+       case RK3588_SRST_PCIE30_PHY:
+               reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
+               bit = 10;
+               break;
        default:
                printf("%s: 0x%08x\n", __func__, idx);
                return;

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index f4b7727..6ca83f5 100644 (file)
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -477,9 +477,18 @@
 #define RK3588_PLL_SPLL                        1022
 #define RK3588_XIN24M                  1023
 
+#define RK3588_SRST_PCIE0_POWER_UP     294
+#define RK3588_SRST_PCIE1_POWER_UP     295
+#define RK3588_SRST_PCIE2_POWER_UP     296
+#define RK3588_SRST_PCIE3_POWER_UP     297
 #define RK3588_SRST_PCIE4_POWER_UP     298
+#define RK3588_SRST_P_PCIE0            299
+#define RK3588_SRST_P_PCIE1            300
+#define RK3588_SRST_P_PCIE2            301
+#define RK3588_SRST_P_PCIE3            302
 #define RK3588_SRST_P_PCIE4            303
 #define RK3588_SRST_A_USB3OTG0         338
 #define RK3588_SRST_A_USB3OTG1         339
 #define RK3588_SRST_REF_PIPE_PHY0      572
 #define RK3588_SRST_P_PCIE2_PHY0       579
+#define RK3588_SRST_PCIE30_PHY         584