drm/i915: Explain the magic numbers for AUX SYNC/precharge length

From Ville Syrjala
7bf7bebdc20df3d53a6c7af583d704e811fed85d in linux-6.1.y/6.1.34
26bfc3f36f2104c174dfc72415547d5c28ef3f1c in mainline linux

diff --git a/sys/dev/pci/drm/i915/display/intel_dp_aux.c b/sys/dev/pci/drm/i915/display/intel_dp_aux.c
index d9e3e7a..08473f8 100644 (file)
--- a/sys/dev/pci/drm/i915/display/intel_dp_aux.c
+++ b/sys/dev/pci/drm/i915/display/intel_dp_aux.c
@@ -119,6 +119,32 @@ static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
        return index ? 0 : 1;
 }
 
+static int intel_dp_aux_sync_len(void)
+{
+       int precharge = 16; /* 10-16 */
+       int preamble = 16;
+
+       return precharge + preamble;
+}
+
+static int intel_dp_aux_fw_sync_len(void)
+{
+       int precharge = 16; /* 10-16 */
+       int preamble = 8;
+
+       return precharge + preamble;
+}
+
+static int g4x_dp_aux_precharge_len(void)
+{
+       int precharge_min = 10;
+       int preamble = 16;
+
+       /* HW wants the length of the extra precharge in 2us units */
+       return (intel_dp_aux_sync_len() -
+               precharge_min - preamble) / 2;
+}
+
 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
                                int send_bytes,
                                u32 aux_clock_divider)
@@ -141,7 +167,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
               timeout |
               DP_AUX_CH_CTL_RECEIVE_ERROR |
               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-              (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+              (g4x_dp_aux_precharge_len() << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
               (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 }
 
@@ -165,8 +191,8 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
              DP_AUX_CH_CTL_TIME_OUT_MAX |
              DP_AUX_CH_CTL_RECEIVE_ERROR |
              (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-             DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(24) |
-             DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+             DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
+             DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
 
        if (intel_tc_port_in_tbt_alt_mode(dig_port))
                ret |= DP_AUX_CH_CTL_TBT_IO;