drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

From Matt Roper
798781b43194c6d2bdea0c4ded660f3135c484d3 in linux-6.6.y/6.6.26
c44d4ef47fdad0a33966de89f9064e19736bb52f in mainline linux

diff --git a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
index ba4c242..cddf8c1 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
+++ b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
@@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
        /* Wa_14016712196 */
-       if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||
+       if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
            IS_DG2(rq->i915)) {
                u32 *cs;
 
@@ -819,7 +819,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
                     PIPE_CONTROL_FLUSH_ENABLE);
 
        /* Wa_14016712196 */
-       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
                /* dummy PIPE_CONTROL + depth flush */
                cs = gen12_emit_pipe_control(cs, 0,
                                             PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);

diff --git a/sys/dev/pci/drm/i915/gt/intel_workarounds.c b/sys/dev/pci/drm/i915/gt/intel_workarounds.c
index b6237e9..37b2b04 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_workarounds.c
+++ b/sys/dev/pci/drm/i915/gt/intel_workarounds.c
@@ -788,8 +788,13 @@ static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 
        dg2_ctx_gt_tuning_init(engine, wal);
 
-       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
-           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
+       /*
+        * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in
+        * gen12_emit_indirect_ctx_rcs() rather than here on some early
+        * steppings.
+        */
+       if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))
                wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -907,7 +912,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
        if (engine->class != RENDER_CLASS)
                goto done;
 
-       if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+       if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
                xelpg_ctx_workarounds_init(engine, wal);
        else if (IS_PONTEVECCHIO(i915))
                ; /* noop; none at this time */
@@ -1638,7 +1643,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-       /* Wa_14018778641 / Wa_18018781329 */
+       /* Wa_14018575942 / Wa_18018781329 */
        wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
 
        /* Wa_22016670082 */
@@ -1688,7 +1693,7 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  */
 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
                wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
                wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
        }
@@ -1721,7 +1726,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
                return;
        }
 
-       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
                xelpg_gt_workarounds_init(gt, wal);
        else if (IS_PONTEVECCHIO(i915))
                pvc_gt_workarounds_init(gt, wal);
@@ -2194,7 +2199,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
        if (engine->gt->type == GT_MEDIA)
                ; /* none yet */
-       else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+       else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
                xelpg_whitelist_build(engine);
        else if (IS_PONTEVECCHIO(i915))
                pvc_whitelist_build(engine);
@@ -2801,7 +2806,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 {
        struct drm_i915_private *i915 = gt->i915;
 
-       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
                wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
 
        /*
@@ -2854,7 +2859,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
        }
 
        if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
-           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
+           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||
+           IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74)))
                /* Wa_14017856879 */
                wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 

diff --git a/sys/dev/pci/drm/i915/i915_perf.c b/sys/dev/pci/drm/i915/i915_perf.c
index 0a111d1..5236810 100644 (file)
--- a/sys/dev/pci/drm/i915/i915_perf.c
+++ b/sys/dev/pci/drm/i915/i915_perf.c
@@ -3288,7 +3288,7 @@ u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
        struct intel_gt *gt = to_gt(i915);
 
        /* Wa_18013179988 */
-       if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+       if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
                intel_wakeref_t wakeref;
                u32 reg, shift;