dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
}
+ if (i915_direct_stolen_access(i915)) {
+ drm_dbg(&i915->drm, "Using direct DSM access\n");
+ io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+ io_size = dsm_size;
#ifdef __linux__
- if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
+ } else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
io_start = 0;
io_size = 0;
} else {
io_size = dsm_size;
}
#else
- if (lmem_len < lmem_size) {
+ } else if (lmem_len < lmem_size) {
io_start = 0;
io_size = 0;
} else {
#include "intel_ring.h"
#include "i915_drv.h"
#include "i915_pci.h"
+#include "i915_reg.h"
#include "i915_request.h"
#include "i915_scatterlist.h"
#include "i915_utils.h"
static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
+ struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
phys_addr_t phys_addr;
u32 pte_flags;
int ret;
GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
- phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
+
+ if (i915_direct_stolen_access(i915)) {
+ drm_dbg(&i915->drm, "Using direct GSM access\n");
+ phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+ } else {
+ phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
+ }
if (needs_wc_ggtt_mapping(i915))
ggtt->gsm = ioremap_wc(phys_addr, size);
static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
+ struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct pci_dev *pdev = i915->drm.pdev;
phys_addr_t phys_addr;
bus_addr_t addr;
return ret;
GEM_WARN_ON(len != gen6_gttmmadr_size(i915));
- phys_addr = addr + gen6_gttadr_offset(i915);
+
+ if (i915_direct_stolen_access(i915)) {
+ drm_dbg(&i915->drm, "Using direct GSM access\n");
+ phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+ } else {
+ phys_addr = addr + gen6_gttadr_offset(i915);
+ }
if (needs_wc_ggtt_mapping(i915))
flags = BUS_SPACE_MAP_PREFETCHABLE;
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
+#define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
+#define STOLEN_ACCESS_ALLOWED 0x1
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
#include <drm/drm_drv.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_utils.h"
#include <sys/syslog.h>
return i915_run_as_guest();
#endif
}
+
+bool i915_direct_stolen_access(struct drm_i915_private *i915)
+{
+ /*
+ * Wa_22018444074
+ *
+ * Access via BAR can hang MTL, go directly to GSM/DSM,
+ * except for VM guests which won't have access to it.
+ *
+ * Normally this would not work but on MTL the system firmware
+ * should have relaxed the access permissions sufficiently.
+ * 0x138914==0x1 indicates that the firmware has done its job.
+ */
+ return IS_METEORLAKE(i915) && !i915_run_as_guest() &&
+ intel_uncore_read(&i915->uncore, MTL_PCODE_STOLEN_ACCESS) == STOLEN_ACCESS_ALLOWED;
+}