drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3

From Vinay Belgaumkar
5fde104ea8587c547732a06d9d6473f6e7e4ac1c in mainline linux

diff --git a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
index cddf8c1..e1bf13e 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
+++ b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
@@ -278,7 +278,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
                 * deals with Protected Memory which is not needed for
                 * AUX CCS invalidation and lead to unwanted side effects.
                 */
-               if (mode & EMIT_FLUSH)
+               if ((mode & EMIT_FLUSH) &&
+                   GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))
                        bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
 
                bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
@@ -812,12 +813,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
        u32 flags = (PIPE_CONTROL_CS_STALL |
                     PIPE_CONTROL_TLB_INVALIDATE |
                     PIPE_CONTROL_TILE_CACHE_FLUSH |
-                    PIPE_CONTROL_FLUSH_L3 |
                     PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
                     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                     PIPE_CONTROL_DC_FLUSH_ENABLE |
                     PIPE_CONTROL_FLUSH_ENABLE);
 
+       if (GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))
+               flags |= PIPE_CONTROL_FLUSH_L3;
+
        /* Wa_14016712196 */
        if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
                /* dummy PIPE_CONTROL + depth flush */