drm/amdgpu: Don't enable LTR if not supported

From Lijo Lazar
dcef16f64969eefb83c8711173fd025611f258f8 in linux 5.15.y/5.15.70
6c20490663553cd7e07d8de8af482012329ab9d6 in mainline linux

diff --git a/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c b/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
index b184b65..6f21154 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
+++ b/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
@@ -366,6 +366,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
                WREG32_PCIE(smnPCIE_LC_CNTL, data);
 }
 
+#ifdef CONFIG_PCIEASPM
 static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
 {
        uint32_t def, data;
@@ -387,9 +388,11 @@ static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
 }
+#endif
 
 static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
 {
+#ifdef CONFIG_PCIEASPM
        uint32_t def, data;
 
        def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
@@ -445,7 +448,10 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnPCIE_LC_CNTL6, data);
 
-       nbio_v2_3_program_ltr(adev);
+       /* Don't bother about LTR if LTR is not enabled
+        * in the path */
+       if (adev->pdev->ltr_path)
+               nbio_v2_3_program_ltr(adev);
 
        def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
        data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
@@ -469,6 +475,7 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
        data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
        if (def != data)
                WREG32_PCIE(smnPCIE_LC_CNTL3, data);
+#endif
 }
 
 static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)

diff --git a/sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c b/sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
index 0d2d629..be3f6c5 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
+++ b/sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
@@ -278,6 +278,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
                WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 
+#ifdef CONFIG_PCIEASPM
 static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
 {
        uint32_t def, data;
@@ -299,9 +300,11 @@ static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
 }
+#endif
 
 static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
 {
+#ifdef CONFIG_PCIEASPM
        uint32_t def, data;
 
        def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
@@ -357,7 +360,10 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnPCIE_LC_CNTL6, data);
 
-       nbio_v6_1_program_ltr(adev);
+       /* Don't bother about LTR if LTR is not enabled
+        * in the path */
+       if (adev->pdev->ltr_path)
+               nbio_v6_1_program_ltr(adev);
 
        def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
        data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
@@ -381,6 +387,7 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
        data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
        if (def != data)
                WREG32_PCIE(smnPCIE_LC_CNTL3, data);
+#endif
 }
 
 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {

diff --git a/sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c b/sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
index f50045c..74cd754 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
+++ b/sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
@@ -630,6 +630,7 @@ const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = {
        .ras_fini = amdgpu_nbio_ras_fini,
 };
 
+#ifdef CONFIG_PCIEASPM
 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
 {
        uint32_t def, data;
@@ -651,9 +652,11 @@ static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
 }
+#endif
 
 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
 {
+#ifdef CONFIG_PCIEASPM
        uint32_t def, data;
 
        def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
@@ -709,7 +712,10 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnPCIE_LC_CNTL6, data);
 
-       nbio_v7_4_program_ltr(adev);
+       /* Don't bother about LTR if LTR is not enabled
+        * in the path */
+       if (adev->pdev->ltr_path)
+               nbio_v7_4_program_ltr(adev);
 
        def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
        data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
@@ -733,6 +739,7 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
        data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
        if (def != data)
                WREG32_PCIE(smnPCIE_LC_CNTL3, data);
+#endif
 }
 
 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {